]> git.proxmox.com Git - mirror_qemu.git/blame - target-tilegx/translate.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-tilegx: Handle most bit manipulation instructions
[mirror_qemu.git] / target-tilegx / translate.c
CommitLineData
8fd29dd7
RH		 1/*
2 * QEMU TILE-Gx CPU
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21#include "cpu.h"
22#include "qemu/log.h"
23#include "disas/disas.h"
24#include "tcg-op.h"
25#include "exec/cpu_ldst.h"
26#include "opcode_tilegx.h"
27
28#define FMT64X "%016" PRIx64
29
30static TCGv_ptr cpu_env;
31static TCGv cpu_pc;
32static TCGv cpu_regs[TILEGX_R_COUNT];
33
34static const char * const reg_names[64] = {
35 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
36 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
37 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
38 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
39 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
40 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
41 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
42 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
43};
44
45/* Modified registers are cached in temporaries until the end of the bundle. */
46typedef struct {
47 unsigned reg;
48 TCGv val;
49} DisasContextTemp;
50
51#define MAX_WRITEBACK 4
52
53/* This is the state at translation time. */
54typedef struct {
55 uint64_t pc; /* Current pc */
56
57 TCGv zero; /* For zero register */
58
59 DisasContextTemp wb[MAX_WRITEBACK];
60 int num_wb;
61 int mmuidx;
62 bool exit_tb;
63
64 struct {
65 TCGCond cond; /* branch condition */
66 TCGv dest; /* branch destination */
67 TCGv val1; /* value to be compared against zero, for cond */
68 } jmp; /* Jump object, only once in each TB block */
69} DisasContext;
70
71#include "exec/gen-icount.h"
72
73/* Differentiate the various pipe encodings. */
74#define TY_X0 0
75#define TY_X1 1
76#define TY_Y0 2
77#define TY_Y1 3
78
79/* Remerge the base opcode and extension fields for switching.
80 The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
81 Y2 opcode field is 2 bits. */
82#define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
83
84/* Similar, but for Y2 only. */
85#define OEY2(OP, MODE) (OP + MODE * 4)
86
87/* Similar, but make sure opcode names match up. */
88#define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
89#define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
90#define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
91#define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
92#define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
93#define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
94#define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
95
96
97static void gen_exception(DisasContext *dc, TileExcp num)
98{
99 TCGv_i32 tmp;
100
101 tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
102
103 tmp = tcg_const_i32(num);
104 gen_helper_exception(cpu_env, tmp);
105 tcg_temp_free_i32(tmp);
106 dc->exit_tb = true;
107}
108
a9fdfc7e
RH		 109static bool check_gr(DisasContext *dc, uint8_t reg)
110{
111 if (likely(reg < TILEGX_R_COUNT)) {
112 return true;
113 }
114
115 switch (reg) {
116 case TILEGX_R_SN:
117 case TILEGX_R_ZERO:
118 break;
119 case TILEGX_R_IDN0:
120 case TILEGX_R_IDN1:
121 gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
122 break;
123 case TILEGX_R_UDN0:
124 case TILEGX_R_UDN1:
125 case TILEGX_R_UDN2:
126 case TILEGX_R_UDN3:
127 gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
128 break;
129 default:
130 g_assert_not_reached();
131 }
132 return false;
133}
134
135static TCGv load_zero(DisasContext *dc)
136{
137 if (TCGV_IS_UNUSED_I64(dc->zero)) {
138 dc->zero = tcg_const_i64(0);
139 }
140 return dc->zero;
141}
142
143static TCGv load_gr(DisasContext *dc, unsigned reg)
144{
145 if (check_gr(dc, reg)) {
146 return cpu_regs[reg];
147 }
148 return load_zero(dc);
149}
150
151static TCGv dest_gr(DisasContext *dc, unsigned reg)
152{
153 int n;
154
155 /* Skip the result, mark the exception if necessary, and continue */
156 check_gr(dc, reg);
157
158 n = dc->num_wb++;
159 dc->wb[n].reg = reg;
160 return dc->wb[n].val = tcg_temp_new_i64();
161}
162
89b8c750
RH		 163static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
164 void (*operate)(TCGv, TCGv, TCGv))
165{
166 TCGv t0 = tcg_temp_new();
167
168 tcg_gen_ext32s_tl(tdest, tsrca);
169 tcg_gen_ext32s_tl(t0, tsrcb);
170 operate(tdest, tdest, t0);
171
172 tcg_gen_movi_tl(t0, 0x7fffffff);
173 tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest);
174 tcg_gen_movi_tl(t0, -0x80000000LL);
175 tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest);
176
177 tcg_temp_free(t0);
178}
179
7f41a8d6
RH		 180/* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
181 specified by the bottom 3 bits of TSRCB, and set TDEST to the
182 low 64 bits of the resulting value. */
183static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
184{
185 TCGv t0 = tcg_temp_new();
186
187 tcg_gen_andi_tl(t0, tsrcb, 7);
188 tcg_gen_shli_tl(t0, t0, 3);
189 tcg_gen_shr_tl(tdest, tsrcd, t0);
190
191 /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
192 arithmetic on a 6-bit field tells us that 64 - t0 is equal
193 to (t0 ^ 63) + 1. So we can do the shift in two parts,
194 neither of which will be an invalid shift by 64. */
195 tcg_gen_xori_tl(t0, t0, 63);
196 tcg_gen_shl_tl(t0, tsrca, t0);
197 tcg_gen_shli_tl(t0, t0, 1);
198 tcg_gen_or_tl(tdest, tdest, t0);
199
200 tcg_temp_free(t0);
201}
202
203/* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
204 right shift is an immediate. */
205static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
206{
207 TCGv t0 = tcg_temp_new();
208
209 tcg_gen_shri_tl(t0, tsrcb, shr);
210 tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
211 tcg_gen_or_tl(tdest, tdest, t0);
212
213 tcg_temp_free(t0);
214}
215
216
8fd29dd7
RH		 217static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
218 unsigned dest, unsigned srca)
219{
a9fdfc7e 220 TCGv tdest, tsrca;
8fd29dd7
RH		 221 const char *mnemonic;
222
223 /* Eliminate nops before doing anything else. */
224 switch (opext) {
225 case OE_RR_Y0(NOP):
226 case OE_RR_Y1(NOP):
227 case OE_RR_X0(NOP):
228 case OE_RR_X1(NOP):
229 mnemonic = "nop";
230 goto do_nop;
231 case OE_RR_Y0(FNOP):
232 case OE_RR_Y1(FNOP):
233 case OE_RR_X0(FNOP):
234 case OE_RR_X1(FNOP):
235 mnemonic = "fnop";
236 do_nop:
237 if (srca || dest) {
238 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
239 }
240 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
241 return TILEGX_EXCP_NONE;
242 }
243
a9fdfc7e
RH		 244 tdest = dest_gr(dc, dest);
245 tsrca = load_gr(dc, srca);
246
8fd29dd7
RH		 247 switch (opext) {
248 case OE_RR_X0(CNTLZ):
249 case OE_RR_Y0(CNTLZ):
7f41a8d6
RH		 250 gen_helper_cntlz(tdest, tsrca);
251 mnemonic = "cntlz";
252 break;
8fd29dd7
RH		 253 case OE_RR_X0(CNTTZ):
254 case OE_RR_Y0(CNTTZ):
7f41a8d6
RH		 255 gen_helper_cnttz(tdest, tsrca);
256 mnemonic = "cnttz";
257 break;
8fd29dd7
RH		 258 case OE_RR_X1(DRAIN):
259 case OE_RR_X1(DTLBPR):
260 case OE_RR_X1(FINV):
261 case OE_RR_X1(FLUSHWB):
262 case OE_RR_X1(FLUSH):
263 case OE_RR_X0(FSINGLE_PACK1):
264 case OE_RR_Y0(FSINGLE_PACK1):
265 case OE_RR_X1(ICOH):
266 case OE_RR_X1(ILL):
267 case OE_RR_Y1(ILL):
268 case OE_RR_X1(INV):
269 case OE_RR_X1(IRET):
270 case OE_RR_X1(JALRP):
271 case OE_RR_Y1(JALRP):
272 case OE_RR_X1(JALR):
273 case OE_RR_Y1(JALR):
274 case OE_RR_X1(JRP):
275 case OE_RR_Y1(JRP):
276 case OE_RR_X1(JR):
277 case OE_RR_Y1(JR):
278 case OE_RR_X1(LD1S):
279 case OE_RR_X1(LD1U):
280 case OE_RR_X1(LD2S):
281 case OE_RR_X1(LD2U):
282 case OE_RR_X1(LD4S):
283 case OE_RR_X1(LD4U):
284 case OE_RR_X1(LDNA):
285 case OE_RR_X1(LDNT1S):
286 case OE_RR_X1(LDNT1U):
287 case OE_RR_X1(LDNT2S):
288 case OE_RR_X1(LDNT2U):
289 case OE_RR_X1(LDNT4S):
290 case OE_RR_X1(LDNT4U):
291 case OE_RR_X1(LDNT):
292 case OE_RR_X1(LD):
293 case OE_RR_X1(LNK):
294 case OE_RR_Y1(LNK):
295 case OE_RR_X1(MF):
296 case OE_RR_X1(NAP):
7f41a8d6 297 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 298 case OE_RR_X0(PCNT):
299 case OE_RR_Y0(PCNT):
7f41a8d6
RH		 300 gen_helper_pcnt(tdest, tsrca);
301 mnemonic = "pcnt";
302 break;
8fd29dd7
RH		 303 case OE_RR_X0(REVBITS):
304 case OE_RR_Y0(REVBITS):
7f41a8d6
RH		 305 gen_helper_revbits(tdest, tsrca);
306 mnemonic = "revbits";
307 break;
8fd29dd7
RH		 308 case OE_RR_X0(REVBYTES):
309 case OE_RR_Y0(REVBYTES):
a9fdfc7e
RH		 310 tcg_gen_bswap64_tl(tdest, tsrca);
311 mnemonic = "revbytes";
312 break;
8fd29dd7
RH		 313 case OE_RR_X1(SWINT0):
314 case OE_RR_X1(SWINT1):
315 case OE_RR_X1(SWINT2):
316 case OE_RR_X1(SWINT3):
317 case OE_RR_X0(TBLIDXB0):
318 case OE_RR_Y0(TBLIDXB0):
319 case OE_RR_X0(TBLIDXB1):
320 case OE_RR_Y0(TBLIDXB1):
321 case OE_RR_X0(TBLIDXB2):
322 case OE_RR_Y0(TBLIDXB2):
323 case OE_RR_X0(TBLIDXB3):
324 case OE_RR_Y0(TBLIDXB3):
325 case OE_RR_X1(WH64):
326 default:
327 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
328 }
329
330 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
331 reg_names[dest], reg_names[srca]);
332 return TILEGX_EXCP_NONE;
333}
334
335static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
336 unsigned dest, unsigned srca, unsigned srcb)
337{
a9fdfc7e
RH		 338 TCGv tdest = dest_gr(dc, dest);
339 TCGv tsrca = load_gr(dc, srca);
340 TCGv tsrcb = load_gr(dc, srcb);
8fd29dd7
RH		 341 const char *mnemonic;
342
343 switch (opext) {
344 case OE_RRR(ADDXSC, 0, X0):
345 case OE_RRR(ADDXSC, 0, X1):
89b8c750
RH		 346 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
347 mnemonic = "addxsc";
348 break;
8fd29dd7
RH		 349 case OE_RRR(ADDX, 0, X0):
350 case OE_RRR(ADDX, 0, X1):
351 case OE_RRR(ADDX, 0, Y0):
352 case OE_RRR(ADDX, 0, Y1):
89b8c750
RH		 353 tcg_gen_add_tl(tdest, tsrca, tsrcb);
354 tcg_gen_ext32s_tl(tdest, tdest);
355 mnemonic = "addx";
356 break;
8fd29dd7
RH		 357 case OE_RRR(ADD, 0, X0):
358 case OE_RRR(ADD, 0, X1):
359 case OE_RRR(ADD, 0, Y0):
360 case OE_RRR(ADD, 0, Y1):
89b8c750
RH		 361 tcg_gen_add_tl(tdest, tsrca, tsrcb);
362 mnemonic = "add";
363 break;
8fd29dd7
RH		 364 case OE_RRR(AND, 0, X0):
365 case OE_RRR(AND, 0, X1):
366 case OE_RRR(AND, 5, Y0):
367 case OE_RRR(AND, 5, Y1):
a9fdfc7e
RH		 368 tcg_gen_and_tl(tdest, tsrca, tsrcb);
369 mnemonic = "and";
370 break;
8fd29dd7
RH		 371 case OE_RRR(CMOVEQZ, 0, X0):
372 case OE_RRR(CMOVEQZ, 4, Y0):
373 case OE_RRR(CMOVNEZ, 0, X0):
374 case OE_RRR(CMOVNEZ, 4, Y0):
375 case OE_RRR(CMPEQ, 0, X0):
376 case OE_RRR(CMPEQ, 0, X1):
377 case OE_RRR(CMPEQ, 3, Y0):
378 case OE_RRR(CMPEQ, 3, Y1):
379 case OE_RRR(CMPEXCH4, 0, X1):
380 case OE_RRR(CMPEXCH, 0, X1):
381 case OE_RRR(CMPLES, 0, X0):
382 case OE_RRR(CMPLES, 0, X1):
383 case OE_RRR(CMPLES, 2, Y0):
384 case OE_RRR(CMPLES, 2, Y1):
385 case OE_RRR(CMPLEU, 0, X0):
386 case OE_RRR(CMPLEU, 0, X1):
387 case OE_RRR(CMPLEU, 2, Y0):
388 case OE_RRR(CMPLEU, 2, Y1):
389 case OE_RRR(CMPLTS, 0, X0):
390 case OE_RRR(CMPLTS, 0, X1):
391 case OE_RRR(CMPLTS, 2, Y0):
392 case OE_RRR(CMPLTS, 2, Y1):
393 case OE_RRR(CMPLTU, 0, X0):
394 case OE_RRR(CMPLTU, 0, X1):
395 case OE_RRR(CMPLTU, 2, Y0):
396 case OE_RRR(CMPLTU, 2, Y1):
397 case OE_RRR(CMPNE, 0, X0):
398 case OE_RRR(CMPNE, 0, X1):
399 case OE_RRR(CMPNE, 3, Y0):
400 case OE_RRR(CMPNE, 3, Y1):
401 case OE_RRR(CMULAF, 0, X0):
402 case OE_RRR(CMULA, 0, X0):
403 case OE_RRR(CMULFR, 0, X0):
404 case OE_RRR(CMULF, 0, X0):
405 case OE_RRR(CMULHR, 0, X0):
406 case OE_RRR(CMULH, 0, X0):
407 case OE_RRR(CMUL, 0, X0):
408 case OE_RRR(CRC32_32, 0, X0):
409 case OE_RRR(CRC32_8, 0, X0):
7f41a8d6 410 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 411 case OE_RRR(DBLALIGN2, 0, X0):
412 case OE_RRR(DBLALIGN2, 0, X1):
7f41a8d6
RH		 413 gen_dblaligni(tdest, tsrca, tsrcb, 16);
414 mnemonic = "dblalign2";
415 break;
8fd29dd7
RH		 416 case OE_RRR(DBLALIGN4, 0, X0):
417 case OE_RRR(DBLALIGN4, 0, X1):
7f41a8d6
RH		 418 gen_dblaligni(tdest, tsrca, tsrcb, 32);
419 mnemonic = "dblalign4";
420 break;
8fd29dd7
RH		 421 case OE_RRR(DBLALIGN6, 0, X0):
422 case OE_RRR(DBLALIGN6, 0, X1):
7f41a8d6
RH		 423 gen_dblaligni(tdest, tsrca, tsrcb, 48);
424 mnemonic = "dblalign6";
425 break;
8fd29dd7 426 case OE_RRR(DBLALIGN, 0, X0):
7f41a8d6
RH		 427 gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb);
428 mnemonic = "dblalign";
429 break;
8fd29dd7
RH		 430 case OE_RRR(EXCH4, 0, X1):
431 case OE_RRR(EXCH, 0, X1):
432 case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
433 case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
434 case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
435 case OE_RRR(FDOUBLE_PACK1, 0, X0):
436 case OE_RRR(FDOUBLE_PACK2, 0, X0):
437 case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
438 case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
439 case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
440 case OE_RRR(FETCHADD4, 0, X1):
441 case OE_RRR(FETCHADDGEZ4, 0, X1):
442 case OE_RRR(FETCHADDGEZ, 0, X1):
443 case OE_RRR(FETCHADD, 0, X1):
444 case OE_RRR(FETCHAND4, 0, X1):
445 case OE_RRR(FETCHAND, 0, X1):
446 case OE_RRR(FETCHOR4, 0, X1):
447 case OE_RRR(FETCHOR, 0, X1):
448 case OE_RRR(FSINGLE_ADD1, 0, X0):
449 case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
450 case OE_RRR(FSINGLE_MUL1, 0, X0):
451 case OE_RRR(FSINGLE_MUL2, 0, X0):
452 case OE_RRR(FSINGLE_PACK2, 0, X0):
453 case OE_RRR(FSINGLE_SUB1, 0, X0):
454 case OE_RRR(MNZ, 0, X0):
455 case OE_RRR(MNZ, 0, X1):
456 case OE_RRR(MNZ, 4, Y0):
457 case OE_RRR(MNZ, 4, Y1):
458 case OE_RRR(MULAX, 0, X0):
459 case OE_RRR(MULAX, 3, Y0):
460 case OE_RRR(MULA_HS_HS, 0, X0):
461 case OE_RRR(MULA_HS_HS, 9, Y0):
462 case OE_RRR(MULA_HS_HU, 0, X0):
463 case OE_RRR(MULA_HS_LS, 0, X0):
464 case OE_RRR(MULA_HS_LU, 0, X0):
465 case OE_RRR(MULA_HU_HU, 0, X0):
466 case OE_RRR(MULA_HU_HU, 9, Y0):
467 case OE_RRR(MULA_HU_LS, 0, X0):
468 case OE_RRR(MULA_HU_LU, 0, X0):
469 case OE_RRR(MULA_LS_LS, 0, X0):
470 case OE_RRR(MULA_LS_LS, 9, Y0):
471 case OE_RRR(MULA_LS_LU, 0, X0):
472 case OE_RRR(MULA_LU_LU, 0, X0):
473 case OE_RRR(MULA_LU_LU, 9, Y0):
474 case OE_RRR(MULX, 0, X0):
475 case OE_RRR(MULX, 3, Y0):
476 case OE_RRR(MUL_HS_HS, 0, X0):
477 case OE_RRR(MUL_HS_HS, 8, Y0):
478 case OE_RRR(MUL_HS_HU, 0, X0):
479 case OE_RRR(MUL_HS_LS, 0, X0):
480 case OE_RRR(MUL_HS_LU, 0, X0):
481 case OE_RRR(MUL_HU_HU, 0, X0):
482 case OE_RRR(MUL_HU_HU, 8, Y0):
483 case OE_RRR(MUL_HU_LS, 0, X0):
484 case OE_RRR(MUL_HU_LU, 0, X0):
485 case OE_RRR(MUL_LS_LS, 0, X0):
486 case OE_RRR(MUL_LS_LS, 8, Y0):
487 case OE_RRR(MUL_LS_LU, 0, X0):
488 case OE_RRR(MUL_LU_LU, 0, X0):
489 case OE_RRR(MUL_LU_LU, 8, Y0):
490 case OE_RRR(MZ, 0, X0):
491 case OE_RRR(MZ, 0, X1):
492 case OE_RRR(MZ, 4, Y0):
493 case OE_RRR(MZ, 4, Y1):
a9fdfc7e 494 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 495 case OE_RRR(NOR, 0, X0):
496 case OE_RRR(NOR, 0, X1):
497 case OE_RRR(NOR, 5, Y0):
498 case OE_RRR(NOR, 5, Y1):
a9fdfc7e
RH		 499 tcg_gen_nor_tl(tdest, tsrca, tsrcb);
500 mnemonic = "nor";
501 break;
8fd29dd7
RH		 502 case OE_RRR(OR, 0, X0):
503 case OE_RRR(OR, 0, X1):
504 case OE_RRR(OR, 5, Y0):
505 case OE_RRR(OR, 5, Y1):
a9fdfc7e
RH		 506 tcg_gen_or_tl(tdest, tsrca, tsrcb);
507 mnemonic = "or";
508 break;
8fd29dd7
RH		 509 case OE_RRR(ROTL, 0, X0):
510 case OE_RRR(ROTL, 0, X1):
511 case OE_RRR(ROTL, 6, Y0):
512 case OE_RRR(ROTL, 6, Y1):
89b8c750 513 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 514 case OE_RRR(SHL1ADDX, 0, X0):
515 case OE_RRR(SHL1ADDX, 0, X1):
516 case OE_RRR(SHL1ADDX, 7, Y0):
517 case OE_RRR(SHL1ADDX, 7, Y1):
89b8c750
RH		 518 tcg_gen_shli_tl(tdest, tsrca, 1);
519 tcg_gen_add_tl(tdest, tdest, tsrcb);
520 tcg_gen_ext32s_tl(tdest, tdest);
521 mnemonic = "shl1addx";
522 break;
8fd29dd7
RH		 523 case OE_RRR(SHL1ADD, 0, X0):
524 case OE_RRR(SHL1ADD, 0, X1):
525 case OE_RRR(SHL1ADD, 1, Y0):
526 case OE_RRR(SHL1ADD, 1, Y1):
89b8c750
RH		 527 tcg_gen_shli_tl(tdest, tsrca, 1);
528 tcg_gen_add_tl(tdest, tdest, tsrcb);
529 mnemonic = "shl1add";
530 break;
8fd29dd7
RH		 531 case OE_RRR(SHL2ADDX, 0, X0):
532 case OE_RRR(SHL2ADDX, 0, X1):
533 case OE_RRR(SHL2ADDX, 7, Y0):
534 case OE_RRR(SHL2ADDX, 7, Y1):
89b8c750
RH		 535 tcg_gen_shli_tl(tdest, tsrca, 2);
536 tcg_gen_add_tl(tdest, tdest, tsrcb);
537 tcg_gen_ext32s_tl(tdest, tdest);
538 mnemonic = "shl2addx";
539 break;
8fd29dd7
RH		 540 case OE_RRR(SHL2ADD, 0, X0):
541 case OE_RRR(SHL2ADD, 0, X1):
542 case OE_RRR(SHL2ADD, 1, Y0):
543 case OE_RRR(SHL2ADD, 1, Y1):
89b8c750
RH		 544 tcg_gen_shli_tl(tdest, tsrca, 2);
545 tcg_gen_add_tl(tdest, tdest, tsrcb);
546 mnemonic = "shl2add";
547 break;
8fd29dd7
RH		 548 case OE_RRR(SHL3ADDX, 0, X0):
549 case OE_RRR(SHL3ADDX, 0, X1):
550 case OE_RRR(SHL3ADDX, 7, Y0):
551 case OE_RRR(SHL3ADDX, 7, Y1):
89b8c750
RH		 552 tcg_gen_shli_tl(tdest, tsrca, 3);
553 tcg_gen_add_tl(tdest, tdest, tsrcb);
554 tcg_gen_ext32s_tl(tdest, tdest);
555 mnemonic = "shl3addx";
556 break;
8fd29dd7
RH		 557 case OE_RRR(SHL3ADD, 0, X0):
558 case OE_RRR(SHL3ADD, 0, X1):
559 case OE_RRR(SHL3ADD, 1, Y0):
560 case OE_RRR(SHL3ADD, 1, Y1):
89b8c750
RH		 561 tcg_gen_shli_tl(tdest, tsrca, 3);
562 tcg_gen_add_tl(tdest, tdest, tsrcb);
563 mnemonic = "shl3add";
564 break;
8fd29dd7
RH		 565 case OE_RRR(SHLX, 0, X0):
566 case OE_RRR(SHLX, 0, X1):
567 case OE_RRR(SHL, 0, X0):
568 case OE_RRR(SHL, 0, X1):
569 case OE_RRR(SHL, 6, Y0):
570 case OE_RRR(SHL, 6, Y1):
571 case OE_RRR(SHRS, 0, X0):
572 case OE_RRR(SHRS, 0, X1):
573 case OE_RRR(SHRS, 6, Y0):
574 case OE_RRR(SHRS, 6, Y1):
575 case OE_RRR(SHRUX, 0, X0):
576 case OE_RRR(SHRUX, 0, X1):
577 case OE_RRR(SHRU, 0, X0):
578 case OE_RRR(SHRU, 0, X1):
579 case OE_RRR(SHRU, 6, Y0):
580 case OE_RRR(SHRU, 6, Y1):
7f41a8d6 581 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7 582 case OE_RRR(SHUFFLEBYTES, 0, X0):
7f41a8d6
RH		 583 gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
584 mnemonic = "shufflebytes";
585 break;
8fd29dd7
RH		 586 case OE_RRR(ST1, 0, X1):
587 case OE_RRR(ST2, 0, X1):
588 case OE_RRR(ST4, 0, X1):
589 case OE_RRR(STNT1, 0, X1):
590 case OE_RRR(STNT2, 0, X1):
591 case OE_RRR(STNT4, 0, X1):
592 case OE_RRR(STNT, 0, X1):
593 case OE_RRR(ST, 0, X1):
89b8c750 594 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 595 case OE_RRR(SUBXSC, 0, X0):
596 case OE_RRR(SUBXSC, 0, X1):
89b8c750
RH		 597 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
598 mnemonic = "subxsc";
599 break;
8fd29dd7
RH		 600 case OE_RRR(SUBX, 0, X0):
601 case OE_RRR(SUBX, 0, X1):
602 case OE_RRR(SUBX, 0, Y0):
603 case OE_RRR(SUBX, 0, Y1):
89b8c750
RH		 604 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
605 tcg_gen_ext32s_tl(tdest, tdest);
606 mnemonic = "subx";
607 break;
8fd29dd7
RH		 608 case OE_RRR(SUB, 0, X0):
609 case OE_RRR(SUB, 0, X1):
610 case OE_RRR(SUB, 0, Y0):
611 case OE_RRR(SUB, 0, Y1):
89b8c750
RH		 612 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
613 mnemonic = "sub";
614 break;
8fd29dd7
RH		 615 case OE_RRR(V1ADDUC, 0, X0):
616 case OE_RRR(V1ADDUC, 0, X1):
617 case OE_RRR(V1ADD, 0, X0):
618 case OE_RRR(V1ADD, 0, X1):
619 case OE_RRR(V1ADIFFU, 0, X0):
620 case OE_RRR(V1AVGU, 0, X0):
621 case OE_RRR(V1CMPEQ, 0, X0):
622 case OE_RRR(V1CMPEQ, 0, X1):
623 case OE_RRR(V1CMPLES, 0, X0):
624 case OE_RRR(V1CMPLES, 0, X1):
625 case OE_RRR(V1CMPLEU, 0, X0):
626 case OE_RRR(V1CMPLEU, 0, X1):
627 case OE_RRR(V1CMPLTS, 0, X0):
628 case OE_RRR(V1CMPLTS, 0, X1):
629 case OE_RRR(V1CMPLTU, 0, X0):
630 case OE_RRR(V1CMPLTU, 0, X1):
631 case OE_RRR(V1CMPNE, 0, X0):
632 case OE_RRR(V1CMPNE, 0, X1):
633 case OE_RRR(V1DDOTPUA, 0, X0):
634 case OE_RRR(V1DDOTPUSA, 0, X0):
635 case OE_RRR(V1DDOTPUS, 0, X0):
636 case OE_RRR(V1DDOTPU, 0, X0):
637 case OE_RRR(V1DOTPA, 0, X0):
638 case OE_RRR(V1DOTPUA, 0, X0):
639 case OE_RRR(V1DOTPUSA, 0, X0):
640 case OE_RRR(V1DOTPUS, 0, X0):
641 case OE_RRR(V1DOTPU, 0, X0):
642 case OE_RRR(V1DOTP, 0, X0):
643 case OE_RRR(V1INT_H, 0, X0):
644 case OE_RRR(V1INT_H, 0, X1):
645 case OE_RRR(V1INT_L, 0, X0):
646 case OE_RRR(V1INT_L, 0, X1):
647 case OE_RRR(V1MAXU, 0, X0):
648 case OE_RRR(V1MAXU, 0, X1):
649 case OE_RRR(V1MINU, 0, X0):
650 case OE_RRR(V1MINU, 0, X1):
651 case OE_RRR(V1MNZ, 0, X0):
652 case OE_RRR(V1MNZ, 0, X1):
653 case OE_RRR(V1MULTU, 0, X0):
654 case OE_RRR(V1MULUS, 0, X0):
655 case OE_RRR(V1MULU, 0, X0):
656 case OE_RRR(V1MZ, 0, X0):
657 case OE_RRR(V1MZ, 0, X1):
658 case OE_RRR(V1SADAU, 0, X0):
659 case OE_RRR(V1SADU, 0, X0):
660 case OE_RRR(V1SHL, 0, X0):
661 case OE_RRR(V1SHL, 0, X1):
662 case OE_RRR(V1SHRS, 0, X0):
663 case OE_RRR(V1SHRS, 0, X1):
664 case OE_RRR(V1SHRU, 0, X0):
665 case OE_RRR(V1SHRU, 0, X1):
666 case OE_RRR(V1SUBUC, 0, X0):
667 case OE_RRR(V1SUBUC, 0, X1):
668 case OE_RRR(V1SUB, 0, X0):
669 case OE_RRR(V1SUB, 0, X1):
670 case OE_RRR(V2ADDSC, 0, X0):
671 case OE_RRR(V2ADDSC, 0, X1):
672 case OE_RRR(V2ADD, 0, X0):
673 case OE_RRR(V2ADD, 0, X1):
674 case OE_RRR(V2ADIFFS, 0, X0):
675 case OE_RRR(V2AVGS, 0, X0):
676 case OE_RRR(V2CMPEQ, 0, X0):
677 case OE_RRR(V2CMPEQ, 0, X1):
678 case OE_RRR(V2CMPLES, 0, X0):
679 case OE_RRR(V2CMPLES, 0, X1):
680 case OE_RRR(V2CMPLEU, 0, X0):
681 case OE_RRR(V2CMPLEU, 0, X1):
682 case OE_RRR(V2CMPLTS, 0, X0):
683 case OE_RRR(V2CMPLTS, 0, X1):
684 case OE_RRR(V2CMPLTU, 0, X0):
685 case OE_RRR(V2CMPLTU, 0, X1):
686 case OE_RRR(V2CMPNE, 0, X0):
687 case OE_RRR(V2CMPNE, 0, X1):
688 case OE_RRR(V2DOTPA, 0, X0):
689 case OE_RRR(V2DOTP, 0, X0):
690 case OE_RRR(V2INT_H, 0, X0):
691 case OE_RRR(V2INT_H, 0, X1):
692 case OE_RRR(V2INT_L, 0, X0):
693 case OE_RRR(V2INT_L, 0, X1):
694 case OE_RRR(V2MAXS, 0, X0):
695 case OE_RRR(V2MAXS, 0, X1):
696 case OE_RRR(V2MINS, 0, X0):
697 case OE_RRR(V2MINS, 0, X1):
698 case OE_RRR(V2MNZ, 0, X0):
699 case OE_RRR(V2MNZ, 0, X1):
700 case OE_RRR(V2MULFSC, 0, X0):
701 case OE_RRR(V2MULS, 0, X0):
702 case OE_RRR(V2MULTS, 0, X0):
703 case OE_RRR(V2MZ, 0, X0):
704 case OE_RRR(V2MZ, 0, X1):
705 case OE_RRR(V2PACKH, 0, X0):
706 case OE_RRR(V2PACKH, 0, X1):
707 case OE_RRR(V2PACKL, 0, X0):
708 case OE_RRR(V2PACKL, 0, X1):
709 case OE_RRR(V2PACKUC, 0, X0):
710 case OE_RRR(V2PACKUC, 0, X1):
711 case OE_RRR(V2SADAS, 0, X0):
712 case OE_RRR(V2SADAU, 0, X0):
713 case OE_RRR(V2SADS, 0, X0):
714 case OE_RRR(V2SADU, 0, X0):
715 case OE_RRR(V2SHLSC, 0, X0):
716 case OE_RRR(V2SHLSC, 0, X1):
717 case OE_RRR(V2SHL, 0, X0):
718 case OE_RRR(V2SHL, 0, X1):
719 case OE_RRR(V2SHRS, 0, X0):
720 case OE_RRR(V2SHRS, 0, X1):
721 case OE_RRR(V2SHRU, 0, X0):
722 case OE_RRR(V2SHRU, 0, X1):
723 case OE_RRR(V2SUBSC, 0, X0):
724 case OE_RRR(V2SUBSC, 0, X1):
725 case OE_RRR(V2SUB, 0, X0):
726 case OE_RRR(V2SUB, 0, X1):
727 case OE_RRR(V4ADDSC, 0, X0):
728 case OE_RRR(V4ADDSC, 0, X1):
729 case OE_RRR(V4ADD, 0, X0):
730 case OE_RRR(V4ADD, 0, X1):
731 case OE_RRR(V4INT_H, 0, X0):
732 case OE_RRR(V4INT_H, 0, X1):
733 case OE_RRR(V4INT_L, 0, X0):
734 case OE_RRR(V4INT_L, 0, X1):
735 case OE_RRR(V4PACKSC, 0, X0):
736 case OE_RRR(V4PACKSC, 0, X1):
737 case OE_RRR(V4SHLSC, 0, X0):
738 case OE_RRR(V4SHLSC, 0, X1):
739 case OE_RRR(V4SHL, 0, X0):
740 case OE_RRR(V4SHL, 0, X1):
741 case OE_RRR(V4SHRS, 0, X0):
742 case OE_RRR(V4SHRS, 0, X1):
743 case OE_RRR(V4SHRU, 0, X0):
744 case OE_RRR(V4SHRU, 0, X1):
745 case OE_RRR(V4SUBSC, 0, X0):
746 case OE_RRR(V4SUBSC, 0, X1):
747 case OE_RRR(V4SUB, 0, X0):
748 case OE_RRR(V4SUB, 0, X1):
a9fdfc7e 749 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 750 case OE_RRR(XOR, 0, X0):
751 case OE_RRR(XOR, 0, X1):
752 case OE_RRR(XOR, 5, Y0):
753 case OE_RRR(XOR, 5, Y1):
a9fdfc7e
RH		 754 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
755 mnemonic = "xor";
756 break;
8fd29dd7
RH		 757 default:
758 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
759 }
760
761 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
762 reg_names[dest], reg_names[srca], reg_names[srcb]);
763 return TILEGX_EXCP_NONE;
764}
765
766static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
767 unsigned dest, unsigned srca, int imm)
768{
a9fdfc7e
RH		 769 TCGv tdest = dest_gr(dc, dest);
770 TCGv tsrca = load_gr(dc, srca);
8fd29dd7
RH		 771 const char *mnemonic;
772
773 switch (opext) {
89b8c750
RH		 774 case OE(ADDI_OPCODE_Y0, 0, Y0):
775 case OE(ADDI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 776 case OE_IM(ADDI, X0):
777 case OE_IM(ADDI, X1):
89b8c750
RH		 778 tcg_gen_addi_tl(tdest, tsrca, imm);
779 mnemonic = "addi";
780 break;
781 case OE(ADDXI_OPCODE_Y0, 0, Y0):
782 case OE(ADDXI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 783 case OE_IM(ADDXI, X0):
784 case OE_IM(ADDXI, X1):
89b8c750
RH		 785 tcg_gen_addi_tl(tdest, tsrca, imm);
786 tcg_gen_ext32s_tl(tdest, tdest);
787 mnemonic = "addxi";
788 break;
a9fdfc7e
RH		 789 case OE(ANDI_OPCODE_Y0, 0, Y0):
790 case OE(ANDI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 791 case OE_IM(ANDI, X0):
792 case OE_IM(ANDI, X1):
a9fdfc7e
RH		 793 tcg_gen_andi_tl(tdest, tsrca, imm);
794 mnemonic = "andi";
795 break;
8fd29dd7
RH		 796 case OE_IM(CMPEQI, X0):
797 case OE_IM(CMPEQI, X1):
798 case OE_IM(CMPLTSI, X0):
799 case OE_IM(CMPLTSI, X1):
800 case OE_IM(CMPLTUI, X0):
801 case OE_IM(CMPLTUI, X1):
802 case OE_IM(LD1S_ADD, X1):
803 case OE_IM(LD1U_ADD, X1):
804 case OE_IM(LD2S_ADD, X1):
805 case OE_IM(LD2U_ADD, X1):
806 case OE_IM(LD4S_ADD, X1):
807 case OE_IM(LD4U_ADD, X1):
808 case OE_IM(LDNT1S_ADD, X1):
809 case OE_IM(LDNT1U_ADD, X1):
810 case OE_IM(LDNT2S_ADD, X1):
811 case OE_IM(LDNT2U_ADD, X1):
812 case OE_IM(LDNT4S_ADD, X1):
813 case OE_IM(LDNT4U_ADD, X1):
814 case OE_IM(LDNT_ADD, X1):
815 case OE_IM(LD_ADD, X1):
816 case OE_IM(LDNA_ADD, X1):
817 case OE_IM(MFSPR, X1):
818 case OE_IM(MTSPR, X1):
a9fdfc7e 819 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 820 case OE_IM(ORI, X0):
821 case OE_IM(ORI, X1):
a9fdfc7e
RH		 822 tcg_gen_ori_tl(tdest, tsrca, imm);
823 mnemonic = "ori";
824 break;
8fd29dd7
RH		 825 case OE_IM(ST1_ADD, X1):
826 case OE_IM(ST2_ADD, X1):
827 case OE_IM(ST4_ADD, X1):
828 case OE_IM(STNT1_ADD, X1):
829 case OE_IM(STNT2_ADD, X1):
830 case OE_IM(STNT4_ADD, X1):
831 case OE_IM(STNT_ADD, X1):
832 case OE_IM(ST_ADD, X1):
833 case OE_IM(V1ADDI, X0):
834 case OE_IM(V1ADDI, X1):
835 case OE_IM(V1CMPEQI, X0):
836 case OE_IM(V1CMPEQI, X1):
837 case OE_IM(V1CMPLTSI, X0):
838 case OE_IM(V1CMPLTSI, X1):
839 case OE_IM(V1CMPLTUI, X0):
840 case OE_IM(V1CMPLTUI, X1):
841 case OE_IM(V1MAXUI, X0):
842 case OE_IM(V1MAXUI, X1):
843 case OE_IM(V1MINUI, X0):
844 case OE_IM(V1MINUI, X1):
845 case OE_IM(V2ADDI, X0):
846 case OE_IM(V2ADDI, X1):
847 case OE_IM(V2CMPEQI, X0):
848 case OE_IM(V2CMPEQI, X1):
849 case OE_IM(V2CMPLTSI, X0):
850 case OE_IM(V2CMPLTSI, X1):
851 case OE_IM(V2CMPLTUI, X0):
852 case OE_IM(V2CMPLTUI, X1):
853 case OE_IM(V2MAXSI, X0):
854 case OE_IM(V2MAXSI, X1):
855 case OE_IM(V2MINSI, X0):
856 case OE_IM(V2MINSI, X1):
a9fdfc7e 857 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 858 case OE_IM(XORI, X0):
859 case OE_IM(XORI, X1):
a9fdfc7e
RH		 860 tcg_gen_xori_tl(tdest, tsrca, imm);
861 mnemonic = "xori";
862 break;
8fd29dd7
RH		 863
864 case OE_SH(ROTLI, X0):
865 case OE_SH(ROTLI, X1):
866 case OE_SH(ROTLI, Y0):
867 case OE_SH(ROTLI, Y1):
868 case OE_SH(SHLI, X0):
869 case OE_SH(SHLI, X1):
870 case OE_SH(SHLI, Y0):
871 case OE_SH(SHLI, Y1):
872 case OE_SH(SHLXI, X0):
873 case OE_SH(SHLXI, X1):
874 case OE_SH(SHRSI, X0):
875 case OE_SH(SHRSI, X1):
876 case OE_SH(SHRSI, Y0):
877 case OE_SH(SHRSI, Y1):
878 case OE_SH(SHRUI, X0):
879 case OE_SH(SHRUI, X1):
880 case OE_SH(SHRUI, Y0):
881 case OE_SH(SHRUI, Y1):
882 case OE_SH(SHRUXI, X0):
883 case OE_SH(SHRUXI, X1):
884 case OE_SH(V1SHLI, X0):
885 case OE_SH(V1SHLI, X1):
886 case OE_SH(V1SHRSI, X0):
887 case OE_SH(V1SHRSI, X1):
888 case OE_SH(V1SHRUI, X0):
889 case OE_SH(V1SHRUI, X1):
890 case OE_SH(V2SHLI, X0):
891 case OE_SH(V2SHLI, X1):
892 case OE_SH(V2SHRSI, X0):
893 case OE_SH(V2SHRSI, X1):
894 case OE_SH(V2SHRUI, X0):
895 case OE_SH(V2SHRUI, X1):
89b8c750 896 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7 897
8fd29dd7
RH		 898 case OE(ADDLI_OPCODE_X0, 0, X0):
899 case OE(ADDLI_OPCODE_X1, 0, X1):
89b8c750
RH		 900 tcg_gen_addi_tl(tdest, tsrca, imm);
901 mnemonic = "addli";
902 break;
8fd29dd7
RH		 903 case OE(ADDXLI_OPCODE_X0, 0, X0):
904 case OE(ADDXLI_OPCODE_X1, 0, X1):
89b8c750
RH		 905 tcg_gen_addi_tl(tdest, tsrca, imm);
906 tcg_gen_ext32s_tl(tdest, tdest);
907 mnemonic = "addxli";
908 break;
8fd29dd7
RH		 909 case OE(CMPEQI_OPCODE_Y0, 0, Y0):
910 case OE(CMPEQI_OPCODE_Y1, 0, Y1):
911 case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
912 case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
89b8c750 913 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 914 case OE(SHL16INSLI_OPCODE_X0, 0, X0):
915 case OE(SHL16INSLI_OPCODE_X1, 0, X1):
89b8c750
RH		 916 tcg_gen_shli_tl(tdest, tsrca, 16);
917 tcg_gen_ori_tl(tdest, tdest, imm & 0xffff);
918 mnemonic = "shl16insli";
919 break;
8fd29dd7
RH		 920
921 default:
922 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
923 }
924
925 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
926 reg_names[dest], reg_names[srca], imm);
927 return TILEGX_EXCP_NONE;
928}
929
930static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
931 unsigned dest, unsigned srca,
932 unsigned bfs, unsigned bfe)
933{
934 const char *mnemonic;
935
936 switch (ext) {
937 case BFEXTU_BF_OPCODE_X0:
938 case BFEXTS_BF_OPCODE_X0:
939 case BFINS_BF_OPCODE_X0:
940 case MM_BF_OPCODE_X0:
941 default:
942 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
943 }
944
945 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
946 reg_names[dest], reg_names[srca], bfs, bfe);
947 return TILEGX_EXCP_NONE;
948}
949
950static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
951 unsigned srca, int off)
952{
953 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
954 const char *mnemonic;
955
956 switch (ext) {
957 case BEQZT_BRANCH_OPCODE_X1:
958 case BEQZ_BRANCH_OPCODE_X1:
959 case BNEZT_BRANCH_OPCODE_X1:
960 case BNEZ_BRANCH_OPCODE_X1:
961 case BLBC_BRANCH_OPCODE_X1:
962 case BGEZT_BRANCH_OPCODE_X1:
963 case BGEZ_BRANCH_OPCODE_X1:
964 case BGTZT_BRANCH_OPCODE_X1:
965 case BGTZ_BRANCH_OPCODE_X1:
966 case BLBCT_BRANCH_OPCODE_X1:
967 case BLBST_BRANCH_OPCODE_X1:
968 case BLBS_BRANCH_OPCODE_X1:
969 case BLEZT_BRANCH_OPCODE_X1:
970 case BLEZ_BRANCH_OPCODE_X1:
971 case BLTZT_BRANCH_OPCODE_X1:
972 case BLTZ_BRANCH_OPCODE_X1:
973 default:
974 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
975 }
976
977 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
978 qemu_log("%s %s, " TARGET_FMT_lx " <%s>",
979 mnemonic, reg_names[srca], tgt, lookup_symbol(tgt));
980 }
981 return TILEGX_EXCP_NONE;
982}
983
984static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext,
985 int off)
986{
987 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
988 const char *mnemonic;
989
990 switch (ext) {
991 case JAL_JUMP_OPCODE_X1:
992 case J_JUMP_OPCODE_X1:
993 default:
994 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
995 }
996
997 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
998 qemu_log("%s " TARGET_FMT_lx " <%s>",
999 mnemonic, tgt, lookup_symbol(tgt));
1000 }
1001 return TILEGX_EXCP_NONE;
1002}
1003
1004static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
1005{
1006 unsigned opc = get_Opcode_Y0(bundle);
1007 unsigned ext = get_RRROpcodeExtension_Y0(bundle);
1008 unsigned dest = get_Dest_Y0(bundle);
1009 unsigned srca = get_SrcA_Y0(bundle);
1010 unsigned srcb;
1011 int imm;
1012
1013 switch (opc) {
1014 case RRR_1_OPCODE_Y0:
1015 if (ext == UNARY_RRR_1_OPCODE_Y0) {
1016 ext = get_UnaryOpcodeExtension_Y0(bundle);
1017 return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca);
1018 }
1019 /* fallthru */
1020 case RRR_0_OPCODE_Y0:
1021 case RRR_2_OPCODE_Y0:
1022 case RRR_3_OPCODE_Y0:
1023 case RRR_4_OPCODE_Y0:
1024 case RRR_5_OPCODE_Y0:
1025 case RRR_6_OPCODE_Y0:
1026 case RRR_7_OPCODE_Y0:
1027 case RRR_8_OPCODE_Y0:
1028 case RRR_9_OPCODE_Y0:
1029 srcb = get_SrcB_Y0(bundle);
1030 return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb);
1031
1032 case SHIFT_OPCODE_Y0:
1033 ext = get_ShiftOpcodeExtension_Y0(bundle);
1034 imm = get_ShAmt_Y0(bundle);
1035 return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm);
1036
1037 case ADDI_OPCODE_Y0:
1038 case ADDXI_OPCODE_Y0:
1039 case ANDI_OPCODE_Y0:
1040 case CMPEQI_OPCODE_Y0:
1041 case CMPLTSI_OPCODE_Y0:
1042 imm = (int8_t)get_Imm8_Y0(bundle);
1043 return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
1044
1045 default:
1046 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1047 }
1048}
1049
1050static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
1051{
1052 unsigned opc = get_Opcode_Y1(bundle);
1053 unsigned ext = get_RRROpcodeExtension_Y1(bundle);
1054 unsigned dest = get_Dest_Y1(bundle);
1055 unsigned srca = get_SrcA_Y1(bundle);
1056 unsigned srcb;
1057 int imm;
1058
1059 switch (get_Opcode_Y1(bundle)) {
1060 case RRR_1_OPCODE_Y1:
1061 if (ext == UNARY_RRR_1_OPCODE_Y0) {
1062 ext = get_UnaryOpcodeExtension_Y1(bundle);
1063 return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca);
1064 }
1065 /* fallthru */
1066 case RRR_0_OPCODE_Y1:
1067 case RRR_2_OPCODE_Y1:
1068 case RRR_3_OPCODE_Y1:
1069 case RRR_4_OPCODE_Y1:
1070 case RRR_5_OPCODE_Y1:
1071 case RRR_6_OPCODE_Y1:
1072 case RRR_7_OPCODE_Y1:
1073 srcb = get_SrcB_Y1(bundle);
1074 return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb);
1075
1076 case SHIFT_OPCODE_Y1:
1077 ext = get_ShiftOpcodeExtension_Y1(bundle);
1078 imm = get_ShAmt_Y1(bundle);
1079 return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm);
1080
1081 case ADDI_OPCODE_Y1:
1082 case ADDXI_OPCODE_Y1:
1083 case ANDI_OPCODE_Y1:
1084 case CMPEQI_OPCODE_Y1:
1085 case CMPLTSI_OPCODE_Y1:
1086 imm = (int8_t)get_Imm8_Y1(bundle);
1087 return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
1088
1089 default:
1090 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1091 }
1092}
1093
1094static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
1095{
1096 unsigned mode = get_Mode(bundle);
1097 unsigned opc = get_Opcode_Y2(bundle);
1098 unsigned srca = get_SrcA_Y2(bundle);
1099 unsigned srcbdest = get_SrcBDest_Y2(bundle);
1100 const char *mnemonic;
1101
1102 switch (OEY2(opc, mode)) {
1103 case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
1104 case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
1105 case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
1106 case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
1107 case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
1108 case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
1109 case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
1110
1111 case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
1112 case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
1113 case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
1114 case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
1115
1116 default:
1117 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1118 }
1119 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
1120 reg_names[srca], reg_names[srcbdest]);
1121 return TILEGX_EXCP_NONE;
1122}
1123
1124static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
1125{
1126 unsigned opc = get_Opcode_X0(bundle);
1127 unsigned dest = get_Dest_X0(bundle);
1128 unsigned srca = get_SrcA_X0(bundle);
1129 unsigned ext, srcb, bfs, bfe;
1130 int imm;
1131
1132 switch (opc) {
1133 case RRR_0_OPCODE_X0:
1134 ext = get_RRROpcodeExtension_X0(bundle);
1135 if (ext == UNARY_RRR_0_OPCODE_X0) {
1136 ext = get_UnaryOpcodeExtension_X0(bundle);
1137 return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca);
1138 }
1139 srcb = get_SrcB_X0(bundle);
1140 return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
1141
1142 case SHIFT_OPCODE_X0:
1143 ext = get_ShiftOpcodeExtension_X0(bundle);
1144 imm = get_ShAmt_X0(bundle);
1145 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
1146
1147 case IMM8_OPCODE_X0:
1148 ext = get_Imm8OpcodeExtension_X0(bundle);
1149 imm = (int8_t)get_Imm8_X0(bundle);
1150 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
1151
1152 case BF_OPCODE_X0:
1153 ext = get_BFOpcodeExtension_X0(bundle);
1154 bfs = get_BFStart_X0(bundle);
1155 bfe = get_BFEnd_X0(bundle);
1156 return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe);
1157
1158 case ADDLI_OPCODE_X0:
1159 case SHL16INSLI_OPCODE_X0:
1160 case ADDXLI_OPCODE_X0:
1161 imm = (int16_t)get_Imm16_X0(bundle);
1162 return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm);
1163
1164 default:
1165 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1166 }
1167}
1168
1169static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
1170{
1171 unsigned opc = get_Opcode_X1(bundle);
1172 unsigned dest = get_Dest_X1(bundle);
1173 unsigned srca = get_SrcA_X1(bundle);
1174 unsigned ext, srcb;
1175 int imm;
1176
1177 switch (opc) {
1178 case RRR_0_OPCODE_X1:
1179 ext = get_RRROpcodeExtension_X1(bundle);
1180 if (ext == UNARY_RRR_0_OPCODE_X1) {
1181 ext = get_UnaryOpcodeExtension_X1(bundle);
1182 return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca);
1183 }
1184 srcb = get_SrcB_X1(bundle);
1185 return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
1186
1187 case SHIFT_OPCODE_X1:
1188 ext = get_ShiftOpcodeExtension_X1(bundle);
1189 imm = get_ShAmt_X1(bundle);
1190 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
1191
1192 case IMM8_OPCODE_X1:
1193 ext = get_Imm8OpcodeExtension_X1(bundle);
1194 imm = (int8_t)get_Imm8_X1(bundle);
1195 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
1196
1197 case BRANCH_OPCODE_X1:
1198 ext = get_BrType_X1(bundle);
1199 imm = sextract32(get_BrOff_X1(bundle), 0, 17);
1200 return gen_branch_opcode_x1(dc, ext, srca, imm);
1201
1202 case JUMP_OPCODE_X1:
1203 ext = get_JumpOpcodeExtension_X1(bundle);
1204 imm = sextract32(get_JumpOff_X1(bundle), 0, 27);
1205 return gen_jump_opcode_x1(dc, ext, imm);
1206
1207 case ADDLI_OPCODE_X1:
1208 case SHL16INSLI_OPCODE_X1:
1209 case ADDXLI_OPCODE_X1:
1210 imm = (int16_t)get_Imm16_X1(bundle);
1211 return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm);
1212
1213 default:
1214 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1215 }
1216}
1217
1218static void notice_excp(DisasContext *dc, uint64_t bundle,
1219 const char *type, TileExcp excp)
1220{
1221 if (likely(excp == TILEGX_EXCP_NONE)) {
1222 return;
1223 }
1224 gen_exception(dc, excp);
1225 if (excp == TILEGX_EXCP_OPCODE_UNIMPLEMENTED) {
1226 qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
1227 }
1228}
1229
1230static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
1231{
1232 int i;
1233
1234 for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
1235 DisasContextTemp *wb = &dc->wb[i];
1236 wb->reg = TILEGX_R_NOREG;
1237 TCGV_UNUSED_I64(wb->val);
1238 }
1239 dc->num_wb = 0;
1240
1241 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1242 tcg_gen_debug_insn_start(dc->pc);
1243 }
1244
1245 qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
1246 if (get_Mode(bundle)) {
1247 notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
1248 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1249 notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
1250 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1251 notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
1252 } else {
1253 notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
1254 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1255 notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
1256 }
1257 qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n");
1258
1259 for (i = dc->num_wb - 1; i >= 0; --i) {
1260 DisasContextTemp *wb = &dc->wb[i];
1261 if (wb->reg < TILEGX_R_COUNT) {
1262 tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val);
1263 }
1264 tcg_temp_free_i64(wb->val);
1265 }
1266
1267 if (dc->jmp.cond != TCG_COND_NEVER) {
1268 if (dc->jmp.cond == TCG_COND_ALWAYS) {
1269 tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
1270 } else {
1271 TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1272 tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
1273 dc->jmp.val1, load_zero(dc),
1274 dc->jmp.dest, next);
1275 tcg_temp_free_i64(dc->jmp.val1);
1276 tcg_temp_free_i64(next);
1277 }
1278 tcg_temp_free_i64(dc->jmp.dest);
1279 tcg_gen_exit_tb(0);
1280 dc->exit_tb = true;
1281 }
1282}
1283
1284static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
1285 TranslationBlock *tb,
1286 bool search_pc)
1287{
1288 DisasContext ctx;
1289 DisasContext *dc = &ctx;
1290 CPUState *cs = CPU(cpu);
1291 CPUTLGState *env = &cpu->env;
1292 uint64_t pc_start = tb->pc;
1293 uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1294 int j, lj = -1;
1295 int num_insns = 0;
1296 int max_insns = tb->cflags & CF_COUNT_MASK;
1297
1298 dc->pc = pc_start;
1299 dc->mmuidx = 0;
1300 dc->exit_tb = false;
1301 dc->jmp.cond = TCG_COND_NEVER;
1302 TCGV_UNUSED_I64(dc->jmp.dest);
1303 TCGV_UNUSED_I64(dc->jmp.val1);
8fd29dd7
RH		 1304 TCGV_UNUSED_I64(dc->zero);
1305
1306 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1307 qemu_log("IN: %s\n", lookup_symbol(pc_start));
1308 }
1309 if (!max_insns) {
1310 max_insns = CF_COUNT_MASK;
1311 }
1312 if (cs->singlestep_enabled || singlestep) {
1313 max_insns = 1;
1314 }
1315 gen_tb_start(tb);
1316
1317 while (1) {
1318 if (search_pc) {
1319 j = tcg_op_buf_count();
1320 if (lj < j) {
1321 lj++;
1322 while (lj < j) {
1323 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1324 }
1325 }
1326 tcg_ctx.gen_opc_pc[lj] = dc->pc;
1327 tcg_ctx.gen_opc_instr_start[lj] = 1;
1328 tcg_ctx.gen_opc_icount[lj] = num_insns;
1329 }
1330 translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
1331
1332 if (dc->exit_tb) {
1333 /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
1334 break;
1335 }
1336 dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
1337 if (++num_insns >= max_insns
1338 || dc->pc >= next_page_start
1339 || tcg_op_buf_full()) {
1340 /* Ending the TB due to TB size or page boundary. Set PC. */
1341 tcg_gen_movi_tl(cpu_pc, dc->pc);
1342 tcg_gen_exit_tb(0);
1343 break;
1344 }
1345 }
1346
1347 gen_tb_end(tb, num_insns);
1348 if (search_pc) {
1349 j = tcg_op_buf_count();
1350 lj++;
1351 while (lj <= j) {
1352 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1353 }
1354 } else {
1355 tb->size = dc->pc - pc_start;
1356 tb->icount = num_insns;
1357 }
1358
1359 qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
1360}
1361
1362void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
1363{
1364 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, false);
1365}
1366
1367void gen_intermediate_code_pc(CPUTLGState *env, struct TranslationBlock *tb)
1368{
1369 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, true);
1370}
1371
1372void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb, int pc_pos)
1373{
1374 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
1375}
1376
1377void tilegx_tcg_init(void)
1378{
1379 int i;
1380
1381 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1382 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc");
1383 for (i = 0; i < TILEGX_R_COUNT; i++) {
1384 cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0,
1385 offsetof(CPUTLGState, regs[i]),
1386 reg_names[i]);
1387 }
1388}
QEMU mirror