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8fd29dd7 RH |
1 | /* |
2 | * QEMU TILE-Gx CPU | |
3 | * | |
4 | * Copyright (c) 2015 Chen Gang | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | ||
b98ba684 | 21 | #include "qemu/osdep.h" |
8fd29dd7 RH |
22 | #include "cpu.h" |
23 | #include "qemu/log.h" | |
24 | #include "disas/disas.h" | |
25 | #include "tcg-op.h" | |
26 | #include "exec/cpu_ldst.h" | |
dd8070d8 CG |
27 | #include "linux-user/syscall_defs.h" |
28 | ||
8fd29dd7 | 29 | #include "opcode_tilegx.h" |
03b217b1 | 30 | #include "spr_def_64.h" |
8fd29dd7 RH |
31 | |
32 | #define FMT64X "%016" PRIx64 | |
33 | ||
34 | static TCGv_ptr cpu_env; | |
35 | static TCGv cpu_pc; | |
36 | static TCGv cpu_regs[TILEGX_R_COUNT]; | |
37 | ||
38 | static const char * const reg_names[64] = { | |
39 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
40 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
41 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
42 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
43 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
44 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
45 | "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr", | |
46 | "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero" | |
47 | }; | |
48 | ||
49 | /* Modified registers are cached in temporaries until the end of the bundle. */ | |
50 | typedef struct { | |
51 | unsigned reg; | |
52 | TCGv val; | |
53 | } DisasContextTemp; | |
54 | ||
55 | #define MAX_WRITEBACK 4 | |
56 | ||
57 | /* This is the state at translation time. */ | |
58 | typedef struct { | |
59 | uint64_t pc; /* Current pc */ | |
60 | ||
61 | TCGv zero; /* For zero register */ | |
62 | ||
63 | DisasContextTemp wb[MAX_WRITEBACK]; | |
64 | int num_wb; | |
65 | int mmuidx; | |
66 | bool exit_tb; | |
0583b233 | 67 | TileExcp atomic_excp; |
8fd29dd7 RH |
68 | |
69 | struct { | |
70 | TCGCond cond; /* branch condition */ | |
71 | TCGv dest; /* branch destination */ | |
72 | TCGv val1; /* value to be compared against zero, for cond */ | |
73 | } jmp; /* Jump object, only once in each TB block */ | |
74 | } DisasContext; | |
75 | ||
76 | #include "exec/gen-icount.h" | |
77 | ||
78 | /* Differentiate the various pipe encodings. */ | |
79 | #define TY_X0 0 | |
80 | #define TY_X1 1 | |
81 | #define TY_Y0 2 | |
82 | #define TY_Y1 3 | |
83 | ||
84 | /* Remerge the base opcode and extension fields for switching. | |
85 | The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits; | |
86 | Y2 opcode field is 2 bits. */ | |
87 | #define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64) | |
88 | ||
89 | /* Similar, but for Y2 only. */ | |
90 | #define OEY2(OP, MODE) (OP + MODE * 4) | |
91 | ||
92 | /* Similar, but make sure opcode names match up. */ | |
93 | #define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0) | |
94 | #define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1) | |
95 | #define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0) | |
96 | #define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1) | |
97 | #define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY) | |
98 | #define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY) | |
99 | #define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY) | |
100 | ||
e7346cf0 | 101 | #define V1_IMM(X) (((X) & 0xff) * 0x0101010101010101ull) |
c6876d7e | 102 | #define V2_IMM(X) (((X) & 0xffff) * 0x0001000100010001ull) |
e7346cf0 | 103 | |
8fd29dd7 RH |
104 | |
105 | static void gen_exception(DisasContext *dc, TileExcp num) | |
106 | { | |
107 | TCGv_i32 tmp; | |
108 | ||
109 | tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES); | |
110 | ||
111 | tmp = tcg_const_i32(num); | |
112 | gen_helper_exception(cpu_env, tmp); | |
113 | tcg_temp_free_i32(tmp); | |
114 | dc->exit_tb = true; | |
115 | } | |
116 | ||
a9fdfc7e RH |
117 | static bool check_gr(DisasContext *dc, uint8_t reg) |
118 | { | |
119 | if (likely(reg < TILEGX_R_COUNT)) { | |
120 | return true; | |
121 | } | |
122 | ||
123 | switch (reg) { | |
124 | case TILEGX_R_SN: | |
125 | case TILEGX_R_ZERO: | |
126 | break; | |
127 | case TILEGX_R_IDN0: | |
128 | case TILEGX_R_IDN1: | |
129 | gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS); | |
130 | break; | |
131 | case TILEGX_R_UDN0: | |
132 | case TILEGX_R_UDN1: | |
133 | case TILEGX_R_UDN2: | |
134 | case TILEGX_R_UDN3: | |
135 | gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS); | |
136 | break; | |
137 | default: | |
138 | g_assert_not_reached(); | |
139 | } | |
140 | return false; | |
141 | } | |
142 | ||
143 | static TCGv load_zero(DisasContext *dc) | |
144 | { | |
145 | if (TCGV_IS_UNUSED_I64(dc->zero)) { | |
146 | dc->zero = tcg_const_i64(0); | |
147 | } | |
148 | return dc->zero; | |
149 | } | |
150 | ||
151 | static TCGv load_gr(DisasContext *dc, unsigned reg) | |
152 | { | |
153 | if (check_gr(dc, reg)) { | |
154 | return cpu_regs[reg]; | |
155 | } | |
156 | return load_zero(dc); | |
157 | } | |
158 | ||
159 | static TCGv dest_gr(DisasContext *dc, unsigned reg) | |
160 | { | |
161 | int n; | |
162 | ||
163 | /* Skip the result, mark the exception if necessary, and continue */ | |
164 | check_gr(dc, reg); | |
165 | ||
166 | n = dc->num_wb++; | |
167 | dc->wb[n].reg = reg; | |
168 | return dc->wb[n].val = tcg_temp_new_i64(); | |
169 | } | |
170 | ||
89b8c750 RH |
171 | static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb, |
172 | void (*operate)(TCGv, TCGv, TCGv)) | |
173 | { | |
174 | TCGv t0 = tcg_temp_new(); | |
175 | ||
176 | tcg_gen_ext32s_tl(tdest, tsrca); | |
177 | tcg_gen_ext32s_tl(t0, tsrcb); | |
178 | operate(tdest, tdest, t0); | |
179 | ||
180 | tcg_gen_movi_tl(t0, 0x7fffffff); | |
181 | tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest); | |
182 | tcg_gen_movi_tl(t0, -0x80000000LL); | |
183 | tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest); | |
184 | ||
185 | tcg_temp_free(t0); | |
186 | } | |
187 | ||
0583b233 RH |
188 | static void gen_atomic_excp(DisasContext *dc, unsigned dest, TCGv tdest, |
189 | TCGv tsrca, TCGv tsrcb, TileExcp excp) | |
190 | { | |
191 | #ifdef CONFIG_USER_ONLY | |
192 | TCGv_i32 t; | |
193 | ||
194 | tcg_gen_st_tl(tsrca, cpu_env, offsetof(CPUTLGState, atomic_srca)); | |
195 | tcg_gen_st_tl(tsrcb, cpu_env, offsetof(CPUTLGState, atomic_srcb)); | |
196 | t = tcg_const_i32(dest); | |
197 | tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, atomic_dstr)); | |
198 | tcg_temp_free_i32(t); | |
199 | ||
200 | /* We're going to write the real result in the exception. But in | |
201 | the meantime we've already created a writeback register, and | |
202 | we don't want that to remain uninitialized. */ | |
203 | tcg_gen_movi_tl(tdest, 0); | |
204 | ||
205 | /* Note that we need to delay issuing the exception that implements | |
206 | the atomic operation until after writing back the results of the | |
207 | instruction occupying the X0 pipe. */ | |
208 | dc->atomic_excp = excp; | |
209 | #else | |
210 | gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED); | |
211 | #endif | |
212 | } | |
213 | ||
7f41a8d6 RH |
214 | /* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes |
215 | specified by the bottom 3 bits of TSRCB, and set TDEST to the | |
216 | low 64 bits of the resulting value. */ | |
217 | static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb) | |
218 | { | |
219 | TCGv t0 = tcg_temp_new(); | |
220 | ||
221 | tcg_gen_andi_tl(t0, tsrcb, 7); | |
222 | tcg_gen_shli_tl(t0, t0, 3); | |
223 | tcg_gen_shr_tl(tdest, tsrcd, t0); | |
224 | ||
225 | /* We want to do "t0 = tsrca << (64 - t0)". Two's complement | |
226 | arithmetic on a 6-bit field tells us that 64 - t0 is equal | |
227 | to (t0 ^ 63) + 1. So we can do the shift in two parts, | |
228 | neither of which will be an invalid shift by 64. */ | |
229 | tcg_gen_xori_tl(t0, t0, 63); | |
230 | tcg_gen_shl_tl(t0, tsrca, t0); | |
231 | tcg_gen_shli_tl(t0, t0, 1); | |
232 | tcg_gen_or_tl(tdest, tdest, t0); | |
233 | ||
234 | tcg_temp_free(t0); | |
235 | } | |
236 | ||
237 | /* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the | |
238 | right shift is an immediate. */ | |
239 | static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr) | |
240 | { | |
241 | TCGv t0 = tcg_temp_new(); | |
242 | ||
243 | tcg_gen_shri_tl(t0, tsrcb, shr); | |
244 | tcg_gen_shli_tl(tdest, tsrca, 64 - shr); | |
245 | tcg_gen_or_tl(tdest, tdest, t0); | |
246 | ||
247 | tcg_temp_free(t0); | |
248 | } | |
249 | ||
4ff49775 RH |
250 | typedef enum { |
251 | LU, LS, HU, HS | |
252 | } MulHalf; | |
253 | ||
254 | static void gen_ext_half(TCGv d, TCGv s, MulHalf h) | |
255 | { | |
256 | switch (h) { | |
257 | case LU: | |
258 | tcg_gen_ext32u_tl(d, s); | |
259 | break; | |
260 | case LS: | |
261 | tcg_gen_ext32s_tl(d, s); | |
262 | break; | |
263 | case HU: | |
264 | tcg_gen_shri_tl(d, s, 32); | |
265 | break; | |
266 | case HS: | |
267 | tcg_gen_sari_tl(d, s, 32); | |
268 | break; | |
269 | } | |
270 | } | |
271 | ||
272 | static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb, | |
273 | MulHalf ha, MulHalf hb) | |
274 | { | |
275 | TCGv t = tcg_temp_new(); | |
276 | gen_ext_half(t, tsrca, ha); | |
277 | gen_ext_half(tdest, tsrcb, hb); | |
278 | tcg_gen_mul_tl(tdest, tdest, t); | |
279 | tcg_temp_free(t); | |
280 | } | |
281 | ||
9ff5b57c RH |
282 | static void gen_cmul2(TCGv tdest, TCGv tsrca, TCGv tsrcb, int sh, int rd) |
283 | { | |
284 | TCGv_i32 tsh = tcg_const_i32(sh); | |
285 | TCGv_i32 trd = tcg_const_i32(rd); | |
286 | gen_helper_cmul2(tdest, tsrca, tsrcb, tsh, trd); | |
287 | tcg_temp_free_i32(tsh); | |
288 | tcg_temp_free_i32(trd); | |
289 | } | |
290 | ||
c6876d7e CG |
291 | static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca, |
292 | unsigned srcb, TCGMemOp memop, const char *name) | |
293 | { | |
294 | if (dest) { | |
77b3adc0 | 295 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
c6876d7e CG |
296 | } |
297 | ||
298 | tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca), | |
299 | dc->mmuidx, memop); | |
300 | ||
301 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name, | |
302 | reg_names[srca], reg_names[srcb]); | |
303 | return TILEGX_EXCP_NONE; | |
304 | } | |
305 | ||
306 | static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb, | |
307 | int imm, TCGMemOp memop, const char *name) | |
308 | { | |
309 | TCGv tsrca = load_gr(dc, srca); | |
310 | TCGv tsrcb = load_gr(dc, srcb); | |
311 | ||
312 | tcg_gen_qemu_st_tl(tsrcb, tsrca, dc->mmuidx, memop); | |
313 | tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm); | |
314 | ||
315 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", name, | |
316 | reg_names[srca], reg_names[srcb], imm); | |
317 | return TILEGX_EXCP_NONE; | |
318 | } | |
319 | ||
e7346cf0 RH |
320 | /* Equality comparison with zero can be done quickly and efficiently. */ |
321 | static void gen_v1cmpeq0(TCGv v) | |
322 | { | |
323 | TCGv m = tcg_const_tl(V1_IMM(0x7f)); | |
324 | TCGv c = tcg_temp_new(); | |
325 | ||
326 | /* ~(((v & m) + m) | m | v). Sets the msb for each byte == 0. */ | |
327 | tcg_gen_and_tl(c, v, m); | |
328 | tcg_gen_add_tl(c, c, m); | |
329 | tcg_gen_or_tl(c, c, m); | |
330 | tcg_gen_nor_tl(c, c, v); | |
331 | tcg_temp_free(m); | |
332 | ||
333 | /* Shift the msb down to form the lsb boolean result. */ | |
334 | tcg_gen_shri_tl(v, c, 7); | |
335 | tcg_temp_free(c); | |
336 | } | |
337 | ||
338 | static void gen_v1cmpne0(TCGv v) | |
339 | { | |
340 | TCGv m = tcg_const_tl(V1_IMM(0x7f)); | |
341 | TCGv c = tcg_temp_new(); | |
342 | ||
343 | /* (((v & m) + m) | v) & ~m. Sets the msb for each byte != 0. */ | |
344 | tcg_gen_and_tl(c, v, m); | |
345 | tcg_gen_add_tl(c, c, m); | |
346 | tcg_gen_or_tl(c, c, v); | |
347 | tcg_gen_andc_tl(c, c, m); | |
348 | tcg_temp_free(m); | |
349 | ||
350 | /* Shift the msb down to form the lsb boolean result. */ | |
351 | tcg_gen_shri_tl(v, c, 7); | |
352 | tcg_temp_free(c); | |
353 | } | |
354 | ||
c6876d7e CG |
355 | /* Vector addition can be performed via arithmetic plus masking. It is |
356 | efficient this way only for 4 or more elements. */ | |
357 | static void gen_v12add(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign) | |
0426335d | 358 | { |
c6876d7e CG |
359 | TCGv tmask = tcg_const_tl(~sign); |
360 | TCGv t0 = tcg_temp_new(); | |
361 | TCGv t1 = tcg_temp_new(); | |
0426335d | 362 | |
c6876d7e CG |
363 | /* ((a & ~sign) + (b & ~sign)) ^ ((a ^ b) & sign). */ |
364 | tcg_gen_and_tl(t0, tsrca, tmask); | |
365 | tcg_gen_and_tl(t1, tsrcb, tmask); | |
366 | tcg_gen_add_tl(tdest, t0, t1); | |
367 | tcg_gen_xor_tl(t0, tsrca, tsrcb); | |
368 | tcg_gen_andc_tl(t0, t0, tmask); | |
369 | tcg_gen_xor_tl(tdest, tdest, t0); | |
0426335d | 370 | |
c6876d7e CG |
371 | tcg_temp_free(t1); |
372 | tcg_temp_free(t0); | |
373 | tcg_temp_free(tmask); | |
0426335d | 374 | } |
7f41a8d6 | 375 | |
c6876d7e CG |
376 | /* Similarly for vector subtraction. */ |
377 | static void gen_v12sub(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign) | |
01cd675c | 378 | { |
c6876d7e CG |
379 | TCGv tsign = tcg_const_tl(sign); |
380 | TCGv t0 = tcg_temp_new(); | |
381 | TCGv t1 = tcg_temp_new(); | |
01cd675c | 382 | |
c6876d7e CG |
383 | /* ((a | sign) - (b & ~sign)) ^ ((a ^ ~b) & sign). */ |
384 | tcg_gen_or_tl(t0, tsrca, tsign); | |
385 | tcg_gen_andc_tl(t1, tsrcb, tsign); | |
386 | tcg_gen_sub_tl(tdest, t0, t1); | |
387 | tcg_gen_eqv_tl(t0, tsrca, tsrcb); | |
388 | tcg_gen_and_tl(t0, t0, tsign); | |
389 | tcg_gen_xor_tl(tdest, tdest, t0); | |
01cd675c | 390 | |
c6876d7e CG |
391 | tcg_temp_free(t1); |
392 | tcg_temp_free(t0); | |
393 | tcg_temp_free(tsign); | |
01cd675c RH |
394 | } |
395 | ||
0ab0a3d7 CG |
396 | static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64, |
397 | void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32)) | |
398 | { | |
399 | TCGv_i32 al = tcg_temp_new_i32(); | |
400 | TCGv_i32 ah = tcg_temp_new_i32(); | |
401 | TCGv_i32 bl = tcg_temp_new_i32(); | |
402 | ||
403 | tcg_gen_extr_i64_i32(al, ah, a64); | |
404 | tcg_gen_extrl_i64_i32(bl, b64); | |
405 | tcg_gen_andi_i32(bl, bl, 31); | |
406 | generate(al, al, bl); | |
407 | generate(ah, ah, bl); | |
408 | tcg_gen_concat_i32_i64(d64, al, ah); | |
409 | ||
410 | tcg_temp_free_i32(al); | |
411 | tcg_temp_free_i32(ah); | |
412 | tcg_temp_free_i32(bl); | |
413 | } | |
414 | ||
c6876d7e CG |
415 | static void gen_v4op(TCGv d64, TCGv a64, TCGv b64, |
416 | void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32)) | |
417 | { | |
418 | TCGv_i32 al = tcg_temp_new_i32(); | |
419 | TCGv_i32 ah = tcg_temp_new_i32(); | |
420 | TCGv_i32 bl = tcg_temp_new_i32(); | |
421 | TCGv_i32 bh = tcg_temp_new_i32(); | |
422 | ||
423 | tcg_gen_extr_i64_i32(al, ah, a64); | |
424 | tcg_gen_extr_i64_i32(bl, bh, b64); | |
425 | generate(al, al, bl); | |
426 | generate(ah, ah, bh); | |
427 | tcg_gen_concat_i32_i64(d64, al, ah); | |
428 | ||
429 | tcg_temp_free_i32(al); | |
430 | tcg_temp_free_i32(ah); | |
431 | tcg_temp_free_i32(bl); | |
432 | tcg_temp_free_i32(bh); | |
433 | } | |
434 | ||
dd8070d8 CG |
435 | static TileExcp gen_signal(DisasContext *dc, int signo, int sigcode, |
436 | const char *mnemonic) | |
437 | { | |
438 | TCGv_i32 t0 = tcg_const_i32(signo); | |
439 | TCGv_i32 t1 = tcg_const_i32(sigcode); | |
440 | ||
441 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUTLGState, signo)); | |
442 | tcg_gen_st_i32(t1, cpu_env, offsetof(CPUTLGState, sigcode)); | |
443 | ||
444 | tcg_temp_free_i32(t1); | |
445 | tcg_temp_free_i32(t0); | |
446 | ||
447 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic); | |
448 | return TILEGX_EXCP_SIGNAL; | |
449 | } | |
450 | ||
451 | static bool parse_from_addli(uint64_t bundle, int *signo, int *sigcode) | |
452 | { | |
453 | int imm; | |
454 | ||
455 | if ((get_Opcode_X0(bundle) != ADDLI_OPCODE_X0) | |
456 | || (get_Dest_X0(bundle) != TILEGX_R_ZERO) | |
457 | || (get_SrcA_X0(bundle) != TILEGX_R_ZERO)) { | |
458 | return false; | |
459 | } | |
460 | ||
461 | imm = get_Imm16_X0(bundle); | |
462 | *signo = imm & 0x3f; | |
463 | *sigcode = (imm >> 6) & 0xf; | |
464 | ||
465 | /* ??? The linux kernel validates both signo and the sigcode vs the | |
466 | known max for each signal. Don't bother here. */ | |
467 | return true; | |
468 | } | |
469 | ||
470 | static TileExcp gen_specill(DisasContext *dc, unsigned dest, unsigned srca, | |
471 | uint64_t bundle) | |
472 | { | |
473 | const char *mnemonic; | |
474 | int signo; | |
475 | int sigcode; | |
476 | ||
477 | if (dest == 0x1c && srca == 0x25) { | |
478 | signo = TARGET_SIGTRAP; | |
479 | sigcode = TARGET_TRAP_BRKPT; | |
480 | mnemonic = "bpt"; | |
481 | } else if (dest == 0x1d && srca == 0x25 | |
482 | && parse_from_addli(bundle, &signo, &sigcode)) { | |
483 | mnemonic = "raise"; | |
484 | } else { | |
485 | signo = TARGET_SIGILL; | |
486 | sigcode = TARGET_ILL_ILLOPC; | |
487 | mnemonic = "ill"; | |
488 | } | |
489 | ||
490 | return gen_signal(dc, signo, sigcode, mnemonic); | |
491 | } | |
492 | ||
8fd29dd7 | 493 | static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, |
dd8070d8 | 494 | unsigned dest, unsigned srca, uint64_t bundle) |
8fd29dd7 | 495 | { |
a9fdfc7e | 496 | TCGv tdest, tsrca; |
8fd29dd7 | 497 | const char *mnemonic; |
0426335d | 498 | TCGMemOp memop; |
d5dbd6eb | 499 | TileExcp ret = TILEGX_EXCP_NONE; |
133b84c8 | 500 | bool prefetch_nofault = false; |
8fd29dd7 | 501 | |
d5dbd6eb | 502 | /* Eliminate instructions with no output before doing anything else. */ |
8fd29dd7 RH |
503 | switch (opext) { |
504 | case OE_RR_Y0(NOP): | |
505 | case OE_RR_Y1(NOP): | |
506 | case OE_RR_X0(NOP): | |
507 | case OE_RR_X1(NOP): | |
508 | mnemonic = "nop"; | |
d5dbd6eb | 509 | goto done0; |
8fd29dd7 RH |
510 | case OE_RR_Y0(FNOP): |
511 | case OE_RR_Y1(FNOP): | |
512 | case OE_RR_X0(FNOP): | |
513 | case OE_RR_X1(FNOP): | |
514 | mnemonic = "fnop"; | |
d5dbd6eb RH |
515 | goto done0; |
516 | case OE_RR_X1(DRAIN): | |
517 | mnemonic = "drain"; | |
518 | goto done0; | |
519 | case OE_RR_X1(FLUSHWB): | |
520 | mnemonic = "flushwb"; | |
521 | goto done0; | |
522 | case OE_RR_X1(ILL): | |
dd8070d8 | 523 | return gen_specill(dc, dest, srca, bundle); |
d5dbd6eb | 524 | case OE_RR_Y1(ILL): |
dd8070d8 | 525 | return gen_signal(dc, TARGET_SIGILL, TARGET_ILL_ILLOPC, "ill"); |
d5dbd6eb RH |
526 | case OE_RR_X1(MF): |
527 | mnemonic = "mf"; | |
528 | goto done0; | |
529 | case OE_RR_X1(NAP): | |
530 | /* ??? This should yield, especially in system mode. */ | |
531 | mnemonic = "nap"; | |
532 | goto done0; | |
fec7daab CG |
533 | case OE_RR_X1(IRET): |
534 | gen_helper_ext01_ics(cpu_env); | |
535 | dc->jmp.cond = TCG_COND_ALWAYS; | |
536 | dc->jmp.dest = tcg_temp_new(); | |
537 | tcg_gen_ld_tl(dc->jmp.dest, cpu_env, | |
538 | offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_0])); | |
539 | tcg_gen_andi_tl(dc->jmp.dest, dc->jmp.dest, ~7); | |
540 | mnemonic = "iret"; | |
541 | goto done0; | |
d5dbd6eb RH |
542 | case OE_RR_X1(SWINT0): |
543 | case OE_RR_X1(SWINT2): | |
544 | case OE_RR_X1(SWINT3): | |
545 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; | |
546 | case OE_RR_X1(SWINT1): | |
547 | ret = TILEGX_EXCP_SYSCALL; | |
548 | mnemonic = "swint1"; | |
549 | done0: | |
8fd29dd7 | 550 | if (srca || dest) { |
77b3adc0 | 551 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
552 | } |
553 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic); | |
d5dbd6eb | 554 | return ret; |
c230a994 | 555 | |
d5dbd6eb RH |
556 | case OE_RR_X1(DTLBPR): |
557 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; | |
558 | case OE_RR_X1(FINV): | |
559 | mnemonic = "finv"; | |
560 | goto done1; | |
561 | case OE_RR_X1(FLUSH): | |
562 | mnemonic = "flush"; | |
563 | goto done1; | |
564 | case OE_RR_X1(ICOH): | |
565 | mnemonic = "icoh"; | |
566 | goto done1; | |
567 | case OE_RR_X1(INV): | |
568 | mnemonic = "inv"; | |
569 | goto done1; | |
570 | case OE_RR_X1(WH64): | |
571 | mnemonic = "wh64"; | |
572 | goto done1; | |
c230a994 RH |
573 | case OE_RR_X1(JRP): |
574 | case OE_RR_Y1(JRP): | |
575 | mnemonic = "jrp"; | |
576 | goto do_jr; | |
577 | case OE_RR_X1(JR): | |
578 | case OE_RR_Y1(JR): | |
579 | mnemonic = "jr"; | |
580 | goto do_jr; | |
581 | case OE_RR_X1(JALRP): | |
582 | case OE_RR_Y1(JALRP): | |
583 | mnemonic = "jalrp"; | |
584 | goto do_jalr; | |
585 | case OE_RR_X1(JALR): | |
586 | case OE_RR_Y1(JALR): | |
587 | mnemonic = "jalr"; | |
588 | do_jalr: | |
589 | tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR), | |
590 | dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES); | |
591 | do_jr: | |
592 | dc->jmp.cond = TCG_COND_ALWAYS; | |
593 | dc->jmp.dest = tcg_temp_new(); | |
594 | tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7); | |
d5dbd6eb RH |
595 | done1: |
596 | if (dest) { | |
77b3adc0 | 597 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
d5dbd6eb | 598 | } |
c230a994 | 599 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]); |
d5dbd6eb | 600 | return ret; |
8fd29dd7 RH |
601 | } |
602 | ||
a9fdfc7e RH |
603 | tdest = dest_gr(dc, dest); |
604 | tsrca = load_gr(dc, srca); | |
605 | ||
8fd29dd7 RH |
606 | switch (opext) { |
607 | case OE_RR_X0(CNTLZ): | |
608 | case OE_RR_Y0(CNTLZ): | |
7f41a8d6 RH |
609 | gen_helper_cntlz(tdest, tsrca); |
610 | mnemonic = "cntlz"; | |
611 | break; | |
8fd29dd7 RH |
612 | case OE_RR_X0(CNTTZ): |
613 | case OE_RR_Y0(CNTTZ): | |
7f41a8d6 RH |
614 | gen_helper_cnttz(tdest, tsrca); |
615 | mnemonic = "cnttz"; | |
616 | break; | |
8fd29dd7 RH |
617 | case OE_RR_X0(FSINGLE_PACK1): |
618 | case OE_RR_Y0(FSINGLE_PACK1): | |
0426335d | 619 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 | 620 | case OE_RR_X1(LD1S): |
0426335d | 621 | memop = MO_SB; |
133b84c8 | 622 | mnemonic = "ld1s"; /* prefetch_l1_fault */ |
0426335d | 623 | goto do_load; |
8fd29dd7 | 624 | case OE_RR_X1(LD1U): |
0426335d | 625 | memop = MO_UB; |
133b84c8 RH |
626 | mnemonic = "ld1u"; /* prefetch, prefetch_l1 */ |
627 | prefetch_nofault = (dest == TILEGX_R_ZERO); | |
0426335d | 628 | goto do_load; |
8fd29dd7 | 629 | case OE_RR_X1(LD2S): |
0426335d | 630 | memop = MO_TESW; |
133b84c8 | 631 | mnemonic = "ld2s"; /* prefetch_l2_fault */ |
0426335d | 632 | goto do_load; |
8fd29dd7 | 633 | case OE_RR_X1(LD2U): |
0426335d | 634 | memop = MO_TEUW; |
133b84c8 RH |
635 | mnemonic = "ld2u"; /* prefetch_l2 */ |
636 | prefetch_nofault = (dest == TILEGX_R_ZERO); | |
0426335d | 637 | goto do_load; |
8fd29dd7 | 638 | case OE_RR_X1(LD4S): |
0426335d | 639 | memop = MO_TESL; |
133b84c8 | 640 | mnemonic = "ld4s"; /* prefetch_l3_fault */ |
0426335d | 641 | goto do_load; |
8fd29dd7 | 642 | case OE_RR_X1(LD4U): |
0426335d | 643 | memop = MO_TEUL; |
133b84c8 RH |
644 | mnemonic = "ld4u"; /* prefetch_l3 */ |
645 | prefetch_nofault = (dest == TILEGX_R_ZERO); | |
0426335d | 646 | goto do_load; |
8fd29dd7 | 647 | case OE_RR_X1(LDNT1S): |
0426335d RH |
648 | memop = MO_SB; |
649 | mnemonic = "ldnt1s"; | |
650 | goto do_load; | |
8fd29dd7 | 651 | case OE_RR_X1(LDNT1U): |
0426335d RH |
652 | memop = MO_UB; |
653 | mnemonic = "ldnt1u"; | |
654 | goto do_load; | |
8fd29dd7 | 655 | case OE_RR_X1(LDNT2S): |
0426335d RH |
656 | memop = MO_TESW; |
657 | mnemonic = "ldnt2s"; | |
658 | goto do_load; | |
8fd29dd7 | 659 | case OE_RR_X1(LDNT2U): |
0426335d RH |
660 | memop = MO_TEUW; |
661 | mnemonic = "ldnt2u"; | |
662 | goto do_load; | |
8fd29dd7 | 663 | case OE_RR_X1(LDNT4S): |
0426335d RH |
664 | memop = MO_TESL; |
665 | mnemonic = "ldnt4s"; | |
666 | goto do_load; | |
8fd29dd7 | 667 | case OE_RR_X1(LDNT4U): |
0426335d RH |
668 | memop = MO_TEUL; |
669 | mnemonic = "ldnt4u"; | |
670 | goto do_load; | |
8fd29dd7 | 671 | case OE_RR_X1(LDNT): |
0426335d RH |
672 | memop = MO_TEQ; |
673 | mnemonic = "ldnt"; | |
674 | goto do_load; | |
8fd29dd7 | 675 | case OE_RR_X1(LD): |
0426335d RH |
676 | memop = MO_TEQ; |
677 | mnemonic = "ld"; | |
678 | do_load: | |
133b84c8 RH |
679 | if (!prefetch_nofault) { |
680 | tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop); | |
681 | } | |
0426335d RH |
682 | break; |
683 | case OE_RR_X1(LDNA): | |
684 | tcg_gen_andi_tl(tdest, tsrca, ~7); | |
685 | tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ); | |
686 | mnemonic = "ldna"; | |
687 | break; | |
8fd29dd7 RH |
688 | case OE_RR_X1(LNK): |
689 | case OE_RR_Y1(LNK): | |
c230a994 | 690 | if (srca) { |
77b3adc0 | 691 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
c230a994 RH |
692 | } |
693 | tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES); | |
694 | mnemonic = "lnk"; | |
695 | break; | |
8fd29dd7 RH |
696 | case OE_RR_X0(PCNT): |
697 | case OE_RR_Y0(PCNT): | |
7f41a8d6 RH |
698 | gen_helper_pcnt(tdest, tsrca); |
699 | mnemonic = "pcnt"; | |
700 | break; | |
8fd29dd7 RH |
701 | case OE_RR_X0(REVBITS): |
702 | case OE_RR_Y0(REVBITS): | |
7f41a8d6 RH |
703 | gen_helper_revbits(tdest, tsrca); |
704 | mnemonic = "revbits"; | |
705 | break; | |
8fd29dd7 RH |
706 | case OE_RR_X0(REVBYTES): |
707 | case OE_RR_Y0(REVBYTES): | |
a9fdfc7e RH |
708 | tcg_gen_bswap64_tl(tdest, tsrca); |
709 | mnemonic = "revbytes"; | |
710 | break; | |
8fd29dd7 RH |
711 | case OE_RR_X0(TBLIDXB0): |
712 | case OE_RR_Y0(TBLIDXB0): | |
0b4232f1 RH |
713 | tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tsrca, 2, 8); |
714 | mnemonic = "tblidxb0"; | |
715 | break; | |
8fd29dd7 RH |
716 | case OE_RR_X0(TBLIDXB1): |
717 | case OE_RR_Y0(TBLIDXB1): | |
0b4232f1 RH |
718 | tcg_gen_shri_tl(tdest, tsrca, 8); |
719 | tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8); | |
720 | mnemonic = "tblidxb1"; | |
721 | break; | |
8fd29dd7 RH |
722 | case OE_RR_X0(TBLIDXB2): |
723 | case OE_RR_Y0(TBLIDXB2): | |
0b4232f1 RH |
724 | tcg_gen_shri_tl(tdest, tsrca, 16); |
725 | tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8); | |
726 | mnemonic = "tblidxb2"; | |
727 | break; | |
8fd29dd7 RH |
728 | case OE_RR_X0(TBLIDXB3): |
729 | case OE_RR_Y0(TBLIDXB3): | |
0b4232f1 RH |
730 | tcg_gen_shri_tl(tdest, tsrca, 24); |
731 | tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8); | |
732 | mnemonic = "tblidxb3"; | |
733 | break; | |
8fd29dd7 | 734 | default: |
77b3adc0 | 735 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
736 | } |
737 | ||
738 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic, | |
739 | reg_names[dest], reg_names[srca]); | |
d5dbd6eb | 740 | return ret; |
8fd29dd7 RH |
741 | } |
742 | ||
743 | static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, | |
744 | unsigned dest, unsigned srca, unsigned srcb) | |
745 | { | |
a9fdfc7e RH |
746 | TCGv tdest = dest_gr(dc, dest); |
747 | TCGv tsrca = load_gr(dc, srca); | |
748 | TCGv tsrcb = load_gr(dc, srcb); | |
2369976d | 749 | TCGv t0; |
8fd29dd7 RH |
750 | const char *mnemonic; |
751 | ||
752 | switch (opext) { | |
753 | case OE_RRR(ADDXSC, 0, X0): | |
754 | case OE_RRR(ADDXSC, 0, X1): | |
89b8c750 RH |
755 | gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl); |
756 | mnemonic = "addxsc"; | |
757 | break; | |
8fd29dd7 RH |
758 | case OE_RRR(ADDX, 0, X0): |
759 | case OE_RRR(ADDX, 0, X1): | |
760 | case OE_RRR(ADDX, 0, Y0): | |
761 | case OE_RRR(ADDX, 0, Y1): | |
89b8c750 RH |
762 | tcg_gen_add_tl(tdest, tsrca, tsrcb); |
763 | tcg_gen_ext32s_tl(tdest, tdest); | |
764 | mnemonic = "addx"; | |
765 | break; | |
8fd29dd7 RH |
766 | case OE_RRR(ADD, 0, X0): |
767 | case OE_RRR(ADD, 0, X1): | |
768 | case OE_RRR(ADD, 0, Y0): | |
769 | case OE_RRR(ADD, 0, Y1): | |
89b8c750 RH |
770 | tcg_gen_add_tl(tdest, tsrca, tsrcb); |
771 | mnemonic = "add"; | |
772 | break; | |
8fd29dd7 RH |
773 | case OE_RRR(AND, 0, X0): |
774 | case OE_RRR(AND, 0, X1): | |
775 | case OE_RRR(AND, 5, Y0): | |
776 | case OE_RRR(AND, 5, Y1): | |
a9fdfc7e RH |
777 | tcg_gen_and_tl(tdest, tsrca, tsrcb); |
778 | mnemonic = "and"; | |
779 | break; | |
8fd29dd7 RH |
780 | case OE_RRR(CMOVEQZ, 0, X0): |
781 | case OE_RRR(CMOVEQZ, 4, Y0): | |
f090f9f7 RH |
782 | tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, load_zero(dc), |
783 | tsrcb, load_gr(dc, dest)); | |
784 | mnemonic = "cmoveqz"; | |
785 | break; | |
8fd29dd7 RH |
786 | case OE_RRR(CMOVNEZ, 0, X0): |
787 | case OE_RRR(CMOVNEZ, 4, Y0): | |
f090f9f7 RH |
788 | tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, load_zero(dc), |
789 | tsrcb, load_gr(dc, dest)); | |
790 | mnemonic = "cmovnez"; | |
791 | break; | |
8fd29dd7 RH |
792 | case OE_RRR(CMPEQ, 0, X0): |
793 | case OE_RRR(CMPEQ, 0, X1): | |
794 | case OE_RRR(CMPEQ, 3, Y0): | |
795 | case OE_RRR(CMPEQ, 3, Y1): | |
73c54377 RH |
796 | tcg_gen_setcond_tl(TCG_COND_EQ, tdest, tsrca, tsrcb); |
797 | mnemonic = "cmpeq"; | |
798 | break; | |
8fd29dd7 | 799 | case OE_RRR(CMPEXCH4, 0, X1): |
0583b233 RH |
800 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
801 | TILEGX_EXCP_OPCODE_CMPEXCH4); | |
802 | mnemonic = "cmpexch4"; | |
803 | break; | |
8fd29dd7 | 804 | case OE_RRR(CMPEXCH, 0, X1): |
0583b233 RH |
805 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
806 | TILEGX_EXCP_OPCODE_CMPEXCH); | |
807 | mnemonic = "cmpexch"; | |
808 | break; | |
8fd29dd7 RH |
809 | case OE_RRR(CMPLES, 0, X0): |
810 | case OE_RRR(CMPLES, 0, X1): | |
811 | case OE_RRR(CMPLES, 2, Y0): | |
812 | case OE_RRR(CMPLES, 2, Y1): | |
73c54377 RH |
813 | tcg_gen_setcond_tl(TCG_COND_LE, tdest, tsrca, tsrcb); |
814 | mnemonic = "cmples"; | |
815 | break; | |
8fd29dd7 RH |
816 | case OE_RRR(CMPLEU, 0, X0): |
817 | case OE_RRR(CMPLEU, 0, X1): | |
818 | case OE_RRR(CMPLEU, 2, Y0): | |
819 | case OE_RRR(CMPLEU, 2, Y1): | |
73c54377 RH |
820 | tcg_gen_setcond_tl(TCG_COND_LEU, tdest, tsrca, tsrcb); |
821 | mnemonic = "cmpleu"; | |
822 | break; | |
8fd29dd7 RH |
823 | case OE_RRR(CMPLTS, 0, X0): |
824 | case OE_RRR(CMPLTS, 0, X1): | |
825 | case OE_RRR(CMPLTS, 2, Y0): | |
826 | case OE_RRR(CMPLTS, 2, Y1): | |
73c54377 RH |
827 | tcg_gen_setcond_tl(TCG_COND_LT, tdest, tsrca, tsrcb); |
828 | mnemonic = "cmplts"; | |
829 | break; | |
8fd29dd7 RH |
830 | case OE_RRR(CMPLTU, 0, X0): |
831 | case OE_RRR(CMPLTU, 0, X1): | |
832 | case OE_RRR(CMPLTU, 2, Y0): | |
833 | case OE_RRR(CMPLTU, 2, Y1): | |
73c54377 RH |
834 | tcg_gen_setcond_tl(TCG_COND_LTU, tdest, tsrca, tsrcb); |
835 | mnemonic = "cmpltu"; | |
836 | break; | |
8fd29dd7 RH |
837 | case OE_RRR(CMPNE, 0, X0): |
838 | case OE_RRR(CMPNE, 0, X1): | |
839 | case OE_RRR(CMPNE, 3, Y0): | |
840 | case OE_RRR(CMPNE, 3, Y1): | |
73c54377 RH |
841 | tcg_gen_setcond_tl(TCG_COND_NE, tdest, tsrca, tsrcb); |
842 | mnemonic = "cmpne"; | |
843 | break; | |
8fd29dd7 | 844 | case OE_RRR(CMULAF, 0, X0): |
9ff5b57c RH |
845 | gen_helper_cmulaf(tdest, load_gr(dc, dest), tsrca, tsrcb); |
846 | mnemonic = "cmulaf"; | |
847 | break; | |
8fd29dd7 | 848 | case OE_RRR(CMULA, 0, X0): |
9ff5b57c RH |
849 | gen_helper_cmula(tdest, load_gr(dc, dest), tsrca, tsrcb); |
850 | mnemonic = "cmula"; | |
851 | break; | |
8fd29dd7 | 852 | case OE_RRR(CMULFR, 0, X0): |
9ff5b57c RH |
853 | gen_cmul2(tdest, tsrca, tsrcb, 15, 1 << 14); |
854 | mnemonic = "cmulfr"; | |
855 | break; | |
8fd29dd7 | 856 | case OE_RRR(CMULF, 0, X0): |
9ff5b57c RH |
857 | gen_cmul2(tdest, tsrca, tsrcb, 15, 0); |
858 | mnemonic = "cmulf"; | |
859 | break; | |
8fd29dd7 | 860 | case OE_RRR(CMULHR, 0, X0): |
9ff5b57c RH |
861 | gen_cmul2(tdest, tsrca, tsrcb, 16, 1 << 15); |
862 | mnemonic = "cmulhr"; | |
863 | break; | |
8fd29dd7 | 864 | case OE_RRR(CMULH, 0, X0): |
9ff5b57c RH |
865 | gen_cmul2(tdest, tsrca, tsrcb, 16, 0); |
866 | mnemonic = "cmulh"; | |
867 | break; | |
8fd29dd7 | 868 | case OE_RRR(CMUL, 0, X0): |
9ff5b57c RH |
869 | gen_helper_cmula(tdest, load_zero(dc), tsrca, tsrcb); |
870 | mnemonic = "cmul"; | |
871 | break; | |
8fd29dd7 | 872 | case OE_RRR(CRC32_32, 0, X0): |
ba1fc78f RH |
873 | gen_helper_crc32_32(tdest, tsrca, tsrcb); |
874 | mnemonic = "crc32_32"; | |
875 | break; | |
8fd29dd7 | 876 | case OE_RRR(CRC32_8, 0, X0): |
ba1fc78f RH |
877 | gen_helper_crc32_8(tdest, tsrca, tsrcb); |
878 | mnemonic = "crc32_8"; | |
879 | break; | |
8fd29dd7 RH |
880 | case OE_RRR(DBLALIGN2, 0, X0): |
881 | case OE_RRR(DBLALIGN2, 0, X1): | |
7f41a8d6 RH |
882 | gen_dblaligni(tdest, tsrca, tsrcb, 16); |
883 | mnemonic = "dblalign2"; | |
884 | break; | |
8fd29dd7 RH |
885 | case OE_RRR(DBLALIGN4, 0, X0): |
886 | case OE_RRR(DBLALIGN4, 0, X1): | |
7f41a8d6 RH |
887 | gen_dblaligni(tdest, tsrca, tsrcb, 32); |
888 | mnemonic = "dblalign4"; | |
889 | break; | |
8fd29dd7 RH |
890 | case OE_RRR(DBLALIGN6, 0, X0): |
891 | case OE_RRR(DBLALIGN6, 0, X1): | |
7f41a8d6 RH |
892 | gen_dblaligni(tdest, tsrca, tsrcb, 48); |
893 | mnemonic = "dblalign6"; | |
894 | break; | |
8fd29dd7 | 895 | case OE_RRR(DBLALIGN, 0, X0): |
7f41a8d6 RH |
896 | gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb); |
897 | mnemonic = "dblalign"; | |
898 | break; | |
8fd29dd7 | 899 | case OE_RRR(EXCH4, 0, X1): |
0583b233 RH |
900 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
901 | TILEGX_EXCP_OPCODE_EXCH4); | |
902 | mnemonic = "exch4"; | |
903 | break; | |
8fd29dd7 | 904 | case OE_RRR(EXCH, 0, X1): |
0583b233 RH |
905 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
906 | TILEGX_EXCP_OPCODE_EXCH); | |
907 | mnemonic = "exch"; | |
908 | break; | |
8fd29dd7 RH |
909 | case OE_RRR(FDOUBLE_ADDSUB, 0, X0): |
910 | case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0): | |
911 | case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0): | |
912 | case OE_RRR(FDOUBLE_PACK1, 0, X0): | |
913 | case OE_RRR(FDOUBLE_PACK2, 0, X0): | |
914 | case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0): | |
915 | case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0): | |
916 | case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0): | |
0583b233 | 917 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 | 918 | case OE_RRR(FETCHADD4, 0, X1): |
0583b233 RH |
919 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
920 | TILEGX_EXCP_OPCODE_FETCHADD4); | |
921 | mnemonic = "fetchadd4"; | |
922 | break; | |
8fd29dd7 | 923 | case OE_RRR(FETCHADDGEZ4, 0, X1): |
0583b233 RH |
924 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
925 | TILEGX_EXCP_OPCODE_FETCHADDGEZ4); | |
926 | mnemonic = "fetchaddgez4"; | |
927 | break; | |
8fd29dd7 | 928 | case OE_RRR(FETCHADDGEZ, 0, X1): |
0583b233 RH |
929 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
930 | TILEGX_EXCP_OPCODE_FETCHADDGEZ); | |
931 | mnemonic = "fetchaddgez"; | |
932 | break; | |
8fd29dd7 | 933 | case OE_RRR(FETCHADD, 0, X1): |
0583b233 RH |
934 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
935 | TILEGX_EXCP_OPCODE_FETCHADD); | |
936 | mnemonic = "fetchadd"; | |
937 | break; | |
8fd29dd7 | 938 | case OE_RRR(FETCHAND4, 0, X1): |
0583b233 RH |
939 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
940 | TILEGX_EXCP_OPCODE_FETCHAND4); | |
941 | mnemonic = "fetchand4"; | |
942 | break; | |
8fd29dd7 | 943 | case OE_RRR(FETCHAND, 0, X1): |
0583b233 RH |
944 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
945 | TILEGX_EXCP_OPCODE_FETCHAND); | |
946 | mnemonic = "fetchand"; | |
947 | break; | |
8fd29dd7 | 948 | case OE_RRR(FETCHOR4, 0, X1): |
0583b233 RH |
949 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
950 | TILEGX_EXCP_OPCODE_FETCHOR4); | |
951 | mnemonic = "fetchor4"; | |
952 | break; | |
8fd29dd7 | 953 | case OE_RRR(FETCHOR, 0, X1): |
0583b233 RH |
954 | gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, |
955 | TILEGX_EXCP_OPCODE_FETCHOR); | |
956 | mnemonic = "fetchor"; | |
957 | break; | |
8fd29dd7 RH |
958 | case OE_RRR(FSINGLE_ADD1, 0, X0): |
959 | case OE_RRR(FSINGLE_ADDSUB2, 0, X0): | |
960 | case OE_RRR(FSINGLE_MUL1, 0, X0): | |
961 | case OE_RRR(FSINGLE_MUL2, 0, X0): | |
962 | case OE_RRR(FSINGLE_PACK2, 0, X0): | |
963 | case OE_RRR(FSINGLE_SUB1, 0, X0): | |
661ff743 | 964 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
965 | case OE_RRR(MNZ, 0, X0): |
966 | case OE_RRR(MNZ, 0, X1): | |
967 | case OE_RRR(MNZ, 4, Y0): | |
968 | case OE_RRR(MNZ, 4, Y1): | |
661ff743 RH |
969 | t0 = load_zero(dc); |
970 | tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0); | |
971 | mnemonic = "mnz"; | |
972 | break; | |
8fd29dd7 RH |
973 | case OE_RRR(MULAX, 0, X0): |
974 | case OE_RRR(MULAX, 3, Y0): | |
4ff49775 RH |
975 | tcg_gen_mul_tl(tdest, tsrca, tsrcb); |
976 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
977 | tcg_gen_ext32s_tl(tdest, tdest); | |
978 | mnemonic = "mulax"; | |
979 | break; | |
8fd29dd7 RH |
980 | case OE_RRR(MULA_HS_HS, 0, X0): |
981 | case OE_RRR(MULA_HS_HS, 9, Y0): | |
4ff49775 RH |
982 | gen_mul_half(tdest, tsrca, tsrcb, HS, HS); |
983 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
984 | mnemonic = "mula_hs_hs"; | |
985 | break; | |
8fd29dd7 | 986 | case OE_RRR(MULA_HS_HU, 0, X0): |
4ff49775 RH |
987 | gen_mul_half(tdest, tsrca, tsrcb, HS, HU); |
988 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
989 | mnemonic = "mula_hs_hu"; | |
990 | break; | |
8fd29dd7 | 991 | case OE_RRR(MULA_HS_LS, 0, X0): |
4ff49775 RH |
992 | gen_mul_half(tdest, tsrca, tsrcb, HS, LS); |
993 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
994 | mnemonic = "mula_hs_ls"; | |
995 | break; | |
8fd29dd7 | 996 | case OE_RRR(MULA_HS_LU, 0, X0): |
4ff49775 RH |
997 | gen_mul_half(tdest, tsrca, tsrcb, HS, LU); |
998 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
999 | mnemonic = "mula_hs_lu"; | |
1000 | break; | |
8fd29dd7 RH |
1001 | case OE_RRR(MULA_HU_HU, 0, X0): |
1002 | case OE_RRR(MULA_HU_HU, 9, Y0): | |
4ff49775 RH |
1003 | gen_mul_half(tdest, tsrca, tsrcb, HU, HU); |
1004 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
1005 | mnemonic = "mula_hu_hu"; | |
1006 | break; | |
8fd29dd7 | 1007 | case OE_RRR(MULA_HU_LS, 0, X0): |
4ff49775 RH |
1008 | gen_mul_half(tdest, tsrca, tsrcb, HU, LS); |
1009 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
1010 | mnemonic = "mula_hu_ls"; | |
1011 | break; | |
8fd29dd7 | 1012 | case OE_RRR(MULA_HU_LU, 0, X0): |
4ff49775 RH |
1013 | gen_mul_half(tdest, tsrca, tsrcb, HU, LU); |
1014 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
1015 | mnemonic = "mula_hu_lu"; | |
1016 | break; | |
8fd29dd7 RH |
1017 | case OE_RRR(MULA_LS_LS, 0, X0): |
1018 | case OE_RRR(MULA_LS_LS, 9, Y0): | |
4ff49775 RH |
1019 | gen_mul_half(tdest, tsrca, tsrcb, LS, LS); |
1020 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
1021 | mnemonic = "mula_ls_ls"; | |
1022 | break; | |
8fd29dd7 | 1023 | case OE_RRR(MULA_LS_LU, 0, X0): |
4ff49775 RH |
1024 | gen_mul_half(tdest, tsrca, tsrcb, LS, LU); |
1025 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
1026 | mnemonic = "mula_ls_lu"; | |
1027 | break; | |
8fd29dd7 RH |
1028 | case OE_RRR(MULA_LU_LU, 0, X0): |
1029 | case OE_RRR(MULA_LU_LU, 9, Y0): | |
4ff49775 RH |
1030 | gen_mul_half(tdest, tsrca, tsrcb, LU, LU); |
1031 | tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest)); | |
1032 | mnemonic = "mula_lu_lu"; | |
1033 | break; | |
8fd29dd7 RH |
1034 | case OE_RRR(MULX, 0, X0): |
1035 | case OE_RRR(MULX, 3, Y0): | |
4ff49775 RH |
1036 | tcg_gen_mul_tl(tdest, tsrca, tsrcb); |
1037 | tcg_gen_ext32s_tl(tdest, tdest); | |
1038 | mnemonic = "mulx"; | |
1039 | break; | |
8fd29dd7 RH |
1040 | case OE_RRR(MUL_HS_HS, 0, X0): |
1041 | case OE_RRR(MUL_HS_HS, 8, Y0): | |
4ff49775 RH |
1042 | gen_mul_half(tdest, tsrca, tsrcb, HS, HS); |
1043 | mnemonic = "mul_hs_hs"; | |
1044 | break; | |
8fd29dd7 | 1045 | case OE_RRR(MUL_HS_HU, 0, X0): |
4ff49775 RH |
1046 | gen_mul_half(tdest, tsrca, tsrcb, HS, HU); |
1047 | mnemonic = "mul_hs_hu"; | |
1048 | break; | |
8fd29dd7 | 1049 | case OE_RRR(MUL_HS_LS, 0, X0): |
4ff49775 RH |
1050 | gen_mul_half(tdest, tsrca, tsrcb, HS, LS); |
1051 | mnemonic = "mul_hs_ls"; | |
1052 | break; | |
8fd29dd7 | 1053 | case OE_RRR(MUL_HS_LU, 0, X0): |
4ff49775 RH |
1054 | gen_mul_half(tdest, tsrca, tsrcb, HS, LU); |
1055 | mnemonic = "mul_hs_lu"; | |
1056 | break; | |
8fd29dd7 RH |
1057 | case OE_RRR(MUL_HU_HU, 0, X0): |
1058 | case OE_RRR(MUL_HU_HU, 8, Y0): | |
4ff49775 RH |
1059 | gen_mul_half(tdest, tsrca, tsrcb, HU, HU); |
1060 | mnemonic = "mul_hu_hu"; | |
1061 | break; | |
8fd29dd7 | 1062 | case OE_RRR(MUL_HU_LS, 0, X0): |
4ff49775 RH |
1063 | gen_mul_half(tdest, tsrca, tsrcb, HU, LS); |
1064 | mnemonic = "mul_hu_ls"; | |
1065 | break; | |
8fd29dd7 | 1066 | case OE_RRR(MUL_HU_LU, 0, X0): |
4ff49775 RH |
1067 | gen_mul_half(tdest, tsrca, tsrcb, HU, LU); |
1068 | mnemonic = "mul_hu_lu"; | |
1069 | break; | |
8fd29dd7 RH |
1070 | case OE_RRR(MUL_LS_LS, 0, X0): |
1071 | case OE_RRR(MUL_LS_LS, 8, Y0): | |
4ff49775 RH |
1072 | gen_mul_half(tdest, tsrca, tsrcb, LS, LS); |
1073 | mnemonic = "mul_ls_ls"; | |
1074 | break; | |
8fd29dd7 | 1075 | case OE_RRR(MUL_LS_LU, 0, X0): |
4ff49775 RH |
1076 | gen_mul_half(tdest, tsrca, tsrcb, LS, LU); |
1077 | mnemonic = "mul_ls_lu"; | |
1078 | break; | |
8fd29dd7 RH |
1079 | case OE_RRR(MUL_LU_LU, 0, X0): |
1080 | case OE_RRR(MUL_LU_LU, 8, Y0): | |
4ff49775 RH |
1081 | gen_mul_half(tdest, tsrca, tsrcb, LU, LU); |
1082 | mnemonic = "mul_lu_lu"; | |
1083 | break; | |
8fd29dd7 RH |
1084 | case OE_RRR(MZ, 0, X0): |
1085 | case OE_RRR(MZ, 0, X1): | |
1086 | case OE_RRR(MZ, 4, Y0): | |
1087 | case OE_RRR(MZ, 4, Y1): | |
661ff743 RH |
1088 | t0 = load_zero(dc); |
1089 | tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0); | |
1090 | mnemonic = "mz"; | |
1091 | break; | |
8fd29dd7 RH |
1092 | case OE_RRR(NOR, 0, X0): |
1093 | case OE_RRR(NOR, 0, X1): | |
1094 | case OE_RRR(NOR, 5, Y0): | |
1095 | case OE_RRR(NOR, 5, Y1): | |
a9fdfc7e RH |
1096 | tcg_gen_nor_tl(tdest, tsrca, tsrcb); |
1097 | mnemonic = "nor"; | |
1098 | break; | |
8fd29dd7 RH |
1099 | case OE_RRR(OR, 0, X0): |
1100 | case OE_RRR(OR, 0, X1): | |
1101 | case OE_RRR(OR, 5, Y0): | |
1102 | case OE_RRR(OR, 5, Y1): | |
a9fdfc7e RH |
1103 | tcg_gen_or_tl(tdest, tsrca, tsrcb); |
1104 | mnemonic = "or"; | |
1105 | break; | |
8fd29dd7 RH |
1106 | case OE_RRR(ROTL, 0, X0): |
1107 | case OE_RRR(ROTL, 0, X1): | |
1108 | case OE_RRR(ROTL, 6, Y0): | |
1109 | case OE_RRR(ROTL, 6, Y1): | |
2369976d RH |
1110 | tcg_gen_andi_tl(tdest, tsrcb, 63); |
1111 | tcg_gen_rotl_tl(tdest, tsrca, tdest); | |
1112 | mnemonic = "rotl"; | |
1113 | break; | |
8fd29dd7 RH |
1114 | case OE_RRR(SHL1ADDX, 0, X0): |
1115 | case OE_RRR(SHL1ADDX, 0, X1): | |
1116 | case OE_RRR(SHL1ADDX, 7, Y0): | |
1117 | case OE_RRR(SHL1ADDX, 7, Y1): | |
89b8c750 RH |
1118 | tcg_gen_shli_tl(tdest, tsrca, 1); |
1119 | tcg_gen_add_tl(tdest, tdest, tsrcb); | |
1120 | tcg_gen_ext32s_tl(tdest, tdest); | |
1121 | mnemonic = "shl1addx"; | |
1122 | break; | |
8fd29dd7 RH |
1123 | case OE_RRR(SHL1ADD, 0, X0): |
1124 | case OE_RRR(SHL1ADD, 0, X1): | |
1125 | case OE_RRR(SHL1ADD, 1, Y0): | |
1126 | case OE_RRR(SHL1ADD, 1, Y1): | |
89b8c750 RH |
1127 | tcg_gen_shli_tl(tdest, tsrca, 1); |
1128 | tcg_gen_add_tl(tdest, tdest, tsrcb); | |
1129 | mnemonic = "shl1add"; | |
1130 | break; | |
8fd29dd7 RH |
1131 | case OE_RRR(SHL2ADDX, 0, X0): |
1132 | case OE_RRR(SHL2ADDX, 0, X1): | |
1133 | case OE_RRR(SHL2ADDX, 7, Y0): | |
1134 | case OE_RRR(SHL2ADDX, 7, Y1): | |
89b8c750 RH |
1135 | tcg_gen_shli_tl(tdest, tsrca, 2); |
1136 | tcg_gen_add_tl(tdest, tdest, tsrcb); | |
1137 | tcg_gen_ext32s_tl(tdest, tdest); | |
1138 | mnemonic = "shl2addx"; | |
1139 | break; | |
8fd29dd7 RH |
1140 | case OE_RRR(SHL2ADD, 0, X0): |
1141 | case OE_RRR(SHL2ADD, 0, X1): | |
1142 | case OE_RRR(SHL2ADD, 1, Y0): | |
1143 | case OE_RRR(SHL2ADD, 1, Y1): | |
89b8c750 RH |
1144 | tcg_gen_shli_tl(tdest, tsrca, 2); |
1145 | tcg_gen_add_tl(tdest, tdest, tsrcb); | |
1146 | mnemonic = "shl2add"; | |
1147 | break; | |
8fd29dd7 RH |
1148 | case OE_RRR(SHL3ADDX, 0, X0): |
1149 | case OE_RRR(SHL3ADDX, 0, X1): | |
1150 | case OE_RRR(SHL3ADDX, 7, Y0): | |
1151 | case OE_RRR(SHL3ADDX, 7, Y1): | |
89b8c750 RH |
1152 | tcg_gen_shli_tl(tdest, tsrca, 3); |
1153 | tcg_gen_add_tl(tdest, tdest, tsrcb); | |
1154 | tcg_gen_ext32s_tl(tdest, tdest); | |
1155 | mnemonic = "shl3addx"; | |
1156 | break; | |
8fd29dd7 RH |
1157 | case OE_RRR(SHL3ADD, 0, X0): |
1158 | case OE_RRR(SHL3ADD, 0, X1): | |
1159 | case OE_RRR(SHL3ADD, 1, Y0): | |
1160 | case OE_RRR(SHL3ADD, 1, Y1): | |
89b8c750 RH |
1161 | tcg_gen_shli_tl(tdest, tsrca, 3); |
1162 | tcg_gen_add_tl(tdest, tdest, tsrcb); | |
1163 | mnemonic = "shl3add"; | |
1164 | break; | |
8fd29dd7 RH |
1165 | case OE_RRR(SHLX, 0, X0): |
1166 | case OE_RRR(SHLX, 0, X1): | |
2369976d RH |
1167 | tcg_gen_andi_tl(tdest, tsrcb, 31); |
1168 | tcg_gen_shl_tl(tdest, tsrca, tdest); | |
1169 | tcg_gen_ext32s_tl(tdest, tdest); | |
1170 | mnemonic = "shlx"; | |
1171 | break; | |
8fd29dd7 RH |
1172 | case OE_RRR(SHL, 0, X0): |
1173 | case OE_RRR(SHL, 0, X1): | |
1174 | case OE_RRR(SHL, 6, Y0): | |
1175 | case OE_RRR(SHL, 6, Y1): | |
2369976d RH |
1176 | tcg_gen_andi_tl(tdest, tsrcb, 63); |
1177 | tcg_gen_shl_tl(tdest, tsrca, tdest); | |
1178 | mnemonic = "shl"; | |
1179 | break; | |
8fd29dd7 RH |
1180 | case OE_RRR(SHRS, 0, X0): |
1181 | case OE_RRR(SHRS, 0, X1): | |
1182 | case OE_RRR(SHRS, 6, Y0): | |
1183 | case OE_RRR(SHRS, 6, Y1): | |
2369976d RH |
1184 | tcg_gen_andi_tl(tdest, tsrcb, 63); |
1185 | tcg_gen_sar_tl(tdest, tsrca, tdest); | |
1186 | mnemonic = "shrs"; | |
1187 | break; | |
8fd29dd7 RH |
1188 | case OE_RRR(SHRUX, 0, X0): |
1189 | case OE_RRR(SHRUX, 0, X1): | |
2369976d RH |
1190 | t0 = tcg_temp_new(); |
1191 | tcg_gen_andi_tl(t0, tsrcb, 31); | |
1192 | tcg_gen_ext32u_tl(tdest, tsrca); | |
1193 | tcg_gen_shr_tl(tdest, tdest, t0); | |
1194 | tcg_gen_ext32s_tl(tdest, tdest); | |
1195 | tcg_temp_free(t0); | |
1196 | mnemonic = "shrux"; | |
1197 | break; | |
8fd29dd7 RH |
1198 | case OE_RRR(SHRU, 0, X0): |
1199 | case OE_RRR(SHRU, 0, X1): | |
1200 | case OE_RRR(SHRU, 6, Y0): | |
1201 | case OE_RRR(SHRU, 6, Y1): | |
2369976d RH |
1202 | tcg_gen_andi_tl(tdest, tsrcb, 63); |
1203 | tcg_gen_shr_tl(tdest, tsrca, tdest); | |
1204 | mnemonic = "shru"; | |
1205 | break; | |
8fd29dd7 | 1206 | case OE_RRR(SHUFFLEBYTES, 0, X0): |
7f41a8d6 RH |
1207 | gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca); |
1208 | mnemonic = "shufflebytes"; | |
1209 | break; | |
8fd29dd7 RH |
1210 | case OE_RRR(SUBXSC, 0, X0): |
1211 | case OE_RRR(SUBXSC, 0, X1): | |
89b8c750 RH |
1212 | gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl); |
1213 | mnemonic = "subxsc"; | |
1214 | break; | |
8fd29dd7 RH |
1215 | case OE_RRR(SUBX, 0, X0): |
1216 | case OE_RRR(SUBX, 0, X1): | |
1217 | case OE_RRR(SUBX, 0, Y0): | |
1218 | case OE_RRR(SUBX, 0, Y1): | |
89b8c750 RH |
1219 | tcg_gen_sub_tl(tdest, tsrca, tsrcb); |
1220 | tcg_gen_ext32s_tl(tdest, tdest); | |
1221 | mnemonic = "subx"; | |
1222 | break; | |
8fd29dd7 RH |
1223 | case OE_RRR(SUB, 0, X0): |
1224 | case OE_RRR(SUB, 0, X1): | |
1225 | case OE_RRR(SUB, 0, Y0): | |
1226 | case OE_RRR(SUB, 0, Y1): | |
89b8c750 RH |
1227 | tcg_gen_sub_tl(tdest, tsrca, tsrcb); |
1228 | mnemonic = "sub"; | |
1229 | break; | |
8fd29dd7 RH |
1230 | case OE_RRR(V1ADDUC, 0, X0): |
1231 | case OE_RRR(V1ADDUC, 0, X1): | |
c6876d7e | 1232 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1233 | case OE_RRR(V1ADD, 0, X0): |
1234 | case OE_RRR(V1ADD, 0, X1): | |
c6876d7e CG |
1235 | gen_v12add(tdest, tsrca, tsrcb, V1_IMM(0x80)); |
1236 | mnemonic = "v1add"; | |
1237 | break; | |
8fd29dd7 RH |
1238 | case OE_RRR(V1ADIFFU, 0, X0): |
1239 | case OE_RRR(V1AVGU, 0, X0): | |
e7346cf0 | 1240 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1241 | case OE_RRR(V1CMPEQ, 0, X0): |
1242 | case OE_RRR(V1CMPEQ, 0, X1): | |
e7346cf0 RH |
1243 | tcg_gen_xor_tl(tdest, tsrca, tsrcb); |
1244 | gen_v1cmpeq0(tdest); | |
1245 | mnemonic = "v1cmpeq"; | |
1246 | break; | |
8fd29dd7 RH |
1247 | case OE_RRR(V1CMPLES, 0, X0): |
1248 | case OE_RRR(V1CMPLES, 0, X1): | |
1249 | case OE_RRR(V1CMPLEU, 0, X0): | |
1250 | case OE_RRR(V1CMPLEU, 0, X1): | |
1251 | case OE_RRR(V1CMPLTS, 0, X0): | |
1252 | case OE_RRR(V1CMPLTS, 0, X1): | |
1253 | case OE_RRR(V1CMPLTU, 0, X0): | |
1254 | case OE_RRR(V1CMPLTU, 0, X1): | |
e7346cf0 | 1255 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1256 | case OE_RRR(V1CMPNE, 0, X0): |
1257 | case OE_RRR(V1CMPNE, 0, X1): | |
e7346cf0 RH |
1258 | tcg_gen_xor_tl(tdest, tsrca, tsrcb); |
1259 | gen_v1cmpne0(tdest); | |
1260 | mnemonic = "v1cmpne"; | |
1261 | break; | |
8fd29dd7 RH |
1262 | case OE_RRR(V1DDOTPUA, 0, X0): |
1263 | case OE_RRR(V1DDOTPUSA, 0, X0): | |
1264 | case OE_RRR(V1DDOTPUS, 0, X0): | |
1265 | case OE_RRR(V1DDOTPU, 0, X0): | |
1266 | case OE_RRR(V1DOTPA, 0, X0): | |
1267 | case OE_RRR(V1DOTPUA, 0, X0): | |
1268 | case OE_RRR(V1DOTPUSA, 0, X0): | |
1269 | case OE_RRR(V1DOTPUS, 0, X0): | |
1270 | case OE_RRR(V1DOTPU, 0, X0): | |
1271 | case OE_RRR(V1DOTP, 0, X0): | |
aaf893a6 | 1272 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1273 | case OE_RRR(V1INT_H, 0, X0): |
1274 | case OE_RRR(V1INT_H, 0, X1): | |
aaf893a6 CG |
1275 | gen_helper_v1int_h(tdest, tsrca, tsrcb); |
1276 | mnemonic = "v1int_h"; | |
1277 | break; | |
8fd29dd7 RH |
1278 | case OE_RRR(V1INT_L, 0, X0): |
1279 | case OE_RRR(V1INT_L, 0, X1): | |
aaf893a6 CG |
1280 | gen_helper_v1int_l(tdest, tsrca, tsrcb); |
1281 | mnemonic = "v1int_l"; | |
1282 | break; | |
8fd29dd7 RH |
1283 | case OE_RRR(V1MAXU, 0, X0): |
1284 | case OE_RRR(V1MAXU, 0, X1): | |
1285 | case OE_RRR(V1MINU, 0, X0): | |
1286 | case OE_RRR(V1MINU, 0, X1): | |
1287 | case OE_RRR(V1MNZ, 0, X0): | |
1288 | case OE_RRR(V1MNZ, 0, X1): | |
38c949ff | 1289 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 | 1290 | case OE_RRR(V1MULTU, 0, X0): |
38c949ff CG |
1291 | gen_helper_v1multu(tdest, tsrca, tsrcb); |
1292 | mnemonic = "v1multu"; | |
1293 | break; | |
8fd29dd7 RH |
1294 | case OE_RRR(V1MULUS, 0, X0): |
1295 | case OE_RRR(V1MULU, 0, X0): | |
1296 | case OE_RRR(V1MZ, 0, X0): | |
1297 | case OE_RRR(V1MZ, 0, X1): | |
1298 | case OE_RRR(V1SADAU, 0, X0): | |
1299 | case OE_RRR(V1SADU, 0, X0): | |
461aa678 | 1300 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1301 | case OE_RRR(V1SHL, 0, X0): |
1302 | case OE_RRR(V1SHL, 0, X1): | |
461aa678 RH |
1303 | gen_helper_v1shl(tdest, tsrca, tsrcb); |
1304 | mnemonic = "v1shl"; | |
1305 | break; | |
8fd29dd7 RH |
1306 | case OE_RRR(V1SHRS, 0, X0): |
1307 | case OE_RRR(V1SHRS, 0, X1): | |
461aa678 RH |
1308 | gen_helper_v1shrs(tdest, tsrca, tsrcb); |
1309 | mnemonic = "v1shrs"; | |
1310 | break; | |
8fd29dd7 RH |
1311 | case OE_RRR(V1SHRU, 0, X0): |
1312 | case OE_RRR(V1SHRU, 0, X1): | |
461aa678 RH |
1313 | gen_helper_v1shru(tdest, tsrca, tsrcb); |
1314 | mnemonic = "v1shru"; | |
1315 | break; | |
8fd29dd7 RH |
1316 | case OE_RRR(V1SUBUC, 0, X0): |
1317 | case OE_RRR(V1SUBUC, 0, X1): | |
c6876d7e | 1318 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1319 | case OE_RRR(V1SUB, 0, X0): |
1320 | case OE_RRR(V1SUB, 0, X1): | |
c6876d7e CG |
1321 | gen_v12sub(tdest, tsrca, tsrcb, V1_IMM(0x80)); |
1322 | mnemonic = "v1sub"; | |
1323 | break; | |
8fd29dd7 RH |
1324 | case OE_RRR(V2ADDSC, 0, X0): |
1325 | case OE_RRR(V2ADDSC, 0, X1): | |
c6876d7e | 1326 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1327 | case OE_RRR(V2ADD, 0, X0): |
1328 | case OE_RRR(V2ADD, 0, X1): | |
c6876d7e CG |
1329 | gen_v12add(tdest, tsrca, tsrcb, V2_IMM(0x8000)); |
1330 | mnemonic = "v2add"; | |
1331 | break; | |
8fd29dd7 RH |
1332 | case OE_RRR(V2ADIFFS, 0, X0): |
1333 | case OE_RRR(V2AVGS, 0, X0): | |
1334 | case OE_RRR(V2CMPEQ, 0, X0): | |
1335 | case OE_RRR(V2CMPEQ, 0, X1): | |
1336 | case OE_RRR(V2CMPLES, 0, X0): | |
1337 | case OE_RRR(V2CMPLES, 0, X1): | |
1338 | case OE_RRR(V2CMPLEU, 0, X0): | |
1339 | case OE_RRR(V2CMPLEU, 0, X1): | |
1340 | case OE_RRR(V2CMPLTS, 0, X0): | |
1341 | case OE_RRR(V2CMPLTS, 0, X1): | |
1342 | case OE_RRR(V2CMPLTU, 0, X0): | |
1343 | case OE_RRR(V2CMPLTU, 0, X1): | |
1344 | case OE_RRR(V2CMPNE, 0, X0): | |
1345 | case OE_RRR(V2CMPNE, 0, X1): | |
1346 | case OE_RRR(V2DOTPA, 0, X0): | |
1347 | case OE_RRR(V2DOTP, 0, X0): | |
aaf893a6 | 1348 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1349 | case OE_RRR(V2INT_H, 0, X0): |
1350 | case OE_RRR(V2INT_H, 0, X1): | |
aaf893a6 CG |
1351 | gen_helper_v2int_h(tdest, tsrca, tsrcb); |
1352 | mnemonic = "v2int_h"; | |
1353 | break; | |
8fd29dd7 RH |
1354 | case OE_RRR(V2INT_L, 0, X0): |
1355 | case OE_RRR(V2INT_L, 0, X1): | |
aaf893a6 CG |
1356 | gen_helper_v2int_l(tdest, tsrca, tsrcb); |
1357 | mnemonic = "v2int_l"; | |
1358 | break; | |
8fd29dd7 RH |
1359 | case OE_RRR(V2MAXS, 0, X0): |
1360 | case OE_RRR(V2MAXS, 0, X1): | |
1361 | case OE_RRR(V2MINS, 0, X0): | |
1362 | case OE_RRR(V2MINS, 0, X1): | |
1363 | case OE_RRR(V2MNZ, 0, X0): | |
1364 | case OE_RRR(V2MNZ, 0, X1): | |
1365 | case OE_RRR(V2MULFSC, 0, X0): | |
1366 | case OE_RRR(V2MULS, 0, X0): | |
a419e22d | 1367 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 | 1368 | case OE_RRR(V2MULTS, 0, X0): |
a419e22d CG |
1369 | gen_helper_v2mults(tdest, tsrca, tsrcb); |
1370 | mnemonic = "v2mults"; | |
1371 | break; | |
8fd29dd7 RH |
1372 | case OE_RRR(V2MZ, 0, X0): |
1373 | case OE_RRR(V2MZ, 0, X1): | |
1374 | case OE_RRR(V2PACKH, 0, X0): | |
1375 | case OE_RRR(V2PACKH, 0, X1): | |
1376 | case OE_RRR(V2PACKL, 0, X0): | |
1377 | case OE_RRR(V2PACKL, 0, X1): | |
1378 | case OE_RRR(V2PACKUC, 0, X0): | |
1379 | case OE_RRR(V2PACKUC, 0, X1): | |
1380 | case OE_RRR(V2SADAS, 0, X0): | |
1381 | case OE_RRR(V2SADAU, 0, X0): | |
1382 | case OE_RRR(V2SADS, 0, X0): | |
1383 | case OE_RRR(V2SADU, 0, X0): | |
1384 | case OE_RRR(V2SHLSC, 0, X0): | |
1385 | case OE_RRR(V2SHLSC, 0, X1): | |
0ab0a3d7 | 1386 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1387 | case OE_RRR(V2SHL, 0, X0): |
1388 | case OE_RRR(V2SHL, 0, X1): | |
0ab0a3d7 CG |
1389 | gen_helper_v2shl(tdest, tsrca, tsrcb); |
1390 | mnemonic = "v2shl"; | |
1391 | break; | |
8fd29dd7 RH |
1392 | case OE_RRR(V2SHRS, 0, X0): |
1393 | case OE_RRR(V2SHRS, 0, X1): | |
0ab0a3d7 CG |
1394 | gen_helper_v2shrs(tdest, tsrca, tsrcb); |
1395 | mnemonic = "v2shrs"; | |
1396 | break; | |
8fd29dd7 RH |
1397 | case OE_RRR(V2SHRU, 0, X0): |
1398 | case OE_RRR(V2SHRU, 0, X1): | |
0ab0a3d7 CG |
1399 | gen_helper_v2shru(tdest, tsrca, tsrcb); |
1400 | mnemonic = "v2shru"; | |
1401 | break; | |
8fd29dd7 RH |
1402 | case OE_RRR(V2SUBSC, 0, X0): |
1403 | case OE_RRR(V2SUBSC, 0, X1): | |
c6876d7e | 1404 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1405 | case OE_RRR(V2SUB, 0, X0): |
1406 | case OE_RRR(V2SUB, 0, X1): | |
c6876d7e CG |
1407 | gen_v12sub(tdest, tsrca, tsrcb, V2_IMM(0x8000)); |
1408 | mnemonic = "v2sub"; | |
1409 | break; | |
8fd29dd7 RH |
1410 | case OE_RRR(V4ADDSC, 0, X0): |
1411 | case OE_RRR(V4ADDSC, 0, X1): | |
c6876d7e | 1412 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1413 | case OE_RRR(V4ADD, 0, X0): |
1414 | case OE_RRR(V4ADD, 0, X1): | |
c6876d7e CG |
1415 | gen_v4op(tdest, tsrca, tsrcb, tcg_gen_add_i32); |
1416 | mnemonic = "v4add"; | |
1417 | break; | |
8fd29dd7 RH |
1418 | case OE_RRR(V4INT_H, 0, X0): |
1419 | case OE_RRR(V4INT_H, 0, X1): | |
5151c69a RH |
1420 | tcg_gen_shri_tl(tdest, tsrcb, 32); |
1421 | tcg_gen_deposit_tl(tdest, tsrca, tdest, 0, 32); | |
1422 | mnemonic = "v4int_h"; | |
1423 | break; | |
8fd29dd7 RH |
1424 | case OE_RRR(V4INT_L, 0, X0): |
1425 | case OE_RRR(V4INT_L, 0, X1): | |
5151c69a RH |
1426 | tcg_gen_deposit_tl(tdest, tsrcb, tsrca, 32, 32); |
1427 | mnemonic = "v4int_l"; | |
1428 | break; | |
8fd29dd7 RH |
1429 | case OE_RRR(V4PACKSC, 0, X0): |
1430 | case OE_RRR(V4PACKSC, 0, X1): | |
1431 | case OE_RRR(V4SHLSC, 0, X0): | |
1432 | case OE_RRR(V4SHLSC, 0, X1): | |
0ab0a3d7 | 1433 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1434 | case OE_RRR(V4SHL, 0, X0): |
1435 | case OE_RRR(V4SHL, 0, X1): | |
0ab0a3d7 CG |
1436 | gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shl_i32); |
1437 | mnemonic = "v4shl"; | |
1438 | break; | |
8fd29dd7 RH |
1439 | case OE_RRR(V4SHRS, 0, X0): |
1440 | case OE_RRR(V4SHRS, 0, X1): | |
0ab0a3d7 CG |
1441 | gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_sar_i32); |
1442 | mnemonic = "v4shrs"; | |
1443 | break; | |
8fd29dd7 RH |
1444 | case OE_RRR(V4SHRU, 0, X0): |
1445 | case OE_RRR(V4SHRU, 0, X1): | |
0ab0a3d7 CG |
1446 | gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shr_i32); |
1447 | mnemonic = "v4shru"; | |
1448 | break; | |
8fd29dd7 RH |
1449 | case OE_RRR(V4SUBSC, 0, X0): |
1450 | case OE_RRR(V4SUBSC, 0, X1): | |
c6876d7e | 1451 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1452 | case OE_RRR(V4SUB, 0, X0): |
1453 | case OE_RRR(V4SUB, 0, X1): | |
c6876d7e CG |
1454 | gen_v4op(tdest, tsrca, tsrcb, tcg_gen_sub_i32); |
1455 | mnemonic = "v2sub"; | |
1456 | break; | |
8fd29dd7 RH |
1457 | case OE_RRR(XOR, 0, X0): |
1458 | case OE_RRR(XOR, 0, X1): | |
1459 | case OE_RRR(XOR, 5, Y0): | |
1460 | case OE_RRR(XOR, 5, Y1): | |
a9fdfc7e RH |
1461 | tcg_gen_xor_tl(tdest, tsrca, tsrcb); |
1462 | mnemonic = "xor"; | |
1463 | break; | |
8fd29dd7 | 1464 | default: |
77b3adc0 | 1465 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
1466 | } |
1467 | ||
1468 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic, | |
1469 | reg_names[dest], reg_names[srca], reg_names[srcb]); | |
1470 | return TILEGX_EXCP_NONE; | |
1471 | } | |
1472 | ||
1473 | static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext, | |
1474 | unsigned dest, unsigned srca, int imm) | |
1475 | { | |
a9fdfc7e RH |
1476 | TCGv tdest = dest_gr(dc, dest); |
1477 | TCGv tsrca = load_gr(dc, srca); | |
133b84c8 | 1478 | bool prefetch_nofault = false; |
8fd29dd7 | 1479 | const char *mnemonic; |
01cd675c | 1480 | TCGMemOp memop; |
3be19e8c | 1481 | int i2, i3; |
461aa678 | 1482 | TCGv t0; |
8fd29dd7 RH |
1483 | |
1484 | switch (opext) { | |
89b8c750 RH |
1485 | case OE(ADDI_OPCODE_Y0, 0, Y0): |
1486 | case OE(ADDI_OPCODE_Y1, 0, Y1): | |
8fd29dd7 RH |
1487 | case OE_IM(ADDI, X0): |
1488 | case OE_IM(ADDI, X1): | |
89b8c750 RH |
1489 | tcg_gen_addi_tl(tdest, tsrca, imm); |
1490 | mnemonic = "addi"; | |
1491 | break; | |
1492 | case OE(ADDXI_OPCODE_Y0, 0, Y0): | |
1493 | case OE(ADDXI_OPCODE_Y1, 0, Y1): | |
8fd29dd7 RH |
1494 | case OE_IM(ADDXI, X0): |
1495 | case OE_IM(ADDXI, X1): | |
89b8c750 RH |
1496 | tcg_gen_addi_tl(tdest, tsrca, imm); |
1497 | tcg_gen_ext32s_tl(tdest, tdest); | |
1498 | mnemonic = "addxi"; | |
1499 | break; | |
a9fdfc7e RH |
1500 | case OE(ANDI_OPCODE_Y0, 0, Y0): |
1501 | case OE(ANDI_OPCODE_Y1, 0, Y1): | |
8fd29dd7 RH |
1502 | case OE_IM(ANDI, X0): |
1503 | case OE_IM(ANDI, X1): | |
a9fdfc7e RH |
1504 | tcg_gen_andi_tl(tdest, tsrca, imm); |
1505 | mnemonic = "andi"; | |
1506 | break; | |
73c54377 RH |
1507 | case OE(CMPEQI_OPCODE_Y0, 0, Y0): |
1508 | case OE(CMPEQI_OPCODE_Y1, 0, Y1): | |
8fd29dd7 RH |
1509 | case OE_IM(CMPEQI, X0): |
1510 | case OE_IM(CMPEQI, X1): | |
73c54377 RH |
1511 | tcg_gen_setcondi_tl(TCG_COND_EQ, tdest, tsrca, imm); |
1512 | mnemonic = "cmpeqi"; | |
1513 | break; | |
1514 | case OE(CMPLTSI_OPCODE_Y0, 0, Y0): | |
1515 | case OE(CMPLTSI_OPCODE_Y1, 0, Y1): | |
8fd29dd7 RH |
1516 | case OE_IM(CMPLTSI, X0): |
1517 | case OE_IM(CMPLTSI, X1): | |
73c54377 RH |
1518 | tcg_gen_setcondi_tl(TCG_COND_LT, tdest, tsrca, imm); |
1519 | mnemonic = "cmpltsi"; | |
1520 | break; | |
8fd29dd7 RH |
1521 | case OE_IM(CMPLTUI, X0): |
1522 | case OE_IM(CMPLTUI, X1): | |
73c54377 RH |
1523 | tcg_gen_setcondi_tl(TCG_COND_LTU, tdest, tsrca, imm); |
1524 | mnemonic = "cmpltui"; | |
1525 | break; | |
8fd29dd7 | 1526 | case OE_IM(LD1S_ADD, X1): |
01cd675c | 1527 | memop = MO_SB; |
133b84c8 | 1528 | mnemonic = "ld1s_add"; /* prefetch_add_l1_fault */ |
01cd675c | 1529 | goto do_load_add; |
8fd29dd7 | 1530 | case OE_IM(LD1U_ADD, X1): |
01cd675c | 1531 | memop = MO_UB; |
133b84c8 RH |
1532 | mnemonic = "ld1u_add"; /* prefetch_add_l1 */ |
1533 | prefetch_nofault = (dest == TILEGX_R_ZERO); | |
01cd675c | 1534 | goto do_load_add; |
8fd29dd7 | 1535 | case OE_IM(LD2S_ADD, X1): |
01cd675c | 1536 | memop = MO_TESW; |
133b84c8 | 1537 | mnemonic = "ld2s_add"; /* prefetch_add_l2_fault */ |
01cd675c | 1538 | goto do_load_add; |
8fd29dd7 | 1539 | case OE_IM(LD2U_ADD, X1): |
01cd675c | 1540 | memop = MO_TEUW; |
133b84c8 RH |
1541 | mnemonic = "ld2u_add"; /* prefetch_add_l2 */ |
1542 | prefetch_nofault = (dest == TILEGX_R_ZERO); | |
01cd675c | 1543 | goto do_load_add; |
8fd29dd7 | 1544 | case OE_IM(LD4S_ADD, X1): |
01cd675c | 1545 | memop = MO_TESL; |
133b84c8 | 1546 | mnemonic = "ld4s_add"; /* prefetch_add_l3_fault */ |
01cd675c | 1547 | goto do_load_add; |
8fd29dd7 | 1548 | case OE_IM(LD4U_ADD, X1): |
01cd675c | 1549 | memop = MO_TEUL; |
133b84c8 RH |
1550 | mnemonic = "ld4u_add"; /* prefetch_add_l3 */ |
1551 | prefetch_nofault = (dest == TILEGX_R_ZERO); | |
01cd675c | 1552 | goto do_load_add; |
8fd29dd7 | 1553 | case OE_IM(LDNT1S_ADD, X1): |
01cd675c RH |
1554 | memop = MO_SB; |
1555 | mnemonic = "ldnt1s_add"; | |
1556 | goto do_load_add; | |
8fd29dd7 | 1557 | case OE_IM(LDNT1U_ADD, X1): |
01cd675c RH |
1558 | memop = MO_UB; |
1559 | mnemonic = "ldnt1u_add"; | |
1560 | goto do_load_add; | |
8fd29dd7 | 1561 | case OE_IM(LDNT2S_ADD, X1): |
01cd675c RH |
1562 | memop = MO_TESW; |
1563 | mnemonic = "ldnt2s_add"; | |
1564 | goto do_load_add; | |
8fd29dd7 | 1565 | case OE_IM(LDNT2U_ADD, X1): |
01cd675c RH |
1566 | memop = MO_TEUW; |
1567 | mnemonic = "ldnt2u_add"; | |
1568 | goto do_load_add; | |
8fd29dd7 | 1569 | case OE_IM(LDNT4S_ADD, X1): |
01cd675c RH |
1570 | memop = MO_TESL; |
1571 | mnemonic = "ldnt4s_add"; | |
1572 | goto do_load_add; | |
8fd29dd7 | 1573 | case OE_IM(LDNT4U_ADD, X1): |
01cd675c RH |
1574 | memop = MO_TEUL; |
1575 | mnemonic = "ldnt4u_add"; | |
1576 | goto do_load_add; | |
8fd29dd7 | 1577 | case OE_IM(LDNT_ADD, X1): |
01cd675c RH |
1578 | memop = MO_TEQ; |
1579 | mnemonic = "ldnt_add"; | |
1580 | goto do_load_add; | |
8fd29dd7 | 1581 | case OE_IM(LD_ADD, X1): |
01cd675c | 1582 | memop = MO_TEQ; |
95df61e6 | 1583 | mnemonic = "ld_add"; |
01cd675c | 1584 | do_load_add: |
133b84c8 RH |
1585 | if (!prefetch_nofault) { |
1586 | tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop); | |
1587 | } | |
01cd675c RH |
1588 | tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm); |
1589 | break; | |
8fd29dd7 | 1590 | case OE_IM(LDNA_ADD, X1): |
01cd675c RH |
1591 | tcg_gen_andi_tl(tdest, tsrca, ~7); |
1592 | tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ); | |
1593 | tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm); | |
1594 | mnemonic = "ldna_add"; | |
1595 | break; | |
8fd29dd7 RH |
1596 | case OE_IM(ORI, X0): |
1597 | case OE_IM(ORI, X1): | |
a9fdfc7e RH |
1598 | tcg_gen_ori_tl(tdest, tsrca, imm); |
1599 | mnemonic = "ori"; | |
1600 | break; | |
8fd29dd7 RH |
1601 | case OE_IM(V1ADDI, X0): |
1602 | case OE_IM(V1ADDI, X1): | |
c6876d7e CG |
1603 | t0 = tcg_const_tl(V1_IMM(imm)); |
1604 | gen_v12add(tdest, tsrca, t0, V1_IMM(0x80)); | |
1605 | tcg_temp_free(t0); | |
1606 | mnemonic = "v1addi"; | |
1607 | break; | |
8fd29dd7 RH |
1608 | case OE_IM(V1CMPEQI, X0): |
1609 | case OE_IM(V1CMPEQI, X1): | |
e7346cf0 RH |
1610 | tcg_gen_xori_tl(tdest, tsrca, V1_IMM(imm)); |
1611 | gen_v1cmpeq0(tdest); | |
1612 | mnemonic = "v1cmpeqi"; | |
1613 | break; | |
8fd29dd7 RH |
1614 | case OE_IM(V1CMPLTSI, X0): |
1615 | case OE_IM(V1CMPLTSI, X1): | |
1616 | case OE_IM(V1CMPLTUI, X0): | |
1617 | case OE_IM(V1CMPLTUI, X1): | |
1618 | case OE_IM(V1MAXUI, X0): | |
1619 | case OE_IM(V1MAXUI, X1): | |
1620 | case OE_IM(V1MINUI, X0): | |
1621 | case OE_IM(V1MINUI, X1): | |
c6876d7e | 1622 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1623 | case OE_IM(V2ADDI, X0): |
1624 | case OE_IM(V2ADDI, X1): | |
c6876d7e CG |
1625 | t0 = tcg_const_tl(V2_IMM(imm)); |
1626 | gen_v12add(tdest, tsrca, t0, V2_IMM(0x8000)); | |
1627 | tcg_temp_free(t0); | |
1628 | mnemonic = "v2addi"; | |
1629 | break; | |
8fd29dd7 RH |
1630 | case OE_IM(V2CMPEQI, X0): |
1631 | case OE_IM(V2CMPEQI, X1): | |
1632 | case OE_IM(V2CMPLTSI, X0): | |
1633 | case OE_IM(V2CMPLTSI, X1): | |
1634 | case OE_IM(V2CMPLTUI, X0): | |
1635 | case OE_IM(V2CMPLTUI, X1): | |
1636 | case OE_IM(V2MAXSI, X0): | |
1637 | case OE_IM(V2MAXSI, X1): | |
1638 | case OE_IM(V2MINSI, X0): | |
1639 | case OE_IM(V2MINSI, X1): | |
a9fdfc7e | 1640 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
8fd29dd7 RH |
1641 | case OE_IM(XORI, X0): |
1642 | case OE_IM(XORI, X1): | |
a9fdfc7e RH |
1643 | tcg_gen_xori_tl(tdest, tsrca, imm); |
1644 | mnemonic = "xori"; | |
1645 | break; | |
8fd29dd7 RH |
1646 | |
1647 | case OE_SH(ROTLI, X0): | |
1648 | case OE_SH(ROTLI, X1): | |
1649 | case OE_SH(ROTLI, Y0): | |
1650 | case OE_SH(ROTLI, Y1): | |
2369976d RH |
1651 | tcg_gen_rotli_tl(tdest, tsrca, imm); |
1652 | mnemonic = "rotli"; | |
1653 | break; | |
8fd29dd7 RH |
1654 | case OE_SH(SHLI, X0): |
1655 | case OE_SH(SHLI, X1): | |
1656 | case OE_SH(SHLI, Y0): | |
1657 | case OE_SH(SHLI, Y1): | |
2369976d RH |
1658 | tcg_gen_shli_tl(tdest, tsrca, imm); |
1659 | mnemonic = "shli"; | |
1660 | break; | |
8fd29dd7 RH |
1661 | case OE_SH(SHLXI, X0): |
1662 | case OE_SH(SHLXI, X1): | |
2369976d RH |
1663 | tcg_gen_shli_tl(tdest, tsrca, imm & 31); |
1664 | tcg_gen_ext32s_tl(tdest, tdest); | |
1665 | mnemonic = "shlxi"; | |
1666 | break; | |
8fd29dd7 RH |
1667 | case OE_SH(SHRSI, X0): |
1668 | case OE_SH(SHRSI, X1): | |
1669 | case OE_SH(SHRSI, Y0): | |
1670 | case OE_SH(SHRSI, Y1): | |
2369976d RH |
1671 | tcg_gen_sari_tl(tdest, tsrca, imm); |
1672 | mnemonic = "shrsi"; | |
1673 | break; | |
8fd29dd7 RH |
1674 | case OE_SH(SHRUI, X0): |
1675 | case OE_SH(SHRUI, X1): | |
1676 | case OE_SH(SHRUI, Y0): | |
1677 | case OE_SH(SHRUI, Y1): | |
2369976d RH |
1678 | tcg_gen_shri_tl(tdest, tsrca, imm); |
1679 | mnemonic = "shrui"; | |
1680 | break; | |
8fd29dd7 RH |
1681 | case OE_SH(SHRUXI, X0): |
1682 | case OE_SH(SHRUXI, X1): | |
2369976d RH |
1683 | if ((imm & 31) == 0) { |
1684 | tcg_gen_ext32s_tl(tdest, tsrca); | |
1685 | } else { | |
1686 | tcg_gen_ext32u_tl(tdest, tsrca); | |
1687 | tcg_gen_shri_tl(tdest, tdest, imm & 31); | |
1688 | } | |
1689 | mnemonic = "shlxi"; | |
1690 | break; | |
8fd29dd7 RH |
1691 | case OE_SH(V1SHLI, X0): |
1692 | case OE_SH(V1SHLI, X1): | |
3be19e8c RH |
1693 | i2 = imm & 7; |
1694 | i3 = 0xff >> i2; | |
1695 | tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3)); | |
1696 | tcg_gen_shli_tl(tdest, tdest, i2); | |
1697 | mnemonic = "v1shli"; | |
1698 | break; | |
8fd29dd7 RH |
1699 | case OE_SH(V1SHRSI, X0): |
1700 | case OE_SH(V1SHRSI, X1): | |
461aa678 RH |
1701 | t0 = tcg_const_tl(imm & 7); |
1702 | gen_helper_v1shrs(tdest, tsrca, t0); | |
1703 | tcg_temp_free(t0); | |
1704 | mnemonic = "v1shrsi"; | |
1705 | break; | |
8fd29dd7 RH |
1706 | case OE_SH(V1SHRUI, X0): |
1707 | case OE_SH(V1SHRUI, X1): | |
3be19e8c RH |
1708 | i2 = imm & 7; |
1709 | i3 = (0xff << i2) & 0xff; | |
1710 | tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3)); | |
1711 | tcg_gen_shri_tl(tdest, tdest, i2); | |
1712 | mnemonic = "v1shrui"; | |
1713 | break; | |
8fd29dd7 RH |
1714 | case OE_SH(V2SHLI, X0): |
1715 | case OE_SH(V2SHLI, X1): | |
78affcb7 CG |
1716 | i2 = imm & 15; |
1717 | i3 = 0xffff >> i2; | |
1718 | tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3)); | |
1719 | tcg_gen_shli_tl(tdest, tdest, i2); | |
1720 | mnemonic = "v2shli"; | |
1721 | break; | |
8fd29dd7 RH |
1722 | case OE_SH(V2SHRSI, X0): |
1723 | case OE_SH(V2SHRSI, X1): | |
78affcb7 CG |
1724 | t0 = tcg_const_tl(imm & 15); |
1725 | gen_helper_v2shrs(tdest, tsrca, t0); | |
1726 | tcg_temp_free(t0); | |
1727 | mnemonic = "v2shrsi"; | |
1728 | break; | |
8fd29dd7 RH |
1729 | case OE_SH(V2SHRUI, X0): |
1730 | case OE_SH(V2SHRUI, X1): | |
78affcb7 CG |
1731 | i2 = imm & 15; |
1732 | i3 = (0xffff << i2) & 0xffff; | |
1733 | tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3)); | |
1734 | tcg_gen_shri_tl(tdest, tdest, i2); | |
1735 | mnemonic = "v2shrui"; | |
1736 | break; | |
8fd29dd7 | 1737 | |
8fd29dd7 RH |
1738 | case OE(ADDLI_OPCODE_X0, 0, X0): |
1739 | case OE(ADDLI_OPCODE_X1, 0, X1): | |
89b8c750 RH |
1740 | tcg_gen_addi_tl(tdest, tsrca, imm); |
1741 | mnemonic = "addli"; | |
1742 | break; | |
8fd29dd7 RH |
1743 | case OE(ADDXLI_OPCODE_X0, 0, X0): |
1744 | case OE(ADDXLI_OPCODE_X1, 0, X1): | |
89b8c750 RH |
1745 | tcg_gen_addi_tl(tdest, tsrca, imm); |
1746 | tcg_gen_ext32s_tl(tdest, tdest); | |
1747 | mnemonic = "addxli"; | |
1748 | break; | |
8fd29dd7 RH |
1749 | case OE(SHL16INSLI_OPCODE_X0, 0, X0): |
1750 | case OE(SHL16INSLI_OPCODE_X1, 0, X1): | |
89b8c750 RH |
1751 | tcg_gen_shli_tl(tdest, tsrca, 16); |
1752 | tcg_gen_ori_tl(tdest, tdest, imm & 0xffff); | |
1753 | mnemonic = "shl16insli"; | |
1754 | break; | |
8fd29dd7 RH |
1755 | |
1756 | default: | |
77b3adc0 | 1757 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
1758 | } |
1759 | ||
1760 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic, | |
1761 | reg_names[dest], reg_names[srca], imm); | |
1762 | return TILEGX_EXCP_NONE; | |
1763 | } | |
1764 | ||
1765 | static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext, | |
1766 | unsigned dest, unsigned srca, | |
1767 | unsigned bfs, unsigned bfe) | |
1768 | { | |
c06b1817 RH |
1769 | TCGv tdest = dest_gr(dc, dest); |
1770 | TCGv tsrca = load_gr(dc, srca); | |
1771 | TCGv tsrcd; | |
1772 | int len; | |
8fd29dd7 RH |
1773 | const char *mnemonic; |
1774 | ||
c06b1817 RH |
1775 | /* The bitfield is either between E and S inclusive, |
1776 | or up from S and down from E inclusive. */ | |
1777 | if (bfs <= bfe) { | |
1778 | len = bfe - bfs + 1; | |
1779 | } else { | |
1780 | len = (64 - bfs) + (bfe + 1); | |
1781 | } | |
1782 | ||
8fd29dd7 RH |
1783 | switch (ext) { |
1784 | case BFEXTU_BF_OPCODE_X0: | |
c06b1817 RH |
1785 | if (bfs == 0 && bfe == 7) { |
1786 | tcg_gen_ext8u_tl(tdest, tsrca); | |
1787 | } else if (bfs == 0 && bfe == 15) { | |
1788 | tcg_gen_ext16u_tl(tdest, tsrca); | |
1789 | } else if (bfs == 0 && bfe == 31) { | |
1790 | tcg_gen_ext32u_tl(tdest, tsrca); | |
1791 | } else { | |
1792 | int rol = 63 - bfe; | |
1793 | if (bfs <= bfe) { | |
1794 | tcg_gen_shli_tl(tdest, tsrca, rol); | |
1795 | } else { | |
1796 | tcg_gen_rotli_tl(tdest, tsrca, rol); | |
1797 | } | |
1798 | tcg_gen_shri_tl(tdest, tdest, (bfs + rol) & 63); | |
1799 | } | |
1800 | mnemonic = "bfextu"; | |
1801 | break; | |
1802 | ||
8fd29dd7 | 1803 | case BFEXTS_BF_OPCODE_X0: |
c06b1817 RH |
1804 | if (bfs == 0 && bfe == 7) { |
1805 | tcg_gen_ext8s_tl(tdest, tsrca); | |
1806 | } else if (bfs == 0 && bfe == 15) { | |
1807 | tcg_gen_ext16s_tl(tdest, tsrca); | |
1808 | } else if (bfs == 0 && bfe == 31) { | |
1809 | tcg_gen_ext32s_tl(tdest, tsrca); | |
1810 | } else { | |
1811 | int rol = 63 - bfe; | |
1812 | if (bfs <= bfe) { | |
1813 | tcg_gen_shli_tl(tdest, tsrca, rol); | |
1814 | } else { | |
1815 | tcg_gen_rotli_tl(tdest, tsrca, rol); | |
1816 | } | |
1817 | tcg_gen_sari_tl(tdest, tdest, (bfs + rol) & 63); | |
1818 | } | |
1819 | mnemonic = "bfexts"; | |
1820 | break; | |
1821 | ||
8fd29dd7 | 1822 | case BFINS_BF_OPCODE_X0: |
c06b1817 RH |
1823 | tsrcd = load_gr(dc, dest); |
1824 | if (bfs <= bfe) { | |
1825 | tcg_gen_deposit_tl(tdest, tsrcd, tsrca, bfs, len); | |
1826 | } else { | |
1827 | tcg_gen_rotri_tl(tdest, tsrcd, bfs); | |
1828 | tcg_gen_deposit_tl(tdest, tdest, tsrca, 0, len); | |
1829 | tcg_gen_rotli_tl(tdest, tdest, bfs); | |
1830 | } | |
1831 | mnemonic = "bfins"; | |
1832 | break; | |
1833 | ||
8fd29dd7 | 1834 | case MM_BF_OPCODE_X0: |
c06b1817 RH |
1835 | tsrcd = load_gr(dc, dest); |
1836 | if (bfs == 0) { | |
1837 | tcg_gen_deposit_tl(tdest, tsrca, tsrcd, 0, len); | |
1838 | } else { | |
1839 | uint64_t mask = len == 64 ? -1 : rol64((1ULL << len) - 1, bfs); | |
1840 | TCGv tmp = tcg_const_tl(mask); | |
1841 | ||
1842 | tcg_gen_and_tl(tdest, tsrcd, tmp); | |
1843 | tcg_gen_andc_tl(tmp, tsrca, tmp); | |
1844 | tcg_gen_or_tl(tdest, tdest, tmp); | |
1845 | tcg_temp_free(tmp); | |
1846 | } | |
1847 | mnemonic = "mm"; | |
1848 | break; | |
1849 | ||
8fd29dd7 | 1850 | default: |
77b3adc0 | 1851 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
1852 | } |
1853 | ||
1854 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic, | |
1855 | reg_names[dest], reg_names[srca], bfs, bfe); | |
1856 | return TILEGX_EXCP_NONE; | |
1857 | } | |
1858 | ||
1859 | static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext, | |
1860 | unsigned srca, int off) | |
1861 | { | |
1862 | target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES; | |
1863 | const char *mnemonic; | |
1864 | ||
e04e98bf RH |
1865 | dc->jmp.dest = tcg_const_tl(tgt); |
1866 | dc->jmp.val1 = tcg_temp_new(); | |
1867 | tcg_gen_mov_tl(dc->jmp.val1, load_gr(dc, srca)); | |
1868 | ||
1869 | /* Note that the "predict taken" opcodes have bit 0 clear. | |
1870 | Therefore, fold the two cases together by setting bit 0. */ | |
1871 | switch (ext | 1) { | |
8fd29dd7 | 1872 | case BEQZ_BRANCH_OPCODE_X1: |
e04e98bf RH |
1873 | dc->jmp.cond = TCG_COND_EQ; |
1874 | mnemonic = "beqz"; | |
1875 | break; | |
8fd29dd7 | 1876 | case BNEZ_BRANCH_OPCODE_X1: |
e04e98bf RH |
1877 | dc->jmp.cond = TCG_COND_NE; |
1878 | mnemonic = "bnez"; | |
1879 | break; | |
8fd29dd7 | 1880 | case BGEZ_BRANCH_OPCODE_X1: |
e04e98bf RH |
1881 | dc->jmp.cond = TCG_COND_GE; |
1882 | mnemonic = "bgez"; | |
1883 | break; | |
8fd29dd7 | 1884 | case BGTZ_BRANCH_OPCODE_X1: |
e04e98bf RH |
1885 | dc->jmp.cond = TCG_COND_GT; |
1886 | mnemonic = "bgtz"; | |
1887 | break; | |
8fd29dd7 | 1888 | case BLEZ_BRANCH_OPCODE_X1: |
e04e98bf RH |
1889 | dc->jmp.cond = TCG_COND_LE; |
1890 | mnemonic = "blez"; | |
1891 | break; | |
8fd29dd7 | 1892 | case BLTZ_BRANCH_OPCODE_X1: |
e04e98bf RH |
1893 | dc->jmp.cond = TCG_COND_LT; |
1894 | mnemonic = "bltz"; | |
1895 | break; | |
1896 | case BLBC_BRANCH_OPCODE_X1: | |
1897 | dc->jmp.cond = TCG_COND_EQ; | |
1898 | tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1); | |
1899 | mnemonic = "blbc"; | |
1900 | break; | |
1901 | case BLBS_BRANCH_OPCODE_X1: | |
1902 | dc->jmp.cond = TCG_COND_NE; | |
1903 | tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1); | |
1904 | mnemonic = "blbs"; | |
1905 | break; | |
8fd29dd7 | 1906 | default: |
77b3adc0 | 1907 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
1908 | } |
1909 | ||
1910 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
e04e98bf RH |
1911 | qemu_log("%s%s %s, " TARGET_FMT_lx " <%s>", |
1912 | mnemonic, ext & 1 ? "" : "t", | |
1913 | reg_names[srca], tgt, lookup_symbol(tgt)); | |
8fd29dd7 RH |
1914 | } |
1915 | return TILEGX_EXCP_NONE; | |
1916 | } | |
1917 | ||
c230a994 | 1918 | static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off) |
8fd29dd7 RH |
1919 | { |
1920 | target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES; | |
c230a994 | 1921 | const char *mnemonic = "j"; |
8fd29dd7 | 1922 | |
c230a994 RH |
1923 | /* The extension field is 1 bit, therefore we only have JAL and J. */ |
1924 | if (ext == JAL_JUMP_OPCODE_X1) { | |
1925 | tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR), | |
1926 | dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES); | |
1927 | mnemonic = "jal"; | |
8fd29dd7 | 1928 | } |
c230a994 RH |
1929 | dc->jmp.cond = TCG_COND_ALWAYS; |
1930 | dc->jmp.dest = tcg_const_tl(tgt); | |
8fd29dd7 RH |
1931 | |
1932 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
1933 | qemu_log("%s " TARGET_FMT_lx " <%s>", | |
1934 | mnemonic, tgt, lookup_symbol(tgt)); | |
1935 | } | |
1936 | return TILEGX_EXCP_NONE; | |
1937 | } | |
1938 | ||
03b217b1 RH |
1939 | typedef struct { |
1940 | const char *name; | |
1941 | intptr_t offset; | |
1942 | void (*get)(TCGv, TCGv_ptr); | |
1943 | void (*put)(TCGv_ptr, TCGv); | |
1944 | } TileSPR; | |
1945 | ||
1946 | static const TileSPR *find_spr(unsigned spr) | |
1947 | { | |
1948 | /* Allow the compiler to construct the binary search tree. */ | |
1949 | #define D(N, O, G, P) \ | |
1950 | case SPR_##N: { static const TileSPR x = { #N, O, G, P }; return &x; } | |
1951 | ||
1952 | switch (spr) { | |
1953 | D(CMPEXCH_VALUE, | |
1954 | offsetof(CPUTLGState, spregs[TILEGX_SPR_CMPEXCH]), 0, 0) | |
1955 | D(INTERRUPT_CRITICAL_SECTION, | |
1956 | offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0) | |
1957 | D(SIM_CONTROL, | |
1958 | offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0) | |
fec7daab CG |
1959 | D(EX_CONTEXT_0_0, |
1960 | offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_0]), 0, 0) | |
1961 | D(EX_CONTEXT_0_1, | |
1962 | offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_1]), 0, 0) | |
03b217b1 RH |
1963 | } |
1964 | ||
1965 | #undef D | |
1966 | ||
1967 | qemu_log_mask(LOG_UNIMP, "UNIMP SPR %u\n", spr); | |
1968 | return NULL; | |
1969 | } | |
1970 | ||
1971 | static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca) | |
1972 | { | |
1973 | const TileSPR *def = find_spr(spr); | |
1974 | TCGv tsrca; | |
1975 | ||
1976 | if (def == NULL) { | |
1977 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr, reg_names[srca]); | |
77b3adc0 | 1978 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
03b217b1 RH |
1979 | } |
1980 | ||
1981 | tsrca = load_gr(dc, srca); | |
1982 | if (def->put) { | |
1983 | def->put(cpu_env, tsrca); | |
1984 | } else { | |
1985 | tcg_gen_st_tl(tsrca, cpu_env, def->offset); | |
1986 | } | |
1987 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name, reg_names[srca]); | |
1988 | return TILEGX_EXCP_NONE; | |
1989 | } | |
1990 | ||
1991 | static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned dest, unsigned spr) | |
1992 | { | |
1993 | const TileSPR *def = find_spr(spr); | |
1994 | TCGv tdest; | |
1995 | ||
1996 | if (def == NULL) { | |
1997 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest], spr); | |
77b3adc0 | 1998 | return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; |
03b217b1 RH |
1999 | } |
2000 | ||
2001 | tdest = dest_gr(dc, dest); | |
2002 | if (def->get) { | |
2003 | def->get(tdest, cpu_env); | |
2004 | } else { | |
2005 | tcg_gen_ld_tl(tdest, cpu_env, def->offset); | |
2006 | } | |
2007 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "mfspr %s, %s", reg_names[dest], def->name); | |
2008 | return TILEGX_EXCP_NONE; | |
2009 | } | |
2010 | ||
8fd29dd7 RH |
2011 | static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle) |
2012 | { | |
2013 | unsigned opc = get_Opcode_Y0(bundle); | |
2014 | unsigned ext = get_RRROpcodeExtension_Y0(bundle); | |
2015 | unsigned dest = get_Dest_Y0(bundle); | |
2016 | unsigned srca = get_SrcA_Y0(bundle); | |
2017 | unsigned srcb; | |
2018 | int imm; | |
2019 | ||
2020 | switch (opc) { | |
2021 | case RRR_1_OPCODE_Y0: | |
2022 | if (ext == UNARY_RRR_1_OPCODE_Y0) { | |
2023 | ext = get_UnaryOpcodeExtension_Y0(bundle); | |
dd8070d8 | 2024 | return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca, bundle); |
8fd29dd7 RH |
2025 | } |
2026 | /* fallthru */ | |
2027 | case RRR_0_OPCODE_Y0: | |
2028 | case RRR_2_OPCODE_Y0: | |
2029 | case RRR_3_OPCODE_Y0: | |
2030 | case RRR_4_OPCODE_Y0: | |
2031 | case RRR_5_OPCODE_Y0: | |
2032 | case RRR_6_OPCODE_Y0: | |
2033 | case RRR_7_OPCODE_Y0: | |
2034 | case RRR_8_OPCODE_Y0: | |
2035 | case RRR_9_OPCODE_Y0: | |
2036 | srcb = get_SrcB_Y0(bundle); | |
2037 | return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb); | |
2038 | ||
2039 | case SHIFT_OPCODE_Y0: | |
2040 | ext = get_ShiftOpcodeExtension_Y0(bundle); | |
2041 | imm = get_ShAmt_Y0(bundle); | |
2042 | return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm); | |
2043 | ||
2044 | case ADDI_OPCODE_Y0: | |
2045 | case ADDXI_OPCODE_Y0: | |
2046 | case ANDI_OPCODE_Y0: | |
2047 | case CMPEQI_OPCODE_Y0: | |
2048 | case CMPLTSI_OPCODE_Y0: | |
2049 | imm = (int8_t)get_Imm8_Y0(bundle); | |
2050 | return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm); | |
2051 | ||
2052 | default: | |
77b3adc0 | 2053 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
2054 | } |
2055 | } | |
2056 | ||
2057 | static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle) | |
2058 | { | |
2059 | unsigned opc = get_Opcode_Y1(bundle); | |
2060 | unsigned ext = get_RRROpcodeExtension_Y1(bundle); | |
2061 | unsigned dest = get_Dest_Y1(bundle); | |
2062 | unsigned srca = get_SrcA_Y1(bundle); | |
2063 | unsigned srcb; | |
2064 | int imm; | |
2065 | ||
2066 | switch (get_Opcode_Y1(bundle)) { | |
2067 | case RRR_1_OPCODE_Y1: | |
2068 | if (ext == UNARY_RRR_1_OPCODE_Y0) { | |
2069 | ext = get_UnaryOpcodeExtension_Y1(bundle); | |
dd8070d8 | 2070 | return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca, bundle); |
8fd29dd7 RH |
2071 | } |
2072 | /* fallthru */ | |
2073 | case RRR_0_OPCODE_Y1: | |
2074 | case RRR_2_OPCODE_Y1: | |
2075 | case RRR_3_OPCODE_Y1: | |
2076 | case RRR_4_OPCODE_Y1: | |
2077 | case RRR_5_OPCODE_Y1: | |
2078 | case RRR_6_OPCODE_Y1: | |
2079 | case RRR_7_OPCODE_Y1: | |
2080 | srcb = get_SrcB_Y1(bundle); | |
2081 | return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb); | |
2082 | ||
2083 | case SHIFT_OPCODE_Y1: | |
2084 | ext = get_ShiftOpcodeExtension_Y1(bundle); | |
2085 | imm = get_ShAmt_Y1(bundle); | |
2086 | return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm); | |
2087 | ||
2088 | case ADDI_OPCODE_Y1: | |
2089 | case ADDXI_OPCODE_Y1: | |
2090 | case ANDI_OPCODE_Y1: | |
2091 | case CMPEQI_OPCODE_Y1: | |
2092 | case CMPLTSI_OPCODE_Y1: | |
2093 | imm = (int8_t)get_Imm8_Y1(bundle); | |
2094 | return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm); | |
2095 | ||
2096 | default: | |
77b3adc0 | 2097 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
2098 | } |
2099 | } | |
2100 | ||
2101 | static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle) | |
2102 | { | |
2103 | unsigned mode = get_Mode(bundle); | |
2104 | unsigned opc = get_Opcode_Y2(bundle); | |
2105 | unsigned srca = get_SrcA_Y2(bundle); | |
2106 | unsigned srcbdest = get_SrcBDest_Y2(bundle); | |
2107 | const char *mnemonic; | |
0426335d | 2108 | TCGMemOp memop; |
2a080ce2 | 2109 | bool prefetch_nofault = false; |
8fd29dd7 RH |
2110 | |
2111 | switch (OEY2(opc, mode)) { | |
2112 | case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2): | |
0426335d | 2113 | memop = MO_SB; |
2a080ce2 | 2114 | mnemonic = "ld1s"; /* prefetch_l1_fault */ |
0426335d | 2115 | goto do_load; |
8fd29dd7 | 2116 | case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2): |
0426335d | 2117 | memop = MO_UB; |
2a080ce2 CG |
2118 | mnemonic = "ld1u"; /* prefetch, prefetch_l1 */ |
2119 | prefetch_nofault = (srcbdest == TILEGX_R_ZERO); | |
0426335d | 2120 | goto do_load; |
8fd29dd7 | 2121 | case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2): |
0426335d | 2122 | memop = MO_TESW; |
2a080ce2 | 2123 | mnemonic = "ld2s"; /* prefetch_l2_fault */ |
0426335d | 2124 | goto do_load; |
8fd29dd7 | 2125 | case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2): |
0426335d | 2126 | memop = MO_TEUW; |
2a080ce2 CG |
2127 | mnemonic = "ld2u"; /* prefetch_l2 */ |
2128 | prefetch_nofault = (srcbdest == TILEGX_R_ZERO); | |
0426335d | 2129 | goto do_load; |
8fd29dd7 | 2130 | case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2): |
0426335d | 2131 | memop = MO_TESL; |
2a080ce2 | 2132 | mnemonic = "ld4s"; /* prefetch_l3_fault */ |
0426335d | 2133 | goto do_load; |
8fd29dd7 | 2134 | case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2): |
0426335d | 2135 | memop = MO_TEUL; |
2a080ce2 CG |
2136 | mnemonic = "ld4u"; /* prefetch_l3 */ |
2137 | prefetch_nofault = (srcbdest == TILEGX_R_ZERO); | |
0426335d | 2138 | goto do_load; |
8fd29dd7 | 2139 | case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2): |
0426335d RH |
2140 | memop = MO_TEQ; |
2141 | mnemonic = "ld"; | |
2142 | do_load: | |
2a080ce2 CG |
2143 | if (!prefetch_nofault) { |
2144 | tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca), | |
2145 | dc->mmuidx, memop); | |
2146 | } | |
0426335d RH |
2147 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic, |
2148 | reg_names[srcbdest], reg_names[srca]); | |
2149 | return TILEGX_EXCP_NONE; | |
8fd29dd7 RH |
2150 | |
2151 | case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2): | |
0426335d | 2152 | return gen_st_opcode(dc, 0, srca, srcbdest, MO_UB, "st1"); |
8fd29dd7 | 2153 | case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2): |
0426335d | 2154 | return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUW, "st2"); |
8fd29dd7 | 2155 | case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2): |
0426335d | 2156 | return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUL, "st4"); |
8fd29dd7 | 2157 | case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2): |
0426335d | 2158 | return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st"); |
8fd29dd7 RH |
2159 | |
2160 | default: | |
77b3adc0 | 2161 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 | 2162 | } |
8fd29dd7 RH |
2163 | } |
2164 | ||
2165 | static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle) | |
2166 | { | |
2167 | unsigned opc = get_Opcode_X0(bundle); | |
2168 | unsigned dest = get_Dest_X0(bundle); | |
2169 | unsigned srca = get_SrcA_X0(bundle); | |
2170 | unsigned ext, srcb, bfs, bfe; | |
2171 | int imm; | |
2172 | ||
2173 | switch (opc) { | |
2174 | case RRR_0_OPCODE_X0: | |
2175 | ext = get_RRROpcodeExtension_X0(bundle); | |
2176 | if (ext == UNARY_RRR_0_OPCODE_X0) { | |
2177 | ext = get_UnaryOpcodeExtension_X0(bundle); | |
dd8070d8 | 2178 | return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca, bundle); |
8fd29dd7 RH |
2179 | } |
2180 | srcb = get_SrcB_X0(bundle); | |
2181 | return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb); | |
2182 | ||
2183 | case SHIFT_OPCODE_X0: | |
2184 | ext = get_ShiftOpcodeExtension_X0(bundle); | |
2185 | imm = get_ShAmt_X0(bundle); | |
2186 | return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm); | |
2187 | ||
2188 | case IMM8_OPCODE_X0: | |
2189 | ext = get_Imm8OpcodeExtension_X0(bundle); | |
2190 | imm = (int8_t)get_Imm8_X0(bundle); | |
2191 | return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm); | |
2192 | ||
2193 | case BF_OPCODE_X0: | |
2194 | ext = get_BFOpcodeExtension_X0(bundle); | |
2195 | bfs = get_BFStart_X0(bundle); | |
2196 | bfe = get_BFEnd_X0(bundle); | |
2197 | return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe); | |
2198 | ||
2199 | case ADDLI_OPCODE_X0: | |
2200 | case SHL16INSLI_OPCODE_X0: | |
2201 | case ADDXLI_OPCODE_X0: | |
2202 | imm = (int16_t)get_Imm16_X0(bundle); | |
2203 | return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm); | |
2204 | ||
2205 | default: | |
77b3adc0 | 2206 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
2207 | } |
2208 | } | |
2209 | ||
2210 | static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle) | |
2211 | { | |
2212 | unsigned opc = get_Opcode_X1(bundle); | |
2213 | unsigned dest = get_Dest_X1(bundle); | |
2214 | unsigned srca = get_SrcA_X1(bundle); | |
2215 | unsigned ext, srcb; | |
2216 | int imm; | |
2217 | ||
2218 | switch (opc) { | |
2219 | case RRR_0_OPCODE_X1: | |
2220 | ext = get_RRROpcodeExtension_X1(bundle); | |
0426335d RH |
2221 | srcb = get_SrcB_X1(bundle); |
2222 | switch (ext) { | |
2223 | case UNARY_RRR_0_OPCODE_X1: | |
8fd29dd7 | 2224 | ext = get_UnaryOpcodeExtension_X1(bundle); |
dd8070d8 | 2225 | return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca, bundle); |
0426335d RH |
2226 | case ST1_RRR_0_OPCODE_X1: |
2227 | return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1"); | |
2228 | case ST2_RRR_0_OPCODE_X1: | |
2229 | return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "st2"); | |
2230 | case ST4_RRR_0_OPCODE_X1: | |
2231 | return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "st4"); | |
2232 | case STNT1_RRR_0_OPCODE_X1: | |
2233 | return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "stnt1"); | |
2234 | case STNT2_RRR_0_OPCODE_X1: | |
2235 | return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "stnt2"); | |
2236 | case STNT4_RRR_0_OPCODE_X1: | |
2237 | return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "stnt4"); | |
2238 | case STNT_RRR_0_OPCODE_X1: | |
2239 | return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "stnt"); | |
2240 | case ST_RRR_0_OPCODE_X1: | |
2241 | return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "st"); | |
8fd29dd7 | 2242 | } |
8fd29dd7 RH |
2243 | return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb); |
2244 | ||
2245 | case SHIFT_OPCODE_X1: | |
2246 | ext = get_ShiftOpcodeExtension_X1(bundle); | |
2247 | imm = get_ShAmt_X1(bundle); | |
2248 | return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm); | |
2249 | ||
2250 | case IMM8_OPCODE_X1: | |
2251 | ext = get_Imm8OpcodeExtension_X1(bundle); | |
01cd675c RH |
2252 | imm = (int8_t)get_Dest_Imm8_X1(bundle); |
2253 | srcb = get_SrcB_X1(bundle); | |
2254 | switch (ext) { | |
2255 | case ST1_ADD_IMM8_OPCODE_X1: | |
2256 | return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "st1_add"); | |
2257 | case ST2_ADD_IMM8_OPCODE_X1: | |
2258 | return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "st2_add"); | |
2259 | case ST4_ADD_IMM8_OPCODE_X1: | |
2260 | return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "st4_add"); | |
2261 | case STNT1_ADD_IMM8_OPCODE_X1: | |
2262 | return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "stnt1_add"); | |
2263 | case STNT2_ADD_IMM8_OPCODE_X1: | |
2264 | return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "stnt2_add"); | |
2265 | case STNT4_ADD_IMM8_OPCODE_X1: | |
2266 | return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "stnt4_add"); | |
2267 | case STNT_ADD_IMM8_OPCODE_X1: | |
2268 | return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "stnt_add"); | |
2269 | case ST_ADD_IMM8_OPCODE_X1: | |
2270 | return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "st_add"); | |
03b217b1 RH |
2271 | case MFSPR_IMM8_OPCODE_X1: |
2272 | return gen_mfspr_x1(dc, dest, get_MF_Imm14_X1(bundle)); | |
2273 | case MTSPR_IMM8_OPCODE_X1: | |
2274 | return gen_mtspr_x1(dc, get_MT_Imm14_X1(bundle), srca); | |
01cd675c | 2275 | } |
8fd29dd7 RH |
2276 | imm = (int8_t)get_Imm8_X1(bundle); |
2277 | return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm); | |
2278 | ||
2279 | case BRANCH_OPCODE_X1: | |
2280 | ext = get_BrType_X1(bundle); | |
2281 | imm = sextract32(get_BrOff_X1(bundle), 0, 17); | |
2282 | return gen_branch_opcode_x1(dc, ext, srca, imm); | |
2283 | ||
2284 | case JUMP_OPCODE_X1: | |
2285 | ext = get_JumpOpcodeExtension_X1(bundle); | |
2286 | imm = sextract32(get_JumpOff_X1(bundle), 0, 27); | |
2287 | return gen_jump_opcode_x1(dc, ext, imm); | |
2288 | ||
2289 | case ADDLI_OPCODE_X1: | |
2290 | case SHL16INSLI_OPCODE_X1: | |
2291 | case ADDXLI_OPCODE_X1: | |
2292 | imm = (int16_t)get_Imm16_X1(bundle); | |
2293 | return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm); | |
2294 | ||
2295 | default: | |
77b3adc0 | 2296 | return TILEGX_EXCP_OPCODE_UNKNOWN; |
8fd29dd7 RH |
2297 | } |
2298 | } | |
2299 | ||
2300 | static void notice_excp(DisasContext *dc, uint64_t bundle, | |
2301 | const char *type, TileExcp excp) | |
2302 | { | |
2303 | if (likely(excp == TILEGX_EXCP_NONE)) { | |
2304 | return; | |
2305 | } | |
2306 | gen_exception(dc, excp); | |
77b3adc0 CG |
2307 | switch (excp) { |
2308 | case TILEGX_EXCP_OPCODE_UNIMPLEMENTED: | |
8fd29dd7 | 2309 | qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle); |
77b3adc0 CG |
2310 | break; |
2311 | case TILEGX_EXCP_OPCODE_UNKNOWN: | |
2312 | qemu_log_mask(LOG_UNIMP, "UNKNOWN %s, [" FMT64X "]\n", type, bundle); | |
2313 | break; | |
2314 | default: | |
2315 | break; | |
8fd29dd7 RH |
2316 | } |
2317 | } | |
2318 | ||
2319 | static void translate_one_bundle(DisasContext *dc, uint64_t bundle) | |
2320 | { | |
2321 | int i; | |
2322 | ||
2323 | for (i = 0; i < ARRAY_SIZE(dc->wb); i++) { | |
2324 | DisasContextTemp *wb = &dc->wb[i]; | |
2325 | wb->reg = TILEGX_R_NOREG; | |
2326 | TCGV_UNUSED_I64(wb->val); | |
2327 | } | |
2328 | dc->num_wb = 0; | |
2329 | ||
8fd29dd7 RH |
2330 | qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc); |
2331 | if (get_Mode(bundle)) { | |
2332 | notice_excp(dc, bundle, "y0", decode_y0(dc, bundle)); | |
2333 | qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; "); | |
2334 | notice_excp(dc, bundle, "y1", decode_y1(dc, bundle)); | |
2335 | qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; "); | |
2336 | notice_excp(dc, bundle, "y2", decode_y2(dc, bundle)); | |
2337 | } else { | |
2338 | notice_excp(dc, bundle, "x0", decode_x0(dc, bundle)); | |
2339 | qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; "); | |
2340 | notice_excp(dc, bundle, "x1", decode_x1(dc, bundle)); | |
2341 | } | |
2342 | qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n"); | |
2343 | ||
2344 | for (i = dc->num_wb - 1; i >= 0; --i) { | |
2345 | DisasContextTemp *wb = &dc->wb[i]; | |
2346 | if (wb->reg < TILEGX_R_COUNT) { | |
2347 | tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val); | |
2348 | } | |
2349 | tcg_temp_free_i64(wb->val); | |
2350 | } | |
2351 | ||
2352 | if (dc->jmp.cond != TCG_COND_NEVER) { | |
2353 | if (dc->jmp.cond == TCG_COND_ALWAYS) { | |
2354 | tcg_gen_mov_i64(cpu_pc, dc->jmp.dest); | |
2355 | } else { | |
2356 | TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES); | |
2357 | tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc, | |
2358 | dc->jmp.val1, load_zero(dc), | |
2359 | dc->jmp.dest, next); | |
2360 | tcg_temp_free_i64(dc->jmp.val1); | |
2361 | tcg_temp_free_i64(next); | |
2362 | } | |
2363 | tcg_temp_free_i64(dc->jmp.dest); | |
2364 | tcg_gen_exit_tb(0); | |
2365 | dc->exit_tb = true; | |
0583b233 RH |
2366 | } else if (dc->atomic_excp != TILEGX_EXCP_NONE) { |
2367 | gen_exception(dc, dc->atomic_excp); | |
8fd29dd7 RH |
2368 | } |
2369 | } | |
2370 | ||
4e5e1215 | 2371 | void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb) |
8fd29dd7 | 2372 | { |
4e5e1215 | 2373 | TileGXCPU *cpu = tilegx_env_get_cpu(env); |
8fd29dd7 RH |
2374 | DisasContext ctx; |
2375 | DisasContext *dc = &ctx; | |
2376 | CPUState *cs = CPU(cpu); | |
8fd29dd7 RH |
2377 | uint64_t pc_start = tb->pc; |
2378 | uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
8fd29dd7 RH |
2379 | int num_insns = 0; |
2380 | int max_insns = tb->cflags & CF_COUNT_MASK; | |
2381 | ||
2382 | dc->pc = pc_start; | |
2383 | dc->mmuidx = 0; | |
2384 | dc->exit_tb = false; | |
0583b233 | 2385 | dc->atomic_excp = TILEGX_EXCP_NONE; |
8fd29dd7 RH |
2386 | dc->jmp.cond = TCG_COND_NEVER; |
2387 | TCGV_UNUSED_I64(dc->jmp.dest); | |
2388 | TCGV_UNUSED_I64(dc->jmp.val1); | |
8fd29dd7 RH |
2389 | TCGV_UNUSED_I64(dc->zero); |
2390 | ||
2391 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
2392 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
2393 | } | |
2394 | if (!max_insns) { | |
2395 | max_insns = CF_COUNT_MASK; | |
2396 | } | |
2397 | if (cs->singlestep_enabled || singlestep) { | |
2398 | max_insns = 1; | |
2399 | } | |
190ce7fb RH |
2400 | if (max_insns > TCG_MAX_INSNS) { |
2401 | max_insns = TCG_MAX_INSNS; | |
2402 | } | |
8fd29dd7 RH |
2403 | gen_tb_start(tb); |
2404 | ||
2405 | while (1) { | |
667b8e29 | 2406 | tcg_gen_insn_start(dc->pc); |
959082fc | 2407 | num_insns++; |
667b8e29 | 2408 | |
8fd29dd7 RH |
2409 | translate_one_bundle(dc, cpu_ldq_data(env, dc->pc)); |
2410 | ||
2411 | if (dc->exit_tb) { | |
2412 | /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */ | |
2413 | break; | |
2414 | } | |
2415 | dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES; | |
959082fc | 2416 | if (num_insns >= max_insns |
8fd29dd7 RH |
2417 | || dc->pc >= next_page_start |
2418 | || tcg_op_buf_full()) { | |
2419 | /* Ending the TB due to TB size or page boundary. Set PC. */ | |
2420 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
2421 | tcg_gen_exit_tb(0); | |
2422 | break; | |
2423 | } | |
2424 | } | |
2425 | ||
2426 | gen_tb_end(tb, num_insns); | |
4e5e1215 RH |
2427 | tb->size = dc->pc - pc_start; |
2428 | tb->icount = num_insns; | |
8fd29dd7 RH |
2429 | |
2430 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n"); | |
2431 | } | |
2432 | ||
bad729e2 RH |
2433 | void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb, |
2434 | target_ulong *data) | |
8fd29dd7 | 2435 | { |
bad729e2 | 2436 | env->pc = data[0]; |
8fd29dd7 RH |
2437 | } |
2438 | ||
2439 | void tilegx_tcg_init(void) | |
2440 | { | |
2441 | int i; | |
2442 | ||
2443 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
2444 | cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc"); | |
2445 | for (i = 0; i < TILEGX_R_COUNT; i++) { | |
2446 | cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
2447 | offsetof(CPUTLGState, regs[i]), | |
2448 | reg_names[i]); | |
2449 | } | |
2450 | } |