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target-tricore: Add instructions of RLC opcode format
[mirror_qemu.git] / target-tricore / translate.c
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48e06fe0
BK		 1/*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21#include "cpu.h"
22#include "disas/disas.h"
23#include "tcg-op.h"
24#include "exec/cpu_ldst.h"
25
26#include "exec/helper-proto.h"
27#include "exec/helper-gen.h"
28
7c87d074 29#include "tricore-opcodes.h"
0707ec1b 30
0aaeb118
BK		 31/*
32 * TCG registers
33 */
34static TCGv cpu_PC;
35static TCGv cpu_PCXI;
36static TCGv cpu_PSW;
37static TCGv cpu_ICR;
38/* GPR registers */
39static TCGv cpu_gpr_a[16];
40static TCGv cpu_gpr_d[16];
41/* PSW Flag cache */
42static TCGv cpu_PSW_C;
43static TCGv cpu_PSW_V;
44static TCGv cpu_PSW_SV;
45static TCGv cpu_PSW_AV;
46static TCGv cpu_PSW_SAV;
47/* CPU env */
48static TCGv_ptr cpu_env;
49
50#include "exec/gen-icount.h"
48e06fe0
BK		 51
52static const char *regnames_a[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
56 };
57
58static const char *regnames_d[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
62 };
63
0aaeb118
BK		 64typedef struct DisasContext {
65 struct TranslationBlock *tb;
66 target_ulong pc, saved_pc, next_pc;
67 uint32_t opcode;
68 int singlestep_enabled;
69 /* Routine used to access memory */
70 int mem_idx;
71 uint32_t hflags, saved_hflags;
72 int bstate;
73} DisasContext;
74
75enum {
76
77 BS_NONE = 0,
78 BS_STOP = 1,
79 BS_BRANCH = 2,
80 BS_EXCP = 3,
81};
82
48e06fe0
BK		 83void tricore_cpu_dump_state(CPUState *cs, FILE *f,
84 fprintf_function cpu_fprintf, int flags)
85{
86 TriCoreCPU *cpu = TRICORE_CPU(cs);
87 CPUTriCoreState *env = &cpu->env;
88 int i;
89
90 cpu_fprintf(f, "PC=%08x\n", env->PC);
91 for (i = 0; i < 16; ++i) {
92 if ((i & 3) == 0) {
93 cpu_fprintf(f, "GPR A%02d:", i);
94 }
95 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
96 }
97 for (i = 0; i < 16; ++i) {
98 if ((i & 3) == 0) {
99 cpu_fprintf(f, "GPR D%02d:", i);
100 }
101 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
102 }
103
104}
105
0707ec1b
BK		 106/*
107 * Functions to generate micro-ops
108 */
109
9a31922b
BK		 110/* Makros for generating helpers */
111
112#define gen_helper_1arg(name, arg) do { \
113 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
114 gen_helper_##name(cpu_env, helper_tmp); \
115 tcg_temp_free_i32(helper_tmp); \
116 } while (0)
117
59543d4e 118#define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
f718b0bb
BK		 119#define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
120 ((offset & 0x0fffff) << 1))
59543d4e 121
d2798210
BK		 122/* Functions for load/save to/from memory */
123
124static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
125 int16_t con, TCGMemOp mop)
126{
127 TCGv temp = tcg_temp_new();
128 tcg_gen_addi_tl(temp, r2, con);
129 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
130 tcg_temp_free(temp);
131}
132
133static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
134 int16_t con, TCGMemOp mop)
135{
136 TCGv temp = tcg_temp_new();
137 tcg_gen_addi_tl(temp, r2, con);
138 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
139 tcg_temp_free(temp);
140}
141
59543d4e
BK		 142static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
143{
144 TCGv_i64 temp = tcg_temp_new_i64();
145
146 tcg_gen_concat_i32_i64(temp, rl, rh);
147 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
148
149 tcg_temp_free_i64(temp);
150}
151
3a16ecb0
BK		 152static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
153 DisasContext *ctx)
154{
155 TCGv temp = tcg_temp_new();
156 tcg_gen_addi_tl(temp, base, con);
157 gen_st_2regs_64(rh, rl, temp, ctx);
158 tcg_temp_free(temp);
159}
160
59543d4e
BK		 161static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
162{
163 TCGv_i64 temp = tcg_temp_new_i64();
164
165 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
166 /* write back to two 32 bit regs */
167 tcg_gen_extr_i64_i32(rl, rh, temp);
168
169 tcg_temp_free_i64(temp);
170}
171
3a16ecb0
BK		 172static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
173 DisasContext *ctx)
174{
175 TCGv temp = tcg_temp_new();
176 tcg_gen_addi_tl(temp, base, con);
177 gen_ld_2regs_64(rh, rl, temp, ctx);
178 tcg_temp_free(temp);
179}
180
181static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
182 TCGMemOp mop)
183{
184 TCGv temp = tcg_temp_new();
185 tcg_gen_addi_tl(temp, r2, off);
186 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
187 tcg_gen_mov_tl(r2, temp);
188 tcg_temp_free(temp);
189}
190
191static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
192 TCGMemOp mop)
193{
194 TCGv temp = tcg_temp_new();
195 tcg_gen_addi_tl(temp, r2, off);
196 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
197 tcg_gen_mov_tl(r2, temp);
198 tcg_temp_free(temp);
199}
200
59543d4e
BK		 201/* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
202static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
203{
204 TCGv temp = tcg_temp_new();
205 TCGv temp2 = tcg_temp_new();
206
207 /* temp = (M(EA, word) */
208 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
209 /* temp = temp & ~E[a][63:32]) */
210 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
211 /* temp2 = (E[a][31:0] & E[a][63:32]); */
212 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
213 /* temp = temp | temp2; */
214 tcg_gen_or_tl(temp, temp, temp2);
215 /* M(EA, word) = temp; */
216 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
217
218 tcg_temp_free(temp);
219 tcg_temp_free(temp2);
220}
221
222/* tmp = M(EA, word);
223 M(EA, word) = D[a];
224 D[a] = tmp[31:0];*/
225static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
226{
227 TCGv temp = tcg_temp_new();
228
229 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
230 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
231 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
232
233 tcg_temp_free(temp);
234}
235
2b2f7d97
BK		 236/* We generate loads and store to core special function register (csfr) through
237 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
238 makros R, A and E, which allow read-only, all and endinit protected access.
239 These makros also specify in which ISA version the csfr was introduced. */
240#define R(ADDRESS, REG, FEATURE) \
241 case ADDRESS: \
242 if (tricore_feature(env, FEATURE)) { \
243 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
244 } \
245 break;
246#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
247#define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
248static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
249{
250 /* since we're caching PSW make this a special case */
251 if (offset == 0xfe04) {
252 gen_helper_psw_read(ret, cpu_env);
253 } else {
254 switch (offset) {
255#include "csfr.def"
256 }
257 }
258}
259#undef R
260#undef A
261#undef E
262
263#define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
264 since no execption occurs */
265#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
266 case ADDRESS: \
267 if (tricore_feature(env, FEATURE)) { \
268 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
269 } \
270 break;
271/* Endinit protected registers
272 TODO: Since the endinit bit is in a register of a not yet implemented
273 watchdog device, we handle endinit protected registers like
274 all-access registers for now. */
275#define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
276static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
277 int32_t offset)
278{
279 if (ctx->hflags & TRICORE_HFLAG_SM) {
280 /* since we're caching PSW make this a special case */
281 if (offset == 0xfe04) {
282 gen_helper_psw_write(cpu_env, r1);
283 } else {
284 switch (offset) {
285#include "csfr.def"
286 }
287 }
288 } else {
289 /* generate privilege trap */
290 }
291}
292
0707ec1b
BK		 293/* Functions for arithmetic instructions */
294
295static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
296{
297 TCGv t0 = tcg_temp_new_i32();
298 TCGv result = tcg_temp_new_i32();
299 /* Addition and set V/SV bits */
300 tcg_gen_add_tl(result, r1, r2);
301 /* calc V bit */
302 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
303 tcg_gen_xor_tl(t0, r1, r2);
304 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
305 /* Calc SV bit */
306 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
307 /* Calc AV/SAV bits */
308 tcg_gen_add_tl(cpu_PSW_AV, result, result);
309 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
310 /* calc SAV */
311 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
312 /* write back result */
313 tcg_gen_mov_tl(ret, result);
314
315 tcg_temp_free(result);
316 tcg_temp_free(t0);
317}
318
319static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
320{
321 TCGv temp = tcg_const_i32(r2);
322 gen_add_d(ret, r1, temp);
323 tcg_temp_free(temp);
324}
0974257e
BK		 325/* calculate the carry bit too */
326static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
327{
328 TCGv t0 = tcg_temp_new_i32();
329 TCGv result = tcg_temp_new_i32();
330
331 tcg_gen_movi_tl(t0, 0);
332 /* Addition and set C/V/SV bits */
333 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
334 /* calc V bit */
335 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
336 tcg_gen_xor_tl(t0, r1, r2);
337 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
338 /* Calc SV bit */
339 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
340 /* Calc AV/SAV bits */
341 tcg_gen_add_tl(cpu_PSW_AV, result, result);
342 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
343 /* calc SAV */
344 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
345 /* write back result */
346 tcg_gen_mov_tl(ret, result);
347
348 tcg_temp_free(result);
349 tcg_temp_free(t0);
350}
351
352static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
353{
354 TCGv temp = tcg_const_i32(con);
355 gen_add_CC(ret, r1, temp);
356 tcg_temp_free(temp);
357}
358
359static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
360{
361 TCGv carry = tcg_temp_new_i32();
362 TCGv t0 = tcg_temp_new_i32();
363 TCGv result = tcg_temp_new_i32();
364
365 tcg_gen_movi_tl(t0, 0);
366 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
367 /* Addition, carry and set C/V/SV bits */
368 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
369 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
370 /* calc V bit */
371 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
372 tcg_gen_xor_tl(t0, r1, r2);
373 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
374 /* Calc SV bit */
375 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
376 /* Calc AV/SAV bits */
377 tcg_gen_add_tl(cpu_PSW_AV, result, result);
378 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
379 /* calc SAV */
380 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
381 /* write back result */
382 tcg_gen_mov_tl(ret, result);
383
384 tcg_temp_free(result);
385 tcg_temp_free(t0);
386 tcg_temp_free(carry);
387}
388
389static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
390{
391 TCGv temp = tcg_const_i32(con);
392 gen_addc_CC(ret, r1, temp);
393 tcg_temp_free(temp);
394}
0707ec1b
BK		 395
396static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
397 TCGv r4)
398{
399 TCGv temp = tcg_temp_new();
400 TCGv temp2 = tcg_temp_new();
401 TCGv result = tcg_temp_new();
402 TCGv mask = tcg_temp_new();
403 TCGv t0 = tcg_const_i32(0);
404
405 /* create mask for sticky bits */
406 tcg_gen_setcond_tl(cond, mask, r4, t0);
407 tcg_gen_shli_tl(mask, mask, 31);
408
409 tcg_gen_add_tl(result, r1, r2);
410 /* Calc PSW_V */
411 tcg_gen_xor_tl(temp, result, r1);
412 tcg_gen_xor_tl(temp2, r1, r2);
413 tcg_gen_andc_tl(temp, temp, temp2);
414 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
415 /* Set PSW_SV */
416 tcg_gen_and_tl(temp, temp, mask);
417 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
418 /* calc AV bit */
419 tcg_gen_add_tl(temp, result, result);
420 tcg_gen_xor_tl(temp, temp, result);
421 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
422 /* calc SAV bit */
423 tcg_gen_and_tl(temp, temp, mask);
424 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
425 /* write back result */
426 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
427
428 tcg_temp_free(t0);
429 tcg_temp_free(temp);
430 tcg_temp_free(temp2);
431 tcg_temp_free(result);
432 tcg_temp_free(mask);
433}
434
435static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
436 TCGv r3, TCGv r4)
437{
438 TCGv temp = tcg_const_i32(r2);
439 gen_cond_add(cond, r1, temp, r3, r4);
440 tcg_temp_free(temp);
441}
442
2692802a
BK		 443static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
444{
445 TCGv temp = tcg_temp_new_i32();
446 TCGv result = tcg_temp_new_i32();
447
448 tcg_gen_sub_tl(result, r1, r2);
449 /* calc V bit */
450 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
451 tcg_gen_xor_tl(temp, r1, r2);
452 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
453 /* calc SV bit */
454 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
455 /* Calc AV bit */
456 tcg_gen_add_tl(cpu_PSW_AV, result, result);
457 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
458 /* calc SAV bit */
459 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
460 /* write back result */
461 tcg_gen_mov_tl(ret, result);
462
463 tcg_temp_free(temp);
464 tcg_temp_free(result);
465}
466
0974257e
BK		 467static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
468{
469 TCGv temp = tcg_temp_new_i32();
470 TCGv result = tcg_temp_new_i32();
471
472 tcg_gen_sub_tl(result, r1, r2);
473 tcg_gen_sub_tl(temp, r2, r1);
474 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
475
476 /* calc V bit */
477 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
478 tcg_gen_xor_tl(temp, result, r2);
479 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
480 tcg_gen_xor_tl(temp, r1, r2);
481 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
482 /* calc SV bit */
483 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
484 /* Calc AV bit */
485 tcg_gen_add_tl(cpu_PSW_AV, result, result);
486 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
487 /* calc SAV bit */
488 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
489 /* write back result */
490 tcg_gen_mov_tl(ret, result);
491
492 tcg_temp_free(temp);
493 tcg_temp_free(result);
494}
495
496static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
497{
498 TCGv temp = tcg_const_i32(con);
499 gen_absdif(ret, r1, temp);
500 tcg_temp_free(temp);
501}
502
503static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
504{
505 TCGv temp = tcg_const_i32(con);
506 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
507 tcg_temp_free(temp);
508}
509
2692802a
BK		 510static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
511{
512 TCGv high = tcg_temp_new();
513 TCGv low = tcg_temp_new();
514
515 tcg_gen_muls2_tl(low, high, r1, r2);
516 tcg_gen_mov_tl(ret, low);
517 /* calc V bit */
518 tcg_gen_sari_tl(low, low, 31);
519 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
520 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
521 /* calc SV bit */
522 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
523 /* Calc AV bit */
524 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
525 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
526 /* calc SAV bit */
527 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
528
529 tcg_temp_free(high);
530 tcg_temp_free(low);
531}
532
0974257e
BK		 533static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
534{
535 TCGv temp = tcg_const_i32(con);
536 gen_mul_i32s(ret, r1, temp);
537 tcg_temp_free(temp);
538}
539
540static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
541{
542 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
543 /* clear V bit */
544 tcg_gen_movi_tl(cpu_PSW_V, 0);
545 /* calc SV bit */
546 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
547 /* Calc AV bit */
548 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
549 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
550 /* calc SAV bit */
551 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
552}
553
554static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
555 int32_t con)
556{
557 TCGv temp = tcg_const_i32(con);
558 gen_mul_i64s(ret_low, ret_high, r1, temp);
559 tcg_temp_free(temp);
560}
561
562static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
563{
564 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
565 /* clear V bit */
566 tcg_gen_movi_tl(cpu_PSW_V, 0);
567 /* calc SV bit */
568 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
569 /* Calc AV bit */
570 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
571 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
572 /* calc SAV bit */
573 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
574}
575
576static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
577 int32_t con)
578{
579 TCGv temp = tcg_const_i32(con);
580 gen_mul_i64u(ret_low, ret_high, r1, temp);
581 tcg_temp_free(temp);
582}
583
584static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
585{
586 TCGv temp = tcg_const_i32(con);
587 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
588 tcg_temp_free(temp);
589}
590
591static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
592{
593 TCGv temp = tcg_const_i32(con);
594 gen_helper_mul_suov(ret, cpu_env, r1, temp);
595 tcg_temp_free(temp);
596}
597
44ea3430
BK		 598static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
599{
600 TCGv sat_neg = tcg_const_i32(low);
601 TCGv temp = tcg_const_i32(up);
602
603 /* sat_neg = (arg < low ) ? low : arg; */
604 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
605
606 /* ret = (sat_neg > up ) ? up : sat_neg; */
607 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
608
609 tcg_temp_free(sat_neg);
610 tcg_temp_free(temp);
611}
612
613static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
614{
615 TCGv temp = tcg_const_i32(up);
616 /* sat_neg = (arg > up ) ? up : arg; */
617 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
618 tcg_temp_free(temp);
619}
620
0707ec1b
BK		 621static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
622{
623 if (shift_count == -32) {
624 tcg_gen_movi_tl(ret, 0);
625 } else if (shift_count >= 0) {
626 tcg_gen_shli_tl(ret, r1, shift_count);
627 } else {
628 tcg_gen_shri_tl(ret, r1, -shift_count);
629 }
630}
631
0974257e
BK		 632static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
633{
634 TCGv temp_low, temp_high;
635
636 if (shiftcount == -16) {
637 tcg_gen_movi_tl(ret, 0);
638 } else {
639 temp_high = tcg_temp_new();
640 temp_low = tcg_temp_new();
641
642 tcg_gen_andi_tl(temp_low, r1, 0xffff);
643 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
644 gen_shi(temp_low, temp_low, shiftcount);
645 gen_shi(ret, temp_high, shiftcount);
646 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
647
648 tcg_temp_free(temp_low);
649 tcg_temp_free(temp_high);
650 }
651}
652
0707ec1b
BK		 653static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
654{
655 uint32_t msk, msk_start;
656 TCGv temp = tcg_temp_new();
657 TCGv temp2 = tcg_temp_new();
658 TCGv t_0 = tcg_const_i32(0);
659
660 if (shift_count == 0) {
661 /* Clear PSW.C and PSW.V */
662 tcg_gen_movi_tl(cpu_PSW_C, 0);
663 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
664 tcg_gen_mov_tl(ret, r1);
665 } else if (shift_count == -32) {
666 /* set PSW.C */
667 tcg_gen_mov_tl(cpu_PSW_C, r1);
668 /* fill ret completly with sign bit */
669 tcg_gen_sari_tl(ret, r1, 31);
670 /* clear PSW.V */
671 tcg_gen_movi_tl(cpu_PSW_V, 0);
672 } else if (shift_count > 0) {
673 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
674 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
675
676 /* calc carry */
677 msk_start = 32 - shift_count;
678 msk = ((1 << shift_count) - 1) << msk_start;
679 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
680 /* calc v/sv bits */
681 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
682 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
683 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
684 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
685 /* calc sv */
686 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
687 /* do shift */
688 tcg_gen_shli_tl(ret, r1, shift_count);
689
690 tcg_temp_free(t_max);
691 tcg_temp_free(t_min);
692 } else {
693 /* clear PSW.V */
694 tcg_gen_movi_tl(cpu_PSW_V, 0);
695 /* calc carry */
696 msk = (1 << -shift_count) - 1;
697 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
698 /* do shift */
699 tcg_gen_sari_tl(ret, r1, -shift_count);
700 }
701 /* calc av overflow bit */
702 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
703 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
704 /* calc sav overflow bit */
705 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
706
707 tcg_temp_free(temp);
708 tcg_temp_free(temp2);
709 tcg_temp_free(t_0);
710}
711
0974257e
BK		 712static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
713{
714 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
715}
716
717static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
718{
719 TCGv temp = tcg_const_i32(con);
720 gen_shas(ret, r1, temp);
721 tcg_temp_free(temp);
722}
723
724static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
725{
726 TCGv low, high;
727
728 if (shift_count == 0) {
729 tcg_gen_mov_tl(ret, r1);
730 } else if (shift_count > 0) {
731 low = tcg_temp_new();
732 high = tcg_temp_new();
733
734 tcg_gen_andi_tl(high, r1, 0xffff0000);
735 tcg_gen_shli_tl(low, r1, shift_count);
736 tcg_gen_shli_tl(ret, high, shift_count);
737 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
738
739 tcg_temp_free(low);
740 tcg_temp_free(high);
741 } else {
742 low = tcg_temp_new();
743 high = tcg_temp_new();
744
745 tcg_gen_ext16s_tl(low, r1);
746 tcg_gen_sari_tl(low, low, -shift_count);
747 tcg_gen_sari_tl(ret, r1, -shift_count);
748 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
749
750 tcg_temp_free(low);
751 tcg_temp_free(high);
752 }
753
754}
755
756/* ret = {ret[30:0], (r1 cond r2)}; */
757static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
758{
759 TCGv temp = tcg_temp_new();
760 TCGv temp2 = tcg_temp_new();
761
762 tcg_gen_shli_tl(temp, ret, 1);
763 tcg_gen_setcond_tl(cond, temp2, r1, r2);
764 tcg_gen_or_tl(ret, temp, temp2);
765
766 tcg_temp_free(temp);
767 tcg_temp_free(temp2);
768}
769
770static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
771{
772 TCGv temp = tcg_const_i32(con);
773 gen_sh_cond(cond, ret, r1, temp);
774 tcg_temp_free(temp);
775}
776
2692802a
BK		 777static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
778{
779 gen_helper_add_ssov(ret, cpu_env, r1, r2);
780}
781
0974257e
BK		 782static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
783{
784 TCGv temp = tcg_const_i32(con);
785 gen_helper_add_ssov(ret, cpu_env, r1, temp);
786 tcg_temp_free(temp);
787}
788
789static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
790{
791 TCGv temp = tcg_const_i32(con);
792 gen_helper_add_suov(ret, cpu_env, r1, temp);
793 tcg_temp_free(temp);
794}
795
2692802a
BK		 796static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
797{
798 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
799}
800
0974257e
BK		 801static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
802{
803 gen_helper_sub_suov(ret, cpu_env, r1, r2);
804}
805
b74f2b5b
BK		 806static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
807 int pos1, int pos2,
808 void(*op1)(TCGv, TCGv, TCGv),
809 void(*op2)(TCGv, TCGv, TCGv))
810{
811 TCGv temp1, temp2;
812
813 temp1 = tcg_temp_new();
814 temp2 = tcg_temp_new();
815
816 tcg_gen_shri_tl(temp2, r2, pos2);
817 tcg_gen_shri_tl(temp1, r1, pos1);
818
819 (*op1)(temp1, temp1, temp2);
820 (*op2)(temp1 , ret, temp1);
821
822 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
823
824 tcg_temp_free(temp1);
825 tcg_temp_free(temp2);
826}
827
828/* ret = r1[pos1] op1 r2[pos2]; */
829static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
830 int pos1, int pos2,
831 void(*op1)(TCGv, TCGv, TCGv))
832{
833 TCGv temp1, temp2;
834
835 temp1 = tcg_temp_new();
836 temp2 = tcg_temp_new();
837
838 tcg_gen_shri_tl(temp2, r2, pos2);
839 tcg_gen_shri_tl(temp1, r1, pos1);
840
841 (*op1)(ret, temp1, temp2);
842
843 tcg_gen_andi_tl(ret, ret, 0x1);
844
845 tcg_temp_free(temp1);
846 tcg_temp_free(temp2);
847}
848
0974257e
BK		 849static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
850 void(*op)(TCGv, TCGv, TCGv))
851{
852 TCGv temp = tcg_temp_new();
853 TCGv temp2 = tcg_temp_new();
854 /* temp = (arg1 cond arg2 )*/
855 tcg_gen_setcond_tl(cond, temp, r1, r2);
856 /* temp2 = ret[0]*/
857 tcg_gen_andi_tl(temp2, ret, 0x1);
858 /* temp = temp insn temp2 */
859 (*op)(temp, temp, temp2);
860 /* ret = {ret[31:1], temp} */
861 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
862
863 tcg_temp_free(temp);
864 tcg_temp_free(temp2);
865}
866
867static inline void
868gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
869 void(*op)(TCGv, TCGv, TCGv))
870{
871 TCGv temp = tcg_const_i32(con);
872 gen_accumulating_cond(cond, ret, r1, temp, op);
873 tcg_temp_free(temp);
874}
875
876static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
877{
878 TCGv b0 = tcg_temp_new();
879 TCGv b1 = tcg_temp_new();
880 TCGv b2 = tcg_temp_new();
881 TCGv b3 = tcg_temp_new();
882
883 /* byte 0 */
884 tcg_gen_andi_tl(b0, r1, 0xff);
885 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
886
887 /* byte 1 */
888 tcg_gen_andi_tl(b1, r1, 0xff00);
889 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
890
891 /* byte 2 */
892 tcg_gen_andi_tl(b2, r1, 0xff0000);
893 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
894
895 /* byte 3 */
896 tcg_gen_andi_tl(b3, r1, 0xff000000);
897 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
898
899 /* combine them */
900 tcg_gen_or_tl(ret, b0, b1);
901 tcg_gen_or_tl(ret, ret, b2);
902 tcg_gen_or_tl(ret, ret, b3);
903
904 tcg_temp_free(b0);
905 tcg_temp_free(b1);
906 tcg_temp_free(b2);
907 tcg_temp_free(b3);
908}
909
910static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
911{
912 TCGv h0 = tcg_temp_new();
913 TCGv h1 = tcg_temp_new();
914
915 /* halfword 0 */
916 tcg_gen_andi_tl(h0, r1, 0xffff);
917 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
918
919 /* halfword 1 */
920 tcg_gen_andi_tl(h1, r1, 0xffff0000);
921 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
922
923 /* combine them */
924 tcg_gen_or_tl(ret, h0, h1);
925
926 tcg_temp_free(h0);
927 tcg_temp_free(h1);
928}
ed516260
BK		 929/* mask = ((1 << width) -1) << pos;
930 ret = (r1 & ~mask) | (r2 << pos) & mask); */
931static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
932{
933 TCGv mask = tcg_temp_new();
934 TCGv temp = tcg_temp_new();
935 TCGv temp2 = tcg_temp_new();
0974257e 936
ed516260
BK		 937 tcg_gen_movi_tl(mask, 1);
938 tcg_gen_shl_tl(mask, mask, width);
939 tcg_gen_subi_tl(mask, mask, 1);
940 tcg_gen_shl_tl(mask, mask, pos);
941
942 tcg_gen_shl_tl(temp, r2, pos);
943 tcg_gen_and_tl(temp, temp, mask);
944 tcg_gen_andc_tl(temp2, r1, mask);
945 tcg_gen_or_tl(ret, temp, temp2);
946
947 tcg_temp_free(mask);
948 tcg_temp_free(temp);
949 tcg_temp_free(temp2);
950}
0974257e 951
9a31922b
BK		 952/* helpers for generating program flow micro-ops */
953
954static inline void gen_save_pc(target_ulong pc)
955{
956 tcg_gen_movi_tl(cpu_PC, pc);
957}
958
959static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
960{
961 TranslationBlock *tb;
962 tb = ctx->tb;
963 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
964 likely(!ctx->singlestep_enabled)) {
965 tcg_gen_goto_tb(n);
966 gen_save_pc(dest);
967 tcg_gen_exit_tb((uintptr_t)tb + n);
968 } else {
969 gen_save_pc(dest);
970 if (ctx->singlestep_enabled) {
971 /* raise exception debug */
972 }
973 tcg_gen_exit_tb(0);
974 }
975}
976
977static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
978 TCGv r2, int16_t address)
979{
980 int jumpLabel;
981 jumpLabel = gen_new_label();
982 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
983
984 gen_goto_tb(ctx, 1, ctx->next_pc);
985
986 gen_set_label(jumpLabel);
987 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
988}
989
990static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
991 int r2, int16_t address)
992{
993 TCGv temp = tcg_const_i32(r2);
994 gen_branch_cond(ctx, cond, r1, temp, address);
995 tcg_temp_free(temp);
996}
997
a47b50db
BK		 998static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
999{
1000 int l1;
1001 l1 = gen_new_label();
1002
1003 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
1004 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
1005 gen_goto_tb(ctx, 1, ctx->pc + offset);
1006 gen_set_label(l1);
1007 gen_goto_tb(ctx, 0, ctx->next_pc);
1008}
1009
9a31922b
BK		 1010static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
1011 int r2 , int32_t constant , int32_t offset)
1012{
a68e0d54 1013 TCGv temp, temp2;
83c1bb18 1014 int n;
70b02262 1015
9a31922b
BK		 1016 switch (opc) {
1017/* SB-format jumps */
1018 case OPC1_16_SB_J:
1019 case OPC1_32_B_J:
1020 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
1021 break;
f718b0bb 1022 case OPC1_32_B_CALL:
9a31922b
BK		 1023 case OPC1_16_SB_CALL:
1024 gen_helper_1arg(call, ctx->next_pc);
1025 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
1026 break;
1027 case OPC1_16_SB_JZ:
1028 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
1029 break;
1030 case OPC1_16_SB_JNZ:
1031 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
1032 break;
70b02262
BK		 1033/* SBC-format jumps */
1034 case OPC1_16_SBC_JEQ:
1035 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
1036 break;
1037 case OPC1_16_SBC_JNE:
1038 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
1039 break;
1040/* SBRN-format jumps */
1041 case OPC1_16_SBRN_JZ_T:
1042 temp = tcg_temp_new();
1043 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
1044 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
1045 tcg_temp_free(temp);
1046 break;
1047 case OPC1_16_SBRN_JNZ_T:
1048 temp = tcg_temp_new();
1049 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
1050 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
1051 tcg_temp_free(temp);
1052 break;
a47b50db
BK		 1053/* SBR-format jumps */
1054 case OPC1_16_SBR_JEQ:
1055 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
1056 offset);
1057 break;
1058 case OPC1_16_SBR_JNE:
1059 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
1060 offset);
1061 break;
1062 case OPC1_16_SBR_JNZ:
1063 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
1064 break;
1065 case OPC1_16_SBR_JNZ_A:
1066 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
1067 break;
1068 case OPC1_16_SBR_JGEZ:
1069 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
1070 break;
1071 case OPC1_16_SBR_JGTZ:
1072 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
1073 break;
1074 case OPC1_16_SBR_JLEZ:
1075 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
1076 break;
1077 case OPC1_16_SBR_JLTZ:
1078 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
1079 break;
1080 case OPC1_16_SBR_JZ:
1081 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
1082 break;
1083 case OPC1_16_SBR_JZ_A:
1084 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
1085 break;
1086 case OPC1_16_SBR_LOOP:
1087 gen_loop(ctx, r1, offset * 2 - 32);
1088 break;
44ea3430
BK		 1089/* SR-format jumps */
1090 case OPC1_16_SR_JI:
1091 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
1092 tcg_gen_exit_tb(0);
1093 break;
1094 case OPC2_16_SR_RET:
1095 gen_helper_ret(cpu_env);
1096 tcg_gen_exit_tb(0);
1097 break;
f718b0bb
BK		 1098/* B-format */
1099 case OPC1_32_B_CALLA:
1100 gen_helper_1arg(call, ctx->next_pc);
1101 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
1102 break;
1103 case OPC1_32_B_JLA:
1104 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
1105 case OPC1_32_B_JA:
1106 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
1107 break;
1108 case OPC1_32_B_JL:
1109 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
1110 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
1111 break;
fc2ef4a3
BK		 1112/* BOL format */
1113 case OPCM_32_BRC_EQ_NEQ:
1114 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
1115 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
1116 } else {
1117 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
1118 }
1119 break;
1120 case OPCM_32_BRC_GE:
1121 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
1122 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
1123 } else {
1124 constant = MASK_OP_BRC_CONST4(ctx->opcode);
1125 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
1126 offset);
1127 }
1128 break;
1129 case OPCM_32_BRC_JLT:
1130 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
1131 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
1132 } else {
1133 constant = MASK_OP_BRC_CONST4(ctx->opcode);
1134 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
1135 offset);
1136 }
1137 break;
1138 case OPCM_32_BRC_JNE:
1139 temp = tcg_temp_new();
1140 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
1141 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
1142 /* subi is unconditional */
1143 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
1144 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
1145 } else {
1146 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
1147 /* addi is unconditional */
1148 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
1149 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
1150 }
1151 tcg_temp_free(temp);
1152 break;
83c1bb18
BK		 1153/* BRN format */
1154 case OPCM_32_BRN_JTT:
1155 n = MASK_OP_BRN_N(ctx->opcode);
1156
1157 temp = tcg_temp_new();
1158 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
1159
1160 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
1161 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
1162 } else {
1163 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
1164 }
1165 tcg_temp_free(temp);
1166 break;
a68e0d54
BK		 1167/* BRR Format */
1168 case OPCM_32_BRR_EQ_NEQ:
1169 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
1170 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
1171 offset);
1172 } else {
1173 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
1174 offset);
1175 }
1176 break;
1177 case OPCM_32_BRR_ADDR_EQ_NEQ:
1178 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
1179 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
1180 offset);
1181 } else {
1182 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
1183 offset);
1184 }
1185 break;
1186 case OPCM_32_BRR_GE:
1187 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
1188 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
1189 offset);
1190 } else {
1191 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
1192 offset);
1193 }
1194 break;
1195 case OPCM_32_BRR_JLT:
1196 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
1197 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
1198 offset);
1199 } else {
1200 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
1201 offset);
1202 }
1203 break;
1204 case OPCM_32_BRR_LOOP:
1205 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
1206 gen_loop(ctx, r1, offset * 2);
1207 } else {
1208 /* OPC2_32_BRR_LOOPU */
1209 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
1210 }
1211 break;
1212 case OPCM_32_BRR_JNE:
1213 temp = tcg_temp_new();
1214 temp2 = tcg_temp_new();
1215 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
1216 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
1217 /* also save r2, in case of r1 == r2, so r2 is not decremented */
1218 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
1219 /* subi is unconditional */
1220 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
1221 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
1222 } else {
1223 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
1224 /* also save r2, in case of r1 == r2, so r2 is not decremented */
1225 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
1226 /* addi is unconditional */
1227 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
1228 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
1229 }
1230 tcg_temp_free(temp);
1231 tcg_temp_free(temp2);
1232 break;
1233 case OPCM_32_BRR_JNZ:
1234 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
1235 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
1236 } else {
1237 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
1238 }
1239 break;
9a31922b 1240 default:
a47b50db 1241 printf("Branch Error at %x\n", ctx->pc);
9a31922b
BK		 1242 }
1243 ctx->bstate = BS_BRANCH;
1244}
1245
1246
0707ec1b
BK		 1247/*
1248 * Functions for decoding instructions
1249 */
1250
1251static void decode_src_opc(DisasContext *ctx, int op1)
1252{
1253 int r1;
1254 int32_t const4;
1255 TCGv temp, temp2;
1256
1257 r1 = MASK_OP_SRC_S1D(ctx->opcode);
1258 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
1259
1260 switch (op1) {
1261 case OPC1_16_SRC_ADD:
1262 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
1263 break;
1264 case OPC1_16_SRC_ADD_A15:
1265 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
1266 break;
1267 case OPC1_16_SRC_ADD_15A:
1268 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
1269 break;
1270 case OPC1_16_SRC_ADD_A:
1271 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
1272 break;
1273 case OPC1_16_SRC_CADD:
1274 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
1275 cpu_gpr_d[15]);
1276 break;
1277 case OPC1_16_SRC_CADDN:
1278 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
1279 cpu_gpr_d[15]);
1280 break;
1281 case OPC1_16_SRC_CMOV:
1282 temp = tcg_const_tl(0);
1283 temp2 = tcg_const_tl(const4);
1284 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
1285 temp2, cpu_gpr_d[r1]);
1286 tcg_temp_free(temp);
1287 tcg_temp_free(temp2);
1288 break;
1289 case OPC1_16_SRC_CMOVN:
1290 temp = tcg_const_tl(0);
1291 temp2 = tcg_const_tl(const4);
1292 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
1293 temp2, cpu_gpr_d[r1]);
1294 tcg_temp_free(temp);
1295 tcg_temp_free(temp2);
1296 break;
1297 case OPC1_16_SRC_EQ:
1298 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
1299 const4);
1300 break;
1301 case OPC1_16_SRC_LT:
1302 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
1303 const4);
1304 break;
1305 case OPC1_16_SRC_MOV:
1306 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
1307 break;
1308 case OPC1_16_SRC_MOV_A:
1309 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
1310 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
1311 break;
1312 case OPC1_16_SRC_SH:
1313 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
1314 break;
1315 case OPC1_16_SRC_SHA:
1316 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
1317 break;
1318 }
1319}
1320
2692802a
BK		 1321static void decode_srr_opc(DisasContext *ctx, int op1)
1322{
1323 int r1, r2;
1324 TCGv temp;
1325
1326 r1 = MASK_OP_SRR_S1D(ctx->opcode);
1327 r2 = MASK_OP_SRR_S2(ctx->opcode);
1328
1329 switch (op1) {
1330 case OPC1_16_SRR_ADD:
1331 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1332 break;
1333 case OPC1_16_SRR_ADD_A15:
1334 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
1335 break;
1336 case OPC1_16_SRR_ADD_15A:
1337 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1338 break;
1339 case OPC1_16_SRR_ADD_A:
1340 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
1341 break;
1342 case OPC1_16_SRR_ADDS:
1343 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1344 break;
1345 case OPC1_16_SRR_AND:
1346 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1347 break;
1348 case OPC1_16_SRR_CMOV:
1349 temp = tcg_const_tl(0);
1350 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
1351 cpu_gpr_d[r2], cpu_gpr_d[r1]);
1352 tcg_temp_free(temp);
1353 break;
1354 case OPC1_16_SRR_CMOVN:
1355 temp = tcg_const_tl(0);
1356 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
1357 cpu_gpr_d[r2], cpu_gpr_d[r1]);
1358 tcg_temp_free(temp);
1359 break;
1360 case OPC1_16_SRR_EQ:
1361 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
1362 cpu_gpr_d[r2]);
1363 break;
1364 case OPC1_16_SRR_LT:
1365 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
1366 cpu_gpr_d[r2]);
1367 break;
1368 case OPC1_16_SRR_MOV:
1369 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
1370 break;
1371 case OPC1_16_SRR_MOV_A:
1372 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
1373 break;
1374 case OPC1_16_SRR_MOV_AA:
1375 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
1376 break;
1377 case OPC1_16_SRR_MOV_D:
1378 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
1379 break;
1380 case OPC1_16_SRR_MUL:
1381 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1382 break;
1383 case OPC1_16_SRR_OR:
1384 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1385 break;
1386 case OPC1_16_SRR_SUB:
1387 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1388 break;
1389 case OPC1_16_SRR_SUB_A15B:
1390 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
1391 break;
1392 case OPC1_16_SRR_SUB_15AB:
1393 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1394 break;
1395 case OPC1_16_SRR_SUBS:
1396 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1397 break;
1398 case OPC1_16_SRR_XOR:
1399 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1400 break;
1401 }
1402}
1403
46aa848f
BK		 1404static void decode_ssr_opc(DisasContext *ctx, int op1)
1405{
1406 int r1, r2;
1407
1408 r1 = MASK_OP_SSR_S1(ctx->opcode);
1409 r2 = MASK_OP_SSR_S2(ctx->opcode);
1410
1411 switch (op1) {
1412 case OPC1_16_SSR_ST_A:
1413 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
1414 break;
1415 case OPC1_16_SSR_ST_A_POSTINC:
1416 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
1417 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
1418 break;
1419 case OPC1_16_SSR_ST_B:
1420 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
1421 break;
1422 case OPC1_16_SSR_ST_B_POSTINC:
1423 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
1424 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
1425 break;
1426 case OPC1_16_SSR_ST_H:
1427 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
1428 break;
1429 case OPC1_16_SSR_ST_H_POSTINC:
1430 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
1431 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
1432 break;
1433 case OPC1_16_SSR_ST_W:
1434 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
1435 break;
1436 case OPC1_16_SSR_ST_W_POSTINC:
1437 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
1438 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
1439 break;
1440 }
1441}
1442
5de93515
BK		 1443static void decode_sc_opc(DisasContext *ctx, int op1)
1444{
1445 int32_t const16;
1446
1447 const16 = MASK_OP_SC_CONST8(ctx->opcode);
1448
1449 switch (op1) {
1450 case OPC1_16_SC_AND:
1451 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
1452 break;
1453 case OPC1_16_SC_BISR:
1454 gen_helper_1arg(bisr, const16 & 0xff);
1455 break;
1456 case OPC1_16_SC_LD_A:
1457 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
1458 break;
1459 case OPC1_16_SC_LD_W:
1460 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
1461 break;
1462 case OPC1_16_SC_MOV:
1463 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
1464 break;
1465 case OPC1_16_SC_OR:
1466 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
1467 break;
1468 case OPC1_16_SC_ST_A:
1469 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
1470 break;
1471 case OPC1_16_SC_ST_W:
1472 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
1473 break;
1474 case OPC1_16_SC_SUB_A:
1475 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
1476 break;
1477 }
1478}
5a7634a2
BK		 1479
1480static void decode_slr_opc(DisasContext *ctx, int op1)
1481{
1482 int r1, r2;
1483
1484 r1 = MASK_OP_SLR_D(ctx->opcode);
1485 r2 = MASK_OP_SLR_S2(ctx->opcode);
1486
1487 switch (op1) {
1488/* SLR-format */
1489 case OPC1_16_SLR_LD_A:
1490 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
1491 break;
1492 case OPC1_16_SLR_LD_A_POSTINC:
1493 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
1494 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
1495 break;
1496 case OPC1_16_SLR_LD_BU:
1497 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
1498 break;
1499 case OPC1_16_SLR_LD_BU_POSTINC:
1500 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
1501 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
1502 break;
1503 case OPC1_16_SLR_LD_H:
1504 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
1505 break;
1506 case OPC1_16_SLR_LD_H_POSTINC:
1507 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
1508 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
1509 break;
1510 case OPC1_16_SLR_LD_W:
1511 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
1512 break;
1513 case OPC1_16_SLR_LD_W_POSTINC:
1514 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
1515 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
1516 break;
1517 }
1518}
1519
1520static void decode_sro_opc(DisasContext *ctx, int op1)
1521{
1522 int r2;
1523 int32_t address;
1524
1525 r2 = MASK_OP_SRO_S2(ctx->opcode);
1526 address = MASK_OP_SRO_OFF4(ctx->opcode);
1527
1528/* SRO-format */
1529 switch (op1) {
1530 case OPC1_16_SRO_LD_A:
1531 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1532 break;
1533 case OPC1_16_SRO_LD_BU:
1534 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
1535 break;
1536 case OPC1_16_SRO_LD_H:
1537 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
1538 break;
1539 case OPC1_16_SRO_LD_W:
1540 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1541 break;
1542 case OPC1_16_SRO_ST_A:
1543 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1544 break;
1545 case OPC1_16_SRO_ST_B:
1546 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
1547 break;
1548 case OPC1_16_SRO_ST_H:
1549 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
1550 break;
1551 case OPC1_16_SRO_ST_W:
1552 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1553 break;
1554 }
1555}
1556
44ea3430
BK		 1557static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
1558{
1559 uint32_t op2;
1560 op2 = MASK_OP_SR_OP2(ctx->opcode);
1561
1562 switch (op2) {
1563 case OPC2_16_SR_NOP:
1564 break;
1565 case OPC2_16_SR_RET:
1566 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
1567 break;
1568 case OPC2_16_SR_RFE:
1569 gen_helper_rfe(cpu_env);
1570 tcg_gen_exit_tb(0);
1571 ctx->bstate = BS_BRANCH;
1572 break;
1573 case OPC2_16_SR_DEBUG:
1574 /* raise EXCP_DEBUG */
1575 break;
1576 }
1577}
1578
1579static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
1580{
1581 uint32_t op2;
1582 uint32_t r1;
1583 TCGv temp;
1584
1585 r1 = MASK_OP_SR_S1D(ctx->opcode);
1586 op2 = MASK_OP_SR_OP2(ctx->opcode);
1587
1588 switch (op2) {
1589 case OPC2_16_SR_RSUB:
1590 /* overflow only if r1 = -0x80000000 */
1591 temp = tcg_const_i32(-0x80000000);
1592 /* calc V bit */
1593 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
1594 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1595 /* calc SV bit */
1596 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1597 /* sub */
1598 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
1599 /* calc av */
1600 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
1601 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
1602 /* calc sav */
1603 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1604 tcg_temp_free(temp);
1605 break;
1606 case OPC2_16_SR_SAT_B:
1607 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
1608 break;
1609 case OPC2_16_SR_SAT_BU:
1610 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
1611 break;
1612 case OPC2_16_SR_SAT_H:
1613 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
1614 break;
1615 case OPC2_16_SR_SAT_HU:
1616 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
1617 break;
1618 }
1619}
1620
0aaeb118
BK		 1621static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
1622{
0707ec1b 1623 int op1;
d2798210
BK		 1624 int r1, r2;
1625 int32_t const16;
9a31922b 1626 int32_t address;
d2798210 1627 TCGv temp;
0707ec1b
BK		 1628
1629 op1 = MASK_OP_MAJOR(ctx->opcode);
1630
d2798210
BK		 1631 /* handle ADDSC.A opcode only being 6 bit long */
1632 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
1633 op1 = OPC1_16_SRRS_ADDSC_A;
1634 }
1635
0707ec1b
BK		 1636 switch (op1) {
1637 case OPC1_16_SRC_ADD:
1638 case OPC1_16_SRC_ADD_A15:
1639 case OPC1_16_SRC_ADD_15A:
1640 case OPC1_16_SRC_ADD_A:
1641 case OPC1_16_SRC_CADD:
1642 case OPC1_16_SRC_CADDN:
1643 case OPC1_16_SRC_CMOV:
1644 case OPC1_16_SRC_CMOVN:
1645 case OPC1_16_SRC_EQ:
1646 case OPC1_16_SRC_LT:
1647 case OPC1_16_SRC_MOV:
1648 case OPC1_16_SRC_MOV_A:
1649 case OPC1_16_SRC_SH:
1650 case OPC1_16_SRC_SHA:
1651 decode_src_opc(ctx, op1);
1652 break;
2692802a
BK		 1653/* SRR-format */
1654 case OPC1_16_SRR_ADD:
1655 case OPC1_16_SRR_ADD_A15:
1656 case OPC1_16_SRR_ADD_15A:
1657 case OPC1_16_SRR_ADD_A:
1658 case OPC1_16_SRR_ADDS:
1659 case OPC1_16_SRR_AND:
1660 case OPC1_16_SRR_CMOV:
1661 case OPC1_16_SRR_CMOVN:
1662 case OPC1_16_SRR_EQ:
1663 case OPC1_16_SRR_LT:
1664 case OPC1_16_SRR_MOV:
1665 case OPC1_16_SRR_MOV_A:
1666 case OPC1_16_SRR_MOV_AA:
1667 case OPC1_16_SRR_MOV_D:
1668 case OPC1_16_SRR_MUL:
1669 case OPC1_16_SRR_OR:
1670 case OPC1_16_SRR_SUB:
1671 case OPC1_16_SRR_SUB_A15B:
1672 case OPC1_16_SRR_SUB_15AB:
1673 case OPC1_16_SRR_SUBS:
1674 case OPC1_16_SRR_XOR:
1675 decode_srr_opc(ctx, op1);
1676 break;
46aa848f
BK		 1677/* SSR-format */
1678 case OPC1_16_SSR_ST_A:
1679 case OPC1_16_SSR_ST_A_POSTINC:
1680 case OPC1_16_SSR_ST_B:
1681 case OPC1_16_SSR_ST_B_POSTINC:
1682 case OPC1_16_SSR_ST_H:
1683 case OPC1_16_SSR_ST_H_POSTINC:
1684 case OPC1_16_SSR_ST_W:
1685 case OPC1_16_SSR_ST_W_POSTINC:
1686 decode_ssr_opc(ctx, op1);
1687 break;
d2798210
BK		 1688/* SRRS-format */
1689 case OPC1_16_SRRS_ADDSC_A:
1690 r2 = MASK_OP_SRRS_S2(ctx->opcode);
1691 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
1692 const16 = MASK_OP_SRRS_N(ctx->opcode);
1693 temp = tcg_temp_new();
1694 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
1695 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
1696 tcg_temp_free(temp);
1697 break;
1698/* SLRO-format */
1699 case OPC1_16_SLRO_LD_A:
1700 r1 = MASK_OP_SLRO_D(ctx->opcode);
1701 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1702 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1703 break;
1704 case OPC1_16_SLRO_LD_BU:
1705 r1 = MASK_OP_SLRO_D(ctx->opcode);
1706 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1707 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
1708 break;
1709 case OPC1_16_SLRO_LD_H:
1710 r1 = MASK_OP_SLRO_D(ctx->opcode);
1711 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1712 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
1713 break;
1714 case OPC1_16_SLRO_LD_W:
1715 r1 = MASK_OP_SLRO_D(ctx->opcode);
1716 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1717 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1718 break;
9a31922b
BK		 1719/* SB-format */
1720 case OPC1_16_SB_CALL:
1721 case OPC1_16_SB_J:
1722 case OPC1_16_SB_JNZ:
1723 case OPC1_16_SB_JZ:
1724 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
1725 gen_compute_branch(ctx, op1, 0, 0, 0, address);
1726 break;
70b02262
BK		 1727/* SBC-format */
1728 case OPC1_16_SBC_JEQ:
1729 case OPC1_16_SBC_JNE:
1730 address = MASK_OP_SBC_DISP4(ctx->opcode);
1731 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
1732 gen_compute_branch(ctx, op1, 0, 0, const16, address);
1733 break;
1734/* SBRN-format */
1735 case OPC1_16_SBRN_JNZ_T:
1736 case OPC1_16_SBRN_JZ_T:
1737 address = MASK_OP_SBRN_DISP4(ctx->opcode);
1738 const16 = MASK_OP_SBRN_N(ctx->opcode);
1739 gen_compute_branch(ctx, op1, 0, 0, const16, address);
1740 break;
a47b50db
BK		 1741/* SBR-format */
1742 case OPC1_16_SBR_JEQ:
1743 case OPC1_16_SBR_JGEZ:
1744 case OPC1_16_SBR_JGTZ:
1745 case OPC1_16_SBR_JLEZ:
1746 case OPC1_16_SBR_JLTZ:
1747 case OPC1_16_SBR_JNE:
1748 case OPC1_16_SBR_JNZ:
1749 case OPC1_16_SBR_JNZ_A:
1750 case OPC1_16_SBR_JZ:
1751 case OPC1_16_SBR_JZ_A:
1752 case OPC1_16_SBR_LOOP:
1753 r1 = MASK_OP_SBR_S2(ctx->opcode);
1754 address = MASK_OP_SBR_DISP4(ctx->opcode);
1755 gen_compute_branch(ctx, op1, r1, 0, 0, address);
1756 break;
5de93515
BK		 1757/* SC-format */
1758 case OPC1_16_SC_AND:
1759 case OPC1_16_SC_BISR:
1760 case OPC1_16_SC_LD_A:
1761 case OPC1_16_SC_LD_W:
1762 case OPC1_16_SC_MOV:
1763 case OPC1_16_SC_OR:
1764 case OPC1_16_SC_ST_A:
1765 case OPC1_16_SC_ST_W:
1766 case OPC1_16_SC_SUB_A:
1767 decode_sc_opc(ctx, op1);
1768 break;
5a7634a2
BK		 1769/* SLR-format */
1770 case OPC1_16_SLR_LD_A:
1771 case OPC1_16_SLR_LD_A_POSTINC:
1772 case OPC1_16_SLR_LD_BU:
1773 case OPC1_16_SLR_LD_BU_POSTINC:
1774 case OPC1_16_SLR_LD_H:
1775 case OPC1_16_SLR_LD_H_POSTINC:
1776 case OPC1_16_SLR_LD_W:
1777 case OPC1_16_SLR_LD_W_POSTINC:
1778 decode_slr_opc(ctx, op1);
1779 break;
1780/* SRO-format */
1781 case OPC1_16_SRO_LD_A:
1782 case OPC1_16_SRO_LD_BU:
1783 case OPC1_16_SRO_LD_H:
1784 case OPC1_16_SRO_LD_W:
1785 case OPC1_16_SRO_ST_A:
1786 case OPC1_16_SRO_ST_B:
1787 case OPC1_16_SRO_ST_H:
1788 case OPC1_16_SRO_ST_W:
1789 decode_sro_opc(ctx, op1);
1790 break;
1791/* SSRO-format */
1792 case OPC1_16_SSRO_ST_A:
1793 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1794 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1795 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1796 break;
1797 case OPC1_16_SSRO_ST_B:
1798 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1799 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1800 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
1801 break;
1802 case OPC1_16_SSRO_ST_H:
1803 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1804 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1805 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
1806 break;
1807 case OPC1_16_SSRO_ST_W:
1808 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1809 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1810 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1811 break;
44ea3430
BK		 1812/* SR-format */
1813 case OPCM_16_SR_SYSTEM:
1814 decode_sr_system(env, ctx);
1815 break;
1816 case OPCM_16_SR_ACCU:
1817 decode_sr_accu(env, ctx);
1818 break;
1819 case OPC1_16_SR_JI:
1820 r1 = MASK_OP_SR_S1D(ctx->opcode);
1821 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
1822 break;
1823 case OPC1_16_SR_NOT:
1824 r1 = MASK_OP_SR_S1D(ctx->opcode);
1825 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
1826 break;
0707ec1b 1827 }
0aaeb118
BK		 1828}
1829
59543d4e
BK		 1830/*
1831 * 32 bit instructions
1832 */
1833
1834/* ABS-format */
1835static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
1836{
1837 int32_t op2;
1838 int32_t r1;
1839 uint32_t address;
1840 TCGv temp;
1841
1842 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1843 address = MASK_OP_ABS_OFF18(ctx->opcode);
1844 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1845
1846 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1847
1848 switch (op2) {
1849 case OPC2_32_ABS_LD_A:
1850 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
1851 break;
1852 case OPC2_32_ABS_LD_D:
1853 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
1854 break;
1855 case OPC2_32_ABS_LD_DA:
1856 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
1857 break;
1858 case OPC2_32_ABS_LD_W:
1859 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
1860 break;
1861 }
1862
1863 tcg_temp_free(temp);
1864}
1865
1866static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
1867{
1868 int32_t op2;
1869 int32_t r1;
1870 uint32_t address;
1871 TCGv temp;
1872
1873 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1874 address = MASK_OP_ABS_OFF18(ctx->opcode);
1875 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1876
1877 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1878
1879 switch (op2) {
1880 case OPC2_32_ABS_LD_B:
1881 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
1882 break;
1883 case OPC2_32_ABS_LD_BU:
1884 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
1885 break;
1886 case OPC2_32_ABS_LD_H:
1887 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
1888 break;
1889 case OPC2_32_ABS_LD_HU:
1890 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
1891 break;
1892 }
1893
1894 tcg_temp_free(temp);
1895}
1896
1897static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
1898{
1899 int32_t op2;
1900 int32_t r1;
1901 uint32_t address;
1902 TCGv temp;
1903
1904 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1905 address = MASK_OP_ABS_OFF18(ctx->opcode);
1906 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1907
1908 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1909
1910 switch (op2) {
1911 case OPC2_32_ABS_LDMST:
1912 gen_ldmst(ctx, r1, temp);
1913 break;
1914 case OPC2_32_ABS_SWAP_W:
1915 gen_swap(ctx, r1, temp);
1916 break;
1917 }
1918
1919 tcg_temp_free(temp);
1920}
1921
1922static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
1923{
1924 uint32_t op2;
1925 int32_t off18;
1926
1927 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
1928 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1929
1930 switch (op2) {
1931 case OPC2_32_ABS_LDLCX:
1932 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
1933 break;
1934 case OPC2_32_ABS_LDUCX:
1935 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
1936 break;
1937 case OPC2_32_ABS_STLCX:
1938 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
1939 break;
1940 case OPC2_32_ABS_STUCX:
1941 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
1942 break;
1943 }
1944}
1945
1946static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
1947{
1948 int32_t op2;
1949 int32_t r1;
1950 uint32_t address;
1951 TCGv temp;
1952
1953 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1954 address = MASK_OP_ABS_OFF18(ctx->opcode);
1955 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1956
1957 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1958
1959 switch (op2) {
1960 case OPC2_32_ABS_ST_A:
1961 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
1962 break;
1963 case OPC2_32_ABS_ST_D:
1964 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
1965 break;
1966 case OPC2_32_ABS_ST_DA:
1967 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
1968 break;
1969 case OPC2_32_ABS_ST_W:
1970 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
1971 break;
1972
1973 }
1974 tcg_temp_free(temp);
1975}
1976
1977static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
1978{
1979 int32_t op2;
1980 int32_t r1;
1981 uint32_t address;
1982 TCGv temp;
1983
1984 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1985 address = MASK_OP_ABS_OFF18(ctx->opcode);
1986 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1987
1988 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1989
1990 switch (op2) {
1991 case OPC2_32_ABS_ST_B:
1992 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
1993 break;
1994 case OPC2_32_ABS_ST_H:
1995 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
1996 break;
1997 }
1998 tcg_temp_free(temp);
1999}
2000
b74f2b5b
BK		 2001/* Bit-format */
2002
2003static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
2004{
2005 uint32_t op2;
2006 int r1, r2, r3;
2007 int pos1, pos2;
2008
2009 r1 = MASK_OP_BIT_S1(ctx->opcode);
2010 r2 = MASK_OP_BIT_S2(ctx->opcode);
2011 r3 = MASK_OP_BIT_D(ctx->opcode);
2012 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2013 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2014 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2015
2016
2017 switch (op2) {
2018 case OPC2_32_BIT_AND_AND_T:
2019 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2020 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
2021 break;
2022 case OPC2_32_BIT_AND_ANDN_T:
2023 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2024 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
2025 break;
2026 case OPC2_32_BIT_AND_NOR_T:
2027 if (TCG_TARGET_HAS_andc_i32) {
2028 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2029 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
2030 } else {
2031 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2032 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
2033 }
2034 break;
2035 case OPC2_32_BIT_AND_OR_T:
2036 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2037 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
2038 break;
2039 }
2040}
2041
2042static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
2043{
2044 uint32_t op2;
2045 int r1, r2, r3;
2046 int pos1, pos2;
2047 r1 = MASK_OP_BIT_S1(ctx->opcode);
2048 r2 = MASK_OP_BIT_S2(ctx->opcode);
2049 r3 = MASK_OP_BIT_D(ctx->opcode);
2050 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2051 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2052 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2053
2054 switch (op2) {
2055 case OPC2_32_BIT_AND_T:
2056 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2057 pos1, pos2, &tcg_gen_and_tl);
2058 break;
2059 case OPC2_32_BIT_ANDN_T:
2060 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2061 pos1, pos2, &tcg_gen_andc_tl);
2062 break;
2063 case OPC2_32_BIT_NOR_T:
2064 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2065 pos1, pos2, &tcg_gen_nor_tl);
2066 break;
2067 case OPC2_32_BIT_OR_T:
2068 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2069 pos1, pos2, &tcg_gen_or_tl);
2070 break;
2071 }
2072}
2073
2074static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
2075{
2076 uint32_t op2;
2077 int r1, r2, r3;
2078 int pos1, pos2;
2079 TCGv temp;
2080 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2081 r1 = MASK_OP_BIT_S1(ctx->opcode);
2082 r2 = MASK_OP_BIT_S2(ctx->opcode);
2083 r3 = MASK_OP_BIT_D(ctx->opcode);
2084 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2085 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2086
2087 temp = tcg_temp_new();
2088
2089 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
2090 if (op2 == OPC2_32_BIT_INSN_T) {
2091 tcg_gen_not_tl(temp, temp);
2092 }
2093 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
2094 tcg_temp_free(temp);
2095}
2096
2097static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
2098{
2099 uint32_t op2;
2100
2101 int r1, r2, r3;
2102 int pos1, pos2;
2103
2104 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2105 r1 = MASK_OP_BIT_S1(ctx->opcode);
2106 r2 = MASK_OP_BIT_S2(ctx->opcode);
2107 r3 = MASK_OP_BIT_D(ctx->opcode);
2108 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2109 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2110
2111 switch (op2) {
2112 case OPC2_32_BIT_NAND_T:
2113 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2114 pos1, pos2, &tcg_gen_nand_tl);
2115 break;
2116 case OPC2_32_BIT_ORN_T:
2117 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2118 pos1, pos2, &tcg_gen_orc_tl);
2119 break;
2120 case OPC2_32_BIT_XNOR_T:
2121 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2122 pos1, pos2, &tcg_gen_eqv_tl);
2123 break;
2124 case OPC2_32_BIT_XOR_T:
2125 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2126 pos1, pos2, &tcg_gen_xor_tl);
2127 break;
2128 }
2129}
2130
2131static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
2132{
2133 uint32_t op2;
2134
2135 int r1, r2, r3;
2136 int pos1, pos2;
2137
2138 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2139 r1 = MASK_OP_BIT_S1(ctx->opcode);
2140 r2 = MASK_OP_BIT_S2(ctx->opcode);
2141 r3 = MASK_OP_BIT_D(ctx->opcode);
2142 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2143 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2144
2145 switch (op2) {
2146 case OPC2_32_BIT_OR_AND_T:
2147 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2148 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
2149 break;
2150 case OPC2_32_BIT_OR_ANDN_T:
2151 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2152 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
2153 break;
2154 case OPC2_32_BIT_OR_NOR_T:
2155 if (TCG_TARGET_HAS_orc_i32) {
2156 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2157 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
2158 } else {
2159 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2160 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
2161 }
2162 break;
2163 case OPC2_32_BIT_OR_OR_T:
2164 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2165 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
2166 break;
2167 }
2168}
2169
2170static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
2171{
2172 uint32_t op2;
2173 int r1, r2, r3;
2174 int pos1, pos2;
2175 TCGv temp;
2176
2177 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2178 r1 = MASK_OP_BIT_S1(ctx->opcode);
2179 r2 = MASK_OP_BIT_S2(ctx->opcode);
2180 r3 = MASK_OP_BIT_D(ctx->opcode);
2181 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2182 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2183
2184 temp = tcg_temp_new();
2185
2186 switch (op2) {
2187 case OPC2_32_BIT_SH_AND_T:
2188 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2189 pos1, pos2, &tcg_gen_and_tl);
2190 break;
2191 case OPC2_32_BIT_SH_ANDN_T:
2192 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2193 pos1, pos2, &tcg_gen_andc_tl);
2194 break;
2195 case OPC2_32_BIT_SH_NOR_T:
2196 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2197 pos1, pos2, &tcg_gen_nor_tl);
2198 break;
2199 case OPC2_32_BIT_SH_OR_T:
2200 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2201 pos1, pos2, &tcg_gen_or_tl);
2202 break;
2203 }
2204 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
2205 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
2206 tcg_temp_free(temp);
2207}
2208
2209static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
2210{
2211 uint32_t op2;
2212 int r1, r2, r3;
2213 int pos1, pos2;
2214 TCGv temp;
2215
2216 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2217 r1 = MASK_OP_BIT_S1(ctx->opcode);
2218 r2 = MASK_OP_BIT_S2(ctx->opcode);
2219 r3 = MASK_OP_BIT_D(ctx->opcode);
2220 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2221 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2222
2223 temp = tcg_temp_new();
2224
2225 switch (op2) {
2226 case OPC2_32_BIT_SH_NAND_T:
2227 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
2228 pos1, pos2, &tcg_gen_nand_tl);
2229 break;
2230 case OPC2_32_BIT_SH_ORN_T:
2231 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2232 pos1, pos2, &tcg_gen_orc_tl);
2233 break;
2234 case OPC2_32_BIT_SH_XNOR_T:
2235 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2236 pos1, pos2, &tcg_gen_eqv_tl);
2237 break;
2238 case OPC2_32_BIT_SH_XOR_T:
2239 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2240 pos1, pos2, &tcg_gen_xor_tl);
2241 break;
2242 }
2243 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
2244 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
2245 tcg_temp_free(temp);
2246}
2247
3a16ecb0
BK		 2248/* BO-format */
2249
2250
2251static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
2252 DisasContext *ctx)
2253{
2254 uint32_t op2;
2255 uint32_t off10;
2256 int32_t r1, r2;
2257 TCGv temp;
2258
2259 r1 = MASK_OP_BO_S1D(ctx->opcode);
2260 r2 = MASK_OP_BO_S2(ctx->opcode);
2261 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2262 op2 = MASK_OP_BO_OP2(ctx->opcode);
2263
2264 switch (op2) {
2265 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
2266 case OPC2_32_BO_CACHEA_W_SHORTOFF:
2267 case OPC2_32_BO_CACHEA_I_SHORTOFF:
2268 /* instruction to access the cache */
2269 break;
2270 case OPC2_32_BO_CACHEA_WI_POSTINC:
2271 case OPC2_32_BO_CACHEA_W_POSTINC:
2272 case OPC2_32_BO_CACHEA_I_POSTINC:
2273 /* instruction to access the cache, but we still need to handle
2274 the addressing mode */
2275 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
2276 break;
2277 case OPC2_32_BO_CACHEA_WI_PREINC:
2278 case OPC2_32_BO_CACHEA_W_PREINC:
2279 case OPC2_32_BO_CACHEA_I_PREINC:
2280 /* instruction to access the cache, but we still need to handle
2281 the addressing mode */
2282 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
2283 break;
2284 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
2285 case OPC2_32_BO_CACHEI_W_SHORTOFF:
2286 /* TODO: Raise illegal opcode trap,
47e04430 2287 if !tricore_feature(TRICORE_FEATURE_131) */
3a16ecb0
BK		 2288 break;
2289 case OPC2_32_BO_CACHEI_W_POSTINC:
2290 case OPC2_32_BO_CACHEI_WI_POSTINC:
47e04430 2291 if (tricore_feature(env, TRICORE_FEATURE_131)) {
3a16ecb0
BK		 2292 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
2293 } /* TODO: else raise illegal opcode trap */
2294 break;
2295 case OPC2_32_BO_CACHEI_W_PREINC:
2296 case OPC2_32_BO_CACHEI_WI_PREINC:
47e04430 2297 if (tricore_feature(env, TRICORE_FEATURE_131)) {
3a16ecb0
BK		 2298 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
2299 } /* TODO: else raise illegal opcode trap */
2300 break;
2301 case OPC2_32_BO_ST_A_SHORTOFF:
2302 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
2303 break;
2304 case OPC2_32_BO_ST_A_POSTINC:
2305 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
2306 MO_LESL);
2307 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2308 break;
2309 case OPC2_32_BO_ST_A_PREINC:
2310 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
2311 break;
2312 case OPC2_32_BO_ST_B_SHORTOFF:
2313 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
2314 break;
2315 case OPC2_32_BO_ST_B_POSTINC:
2316 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2317 MO_UB);
2318 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2319 break;
2320 case OPC2_32_BO_ST_B_PREINC:
2321 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
2322 break;
2323 case OPC2_32_BO_ST_D_SHORTOFF:
2324 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
2325 off10, ctx);
2326 break;
2327 case OPC2_32_BO_ST_D_POSTINC:
2328 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
2329 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2330 break;
2331 case OPC2_32_BO_ST_D_PREINC:
2332 temp = tcg_temp_new();
2333 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2334 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
2335 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2336 tcg_temp_free(temp);
2337 break;
2338 case OPC2_32_BO_ST_DA_SHORTOFF:
2339 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
2340 off10, ctx);
2341 break;
2342 case OPC2_32_BO_ST_DA_POSTINC:
2343 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
2344 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2345 break;
2346 case OPC2_32_BO_ST_DA_PREINC:
2347 temp = tcg_temp_new();
2348 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2349 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
2350 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2351 tcg_temp_free(temp);
2352 break;
2353 case OPC2_32_BO_ST_H_SHORTOFF:
2354 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2355 break;
2356 case OPC2_32_BO_ST_H_POSTINC:
2357 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2358 MO_LEUW);
2359 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2360 break;
2361 case OPC2_32_BO_ST_H_PREINC:
2362 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2363 break;
2364 case OPC2_32_BO_ST_Q_SHORTOFF:
2365 temp = tcg_temp_new();
2366 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2367 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
2368 tcg_temp_free(temp);
2369 break;
2370 case OPC2_32_BO_ST_Q_POSTINC:
2371 temp = tcg_temp_new();
2372 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2373 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
2374 MO_LEUW);
2375 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2376 tcg_temp_free(temp);
2377 break;
2378 case OPC2_32_BO_ST_Q_PREINC:
2379 temp = tcg_temp_new();
2380 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2381 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
2382 tcg_temp_free(temp);
2383 break;
2384 case OPC2_32_BO_ST_W_SHORTOFF:
2385 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2386 break;
2387 case OPC2_32_BO_ST_W_POSTINC:
2388 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2389 MO_LEUL);
2390 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2391 break;
2392 case OPC2_32_BO_ST_W_PREINC:
2393 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2394 break;
2395 }
2396}
2397
2398static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
2399 DisasContext *ctx)
2400{
2401 uint32_t op2;
2402 uint32_t off10;
2403 int32_t r1, r2;
2404 TCGv temp, temp2, temp3;
2405
2406 r1 = MASK_OP_BO_S1D(ctx->opcode);
2407 r2 = MASK_OP_BO_S2(ctx->opcode);
2408 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2409 op2 = MASK_OP_BO_OP2(ctx->opcode);
2410
2411 temp = tcg_temp_new();
2412 temp2 = tcg_temp_new();
2413 temp3 = tcg_const_i32(off10);
2414
2415 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
2416 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2417
2418 switch (op2) {
2419 case OPC2_32_BO_CACHEA_WI_BR:
2420 case OPC2_32_BO_CACHEA_W_BR:
2421 case OPC2_32_BO_CACHEA_I_BR:
2422 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2423 break;
2424 case OPC2_32_BO_CACHEA_WI_CIRC:
2425 case OPC2_32_BO_CACHEA_W_CIRC:
2426 case OPC2_32_BO_CACHEA_I_CIRC:
2427 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2428 break;
2429 case OPC2_32_BO_ST_A_BR:
2430 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2431 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2432 break;
2433 case OPC2_32_BO_ST_A_CIRC:
2434 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2435 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2436 break;
2437 case OPC2_32_BO_ST_B_BR:
2438 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2439 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2440 break;
2441 case OPC2_32_BO_ST_B_CIRC:
2442 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2443 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2444 break;
2445 case OPC2_32_BO_ST_D_BR:
2446 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
2447 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2448 break;
2449 case OPC2_32_BO_ST_D_CIRC:
2450 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2451 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2452 tcg_gen_addi_tl(temp, temp, 4);
2453 tcg_gen_rem_tl(temp, temp, temp2);
2454 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2455 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2456 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2457 break;
2458 case OPC2_32_BO_ST_DA_BR:
2459 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
2460 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2461 break;
2462 case OPC2_32_BO_ST_DA_CIRC:
2463 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2464 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2465 tcg_gen_addi_tl(temp, temp, 4);
2466 tcg_gen_rem_tl(temp, temp, temp2);
2467 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2468 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2469 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2470 break;
2471 case OPC2_32_BO_ST_H_BR:
2472 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2473 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2474 break;
2475 case OPC2_32_BO_ST_H_CIRC:
2476 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2477 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2478 break;
2479 case OPC2_32_BO_ST_Q_BR:
2480 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2481 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
2482 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2483 break;
2484 case OPC2_32_BO_ST_Q_CIRC:
2485 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2486 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
2487 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2488 break;
2489 case OPC2_32_BO_ST_W_BR:
2490 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2491 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2492 break;
2493 case OPC2_32_BO_ST_W_CIRC:
2494 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2495 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2496 break;
2497 }
2498 tcg_temp_free(temp);
2499 tcg_temp_free(temp2);
2500 tcg_temp_free(temp3);
2501}
2502
2503static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
2504 DisasContext *ctx)
2505{
2506 uint32_t op2;
2507 uint32_t off10;
2508 int32_t r1, r2;
2509 TCGv temp;
2510
2511 r1 = MASK_OP_BO_S1D(ctx->opcode);
2512 r2 = MASK_OP_BO_S2(ctx->opcode);
2513 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2514 op2 = MASK_OP_BO_OP2(ctx->opcode);
2515
2516 switch (op2) {
2517 case OPC2_32_BO_LD_A_SHORTOFF:
2518 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2519 break;
2520 case OPC2_32_BO_LD_A_POSTINC:
2521 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
2522 MO_LEUL);
2523 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2524 break;
2525 case OPC2_32_BO_LD_A_PREINC:
2526 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2527 break;
2528 case OPC2_32_BO_LD_B_SHORTOFF:
2529 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
2530 break;
2531 case OPC2_32_BO_LD_B_POSTINC:
2532 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2533 MO_SB);
2534 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2535 break;
2536 case OPC2_32_BO_LD_B_PREINC:
2537 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
2538 break;
2539 case OPC2_32_BO_LD_BU_SHORTOFF:
2540 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
2541 break;
2542 case OPC2_32_BO_LD_BU_POSTINC:
2543 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2544 MO_UB);
2545 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2546 break;
2547 case OPC2_32_BO_LD_BU_PREINC:
2548 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
2549 break;
2550 case OPC2_32_BO_LD_D_SHORTOFF:
2551 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
2552 off10, ctx);
2553 break;
2554 case OPC2_32_BO_LD_D_POSTINC:
2555 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
2556 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2557 break;
2558 case OPC2_32_BO_LD_D_PREINC:
2559 temp = tcg_temp_new();
2560 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2561 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
2562 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2563 tcg_temp_free(temp);
2564 break;
2565 case OPC2_32_BO_LD_DA_SHORTOFF:
2566 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
2567 off10, ctx);
2568 break;
2569 case OPC2_32_BO_LD_DA_POSTINC:
2570 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
2571 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2572 break;
2573 case OPC2_32_BO_LD_DA_PREINC:
2574 temp = tcg_temp_new();
2575 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2576 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
2577 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2578 tcg_temp_free(temp);
2579 break;
2580 case OPC2_32_BO_LD_H_SHORTOFF:
2581 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
2582 break;
2583 case OPC2_32_BO_LD_H_POSTINC:
2584 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2585 MO_LESW);
2586 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2587 break;
2588 case OPC2_32_BO_LD_H_PREINC:
2589 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
2590 break;
2591 case OPC2_32_BO_LD_HU_SHORTOFF:
2592 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2593 break;
2594 case OPC2_32_BO_LD_HU_POSTINC:
2595 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2596 MO_LEUW);
2597 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2598 break;
2599 case OPC2_32_BO_LD_HU_PREINC:
2600 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2601 break;
2602 case OPC2_32_BO_LD_Q_SHORTOFF:
2603 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2604 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2605 break;
2606 case OPC2_32_BO_LD_Q_POSTINC:
2607 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2608 MO_LEUW);
2609 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2610 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2611 break;
2612 case OPC2_32_BO_LD_Q_PREINC:
2613 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2614 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2615 break;
2616 case OPC2_32_BO_LD_W_SHORTOFF:
2617 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2618 break;
2619 case OPC2_32_BO_LD_W_POSTINC:
2620 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2621 MO_LEUL);
2622 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2623 break;
2624 case OPC2_32_BO_LD_W_PREINC:
2625 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2626 break;
2627 }
2628}
2629
2630static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
2631 DisasContext *ctx)
2632{
2633 uint32_t op2;
2634 uint32_t off10;
2635 int r1, r2;
2636
2637 TCGv temp, temp2, temp3;
2638
2639 r1 = MASK_OP_BO_S1D(ctx->opcode);
2640 r2 = MASK_OP_BO_S2(ctx->opcode);
2641 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2642 op2 = MASK_OP_BO_OP2(ctx->opcode);
2643
2644 temp = tcg_temp_new();
2645 temp2 = tcg_temp_new();
2646 temp3 = tcg_const_i32(off10);
2647
2648 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
2649 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2650
2651
2652 switch (op2) {
2653 case OPC2_32_BO_LD_A_BR:
2654 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2655 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2656 break;
2657 case OPC2_32_BO_LD_A_CIRC:
2658 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2659 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2660 break;
2661 case OPC2_32_BO_LD_B_BR:
2662 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
2663 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2664 break;
2665 case OPC2_32_BO_LD_B_CIRC:
2666 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
2667 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2668 break;
2669 case OPC2_32_BO_LD_BU_BR:
2670 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2671 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2672 break;
2673 case OPC2_32_BO_LD_BU_CIRC:
2674 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2675 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2676 break;
2677 case OPC2_32_BO_LD_D_BR:
2678 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
2679 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2680 break;
2681 case OPC2_32_BO_LD_D_CIRC:
2682 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2683 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2684 tcg_gen_addi_tl(temp, temp, 4);
2685 tcg_gen_rem_tl(temp, temp, temp2);
2686 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2687 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2688 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2689 break;
2690 case OPC2_32_BO_LD_DA_BR:
2691 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
2692 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2693 break;
2694 case OPC2_32_BO_LD_DA_CIRC:
2695 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2696 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2697 tcg_gen_addi_tl(temp, temp, 4);
2698 tcg_gen_rem_tl(temp, temp, temp2);
2699 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2700 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2701 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2702 break;
2703 case OPC2_32_BO_LD_H_BR:
2704 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
2705 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2706 break;
2707 case OPC2_32_BO_LD_H_CIRC:
2708 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
2709 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2710 break;
2711 case OPC2_32_BO_LD_HU_BR:
2712 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2713 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2714 break;
2715 case OPC2_32_BO_LD_HU_CIRC:
2716 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2717 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2718 break;
2719 case OPC2_32_BO_LD_Q_BR:
2720 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2721 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2722 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2723 break;
2724 case OPC2_32_BO_LD_Q_CIRC:
2725 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2726 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2727 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2728 break;
2729 case OPC2_32_BO_LD_W_BR:
2730 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2731 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2732 break;
2733 case OPC2_32_BO_LD_W_CIRC:
2734 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2735 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2736 break;
2737 }
2738 tcg_temp_free(temp);
2739 tcg_temp_free(temp2);
2740 tcg_temp_free(temp3);
2741}
2742
2743static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
2744 DisasContext *ctx)
2745{
2746 uint32_t op2;
2747 uint32_t off10;
2748 int r1, r2;
2749
2750 TCGv temp, temp2;
2751
2752 r1 = MASK_OP_BO_S1D(ctx->opcode);
2753 r2 = MASK_OP_BO_S2(ctx->opcode);
2754 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2755 op2 = MASK_OP_BO_OP2(ctx->opcode);
2756
2757
2758 temp = tcg_temp_new();
2759 temp2 = tcg_temp_new();
2760
2761 switch (op2) {
2762 case OPC2_32_BO_LDLCX_SHORTOFF:
2763 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2764 gen_helper_ldlcx(cpu_env, temp);
2765 break;
2766 case OPC2_32_BO_LDMST_SHORTOFF:
2767 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2768 gen_ldmst(ctx, r1, temp);
2769 break;
2770 case OPC2_32_BO_LDMST_POSTINC:
2771 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
2772 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2773 break;
2774 case OPC2_32_BO_LDMST_PREINC:
2775 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2776 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
2777 break;
2778 case OPC2_32_BO_LDUCX_SHORTOFF:
2779 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2780 gen_helper_lducx(cpu_env, temp);
2781 break;
2782 case OPC2_32_BO_LEA_SHORTOFF:
2783 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
2784 break;
2785 case OPC2_32_BO_STLCX_SHORTOFF:
2786 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2787 gen_helper_stlcx(cpu_env, temp);
2788 break;
2789 case OPC2_32_BO_STUCX_SHORTOFF:
2790 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2791 gen_helper_stucx(cpu_env, temp);
2792 break;
2793 case OPC2_32_BO_SWAP_W_SHORTOFF:
2794 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2795 gen_swap(ctx, r1, temp);
2796 break;
2797 case OPC2_32_BO_SWAP_W_POSTINC:
2798 gen_swap(ctx, r1, cpu_gpr_a[r2]);
2799 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2800 break;
2801 case OPC2_32_BO_SWAP_W_PREINC:
2802 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2803 gen_swap(ctx, r1, cpu_gpr_a[r2]);
2804 break;
2805 }
2806 tcg_temp_free(temp);
2807 tcg_temp_free(temp2);
2808}
2809
2810static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
2811 DisasContext *ctx)
2812{
2813 uint32_t op2;
2814 uint32_t off10;
2815 int r1, r2;
2816
2817 TCGv temp, temp2, temp3;
2818
2819 r1 = MASK_OP_BO_S1D(ctx->opcode);
2820 r2 = MASK_OP_BO_S2(ctx->opcode);
2821 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2822 op2 = MASK_OP_BO_OP2(ctx->opcode);
2823
2824 temp = tcg_temp_new();
2825 temp2 = tcg_temp_new();
2826 temp3 = tcg_const_i32(off10);
2827
2828 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
2829 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2830
2831 switch (op2) {
2832 case OPC2_32_BO_LDMST_BR:
2833 gen_ldmst(ctx, r1, temp2);
2834 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2835 break;
2836 case OPC2_32_BO_LDMST_CIRC:
2837 gen_ldmst(ctx, r1, temp2);
2838 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2839 break;
2840 case OPC2_32_BO_SWAP_W_BR:
2841 gen_swap(ctx, r1, temp2);
2842 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2843 break;
2844 case OPC2_32_BO_SWAP_W_CIRC:
2845 gen_swap(ctx, r1, temp2);
2846 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2847 break;
2848 }
2849 tcg_temp_free(temp);
2850 tcg_temp_free(temp2);
2851 tcg_temp_free(temp3);
2852}
2853
3fb763cb
BK		 2854static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
2855{
2856 int r1, r2;
2857 int32_t address;
2858 TCGv temp;
2859
2860 r1 = MASK_OP_BOL_S1D(ctx->opcode);
2861 r2 = MASK_OP_BOL_S2(ctx->opcode);
2862 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
2863
2864 switch (op1) {
2865 case OPC1_32_BOL_LD_A_LONGOFF:
2866 temp = tcg_temp_new();
2867 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
2868 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
2869 tcg_temp_free(temp);
2870 break;
2871 case OPC1_32_BOL_LD_W_LONFOFF:
2872 temp = tcg_temp_new();
2873 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
2874 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
2875 tcg_temp_free(temp);
2876 break;
2877 case OPC1_32_BOL_LEA_LONGOFF:
2878 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
2879 break;
2880 case OPC1_32_BOL_ST_A_LONGOFF:
2881 if (tricore_feature(env, TRICORE_FEATURE_16)) {
2882 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
2883 } else {
2884 /* raise illegal opcode trap */
2885 }
2886 break;
2887 case OPC1_32_BOL_ST_W_LONGOFF:
2888 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
2889 break;
2890 }
2891
2892}
2893
0974257e
BK		 2894/* RC format */
2895static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
2896{
2897 uint32_t op2;
2898 int r1, r2;
2899 int32_t const9;
2900 TCGv temp;
2901
2902 r2 = MASK_OP_RC_D(ctx->opcode);
2903 r1 = MASK_OP_RC_S1(ctx->opcode);
2904 const9 = MASK_OP_RC_CONST9(ctx->opcode);
2905 op2 = MASK_OP_RC_OP2(ctx->opcode);
2906
2907 temp = tcg_temp_new();
2908
2909 switch (op2) {
2910 case OPC2_32_RC_AND:
2911 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2912 break;
2913 case OPC2_32_RC_ANDN:
2914 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
2915 break;
2916 case OPC2_32_RC_NAND:
2917 tcg_gen_movi_tl(temp, const9);
2918 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
2919 break;
2920 case OPC2_32_RC_NOR:
2921 tcg_gen_movi_tl(temp, const9);
2922 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
2923 break;
2924 case OPC2_32_RC_OR:
2925 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2926 break;
2927 case OPC2_32_RC_ORN:
2928 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
2929 break;
2930 case OPC2_32_RC_SH:
2931 const9 = sextract32(const9, 0, 6);
2932 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2933 break;
2934 case OPC2_32_RC_SH_H:
2935 const9 = sextract32(const9, 0, 5);
2936 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2937 break;
2938 case OPC2_32_RC_SHA:
2939 const9 = sextract32(const9, 0, 6);
2940 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2941 break;
2942 case OPC2_32_RC_SHA_H:
2943 const9 = sextract32(const9, 0, 5);
2944 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2945 break;
2946 case OPC2_32_RC_SHAS:
2947 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2948 break;
2949 case OPC2_32_RC_XNOR:
2950 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2951 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
2952 break;
2953 case OPC2_32_RC_XOR:
2954 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2955 break;
2956 }
2957 tcg_temp_free(temp);
2958}
2959
2960static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
2961{
2962 uint32_t op2;
2963 int r1, r2;
2964 int16_t const9;
2965
2966 TCGv temp;
2967
2968 r2 = MASK_OP_RC_D(ctx->opcode);
2969 r1 = MASK_OP_RC_S1(ctx->opcode);
2970 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
2971
2972 op2 = MASK_OP_RC_OP2(ctx->opcode);
2973
2974 temp = tcg_temp_new();
2975
2976 switch (op2) {
2977 case OPC2_32_RC_ABSDIF:
2978 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2979 break;
2980 case OPC2_32_RC_ABSDIFS:
2981 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2982 break;
2983 case OPC2_32_RC_ADD:
2984 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2985 break;
2986 case OPC2_32_RC_ADDC:
2987 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2988 break;
2989 case OPC2_32_RC_ADDS:
2990 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2991 break;
2992 case OPC2_32_RC_ADDS_U:
2993 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2994 break;
2995 case OPC2_32_RC_ADDX:
2996 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2997 break;
2998 case OPC2_32_RC_AND_EQ:
2999 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
3000 const9, &tcg_gen_and_tl);
3001 break;
3002 case OPC2_32_RC_AND_GE:
3003 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
3004 const9, &tcg_gen_and_tl);
3005 break;
3006 case OPC2_32_RC_AND_GE_U:
3007 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3008 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3009 const9, &tcg_gen_and_tl);
3010 break;
3011 case OPC2_32_RC_AND_LT:
3012 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
3013 const9, &tcg_gen_and_tl);
3014 break;
3015 case OPC2_32_RC_AND_LT_U:
3016 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3017 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3018 const9, &tcg_gen_and_tl);
3019 break;
3020 case OPC2_32_RC_AND_NE:
3021 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
3022 const9, &tcg_gen_and_tl);
3023 break;
3024 case OPC2_32_RC_EQ:
3025 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3026 break;
3027 case OPC2_32_RC_EQANY_B:
3028 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3029 break;
3030 case OPC2_32_RC_EQANY_H:
3031 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3032 break;
3033 case OPC2_32_RC_GE:
3034 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3035 break;
3036 case OPC2_32_RC_GE_U:
3037 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3038 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3039 break;
3040 case OPC2_32_RC_LT:
3041 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3042 break;
3043 case OPC2_32_RC_LT_U:
3044 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3045 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3046 break;
3047 case OPC2_32_RC_MAX:
3048 tcg_gen_movi_tl(temp, const9);
3049 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
3050 cpu_gpr_d[r1], temp);
3051 break;
3052 case OPC2_32_RC_MAX_U:
3053 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
3054 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
3055 cpu_gpr_d[r1], temp);
3056 break;
3057 case OPC2_32_RC_MIN:
3058 tcg_gen_movi_tl(temp, const9);
3059 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
3060 cpu_gpr_d[r1], temp);
3061 break;
3062 case OPC2_32_RC_MIN_U:
3063 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
3064 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
3065 cpu_gpr_d[r1], temp);
3066 break;
3067 case OPC2_32_RC_NE:
3068 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3069 break;
3070 case OPC2_32_RC_OR_EQ:
3071 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
3072 const9, &tcg_gen_or_tl);
3073 break;
3074 case OPC2_32_RC_OR_GE:
3075 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
3076 const9, &tcg_gen_or_tl);
3077 break;
3078 case OPC2_32_RC_OR_GE_U:
3079 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3080 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3081 const9, &tcg_gen_or_tl);
3082 break;
3083 case OPC2_32_RC_OR_LT:
3084 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
3085 const9, &tcg_gen_or_tl);
3086 break;
3087 case OPC2_32_RC_OR_LT_U:
3088 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3089 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3090 const9, &tcg_gen_or_tl);
3091 break;
3092 case OPC2_32_RC_OR_NE:
3093 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
3094 const9, &tcg_gen_or_tl);
3095 break;
3096 case OPC2_32_RC_RSUB:
3097 tcg_gen_movi_tl(temp, const9);
3098 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
3099 break;
3100 case OPC2_32_RC_RSUBS:
3101 tcg_gen_movi_tl(temp, const9);
3102 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
3103 break;
3104 case OPC2_32_RC_RSUBS_U:
3105 tcg_gen_movi_tl(temp, const9);
3106 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
3107 break;
3108 case OPC2_32_RC_SH_EQ:
3109 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3110 break;
3111 case OPC2_32_RC_SH_GE:
3112 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3113 break;
3114 case OPC2_32_RC_SH_GE_U:
3115 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3116 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3117 break;
3118 case OPC2_32_RC_SH_LT:
3119 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3120 break;
3121 case OPC2_32_RC_SH_LT_U:
3122 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3123 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3124 break;
3125 case OPC2_32_RC_SH_NE:
3126 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3127 break;
3128 case OPC2_32_RC_XOR_EQ:
3129 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
3130 const9, &tcg_gen_xor_tl);
3131 break;
3132 case OPC2_32_RC_XOR_GE:
3133 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
3134 const9, &tcg_gen_xor_tl);
3135 break;
3136 case OPC2_32_RC_XOR_GE_U:
3137 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3138 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3139 const9, &tcg_gen_xor_tl);
3140 break;
3141 case OPC2_32_RC_XOR_LT:
3142 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
3143 const9, &tcg_gen_xor_tl);
3144 break;
3145 case OPC2_32_RC_XOR_LT_U:
3146 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3147 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3148 const9, &tcg_gen_xor_tl);
3149 break;
3150 case OPC2_32_RC_XOR_NE:
3151 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
3152 const9, &tcg_gen_xor_tl);
3153 break;
3154 }
3155 tcg_temp_free(temp);
3156}
3157
3158static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
3159{
3160 uint32_t op2;
3161 uint32_t const9;
3162
3163 op2 = MASK_OP_RC_OP2(ctx->opcode);
3164 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3165
3166 switch (op2) {
3167 case OPC2_32_RC_BISR:
3168 gen_helper_1arg(bisr, const9);
3169 break;
3170 case OPC2_32_RC_SYSCALL:
3171 /* TODO: Add exception generation */
3172 break;
3173 }
3174}
3175
3176static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
3177{
3178 uint32_t op2;
3179 int r1, r2;
3180 int16_t const9;
3181
3182 r2 = MASK_OP_RC_D(ctx->opcode);
3183 r1 = MASK_OP_RC_S1(ctx->opcode);
3184 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
3185
3186 op2 = MASK_OP_RC_OP2(ctx->opcode);
3187
3188 switch (op2) {
3189 case OPC2_32_RC_MUL_32:
3190 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3191 break;
3192 case OPC2_32_RC_MUL_64:
3193 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
3194 break;
3195 case OPC2_32_RC_MULS_32:
3196 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3197 break;
3198 case OPC2_32_RC_MUL_U_64:
3199 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3200 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
3201 break;
3202 case OPC2_32_RC_MULS_U_32:
3203 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3204 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3205 break;
3206 }
3207}
3208
ed516260
BK		 3209/* RCPW format */
3210static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
3211{
3212 uint32_t op2;
3213 int r1, r2;
3214 int32_t pos, width, const4;
3215
3216 TCGv temp;
3217
3218 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
3219 r1 = MASK_OP_RCPW_S1(ctx->opcode);
3220 r2 = MASK_OP_RCPW_D(ctx->opcode);
3221 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
3222 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
3223 pos = MASK_OP_RCPW_POS(ctx->opcode);
3224
3225 switch (op2) {
3226 case OPC2_32_RCPW_IMASK:
3227 /* if pos + width > 31 undefined result */
3228 if (pos + width <= 31) {
3229 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
3230 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
3231 }
3232 break;
3233 case OPC2_32_RCPW_INSERT:
3234 /* if pos + width > 32 undefined result */
3235 if (pos + width <= 32) {
3236 temp = tcg_const_i32(const4);
3237 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
3238 tcg_temp_free(temp);
3239 }
3240 break;
3241 }
3242}
3243
3244/* RCRW format */
3245
3246static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
3247{
3248 uint32_t op2;
3249 int r1, r3, r4;
3250 int32_t width, const4;
3251
3252 TCGv temp, temp2, temp3;
3253
3254 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
3255 r1 = MASK_OP_RCRW_S1(ctx->opcode);
3256 r3 = MASK_OP_RCRW_S3(ctx->opcode);
3257 r4 = MASK_OP_RCRW_D(ctx->opcode);
3258 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
3259 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
3260
3261 temp = tcg_temp_new();
3262 temp2 = tcg_temp_new();
3263
3264 switch (op2) {
3265 case OPC2_32_RCRW_IMASK:
3266 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
3267 tcg_gen_movi_tl(temp2, (1 << width) - 1);
3268 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
3269 tcg_gen_movi_tl(temp2, const4);
3270 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
3271 break;
3272 case OPC2_32_RCRW_INSERT:
3273 temp3 = tcg_temp_new();
3274
3275 tcg_gen_movi_tl(temp, width);
3276 tcg_gen_movi_tl(temp2, const4);
3277 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
3278 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
3279
3280 tcg_temp_free(temp3);
3281 break;
3282 }
3283 tcg_temp_free(temp);
3284 tcg_temp_free(temp2);
3285}
3286
2b2f7d97
BK		 3287/* RLC format */
3288
3289static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
3290 uint32_t op1)
3291{
3292 int32_t const16;
3293 int r1, r2;
3294
3295 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
3296 r1 = MASK_OP_RLC_S1(ctx->opcode);
3297 r2 = MASK_OP_RLC_D(ctx->opcode);
3298
3299 switch (op1) {
3300 case OPC1_32_RLC_ADDI:
3301 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
3302 break;
3303 case OPC1_32_RLC_ADDIH:
3304 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
3305 break;
3306 case OPC1_32_RLC_ADDIH_A:
3307 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
3308 break;
3309 case OPC1_32_RLC_MFCR:
3310 gen_mfcr(env, cpu_gpr_d[r2], const16);
3311 break;
3312 case OPC1_32_RLC_MOV:
3313 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
3314 break;
3315 case OPC1_32_RLC_MOV_U:
3316 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
3317 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
3318 break;
3319 case OPC1_32_RLC_MOV_H:
3320 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
3321 break;
3322 case OPC1_32_RLC_MOVH_A:
3323 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
3324 break;
3325 case OPC1_32_RLC_MTCR:
3326 gen_mtcr(env, ctx, cpu_gpr_d[r2], const16);
3327 break;
3328 }
3329}
3330
0aaeb118
BK		 3331static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
3332{
59543d4e 3333 int op1;
ed516260
BK		 3334 int32_t r1, r2, r3;
3335 int32_t address, const16;
fc2ef4a3 3336 int8_t b, const4;
59543d4e 3337 int32_t bpos;
ed516260 3338 TCGv temp, temp2, temp3;
59543d4e
BK		 3339
3340 op1 = MASK_OP_MAJOR(ctx->opcode);
3341
83c1bb18
BK		 3342 /* handle JNZ.T opcode only being 6 bit long */
3343 if (unlikely((op1 & 0x3f) == OPCM_32_BRN_JTT)) {
3344 op1 = OPCM_32_BRN_JTT;
3345 }
3346
59543d4e
BK		 3347 switch (op1) {
3348/* ABS-format */
3349 case OPCM_32_ABS_LDW:
3350 decode_abs_ldw(env, ctx);
3351 break;
3352 case OPCM_32_ABS_LDB:
3353 decode_abs_ldb(env, ctx);
3354 break;
3355 case OPCM_32_ABS_LDMST_SWAP:
3356 decode_abs_ldst_swap(env, ctx);
3357 break;
3358 case OPCM_32_ABS_LDST_CONTEXT:
3359 decode_abs_ldst_context(env, ctx);
3360 break;
3361 case OPCM_32_ABS_STORE:
3362 decode_abs_store(env, ctx);
3363 break;
3364 case OPCM_32_ABS_STOREB_H:
3365 decode_abs_storeb_h(env, ctx);
3366 break;
3367 case OPC1_32_ABS_STOREQ:
3368 address = MASK_OP_ABS_OFF18(ctx->opcode);
3369 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3370 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3371 temp2 = tcg_temp_new();
3372
3373 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
3374 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
3375
3376 tcg_temp_free(temp2);
3377 tcg_temp_free(temp);
3378 break;
3379 case OPC1_32_ABS_LD_Q:
3380 address = MASK_OP_ABS_OFF18(ctx->opcode);
3381 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3382 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3383
3384 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3385 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
3386
3387 tcg_temp_free(temp);
3388 break;
3389 case OPC1_32_ABS_LEA:
3390 address = MASK_OP_ABS_OFF18(ctx->opcode);
3391 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3392 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
3393 break;
3394/* ABSB-format */
3395 case OPC1_32_ABSB_ST_T:
3396 address = MASK_OP_ABS_OFF18(ctx->opcode);
3397 b = MASK_OP_ABSB_B(ctx->opcode);
3398 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
3399
3400 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3401 temp2 = tcg_temp_new();
3402
3403 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
3404 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
3405 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
3406 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
3407
3408 tcg_temp_free(temp);
3409 tcg_temp_free(temp2);
3410 break;
f718b0bb
BK		 3411/* B-format */
3412 case OPC1_32_B_CALL:
3413 case OPC1_32_B_CALLA:
3414 case OPC1_32_B_J:
3415 case OPC1_32_B_JA:
3416 case OPC1_32_B_JL:
3417 case OPC1_32_B_JLA:
3418 address = MASK_OP_B_DISP24(ctx->opcode);
3419 gen_compute_branch(ctx, op1, 0, 0, 0, address);
3420 break;
b74f2b5b
BK		 3421/* Bit-format */
3422 case OPCM_32_BIT_ANDACC:
3423 decode_bit_andacc(env, ctx);
3424 break;
3425 case OPCM_32_BIT_LOGICAL_T1:
3426 decode_bit_logical_t(env, ctx);
3427 break;
3428 case OPCM_32_BIT_INSERT:
3429 decode_bit_insert(env, ctx);
3430 break;
3431 case OPCM_32_BIT_LOGICAL_T2:
3432 decode_bit_logical_t2(env, ctx);
3433 break;
3434 case OPCM_32_BIT_ORAND:
3435 decode_bit_orand(env, ctx);
3436 break;
3437 case OPCM_32_BIT_SH_LOGIC1:
3438 decode_bit_sh_logic1(env, ctx);
3439 break;
3440 case OPCM_32_BIT_SH_LOGIC2:
3441 decode_bit_sh_logic2(env, ctx);
3442 break;
3a16ecb0
BK		 3443 /* BO Format */
3444 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
3445 decode_bo_addrmode_post_pre_base(env, ctx);
3446 break;
3447 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
3448 decode_bo_addrmode_bitreverse_circular(env, ctx);
3449 break;
3450 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
3451 decode_bo_addrmode_ld_post_pre_base(env, ctx);
3452 break;
3453 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
3454 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
3455 break;
3456 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
3457 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
3458 break;
3459 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
3460 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
3461 break;
3fb763cb
BK		 3462/* BOL-format */
3463 case OPC1_32_BOL_LD_A_LONGOFF:
3464 case OPC1_32_BOL_LD_W_LONFOFF:
3465 case OPC1_32_BOL_LEA_LONGOFF:
3466 case OPC1_32_BOL_ST_W_LONGOFF:
3467 case OPC1_32_BOL_ST_A_LONGOFF:
3468 decode_bol_opc(env, ctx, op1);
3469 break;
fc2ef4a3
BK		 3470/* BRC Format */
3471 case OPCM_32_BRC_EQ_NEQ:
3472 case OPCM_32_BRC_GE:
3473 case OPCM_32_BRC_JLT:
3474 case OPCM_32_BRC_JNE:
3475 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
3476 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
3477 r1 = MASK_OP_BRC_S1(ctx->opcode);
3478 gen_compute_branch(ctx, op1, r1, 0, const4, address);
3479 break;
83c1bb18
BK		 3480/* BRN Format */
3481 case OPCM_32_BRN_JTT:
3482 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
3483 r1 = MASK_OP_BRN_S1(ctx->opcode);
3484 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3485 break;
a68e0d54
BK		 3486/* BRR Format */
3487 case OPCM_32_BRR_EQ_NEQ:
3488 case OPCM_32_BRR_ADDR_EQ_NEQ:
3489 case OPCM_32_BRR_GE:
3490 case OPCM_32_BRR_JLT:
3491 case OPCM_32_BRR_JNE:
3492 case OPCM_32_BRR_JNZ:
3493 case OPCM_32_BRR_LOOP:
3494 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
3495 r2 = MASK_OP_BRR_S2(ctx->opcode);
3496 r1 = MASK_OP_BRR_S1(ctx->opcode);
3497 gen_compute_branch(ctx, op1, r1, r2, 0, address);
3498 break;
0974257e
BK		 3499/* RC Format */
3500 case OPCM_32_RC_LOGICAL_SHIFT:
3501 decode_rc_logical_shift(env, ctx);
3502 break;
3503 case OPCM_32_RC_ACCUMULATOR:
3504 decode_rc_accumulator(env, ctx);
3505 break;
3506 case OPCM_32_RC_SERVICEROUTINE:
3507 decode_rc_serviceroutine(env, ctx);
3508 break;
3509 case OPCM_32_RC_MUL:
3510 decode_rc_mul(env, ctx);
3511 break;
ed516260
BK		 3512/* RCPW Format */
3513 case OPCM_32_RCPW_MASK_INSERT:
3514 decode_rcpw_insert(env, ctx);
3515 break;
3516/* RCRR Format */
3517 case OPC1_32_RCRR_INSERT:
3518 r1 = MASK_OP_RCRR_S1(ctx->opcode);
3519 r2 = MASK_OP_RCRR_S3(ctx->opcode);
3520 r3 = MASK_OP_RCRR_D(ctx->opcode);
3521 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
3522 temp = tcg_const_i32(const16);
3523 temp2 = tcg_temp_new(); /* width*/
3524 temp3 = tcg_temp_new(); /* pos */
3525
3526 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
3527 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
3528
3529 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
3530
3531 tcg_temp_free(temp);
3532 tcg_temp_free(temp2);
3533 tcg_temp_free(temp3);
3534 break;
3535/* RCRW Format */
3536 case OPCM_32_RCRW_MASK_INSERT:
3537 decode_rcrw_insert(env, ctx);
3538 break;
2b2f7d97
BK		 3539/* RLC Format */
3540 case OPC1_32_RLC_ADDI:
3541 case OPC1_32_RLC_ADDIH:
3542 case OPC1_32_RLC_ADDIH_A:
3543 case OPC1_32_RLC_MFCR:
3544 case OPC1_32_RLC_MOV:
3545 case OPC1_32_RLC_MOV_U:
3546 case OPC1_32_RLC_MOV_H:
3547 case OPC1_32_RLC_MOVH_A:
3548 case OPC1_32_RLC_MTCR:
3549 decode_rlc_opc(env, ctx, op1);
3550 break;
59543d4e 3551 }
0aaeb118
BK		 3552}
3553
3554static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
3555{
3556 /* 16-Bit Instruction */
3557 if ((ctx->opcode & 0x1) == 0) {
3558 ctx->next_pc = ctx->pc + 2;
3559 decode_16Bit_opc(env, ctx);
3560 /* 32-Bit Instruction */
3561 } else {
3562 ctx->next_pc = ctx->pc + 4;
3563 decode_32Bit_opc(env, ctx);
3564 }
3565}
3566
48e06fe0
BK		 3567static inline void
3568gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
3569 int search_pc)
3570{
0aaeb118
BK		 3571 CPUState *cs = CPU(cpu);
3572 CPUTriCoreState *env = &cpu->env;
3573 DisasContext ctx;
3574 target_ulong pc_start;
3575 int num_insns;
3576 uint16_t *gen_opc_end;
3577
3578 if (search_pc) {
3579 qemu_log("search pc %d\n", search_pc);
3580 }
3581
3582 num_insns = 0;
3583 pc_start = tb->pc;
3584 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
3585 ctx.pc = pc_start;
3586 ctx.saved_pc = -1;
3587 ctx.tb = tb;
3588 ctx.singlestep_enabled = cs->singlestep_enabled;
3589 ctx.bstate = BS_NONE;
3590 ctx.mem_idx = cpu_mmu_index(env);
3591
3592 tcg_clear_temp_count();
3593 gen_tb_start();
3594 while (ctx.bstate == BS_NONE) {
3595 ctx.opcode = cpu_ldl_code(env, ctx.pc);
3596 decode_opc(env, &ctx, 0);
3597
3598 num_insns++;
3599
3600 if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
9a31922b
BK		 3601 gen_save_pc(ctx.next_pc);
3602 tcg_gen_exit_tb(0);
0aaeb118
BK		 3603 break;
3604 }
3605 if (singlestep) {
9a31922b
BK		 3606 gen_save_pc(ctx.next_pc);
3607 tcg_gen_exit_tb(0);
0aaeb118
BK		 3608 break;
3609 }
3610 ctx.pc = ctx.next_pc;
3611 }
3612
3613 gen_tb_end(tb, num_insns);
3614 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3615 if (search_pc) {
3616 printf("done_generating search pc\n");
3617 } else {
3618 tb->size = ctx.pc - pc_start;
3619 tb->icount = num_insns;
3620 }
3621 if (tcg_check_temp_count()) {
3622 printf("LEAK at %08x\n", env->PC);
3623 }
3624
3625#ifdef DEBUG_DISAS
3626 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3627 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3628 log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
3629 qemu_log("\n");
3630 }
3631#endif
48e06fe0
BK		 3632}
3633
3634void
3635gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
3636{
3637 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
3638}
3639
3640void
3641gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
3642{
3643 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
3644}
3645
3646void
3647restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
3648{
3649 env->PC = tcg_ctx.gen_opc_pc[pc_pos];
3650}
3651/*
3652 *
3653 * Initialization
3654 *
3655 */
3656
3657void cpu_state_reset(CPUTriCoreState *env)
3658{
0aaeb118
BK		 3659 /* Reset Regs to Default Value */
3660 env->PSW = 0xb80;
3661}
3662
3663static void tricore_tcg_init_csfr(void)
3664{
3665 cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
3666 offsetof(CPUTriCoreState, PCXI), "PCXI");
3667 cpu_PSW = tcg_global_mem_new(TCG_AREG0,
3668 offsetof(CPUTriCoreState, PSW), "PSW");
3669 cpu_PC = tcg_global_mem_new(TCG_AREG0,
3670 offsetof(CPUTriCoreState, PC), "PC");
3671 cpu_ICR = tcg_global_mem_new(TCG_AREG0,
3672 offsetof(CPUTriCoreState, ICR), "ICR");
48e06fe0
BK		 3673}
3674
3675void tricore_tcg_init(void)
3676{
0aaeb118
BK		 3677 int i;
3678 static int inited;
3679 if (inited) {
3680 return;
3681 }
3682 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3683 /* reg init */
3684 for (i = 0 ; i < 16 ; i++) {
3685 cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
3686 offsetof(CPUTriCoreState, gpr_a[i]),
3687 regnames_a[i]);
3688 }
3689 for (i = 0 ; i < 16 ; i++) {
3690 cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
3691 offsetof(CPUTriCoreState, gpr_d[i]),
3692 regnames_d[i]);
3693 }
3694 tricore_tcg_init_csfr();
3695 /* init PSW flag cache */
3696 cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
3697 offsetof(CPUTriCoreState, PSW_USB_C),
3698 "PSW_C");
3699 cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
3700 offsetof(CPUTriCoreState, PSW_USB_V),
3701 "PSW_V");
3702 cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
3703 offsetof(CPUTriCoreState, PSW_USB_SV),
3704 "PSW_SV");
3705 cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
3706 offsetof(CPUTriCoreState, PSW_USB_AV),
3707 "PSW_AV");
3708 cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
3709 offsetof(CPUTriCoreState, PSW_USB_SAV),
3710 "PSW_SAV");
48e06fe0 3711}
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