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target-tricore: Make TRICORE_FEATURES implying others.
[mirror_qemu.git] / target-tricore / translate.c
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48e06fe0
BK		 1/*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21#include "cpu.h"
22#include "disas/disas.h"
23#include "tcg-op.h"
24#include "exec/cpu_ldst.h"
25
26#include "exec/helper-proto.h"
27#include "exec/helper-gen.h"
28
7c87d074 29#include "tricore-opcodes.h"
0707ec1b 30
0aaeb118
BK		 31/*
32 * TCG registers
33 */
34static TCGv cpu_PC;
35static TCGv cpu_PCXI;
36static TCGv cpu_PSW;
37static TCGv cpu_ICR;
38/* GPR registers */
39static TCGv cpu_gpr_a[16];
40static TCGv cpu_gpr_d[16];
41/* PSW Flag cache */
42static TCGv cpu_PSW_C;
43static TCGv cpu_PSW_V;
44static TCGv cpu_PSW_SV;
45static TCGv cpu_PSW_AV;
46static TCGv cpu_PSW_SAV;
47/* CPU env */
48static TCGv_ptr cpu_env;
49
50#include "exec/gen-icount.h"
48e06fe0
BK		 51
52static const char *regnames_a[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
56 };
57
58static const char *regnames_d[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
62 };
63
0aaeb118
BK		 64typedef struct DisasContext {
65 struct TranslationBlock *tb;
66 target_ulong pc, saved_pc, next_pc;
67 uint32_t opcode;
68 int singlestep_enabled;
69 /* Routine used to access memory */
70 int mem_idx;
71 uint32_t hflags, saved_hflags;
72 int bstate;
73} DisasContext;
74
75enum {
76
77 BS_NONE = 0,
78 BS_STOP = 1,
79 BS_BRANCH = 2,
80 BS_EXCP = 3,
81};
82
48e06fe0
BK		 83void tricore_cpu_dump_state(CPUState *cs, FILE *f,
84 fprintf_function cpu_fprintf, int flags)
85{
86 TriCoreCPU *cpu = TRICORE_CPU(cs);
87 CPUTriCoreState *env = &cpu->env;
88 int i;
89
90 cpu_fprintf(f, "PC=%08x\n", env->PC);
91 for (i = 0; i < 16; ++i) {
92 if ((i & 3) == 0) {
93 cpu_fprintf(f, "GPR A%02d:", i);
94 }
95 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
96 }
97 for (i = 0; i < 16; ++i) {
98 if ((i & 3) == 0) {
99 cpu_fprintf(f, "GPR D%02d:", i);
100 }
101 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
102 }
103
104}
105
0707ec1b
BK		 106/*
107 * Functions to generate micro-ops
108 */
109
9a31922b
BK		 110/* Makros for generating helpers */
111
112#define gen_helper_1arg(name, arg) do { \
113 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
114 gen_helper_##name(cpu_env, helper_tmp); \
115 tcg_temp_free_i32(helper_tmp); \
116 } while (0)
117
59543d4e 118#define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
f718b0bb
BK		 119#define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
120 ((offset & 0x0fffff) << 1))
59543d4e 121
d2798210
BK		 122/* Functions for load/save to/from memory */
123
124static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
125 int16_t con, TCGMemOp mop)
126{
127 TCGv temp = tcg_temp_new();
128 tcg_gen_addi_tl(temp, r2, con);
129 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
130 tcg_temp_free(temp);
131}
132
133static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
134 int16_t con, TCGMemOp mop)
135{
136 TCGv temp = tcg_temp_new();
137 tcg_gen_addi_tl(temp, r2, con);
138 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
139 tcg_temp_free(temp);
140}
141
59543d4e
BK		 142static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
143{
144 TCGv_i64 temp = tcg_temp_new_i64();
145
146 tcg_gen_concat_i32_i64(temp, rl, rh);
147 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
148
149 tcg_temp_free_i64(temp);
150}
151
3a16ecb0
BK		 152static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
153 DisasContext *ctx)
154{
155 TCGv temp = tcg_temp_new();
156 tcg_gen_addi_tl(temp, base, con);
157 gen_st_2regs_64(rh, rl, temp, ctx);
158 tcg_temp_free(temp);
159}
160
59543d4e
BK		 161static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
162{
163 TCGv_i64 temp = tcg_temp_new_i64();
164
165 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
166 /* write back to two 32 bit regs */
167 tcg_gen_extr_i64_i32(rl, rh, temp);
168
169 tcg_temp_free_i64(temp);
170}
171
3a16ecb0
BK		 172static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
173 DisasContext *ctx)
174{
175 TCGv temp = tcg_temp_new();
176 tcg_gen_addi_tl(temp, base, con);
177 gen_ld_2regs_64(rh, rl, temp, ctx);
178 tcg_temp_free(temp);
179}
180
181static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
182 TCGMemOp mop)
183{
184 TCGv temp = tcg_temp_new();
185 tcg_gen_addi_tl(temp, r2, off);
186 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
187 tcg_gen_mov_tl(r2, temp);
188 tcg_temp_free(temp);
189}
190
191static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
192 TCGMemOp mop)
193{
194 TCGv temp = tcg_temp_new();
195 tcg_gen_addi_tl(temp, r2, off);
196 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
197 tcg_gen_mov_tl(r2, temp);
198 tcg_temp_free(temp);
199}
200
59543d4e
BK		 201/* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
202static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
203{
204 TCGv temp = tcg_temp_new();
205 TCGv temp2 = tcg_temp_new();
206
207 /* temp = (M(EA, word) */
208 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
209 /* temp = temp & ~E[a][63:32]) */
210 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
211 /* temp2 = (E[a][31:0] & E[a][63:32]); */
212 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
213 /* temp = temp | temp2; */
214 tcg_gen_or_tl(temp, temp, temp2);
215 /* M(EA, word) = temp; */
216 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
217
218 tcg_temp_free(temp);
219 tcg_temp_free(temp2);
220}
221
222/* tmp = M(EA, word);
223 M(EA, word) = D[a];
224 D[a] = tmp[31:0];*/
225static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
226{
227 TCGv temp = tcg_temp_new();
228
229 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
230 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
231 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
232
233 tcg_temp_free(temp);
234}
235
0707ec1b
BK		 236/* Functions for arithmetic instructions */
237
238static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
239{
240 TCGv t0 = tcg_temp_new_i32();
241 TCGv result = tcg_temp_new_i32();
242 /* Addition and set V/SV bits */
243 tcg_gen_add_tl(result, r1, r2);
244 /* calc V bit */
245 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
246 tcg_gen_xor_tl(t0, r1, r2);
247 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
248 /* Calc SV bit */
249 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
250 /* Calc AV/SAV bits */
251 tcg_gen_add_tl(cpu_PSW_AV, result, result);
252 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
253 /* calc SAV */
254 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
255 /* write back result */
256 tcg_gen_mov_tl(ret, result);
257
258 tcg_temp_free(result);
259 tcg_temp_free(t0);
260}
261
262static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
263{
264 TCGv temp = tcg_const_i32(r2);
265 gen_add_d(ret, r1, temp);
266 tcg_temp_free(temp);
267}
0974257e
BK		 268/* calculate the carry bit too */
269static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
270{
271 TCGv t0 = tcg_temp_new_i32();
272 TCGv result = tcg_temp_new_i32();
273
274 tcg_gen_movi_tl(t0, 0);
275 /* Addition and set C/V/SV bits */
276 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
277 /* calc V bit */
278 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
279 tcg_gen_xor_tl(t0, r1, r2);
280 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
281 /* Calc SV bit */
282 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
283 /* Calc AV/SAV bits */
284 tcg_gen_add_tl(cpu_PSW_AV, result, result);
285 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
286 /* calc SAV */
287 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
288 /* write back result */
289 tcg_gen_mov_tl(ret, result);
290
291 tcg_temp_free(result);
292 tcg_temp_free(t0);
293}
294
295static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
296{
297 TCGv temp = tcg_const_i32(con);
298 gen_add_CC(ret, r1, temp);
299 tcg_temp_free(temp);
300}
301
302static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
303{
304 TCGv carry = tcg_temp_new_i32();
305 TCGv t0 = tcg_temp_new_i32();
306 TCGv result = tcg_temp_new_i32();
307
308 tcg_gen_movi_tl(t0, 0);
309 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
310 /* Addition, carry and set C/V/SV bits */
311 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
312 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
313 /* calc V bit */
314 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
315 tcg_gen_xor_tl(t0, r1, r2);
316 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
317 /* Calc SV bit */
318 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
319 /* Calc AV/SAV bits */
320 tcg_gen_add_tl(cpu_PSW_AV, result, result);
321 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
322 /* calc SAV */
323 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
324 /* write back result */
325 tcg_gen_mov_tl(ret, result);
326
327 tcg_temp_free(result);
328 tcg_temp_free(t0);
329 tcg_temp_free(carry);
330}
331
332static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
333{
334 TCGv temp = tcg_const_i32(con);
335 gen_addc_CC(ret, r1, temp);
336 tcg_temp_free(temp);
337}
0707ec1b
BK		 338
339static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
340 TCGv r4)
341{
342 TCGv temp = tcg_temp_new();
343 TCGv temp2 = tcg_temp_new();
344 TCGv result = tcg_temp_new();
345 TCGv mask = tcg_temp_new();
346 TCGv t0 = tcg_const_i32(0);
347
348 /* create mask for sticky bits */
349 tcg_gen_setcond_tl(cond, mask, r4, t0);
350 tcg_gen_shli_tl(mask, mask, 31);
351
352 tcg_gen_add_tl(result, r1, r2);
353 /* Calc PSW_V */
354 tcg_gen_xor_tl(temp, result, r1);
355 tcg_gen_xor_tl(temp2, r1, r2);
356 tcg_gen_andc_tl(temp, temp, temp2);
357 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
358 /* Set PSW_SV */
359 tcg_gen_and_tl(temp, temp, mask);
360 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
361 /* calc AV bit */
362 tcg_gen_add_tl(temp, result, result);
363 tcg_gen_xor_tl(temp, temp, result);
364 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
365 /* calc SAV bit */
366 tcg_gen_and_tl(temp, temp, mask);
367 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
368 /* write back result */
369 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
370
371 tcg_temp_free(t0);
372 tcg_temp_free(temp);
373 tcg_temp_free(temp2);
374 tcg_temp_free(result);
375 tcg_temp_free(mask);
376}
377
378static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
379 TCGv r3, TCGv r4)
380{
381 TCGv temp = tcg_const_i32(r2);
382 gen_cond_add(cond, r1, temp, r3, r4);
383 tcg_temp_free(temp);
384}
385
2692802a
BK		 386static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
387{
388 TCGv temp = tcg_temp_new_i32();
389 TCGv result = tcg_temp_new_i32();
390
391 tcg_gen_sub_tl(result, r1, r2);
392 /* calc V bit */
393 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
394 tcg_gen_xor_tl(temp, r1, r2);
395 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
396 /* calc SV bit */
397 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
398 /* Calc AV bit */
399 tcg_gen_add_tl(cpu_PSW_AV, result, result);
400 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
401 /* calc SAV bit */
402 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
403 /* write back result */
404 tcg_gen_mov_tl(ret, result);
405
406 tcg_temp_free(temp);
407 tcg_temp_free(result);
408}
409
0974257e
BK		 410static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
411{
412 TCGv temp = tcg_temp_new_i32();
413 TCGv result = tcg_temp_new_i32();
414
415 tcg_gen_sub_tl(result, r1, r2);
416 tcg_gen_sub_tl(temp, r2, r1);
417 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
418
419 /* calc V bit */
420 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
421 tcg_gen_xor_tl(temp, result, r2);
422 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
423 tcg_gen_xor_tl(temp, r1, r2);
424 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
425 /* calc SV bit */
426 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
427 /* Calc AV bit */
428 tcg_gen_add_tl(cpu_PSW_AV, result, result);
429 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
430 /* calc SAV bit */
431 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
432 /* write back result */
433 tcg_gen_mov_tl(ret, result);
434
435 tcg_temp_free(temp);
436 tcg_temp_free(result);
437}
438
439static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
440{
441 TCGv temp = tcg_const_i32(con);
442 gen_absdif(ret, r1, temp);
443 tcg_temp_free(temp);
444}
445
446static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
447{
448 TCGv temp = tcg_const_i32(con);
449 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
450 tcg_temp_free(temp);
451}
452
2692802a
BK		 453static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
454{
455 TCGv high = tcg_temp_new();
456 TCGv low = tcg_temp_new();
457
458 tcg_gen_muls2_tl(low, high, r1, r2);
459 tcg_gen_mov_tl(ret, low);
460 /* calc V bit */
461 tcg_gen_sari_tl(low, low, 31);
462 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
463 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
464 /* calc SV bit */
465 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
466 /* Calc AV bit */
467 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
468 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
469 /* calc SAV bit */
470 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
471
472 tcg_temp_free(high);
473 tcg_temp_free(low);
474}
475
0974257e
BK		 476static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
477{
478 TCGv temp = tcg_const_i32(con);
479 gen_mul_i32s(ret, r1, temp);
480 tcg_temp_free(temp);
481}
482
483static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
484{
485 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
486 /* clear V bit */
487 tcg_gen_movi_tl(cpu_PSW_V, 0);
488 /* calc SV bit */
489 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
490 /* Calc AV bit */
491 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
492 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
493 /* calc SAV bit */
494 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
495}
496
497static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
498 int32_t con)
499{
500 TCGv temp = tcg_const_i32(con);
501 gen_mul_i64s(ret_low, ret_high, r1, temp);
502 tcg_temp_free(temp);
503}
504
505static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
506{
507 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
508 /* clear V bit */
509 tcg_gen_movi_tl(cpu_PSW_V, 0);
510 /* calc SV bit */
511 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
512 /* Calc AV bit */
513 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
514 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
515 /* calc SAV bit */
516 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
517}
518
519static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
520 int32_t con)
521{
522 TCGv temp = tcg_const_i32(con);
523 gen_mul_i64u(ret_low, ret_high, r1, temp);
524 tcg_temp_free(temp);
525}
526
527static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
528{
529 TCGv temp = tcg_const_i32(con);
530 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
531 tcg_temp_free(temp);
532}
533
534static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
535{
536 TCGv temp = tcg_const_i32(con);
537 gen_helper_mul_suov(ret, cpu_env, r1, temp);
538 tcg_temp_free(temp);
539}
540
44ea3430
BK		 541static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
542{
543 TCGv sat_neg = tcg_const_i32(low);
544 TCGv temp = tcg_const_i32(up);
545
546 /* sat_neg = (arg < low ) ? low : arg; */
547 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
548
549 /* ret = (sat_neg > up ) ? up : sat_neg; */
550 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
551
552 tcg_temp_free(sat_neg);
553 tcg_temp_free(temp);
554}
555
556static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
557{
558 TCGv temp = tcg_const_i32(up);
559 /* sat_neg = (arg > up ) ? up : arg; */
560 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
561 tcg_temp_free(temp);
562}
563
0707ec1b
BK		 564static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
565{
566 if (shift_count == -32) {
567 tcg_gen_movi_tl(ret, 0);
568 } else if (shift_count >= 0) {
569 tcg_gen_shli_tl(ret, r1, shift_count);
570 } else {
571 tcg_gen_shri_tl(ret, r1, -shift_count);
572 }
573}
574
0974257e
BK		 575static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
576{
577 TCGv temp_low, temp_high;
578
579 if (shiftcount == -16) {
580 tcg_gen_movi_tl(ret, 0);
581 } else {
582 temp_high = tcg_temp_new();
583 temp_low = tcg_temp_new();
584
585 tcg_gen_andi_tl(temp_low, r1, 0xffff);
586 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
587 gen_shi(temp_low, temp_low, shiftcount);
588 gen_shi(ret, temp_high, shiftcount);
589 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
590
591 tcg_temp_free(temp_low);
592 tcg_temp_free(temp_high);
593 }
594}
595
0707ec1b
BK		 596static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
597{
598 uint32_t msk, msk_start;
599 TCGv temp = tcg_temp_new();
600 TCGv temp2 = tcg_temp_new();
601 TCGv t_0 = tcg_const_i32(0);
602
603 if (shift_count == 0) {
604 /* Clear PSW.C and PSW.V */
605 tcg_gen_movi_tl(cpu_PSW_C, 0);
606 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
607 tcg_gen_mov_tl(ret, r1);
608 } else if (shift_count == -32) {
609 /* set PSW.C */
610 tcg_gen_mov_tl(cpu_PSW_C, r1);
611 /* fill ret completly with sign bit */
612 tcg_gen_sari_tl(ret, r1, 31);
613 /* clear PSW.V */
614 tcg_gen_movi_tl(cpu_PSW_V, 0);
615 } else if (shift_count > 0) {
616 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
617 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
618
619 /* calc carry */
620 msk_start = 32 - shift_count;
621 msk = ((1 << shift_count) - 1) << msk_start;
622 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
623 /* calc v/sv bits */
624 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
625 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
626 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
627 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
628 /* calc sv */
629 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
630 /* do shift */
631 tcg_gen_shli_tl(ret, r1, shift_count);
632
633 tcg_temp_free(t_max);
634 tcg_temp_free(t_min);
635 } else {
636 /* clear PSW.V */
637 tcg_gen_movi_tl(cpu_PSW_V, 0);
638 /* calc carry */
639 msk = (1 << -shift_count) - 1;
640 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
641 /* do shift */
642 tcg_gen_sari_tl(ret, r1, -shift_count);
643 }
644 /* calc av overflow bit */
645 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
646 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
647 /* calc sav overflow bit */
648 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
649
650 tcg_temp_free(temp);
651 tcg_temp_free(temp2);
652 tcg_temp_free(t_0);
653}
654
0974257e
BK		 655static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
656{
657 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
658}
659
660static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
661{
662 TCGv temp = tcg_const_i32(con);
663 gen_shas(ret, r1, temp);
664 tcg_temp_free(temp);
665}
666
667static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
668{
669 TCGv low, high;
670
671 if (shift_count == 0) {
672 tcg_gen_mov_tl(ret, r1);
673 } else if (shift_count > 0) {
674 low = tcg_temp_new();
675 high = tcg_temp_new();
676
677 tcg_gen_andi_tl(high, r1, 0xffff0000);
678 tcg_gen_shli_tl(low, r1, shift_count);
679 tcg_gen_shli_tl(ret, high, shift_count);
680 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
681
682 tcg_temp_free(low);
683 tcg_temp_free(high);
684 } else {
685 low = tcg_temp_new();
686 high = tcg_temp_new();
687
688 tcg_gen_ext16s_tl(low, r1);
689 tcg_gen_sari_tl(low, low, -shift_count);
690 tcg_gen_sari_tl(ret, r1, -shift_count);
691 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
692
693 tcg_temp_free(low);
694 tcg_temp_free(high);
695 }
696
697}
698
699/* ret = {ret[30:0], (r1 cond r2)}; */
700static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
701{
702 TCGv temp = tcg_temp_new();
703 TCGv temp2 = tcg_temp_new();
704
705 tcg_gen_shli_tl(temp, ret, 1);
706 tcg_gen_setcond_tl(cond, temp2, r1, r2);
707 tcg_gen_or_tl(ret, temp, temp2);
708
709 tcg_temp_free(temp);
710 tcg_temp_free(temp2);
711}
712
713static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
714{
715 TCGv temp = tcg_const_i32(con);
716 gen_sh_cond(cond, ret, r1, temp);
717 tcg_temp_free(temp);
718}
719
2692802a
BK		 720static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
721{
722 gen_helper_add_ssov(ret, cpu_env, r1, r2);
723}
724
0974257e
BK		 725static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
726{
727 TCGv temp = tcg_const_i32(con);
728 gen_helper_add_ssov(ret, cpu_env, r1, temp);
729 tcg_temp_free(temp);
730}
731
732static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
733{
734 TCGv temp = tcg_const_i32(con);
735 gen_helper_add_suov(ret, cpu_env, r1, temp);
736 tcg_temp_free(temp);
737}
738
2692802a
BK		 739static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
740{
741 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
742}
743
0974257e
BK		 744static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
745{
746 gen_helper_sub_suov(ret, cpu_env, r1, r2);
747}
748
b74f2b5b
BK		 749static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
750 int pos1, int pos2,
751 void(*op1)(TCGv, TCGv, TCGv),
752 void(*op2)(TCGv, TCGv, TCGv))
753{
754 TCGv temp1, temp2;
755
756 temp1 = tcg_temp_new();
757 temp2 = tcg_temp_new();
758
759 tcg_gen_shri_tl(temp2, r2, pos2);
760 tcg_gen_shri_tl(temp1, r1, pos1);
761
762 (*op1)(temp1, temp1, temp2);
763 (*op2)(temp1 , ret, temp1);
764
765 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
766
767 tcg_temp_free(temp1);
768 tcg_temp_free(temp2);
769}
770
771/* ret = r1[pos1] op1 r2[pos2]; */
772static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
773 int pos1, int pos2,
774 void(*op1)(TCGv, TCGv, TCGv))
775{
776 TCGv temp1, temp2;
777
778 temp1 = tcg_temp_new();
779 temp2 = tcg_temp_new();
780
781 tcg_gen_shri_tl(temp2, r2, pos2);
782 tcg_gen_shri_tl(temp1, r1, pos1);
783
784 (*op1)(ret, temp1, temp2);
785
786 tcg_gen_andi_tl(ret, ret, 0x1);
787
788 tcg_temp_free(temp1);
789 tcg_temp_free(temp2);
790}
791
0974257e
BK		 792static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
793 void(*op)(TCGv, TCGv, TCGv))
794{
795 TCGv temp = tcg_temp_new();
796 TCGv temp2 = tcg_temp_new();
797 /* temp = (arg1 cond arg2 )*/
798 tcg_gen_setcond_tl(cond, temp, r1, r2);
799 /* temp2 = ret[0]*/
800 tcg_gen_andi_tl(temp2, ret, 0x1);
801 /* temp = temp insn temp2 */
802 (*op)(temp, temp, temp2);
803 /* ret = {ret[31:1], temp} */
804 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
805
806 tcg_temp_free(temp);
807 tcg_temp_free(temp2);
808}
809
810static inline void
811gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
812 void(*op)(TCGv, TCGv, TCGv))
813{
814 TCGv temp = tcg_const_i32(con);
815 gen_accumulating_cond(cond, ret, r1, temp, op);
816 tcg_temp_free(temp);
817}
818
819static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
820{
821 TCGv b0 = tcg_temp_new();
822 TCGv b1 = tcg_temp_new();
823 TCGv b2 = tcg_temp_new();
824 TCGv b3 = tcg_temp_new();
825
826 /* byte 0 */
827 tcg_gen_andi_tl(b0, r1, 0xff);
828 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
829
830 /* byte 1 */
831 tcg_gen_andi_tl(b1, r1, 0xff00);
832 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
833
834 /* byte 2 */
835 tcg_gen_andi_tl(b2, r1, 0xff0000);
836 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
837
838 /* byte 3 */
839 tcg_gen_andi_tl(b3, r1, 0xff000000);
840 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
841
842 /* combine them */
843 tcg_gen_or_tl(ret, b0, b1);
844 tcg_gen_or_tl(ret, ret, b2);
845 tcg_gen_or_tl(ret, ret, b3);
846
847 tcg_temp_free(b0);
848 tcg_temp_free(b1);
849 tcg_temp_free(b2);
850 tcg_temp_free(b3);
851}
852
853static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
854{
855 TCGv h0 = tcg_temp_new();
856 TCGv h1 = tcg_temp_new();
857
858 /* halfword 0 */
859 tcg_gen_andi_tl(h0, r1, 0xffff);
860 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
861
862 /* halfword 1 */
863 tcg_gen_andi_tl(h1, r1, 0xffff0000);
864 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
865
866 /* combine them */
867 tcg_gen_or_tl(ret, h0, h1);
868
869 tcg_temp_free(h0);
870 tcg_temp_free(h1);
871}
872
873
9a31922b
BK		 874/* helpers for generating program flow micro-ops */
875
876static inline void gen_save_pc(target_ulong pc)
877{
878 tcg_gen_movi_tl(cpu_PC, pc);
879}
880
881static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
882{
883 TranslationBlock *tb;
884 tb = ctx->tb;
885 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
886 likely(!ctx->singlestep_enabled)) {
887 tcg_gen_goto_tb(n);
888 gen_save_pc(dest);
889 tcg_gen_exit_tb((uintptr_t)tb + n);
890 } else {
891 gen_save_pc(dest);
892 if (ctx->singlestep_enabled) {
893 /* raise exception debug */
894 }
895 tcg_gen_exit_tb(0);
896 }
897}
898
899static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
900 TCGv r2, int16_t address)
901{
902 int jumpLabel;
903 jumpLabel = gen_new_label();
904 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
905
906 gen_goto_tb(ctx, 1, ctx->next_pc);
907
908 gen_set_label(jumpLabel);
909 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
910}
911
912static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
913 int r2, int16_t address)
914{
915 TCGv temp = tcg_const_i32(r2);
916 gen_branch_cond(ctx, cond, r1, temp, address);
917 tcg_temp_free(temp);
918}
919
a47b50db
BK		 920static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
921{
922 int l1;
923 l1 = gen_new_label();
924
925 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
926 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
927 gen_goto_tb(ctx, 1, ctx->pc + offset);
928 gen_set_label(l1);
929 gen_goto_tb(ctx, 0, ctx->next_pc);
930}
931
9a31922b
BK		 932static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
933 int r2 , int32_t constant , int32_t offset)
934{
a68e0d54 935 TCGv temp, temp2;
83c1bb18 936 int n;
70b02262 937
9a31922b
BK		 938 switch (opc) {
939/* SB-format jumps */
940 case OPC1_16_SB_J:
941 case OPC1_32_B_J:
942 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
943 break;
f718b0bb 944 case OPC1_32_B_CALL:
9a31922b
BK		 945 case OPC1_16_SB_CALL:
946 gen_helper_1arg(call, ctx->next_pc);
947 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
948 break;
949 case OPC1_16_SB_JZ:
950 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
951 break;
952 case OPC1_16_SB_JNZ:
953 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
954 break;
70b02262
BK		 955/* SBC-format jumps */
956 case OPC1_16_SBC_JEQ:
957 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
958 break;
959 case OPC1_16_SBC_JNE:
960 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
961 break;
962/* SBRN-format jumps */
963 case OPC1_16_SBRN_JZ_T:
964 temp = tcg_temp_new();
965 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
966 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
967 tcg_temp_free(temp);
968 break;
969 case OPC1_16_SBRN_JNZ_T:
970 temp = tcg_temp_new();
971 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
972 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
973 tcg_temp_free(temp);
974 break;
a47b50db
BK		 975/* SBR-format jumps */
976 case OPC1_16_SBR_JEQ:
977 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
978 offset);
979 break;
980 case OPC1_16_SBR_JNE:
981 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
982 offset);
983 break;
984 case OPC1_16_SBR_JNZ:
985 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
986 break;
987 case OPC1_16_SBR_JNZ_A:
988 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
989 break;
990 case OPC1_16_SBR_JGEZ:
991 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
992 break;
993 case OPC1_16_SBR_JGTZ:
994 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
995 break;
996 case OPC1_16_SBR_JLEZ:
997 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
998 break;
999 case OPC1_16_SBR_JLTZ:
1000 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
1001 break;
1002 case OPC1_16_SBR_JZ:
1003 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
1004 break;
1005 case OPC1_16_SBR_JZ_A:
1006 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
1007 break;
1008 case OPC1_16_SBR_LOOP:
1009 gen_loop(ctx, r1, offset * 2 - 32);
1010 break;
44ea3430
BK		 1011/* SR-format jumps */
1012 case OPC1_16_SR_JI:
1013 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
1014 tcg_gen_exit_tb(0);
1015 break;
1016 case OPC2_16_SR_RET:
1017 gen_helper_ret(cpu_env);
1018 tcg_gen_exit_tb(0);
1019 break;
f718b0bb
BK		 1020/* B-format */
1021 case OPC1_32_B_CALLA:
1022 gen_helper_1arg(call, ctx->next_pc);
1023 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
1024 break;
1025 case OPC1_32_B_JLA:
1026 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
1027 case OPC1_32_B_JA:
1028 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
1029 break;
1030 case OPC1_32_B_JL:
1031 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
1032 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
1033 break;
fc2ef4a3
BK		 1034/* BOL format */
1035 case OPCM_32_BRC_EQ_NEQ:
1036 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
1037 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
1038 } else {
1039 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
1040 }
1041 break;
1042 case OPCM_32_BRC_GE:
1043 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
1044 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
1045 } else {
1046 constant = MASK_OP_BRC_CONST4(ctx->opcode);
1047 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
1048 offset);
1049 }
1050 break;
1051 case OPCM_32_BRC_JLT:
1052 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
1053 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
1054 } else {
1055 constant = MASK_OP_BRC_CONST4(ctx->opcode);
1056 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
1057 offset);
1058 }
1059 break;
1060 case OPCM_32_BRC_JNE:
1061 temp = tcg_temp_new();
1062 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
1063 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
1064 /* subi is unconditional */
1065 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
1066 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
1067 } else {
1068 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
1069 /* addi is unconditional */
1070 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
1071 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
1072 }
1073 tcg_temp_free(temp);
1074 break;
83c1bb18
BK		 1075/* BRN format */
1076 case OPCM_32_BRN_JTT:
1077 n = MASK_OP_BRN_N(ctx->opcode);
1078
1079 temp = tcg_temp_new();
1080 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
1081
1082 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
1083 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
1084 } else {
1085 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
1086 }
1087 tcg_temp_free(temp);
1088 break;
a68e0d54
BK		 1089/* BRR Format */
1090 case OPCM_32_BRR_EQ_NEQ:
1091 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
1092 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
1093 offset);
1094 } else {
1095 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
1096 offset);
1097 }
1098 break;
1099 case OPCM_32_BRR_ADDR_EQ_NEQ:
1100 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
1101 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
1102 offset);
1103 } else {
1104 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
1105 offset);
1106 }
1107 break;
1108 case OPCM_32_BRR_GE:
1109 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
1110 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
1111 offset);
1112 } else {
1113 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
1114 offset);
1115 }
1116 break;
1117 case OPCM_32_BRR_JLT:
1118 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
1119 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
1120 offset);
1121 } else {
1122 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
1123 offset);
1124 }
1125 break;
1126 case OPCM_32_BRR_LOOP:
1127 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
1128 gen_loop(ctx, r1, offset * 2);
1129 } else {
1130 /* OPC2_32_BRR_LOOPU */
1131 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
1132 }
1133 break;
1134 case OPCM_32_BRR_JNE:
1135 temp = tcg_temp_new();
1136 temp2 = tcg_temp_new();
1137 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
1138 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
1139 /* also save r2, in case of r1 == r2, so r2 is not decremented */
1140 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
1141 /* subi is unconditional */
1142 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
1143 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
1144 } else {
1145 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
1146 /* also save r2, in case of r1 == r2, so r2 is not decremented */
1147 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
1148 /* addi is unconditional */
1149 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
1150 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
1151 }
1152 tcg_temp_free(temp);
1153 tcg_temp_free(temp2);
1154 break;
1155 case OPCM_32_BRR_JNZ:
1156 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
1157 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
1158 } else {
1159 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
1160 }
1161 break;
9a31922b 1162 default:
a47b50db 1163 printf("Branch Error at %x\n", ctx->pc);
9a31922b
BK		 1164 }
1165 ctx->bstate = BS_BRANCH;
1166}
1167
1168
0707ec1b
BK		 1169/*
1170 * Functions for decoding instructions
1171 */
1172
1173static void decode_src_opc(DisasContext *ctx, int op1)
1174{
1175 int r1;
1176 int32_t const4;
1177 TCGv temp, temp2;
1178
1179 r1 = MASK_OP_SRC_S1D(ctx->opcode);
1180 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
1181
1182 switch (op1) {
1183 case OPC1_16_SRC_ADD:
1184 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
1185 break;
1186 case OPC1_16_SRC_ADD_A15:
1187 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
1188 break;
1189 case OPC1_16_SRC_ADD_15A:
1190 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
1191 break;
1192 case OPC1_16_SRC_ADD_A:
1193 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
1194 break;
1195 case OPC1_16_SRC_CADD:
1196 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
1197 cpu_gpr_d[15]);
1198 break;
1199 case OPC1_16_SRC_CADDN:
1200 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
1201 cpu_gpr_d[15]);
1202 break;
1203 case OPC1_16_SRC_CMOV:
1204 temp = tcg_const_tl(0);
1205 temp2 = tcg_const_tl(const4);
1206 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
1207 temp2, cpu_gpr_d[r1]);
1208 tcg_temp_free(temp);
1209 tcg_temp_free(temp2);
1210 break;
1211 case OPC1_16_SRC_CMOVN:
1212 temp = tcg_const_tl(0);
1213 temp2 = tcg_const_tl(const4);
1214 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
1215 temp2, cpu_gpr_d[r1]);
1216 tcg_temp_free(temp);
1217 tcg_temp_free(temp2);
1218 break;
1219 case OPC1_16_SRC_EQ:
1220 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
1221 const4);
1222 break;
1223 case OPC1_16_SRC_LT:
1224 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
1225 const4);
1226 break;
1227 case OPC1_16_SRC_MOV:
1228 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
1229 break;
1230 case OPC1_16_SRC_MOV_A:
1231 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
1232 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
1233 break;
1234 case OPC1_16_SRC_SH:
1235 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
1236 break;
1237 case OPC1_16_SRC_SHA:
1238 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
1239 break;
1240 }
1241}
1242
2692802a
BK		 1243static void decode_srr_opc(DisasContext *ctx, int op1)
1244{
1245 int r1, r2;
1246 TCGv temp;
1247
1248 r1 = MASK_OP_SRR_S1D(ctx->opcode);
1249 r2 = MASK_OP_SRR_S2(ctx->opcode);
1250
1251 switch (op1) {
1252 case OPC1_16_SRR_ADD:
1253 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1254 break;
1255 case OPC1_16_SRR_ADD_A15:
1256 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
1257 break;
1258 case OPC1_16_SRR_ADD_15A:
1259 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1260 break;
1261 case OPC1_16_SRR_ADD_A:
1262 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
1263 break;
1264 case OPC1_16_SRR_ADDS:
1265 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1266 break;
1267 case OPC1_16_SRR_AND:
1268 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1269 break;
1270 case OPC1_16_SRR_CMOV:
1271 temp = tcg_const_tl(0);
1272 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
1273 cpu_gpr_d[r2], cpu_gpr_d[r1]);
1274 tcg_temp_free(temp);
1275 break;
1276 case OPC1_16_SRR_CMOVN:
1277 temp = tcg_const_tl(0);
1278 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
1279 cpu_gpr_d[r2], cpu_gpr_d[r1]);
1280 tcg_temp_free(temp);
1281 break;
1282 case OPC1_16_SRR_EQ:
1283 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
1284 cpu_gpr_d[r2]);
1285 break;
1286 case OPC1_16_SRR_LT:
1287 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
1288 cpu_gpr_d[r2]);
1289 break;
1290 case OPC1_16_SRR_MOV:
1291 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
1292 break;
1293 case OPC1_16_SRR_MOV_A:
1294 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
1295 break;
1296 case OPC1_16_SRR_MOV_AA:
1297 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
1298 break;
1299 case OPC1_16_SRR_MOV_D:
1300 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
1301 break;
1302 case OPC1_16_SRR_MUL:
1303 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1304 break;
1305 case OPC1_16_SRR_OR:
1306 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1307 break;
1308 case OPC1_16_SRR_SUB:
1309 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1310 break;
1311 case OPC1_16_SRR_SUB_A15B:
1312 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
1313 break;
1314 case OPC1_16_SRR_SUB_15AB:
1315 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1316 break;
1317 case OPC1_16_SRR_SUBS:
1318 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1319 break;
1320 case OPC1_16_SRR_XOR:
1321 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
1322 break;
1323 }
1324}
1325
46aa848f
BK		 1326static void decode_ssr_opc(DisasContext *ctx, int op1)
1327{
1328 int r1, r2;
1329
1330 r1 = MASK_OP_SSR_S1(ctx->opcode);
1331 r2 = MASK_OP_SSR_S2(ctx->opcode);
1332
1333 switch (op1) {
1334 case OPC1_16_SSR_ST_A:
1335 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
1336 break;
1337 case OPC1_16_SSR_ST_A_POSTINC:
1338 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
1339 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
1340 break;
1341 case OPC1_16_SSR_ST_B:
1342 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
1343 break;
1344 case OPC1_16_SSR_ST_B_POSTINC:
1345 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
1346 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
1347 break;
1348 case OPC1_16_SSR_ST_H:
1349 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
1350 break;
1351 case OPC1_16_SSR_ST_H_POSTINC:
1352 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
1353 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
1354 break;
1355 case OPC1_16_SSR_ST_W:
1356 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
1357 break;
1358 case OPC1_16_SSR_ST_W_POSTINC:
1359 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
1360 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
1361 break;
1362 }
1363}
1364
5de93515
BK		 1365static void decode_sc_opc(DisasContext *ctx, int op1)
1366{
1367 int32_t const16;
1368
1369 const16 = MASK_OP_SC_CONST8(ctx->opcode);
1370
1371 switch (op1) {
1372 case OPC1_16_SC_AND:
1373 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
1374 break;
1375 case OPC1_16_SC_BISR:
1376 gen_helper_1arg(bisr, const16 & 0xff);
1377 break;
1378 case OPC1_16_SC_LD_A:
1379 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
1380 break;
1381 case OPC1_16_SC_LD_W:
1382 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
1383 break;
1384 case OPC1_16_SC_MOV:
1385 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
1386 break;
1387 case OPC1_16_SC_OR:
1388 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
1389 break;
1390 case OPC1_16_SC_ST_A:
1391 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
1392 break;
1393 case OPC1_16_SC_ST_W:
1394 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
1395 break;
1396 case OPC1_16_SC_SUB_A:
1397 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
1398 break;
1399 }
1400}
5a7634a2
BK		 1401
1402static void decode_slr_opc(DisasContext *ctx, int op1)
1403{
1404 int r1, r2;
1405
1406 r1 = MASK_OP_SLR_D(ctx->opcode);
1407 r2 = MASK_OP_SLR_S2(ctx->opcode);
1408
1409 switch (op1) {
1410/* SLR-format */
1411 case OPC1_16_SLR_LD_A:
1412 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
1413 break;
1414 case OPC1_16_SLR_LD_A_POSTINC:
1415 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
1416 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
1417 break;
1418 case OPC1_16_SLR_LD_BU:
1419 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
1420 break;
1421 case OPC1_16_SLR_LD_BU_POSTINC:
1422 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
1423 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
1424 break;
1425 case OPC1_16_SLR_LD_H:
1426 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
1427 break;
1428 case OPC1_16_SLR_LD_H_POSTINC:
1429 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
1430 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
1431 break;
1432 case OPC1_16_SLR_LD_W:
1433 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
1434 break;
1435 case OPC1_16_SLR_LD_W_POSTINC:
1436 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
1437 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
1438 break;
1439 }
1440}
1441
1442static void decode_sro_opc(DisasContext *ctx, int op1)
1443{
1444 int r2;
1445 int32_t address;
1446
1447 r2 = MASK_OP_SRO_S2(ctx->opcode);
1448 address = MASK_OP_SRO_OFF4(ctx->opcode);
1449
1450/* SRO-format */
1451 switch (op1) {
1452 case OPC1_16_SRO_LD_A:
1453 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1454 break;
1455 case OPC1_16_SRO_LD_BU:
1456 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
1457 break;
1458 case OPC1_16_SRO_LD_H:
1459 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
1460 break;
1461 case OPC1_16_SRO_LD_W:
1462 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1463 break;
1464 case OPC1_16_SRO_ST_A:
1465 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1466 break;
1467 case OPC1_16_SRO_ST_B:
1468 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
1469 break;
1470 case OPC1_16_SRO_ST_H:
1471 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
1472 break;
1473 case OPC1_16_SRO_ST_W:
1474 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
1475 break;
1476 }
1477}
1478
44ea3430
BK		 1479static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
1480{
1481 uint32_t op2;
1482 op2 = MASK_OP_SR_OP2(ctx->opcode);
1483
1484 switch (op2) {
1485 case OPC2_16_SR_NOP:
1486 break;
1487 case OPC2_16_SR_RET:
1488 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
1489 break;
1490 case OPC2_16_SR_RFE:
1491 gen_helper_rfe(cpu_env);
1492 tcg_gen_exit_tb(0);
1493 ctx->bstate = BS_BRANCH;
1494 break;
1495 case OPC2_16_SR_DEBUG:
1496 /* raise EXCP_DEBUG */
1497 break;
1498 }
1499}
1500
1501static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
1502{
1503 uint32_t op2;
1504 uint32_t r1;
1505 TCGv temp;
1506
1507 r1 = MASK_OP_SR_S1D(ctx->opcode);
1508 op2 = MASK_OP_SR_OP2(ctx->opcode);
1509
1510 switch (op2) {
1511 case OPC2_16_SR_RSUB:
1512 /* overflow only if r1 = -0x80000000 */
1513 temp = tcg_const_i32(-0x80000000);
1514 /* calc V bit */
1515 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
1516 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1517 /* calc SV bit */
1518 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1519 /* sub */
1520 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
1521 /* calc av */
1522 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
1523 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
1524 /* calc sav */
1525 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1526 tcg_temp_free(temp);
1527 break;
1528 case OPC2_16_SR_SAT_B:
1529 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
1530 break;
1531 case OPC2_16_SR_SAT_BU:
1532 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
1533 break;
1534 case OPC2_16_SR_SAT_H:
1535 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
1536 break;
1537 case OPC2_16_SR_SAT_HU:
1538 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
1539 break;
1540 }
1541}
1542
0aaeb118
BK		 1543static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
1544{
0707ec1b 1545 int op1;
d2798210
BK		 1546 int r1, r2;
1547 int32_t const16;
9a31922b 1548 int32_t address;
d2798210 1549 TCGv temp;
0707ec1b
BK		 1550
1551 op1 = MASK_OP_MAJOR(ctx->opcode);
1552
d2798210
BK		 1553 /* handle ADDSC.A opcode only being 6 bit long */
1554 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
1555 op1 = OPC1_16_SRRS_ADDSC_A;
1556 }
1557
0707ec1b
BK		 1558 switch (op1) {
1559 case OPC1_16_SRC_ADD:
1560 case OPC1_16_SRC_ADD_A15:
1561 case OPC1_16_SRC_ADD_15A:
1562 case OPC1_16_SRC_ADD_A:
1563 case OPC1_16_SRC_CADD:
1564 case OPC1_16_SRC_CADDN:
1565 case OPC1_16_SRC_CMOV:
1566 case OPC1_16_SRC_CMOVN:
1567 case OPC1_16_SRC_EQ:
1568 case OPC1_16_SRC_LT:
1569 case OPC1_16_SRC_MOV:
1570 case OPC1_16_SRC_MOV_A:
1571 case OPC1_16_SRC_SH:
1572 case OPC1_16_SRC_SHA:
1573 decode_src_opc(ctx, op1);
1574 break;
2692802a
BK		 1575/* SRR-format */
1576 case OPC1_16_SRR_ADD:
1577 case OPC1_16_SRR_ADD_A15:
1578 case OPC1_16_SRR_ADD_15A:
1579 case OPC1_16_SRR_ADD_A:
1580 case OPC1_16_SRR_ADDS:
1581 case OPC1_16_SRR_AND:
1582 case OPC1_16_SRR_CMOV:
1583 case OPC1_16_SRR_CMOVN:
1584 case OPC1_16_SRR_EQ:
1585 case OPC1_16_SRR_LT:
1586 case OPC1_16_SRR_MOV:
1587 case OPC1_16_SRR_MOV_A:
1588 case OPC1_16_SRR_MOV_AA:
1589 case OPC1_16_SRR_MOV_D:
1590 case OPC1_16_SRR_MUL:
1591 case OPC1_16_SRR_OR:
1592 case OPC1_16_SRR_SUB:
1593 case OPC1_16_SRR_SUB_A15B:
1594 case OPC1_16_SRR_SUB_15AB:
1595 case OPC1_16_SRR_SUBS:
1596 case OPC1_16_SRR_XOR:
1597 decode_srr_opc(ctx, op1);
1598 break;
46aa848f
BK		 1599/* SSR-format */
1600 case OPC1_16_SSR_ST_A:
1601 case OPC1_16_SSR_ST_A_POSTINC:
1602 case OPC1_16_SSR_ST_B:
1603 case OPC1_16_SSR_ST_B_POSTINC:
1604 case OPC1_16_SSR_ST_H:
1605 case OPC1_16_SSR_ST_H_POSTINC:
1606 case OPC1_16_SSR_ST_W:
1607 case OPC1_16_SSR_ST_W_POSTINC:
1608 decode_ssr_opc(ctx, op1);
1609 break;
d2798210
BK		 1610/* SRRS-format */
1611 case OPC1_16_SRRS_ADDSC_A:
1612 r2 = MASK_OP_SRRS_S2(ctx->opcode);
1613 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
1614 const16 = MASK_OP_SRRS_N(ctx->opcode);
1615 temp = tcg_temp_new();
1616 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
1617 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
1618 tcg_temp_free(temp);
1619 break;
1620/* SLRO-format */
1621 case OPC1_16_SLRO_LD_A:
1622 r1 = MASK_OP_SLRO_D(ctx->opcode);
1623 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1624 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1625 break;
1626 case OPC1_16_SLRO_LD_BU:
1627 r1 = MASK_OP_SLRO_D(ctx->opcode);
1628 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1629 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
1630 break;
1631 case OPC1_16_SLRO_LD_H:
1632 r1 = MASK_OP_SLRO_D(ctx->opcode);
1633 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1634 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
1635 break;
1636 case OPC1_16_SLRO_LD_W:
1637 r1 = MASK_OP_SLRO_D(ctx->opcode);
1638 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1639 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1640 break;
9a31922b
BK		 1641/* SB-format */
1642 case OPC1_16_SB_CALL:
1643 case OPC1_16_SB_J:
1644 case OPC1_16_SB_JNZ:
1645 case OPC1_16_SB_JZ:
1646 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
1647 gen_compute_branch(ctx, op1, 0, 0, 0, address);
1648 break;
70b02262
BK		 1649/* SBC-format */
1650 case OPC1_16_SBC_JEQ:
1651 case OPC1_16_SBC_JNE:
1652 address = MASK_OP_SBC_DISP4(ctx->opcode);
1653 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
1654 gen_compute_branch(ctx, op1, 0, 0, const16, address);
1655 break;
1656/* SBRN-format */
1657 case OPC1_16_SBRN_JNZ_T:
1658 case OPC1_16_SBRN_JZ_T:
1659 address = MASK_OP_SBRN_DISP4(ctx->opcode);
1660 const16 = MASK_OP_SBRN_N(ctx->opcode);
1661 gen_compute_branch(ctx, op1, 0, 0, const16, address);
1662 break;
a47b50db
BK		 1663/* SBR-format */
1664 case OPC1_16_SBR_JEQ:
1665 case OPC1_16_SBR_JGEZ:
1666 case OPC1_16_SBR_JGTZ:
1667 case OPC1_16_SBR_JLEZ:
1668 case OPC1_16_SBR_JLTZ:
1669 case OPC1_16_SBR_JNE:
1670 case OPC1_16_SBR_JNZ:
1671 case OPC1_16_SBR_JNZ_A:
1672 case OPC1_16_SBR_JZ:
1673 case OPC1_16_SBR_JZ_A:
1674 case OPC1_16_SBR_LOOP:
1675 r1 = MASK_OP_SBR_S2(ctx->opcode);
1676 address = MASK_OP_SBR_DISP4(ctx->opcode);
1677 gen_compute_branch(ctx, op1, r1, 0, 0, address);
1678 break;
5de93515
BK		 1679/* SC-format */
1680 case OPC1_16_SC_AND:
1681 case OPC1_16_SC_BISR:
1682 case OPC1_16_SC_LD_A:
1683 case OPC1_16_SC_LD_W:
1684 case OPC1_16_SC_MOV:
1685 case OPC1_16_SC_OR:
1686 case OPC1_16_SC_ST_A:
1687 case OPC1_16_SC_ST_W:
1688 case OPC1_16_SC_SUB_A:
1689 decode_sc_opc(ctx, op1);
1690 break;
5a7634a2
BK		 1691/* SLR-format */
1692 case OPC1_16_SLR_LD_A:
1693 case OPC1_16_SLR_LD_A_POSTINC:
1694 case OPC1_16_SLR_LD_BU:
1695 case OPC1_16_SLR_LD_BU_POSTINC:
1696 case OPC1_16_SLR_LD_H:
1697 case OPC1_16_SLR_LD_H_POSTINC:
1698 case OPC1_16_SLR_LD_W:
1699 case OPC1_16_SLR_LD_W_POSTINC:
1700 decode_slr_opc(ctx, op1);
1701 break;
1702/* SRO-format */
1703 case OPC1_16_SRO_LD_A:
1704 case OPC1_16_SRO_LD_BU:
1705 case OPC1_16_SRO_LD_H:
1706 case OPC1_16_SRO_LD_W:
1707 case OPC1_16_SRO_ST_A:
1708 case OPC1_16_SRO_ST_B:
1709 case OPC1_16_SRO_ST_H:
1710 case OPC1_16_SRO_ST_W:
1711 decode_sro_opc(ctx, op1);
1712 break;
1713/* SSRO-format */
1714 case OPC1_16_SSRO_ST_A:
1715 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1716 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1717 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1718 break;
1719 case OPC1_16_SSRO_ST_B:
1720 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1721 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1722 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
1723 break;
1724 case OPC1_16_SSRO_ST_H:
1725 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1726 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1727 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
1728 break;
1729 case OPC1_16_SSRO_ST_W:
1730 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1731 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1732 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1733 break;
44ea3430
BK		 1734/* SR-format */
1735 case OPCM_16_SR_SYSTEM:
1736 decode_sr_system(env, ctx);
1737 break;
1738 case OPCM_16_SR_ACCU:
1739 decode_sr_accu(env, ctx);
1740 break;
1741 case OPC1_16_SR_JI:
1742 r1 = MASK_OP_SR_S1D(ctx->opcode);
1743 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
1744 break;
1745 case OPC1_16_SR_NOT:
1746 r1 = MASK_OP_SR_S1D(ctx->opcode);
1747 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
1748 break;
0707ec1b 1749 }
0aaeb118
BK		 1750}
1751
59543d4e
BK		 1752/*
1753 * 32 bit instructions
1754 */
1755
1756/* ABS-format */
1757static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
1758{
1759 int32_t op2;
1760 int32_t r1;
1761 uint32_t address;
1762 TCGv temp;
1763
1764 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1765 address = MASK_OP_ABS_OFF18(ctx->opcode);
1766 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1767
1768 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1769
1770 switch (op2) {
1771 case OPC2_32_ABS_LD_A:
1772 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
1773 break;
1774 case OPC2_32_ABS_LD_D:
1775 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
1776 break;
1777 case OPC2_32_ABS_LD_DA:
1778 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
1779 break;
1780 case OPC2_32_ABS_LD_W:
1781 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
1782 break;
1783 }
1784
1785 tcg_temp_free(temp);
1786}
1787
1788static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
1789{
1790 int32_t op2;
1791 int32_t r1;
1792 uint32_t address;
1793 TCGv temp;
1794
1795 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1796 address = MASK_OP_ABS_OFF18(ctx->opcode);
1797 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1798
1799 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1800
1801 switch (op2) {
1802 case OPC2_32_ABS_LD_B:
1803 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
1804 break;
1805 case OPC2_32_ABS_LD_BU:
1806 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
1807 break;
1808 case OPC2_32_ABS_LD_H:
1809 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
1810 break;
1811 case OPC2_32_ABS_LD_HU:
1812 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
1813 break;
1814 }
1815
1816 tcg_temp_free(temp);
1817}
1818
1819static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
1820{
1821 int32_t op2;
1822 int32_t r1;
1823 uint32_t address;
1824 TCGv temp;
1825
1826 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1827 address = MASK_OP_ABS_OFF18(ctx->opcode);
1828 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1829
1830 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1831
1832 switch (op2) {
1833 case OPC2_32_ABS_LDMST:
1834 gen_ldmst(ctx, r1, temp);
1835 break;
1836 case OPC2_32_ABS_SWAP_W:
1837 gen_swap(ctx, r1, temp);
1838 break;
1839 }
1840
1841 tcg_temp_free(temp);
1842}
1843
1844static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
1845{
1846 uint32_t op2;
1847 int32_t off18;
1848
1849 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
1850 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1851
1852 switch (op2) {
1853 case OPC2_32_ABS_LDLCX:
1854 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
1855 break;
1856 case OPC2_32_ABS_LDUCX:
1857 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
1858 break;
1859 case OPC2_32_ABS_STLCX:
1860 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
1861 break;
1862 case OPC2_32_ABS_STUCX:
1863 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
1864 break;
1865 }
1866}
1867
1868static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
1869{
1870 int32_t op2;
1871 int32_t r1;
1872 uint32_t address;
1873 TCGv temp;
1874
1875 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1876 address = MASK_OP_ABS_OFF18(ctx->opcode);
1877 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1878
1879 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1880
1881 switch (op2) {
1882 case OPC2_32_ABS_ST_A:
1883 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
1884 break;
1885 case OPC2_32_ABS_ST_D:
1886 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
1887 break;
1888 case OPC2_32_ABS_ST_DA:
1889 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
1890 break;
1891 case OPC2_32_ABS_ST_W:
1892 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
1893 break;
1894
1895 }
1896 tcg_temp_free(temp);
1897}
1898
1899static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
1900{
1901 int32_t op2;
1902 int32_t r1;
1903 uint32_t address;
1904 TCGv temp;
1905
1906 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1907 address = MASK_OP_ABS_OFF18(ctx->opcode);
1908 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1909
1910 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1911
1912 switch (op2) {
1913 case OPC2_32_ABS_ST_B:
1914 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
1915 break;
1916 case OPC2_32_ABS_ST_H:
1917 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
1918 break;
1919 }
1920 tcg_temp_free(temp);
1921}
1922
b74f2b5b
BK		 1923/* Bit-format */
1924
1925static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
1926{
1927 uint32_t op2;
1928 int r1, r2, r3;
1929 int pos1, pos2;
1930
1931 r1 = MASK_OP_BIT_S1(ctx->opcode);
1932 r2 = MASK_OP_BIT_S2(ctx->opcode);
1933 r3 = MASK_OP_BIT_D(ctx->opcode);
1934 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1935 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1936 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1937
1938
1939 switch (op2) {
1940 case OPC2_32_BIT_AND_AND_T:
1941 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1942 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
1943 break;
1944 case OPC2_32_BIT_AND_ANDN_T:
1945 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1946 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
1947 break;
1948 case OPC2_32_BIT_AND_NOR_T:
1949 if (TCG_TARGET_HAS_andc_i32) {
1950 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1951 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
1952 } else {
1953 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1954 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
1955 }
1956 break;
1957 case OPC2_32_BIT_AND_OR_T:
1958 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1959 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
1960 break;
1961 }
1962}
1963
1964static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
1965{
1966 uint32_t op2;
1967 int r1, r2, r3;
1968 int pos1, pos2;
1969 r1 = MASK_OP_BIT_S1(ctx->opcode);
1970 r2 = MASK_OP_BIT_S2(ctx->opcode);
1971 r3 = MASK_OP_BIT_D(ctx->opcode);
1972 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1973 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1974 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1975
1976 switch (op2) {
1977 case OPC2_32_BIT_AND_T:
1978 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1979 pos1, pos2, &tcg_gen_and_tl);
1980 break;
1981 case OPC2_32_BIT_ANDN_T:
1982 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1983 pos1, pos2, &tcg_gen_andc_tl);
1984 break;
1985 case OPC2_32_BIT_NOR_T:
1986 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1987 pos1, pos2, &tcg_gen_nor_tl);
1988 break;
1989 case OPC2_32_BIT_OR_T:
1990 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1991 pos1, pos2, &tcg_gen_or_tl);
1992 break;
1993 }
1994}
1995
1996static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
1997{
1998 uint32_t op2;
1999 int r1, r2, r3;
2000 int pos1, pos2;
2001 TCGv temp;
2002 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2003 r1 = MASK_OP_BIT_S1(ctx->opcode);
2004 r2 = MASK_OP_BIT_S2(ctx->opcode);
2005 r3 = MASK_OP_BIT_D(ctx->opcode);
2006 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2007 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2008
2009 temp = tcg_temp_new();
2010
2011 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
2012 if (op2 == OPC2_32_BIT_INSN_T) {
2013 tcg_gen_not_tl(temp, temp);
2014 }
2015 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
2016 tcg_temp_free(temp);
2017}
2018
2019static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
2020{
2021 uint32_t op2;
2022
2023 int r1, r2, r3;
2024 int pos1, pos2;
2025
2026 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2027 r1 = MASK_OP_BIT_S1(ctx->opcode);
2028 r2 = MASK_OP_BIT_S2(ctx->opcode);
2029 r3 = MASK_OP_BIT_D(ctx->opcode);
2030 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2031 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2032
2033 switch (op2) {
2034 case OPC2_32_BIT_NAND_T:
2035 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2036 pos1, pos2, &tcg_gen_nand_tl);
2037 break;
2038 case OPC2_32_BIT_ORN_T:
2039 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2040 pos1, pos2, &tcg_gen_orc_tl);
2041 break;
2042 case OPC2_32_BIT_XNOR_T:
2043 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2044 pos1, pos2, &tcg_gen_eqv_tl);
2045 break;
2046 case OPC2_32_BIT_XOR_T:
2047 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2048 pos1, pos2, &tcg_gen_xor_tl);
2049 break;
2050 }
2051}
2052
2053static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
2054{
2055 uint32_t op2;
2056
2057 int r1, r2, r3;
2058 int pos1, pos2;
2059
2060 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2061 r1 = MASK_OP_BIT_S1(ctx->opcode);
2062 r2 = MASK_OP_BIT_S2(ctx->opcode);
2063 r3 = MASK_OP_BIT_D(ctx->opcode);
2064 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2065 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2066
2067 switch (op2) {
2068 case OPC2_32_BIT_OR_AND_T:
2069 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2070 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
2071 break;
2072 case OPC2_32_BIT_OR_ANDN_T:
2073 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2074 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
2075 break;
2076 case OPC2_32_BIT_OR_NOR_T:
2077 if (TCG_TARGET_HAS_orc_i32) {
2078 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2079 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
2080 } else {
2081 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2082 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
2083 }
2084 break;
2085 case OPC2_32_BIT_OR_OR_T:
2086 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
2087 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
2088 break;
2089 }
2090}
2091
2092static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
2093{
2094 uint32_t op2;
2095 int r1, r2, r3;
2096 int pos1, pos2;
2097 TCGv temp;
2098
2099 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2100 r1 = MASK_OP_BIT_S1(ctx->opcode);
2101 r2 = MASK_OP_BIT_S2(ctx->opcode);
2102 r3 = MASK_OP_BIT_D(ctx->opcode);
2103 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2104 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2105
2106 temp = tcg_temp_new();
2107
2108 switch (op2) {
2109 case OPC2_32_BIT_SH_AND_T:
2110 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2111 pos1, pos2, &tcg_gen_and_tl);
2112 break;
2113 case OPC2_32_BIT_SH_ANDN_T:
2114 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2115 pos1, pos2, &tcg_gen_andc_tl);
2116 break;
2117 case OPC2_32_BIT_SH_NOR_T:
2118 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2119 pos1, pos2, &tcg_gen_nor_tl);
2120 break;
2121 case OPC2_32_BIT_SH_OR_T:
2122 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2123 pos1, pos2, &tcg_gen_or_tl);
2124 break;
2125 }
2126 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
2127 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
2128 tcg_temp_free(temp);
2129}
2130
2131static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
2132{
2133 uint32_t op2;
2134 int r1, r2, r3;
2135 int pos1, pos2;
2136 TCGv temp;
2137
2138 op2 = MASK_OP_BIT_OP2(ctx->opcode);
2139 r1 = MASK_OP_BIT_S1(ctx->opcode);
2140 r2 = MASK_OP_BIT_S2(ctx->opcode);
2141 r3 = MASK_OP_BIT_D(ctx->opcode);
2142 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
2143 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
2144
2145 temp = tcg_temp_new();
2146
2147 switch (op2) {
2148 case OPC2_32_BIT_SH_NAND_T:
2149 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
2150 pos1, pos2, &tcg_gen_nand_tl);
2151 break;
2152 case OPC2_32_BIT_SH_ORN_T:
2153 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2154 pos1, pos2, &tcg_gen_orc_tl);
2155 break;
2156 case OPC2_32_BIT_SH_XNOR_T:
2157 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2158 pos1, pos2, &tcg_gen_eqv_tl);
2159 break;
2160 case OPC2_32_BIT_SH_XOR_T:
2161 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
2162 pos1, pos2, &tcg_gen_xor_tl);
2163 break;
2164 }
2165 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
2166 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
2167 tcg_temp_free(temp);
2168}
2169
3a16ecb0
BK		 2170/* BO-format */
2171
2172
2173static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
2174 DisasContext *ctx)
2175{
2176 uint32_t op2;
2177 uint32_t off10;
2178 int32_t r1, r2;
2179 TCGv temp;
2180
2181 r1 = MASK_OP_BO_S1D(ctx->opcode);
2182 r2 = MASK_OP_BO_S2(ctx->opcode);
2183 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2184 op2 = MASK_OP_BO_OP2(ctx->opcode);
2185
2186 switch (op2) {
2187 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
2188 case OPC2_32_BO_CACHEA_W_SHORTOFF:
2189 case OPC2_32_BO_CACHEA_I_SHORTOFF:
2190 /* instruction to access the cache */
2191 break;
2192 case OPC2_32_BO_CACHEA_WI_POSTINC:
2193 case OPC2_32_BO_CACHEA_W_POSTINC:
2194 case OPC2_32_BO_CACHEA_I_POSTINC:
2195 /* instruction to access the cache, but we still need to handle
2196 the addressing mode */
2197 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
2198 break;
2199 case OPC2_32_BO_CACHEA_WI_PREINC:
2200 case OPC2_32_BO_CACHEA_W_PREINC:
2201 case OPC2_32_BO_CACHEA_I_PREINC:
2202 /* instruction to access the cache, but we still need to handle
2203 the addressing mode */
2204 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
2205 break;
2206 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
2207 case OPC2_32_BO_CACHEI_W_SHORTOFF:
2208 /* TODO: Raise illegal opcode trap,
47e04430 2209 if !tricore_feature(TRICORE_FEATURE_131) */
3a16ecb0
BK		 2210 break;
2211 case OPC2_32_BO_CACHEI_W_POSTINC:
2212 case OPC2_32_BO_CACHEI_WI_POSTINC:
47e04430 2213 if (tricore_feature(env, TRICORE_FEATURE_131)) {
3a16ecb0
BK		 2214 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
2215 } /* TODO: else raise illegal opcode trap */
2216 break;
2217 case OPC2_32_BO_CACHEI_W_PREINC:
2218 case OPC2_32_BO_CACHEI_WI_PREINC:
47e04430 2219 if (tricore_feature(env, TRICORE_FEATURE_131)) {
3a16ecb0
BK		 2220 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
2221 } /* TODO: else raise illegal opcode trap */
2222 break;
2223 case OPC2_32_BO_ST_A_SHORTOFF:
2224 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
2225 break;
2226 case OPC2_32_BO_ST_A_POSTINC:
2227 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
2228 MO_LESL);
2229 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2230 break;
2231 case OPC2_32_BO_ST_A_PREINC:
2232 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
2233 break;
2234 case OPC2_32_BO_ST_B_SHORTOFF:
2235 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
2236 break;
2237 case OPC2_32_BO_ST_B_POSTINC:
2238 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2239 MO_UB);
2240 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2241 break;
2242 case OPC2_32_BO_ST_B_PREINC:
2243 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
2244 break;
2245 case OPC2_32_BO_ST_D_SHORTOFF:
2246 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
2247 off10, ctx);
2248 break;
2249 case OPC2_32_BO_ST_D_POSTINC:
2250 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
2251 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2252 break;
2253 case OPC2_32_BO_ST_D_PREINC:
2254 temp = tcg_temp_new();
2255 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2256 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
2257 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2258 tcg_temp_free(temp);
2259 break;
2260 case OPC2_32_BO_ST_DA_SHORTOFF:
2261 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
2262 off10, ctx);
2263 break;
2264 case OPC2_32_BO_ST_DA_POSTINC:
2265 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
2266 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2267 break;
2268 case OPC2_32_BO_ST_DA_PREINC:
2269 temp = tcg_temp_new();
2270 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2271 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
2272 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2273 tcg_temp_free(temp);
2274 break;
2275 case OPC2_32_BO_ST_H_SHORTOFF:
2276 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2277 break;
2278 case OPC2_32_BO_ST_H_POSTINC:
2279 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2280 MO_LEUW);
2281 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2282 break;
2283 case OPC2_32_BO_ST_H_PREINC:
2284 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2285 break;
2286 case OPC2_32_BO_ST_Q_SHORTOFF:
2287 temp = tcg_temp_new();
2288 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2289 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
2290 tcg_temp_free(temp);
2291 break;
2292 case OPC2_32_BO_ST_Q_POSTINC:
2293 temp = tcg_temp_new();
2294 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2295 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
2296 MO_LEUW);
2297 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2298 tcg_temp_free(temp);
2299 break;
2300 case OPC2_32_BO_ST_Q_PREINC:
2301 temp = tcg_temp_new();
2302 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2303 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
2304 tcg_temp_free(temp);
2305 break;
2306 case OPC2_32_BO_ST_W_SHORTOFF:
2307 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2308 break;
2309 case OPC2_32_BO_ST_W_POSTINC:
2310 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2311 MO_LEUL);
2312 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2313 break;
2314 case OPC2_32_BO_ST_W_PREINC:
2315 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2316 break;
2317 }
2318}
2319
2320static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
2321 DisasContext *ctx)
2322{
2323 uint32_t op2;
2324 uint32_t off10;
2325 int32_t r1, r2;
2326 TCGv temp, temp2, temp3;
2327
2328 r1 = MASK_OP_BO_S1D(ctx->opcode);
2329 r2 = MASK_OP_BO_S2(ctx->opcode);
2330 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2331 op2 = MASK_OP_BO_OP2(ctx->opcode);
2332
2333 temp = tcg_temp_new();
2334 temp2 = tcg_temp_new();
2335 temp3 = tcg_const_i32(off10);
2336
2337 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
2338 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2339
2340 switch (op2) {
2341 case OPC2_32_BO_CACHEA_WI_BR:
2342 case OPC2_32_BO_CACHEA_W_BR:
2343 case OPC2_32_BO_CACHEA_I_BR:
2344 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2345 break;
2346 case OPC2_32_BO_CACHEA_WI_CIRC:
2347 case OPC2_32_BO_CACHEA_W_CIRC:
2348 case OPC2_32_BO_CACHEA_I_CIRC:
2349 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2350 break;
2351 case OPC2_32_BO_ST_A_BR:
2352 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2353 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2354 break;
2355 case OPC2_32_BO_ST_A_CIRC:
2356 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2357 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2358 break;
2359 case OPC2_32_BO_ST_B_BR:
2360 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2361 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2362 break;
2363 case OPC2_32_BO_ST_B_CIRC:
2364 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2365 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2366 break;
2367 case OPC2_32_BO_ST_D_BR:
2368 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
2369 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2370 break;
2371 case OPC2_32_BO_ST_D_CIRC:
2372 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2373 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2374 tcg_gen_addi_tl(temp, temp, 4);
2375 tcg_gen_rem_tl(temp, temp, temp2);
2376 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2377 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2378 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2379 break;
2380 case OPC2_32_BO_ST_DA_BR:
2381 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
2382 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2383 break;
2384 case OPC2_32_BO_ST_DA_CIRC:
2385 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2386 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2387 tcg_gen_addi_tl(temp, temp, 4);
2388 tcg_gen_rem_tl(temp, temp, temp2);
2389 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2390 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2391 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2392 break;
2393 case OPC2_32_BO_ST_H_BR:
2394 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2395 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2396 break;
2397 case OPC2_32_BO_ST_H_CIRC:
2398 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2399 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2400 break;
2401 case OPC2_32_BO_ST_Q_BR:
2402 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2403 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
2404 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2405 break;
2406 case OPC2_32_BO_ST_Q_CIRC:
2407 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
2408 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
2409 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2410 break;
2411 case OPC2_32_BO_ST_W_BR:
2412 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2413 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2414 break;
2415 case OPC2_32_BO_ST_W_CIRC:
2416 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2417 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2418 break;
2419 }
2420 tcg_temp_free(temp);
2421 tcg_temp_free(temp2);
2422 tcg_temp_free(temp3);
2423}
2424
2425static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
2426 DisasContext *ctx)
2427{
2428 uint32_t op2;
2429 uint32_t off10;
2430 int32_t r1, r2;
2431 TCGv temp;
2432
2433 r1 = MASK_OP_BO_S1D(ctx->opcode);
2434 r2 = MASK_OP_BO_S2(ctx->opcode);
2435 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2436 op2 = MASK_OP_BO_OP2(ctx->opcode);
2437
2438 switch (op2) {
2439 case OPC2_32_BO_LD_A_SHORTOFF:
2440 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2441 break;
2442 case OPC2_32_BO_LD_A_POSTINC:
2443 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
2444 MO_LEUL);
2445 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2446 break;
2447 case OPC2_32_BO_LD_A_PREINC:
2448 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2449 break;
2450 case OPC2_32_BO_LD_B_SHORTOFF:
2451 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
2452 break;
2453 case OPC2_32_BO_LD_B_POSTINC:
2454 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2455 MO_SB);
2456 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2457 break;
2458 case OPC2_32_BO_LD_B_PREINC:
2459 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
2460 break;
2461 case OPC2_32_BO_LD_BU_SHORTOFF:
2462 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
2463 break;
2464 case OPC2_32_BO_LD_BU_POSTINC:
2465 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2466 MO_UB);
2467 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2468 break;
2469 case OPC2_32_BO_LD_BU_PREINC:
2470 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
2471 break;
2472 case OPC2_32_BO_LD_D_SHORTOFF:
2473 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
2474 off10, ctx);
2475 break;
2476 case OPC2_32_BO_LD_D_POSTINC:
2477 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
2478 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2479 break;
2480 case OPC2_32_BO_LD_D_PREINC:
2481 temp = tcg_temp_new();
2482 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2483 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
2484 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2485 tcg_temp_free(temp);
2486 break;
2487 case OPC2_32_BO_LD_DA_SHORTOFF:
2488 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
2489 off10, ctx);
2490 break;
2491 case OPC2_32_BO_LD_DA_POSTINC:
2492 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
2493 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2494 break;
2495 case OPC2_32_BO_LD_DA_PREINC:
2496 temp = tcg_temp_new();
2497 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2498 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
2499 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
2500 tcg_temp_free(temp);
2501 break;
2502 case OPC2_32_BO_LD_H_SHORTOFF:
2503 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
2504 break;
2505 case OPC2_32_BO_LD_H_POSTINC:
2506 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2507 MO_LESW);
2508 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2509 break;
2510 case OPC2_32_BO_LD_H_PREINC:
2511 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
2512 break;
2513 case OPC2_32_BO_LD_HU_SHORTOFF:
2514 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2515 break;
2516 case OPC2_32_BO_LD_HU_POSTINC:
2517 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2518 MO_LEUW);
2519 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2520 break;
2521 case OPC2_32_BO_LD_HU_PREINC:
2522 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2523 break;
2524 case OPC2_32_BO_LD_Q_SHORTOFF:
2525 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2526 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2527 break;
2528 case OPC2_32_BO_LD_Q_POSTINC:
2529 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2530 MO_LEUW);
2531 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2532 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2533 break;
2534 case OPC2_32_BO_LD_Q_PREINC:
2535 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
2536 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2537 break;
2538 case OPC2_32_BO_LD_W_SHORTOFF:
2539 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2540 break;
2541 case OPC2_32_BO_LD_W_POSTINC:
2542 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
2543 MO_LEUL);
2544 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2545 break;
2546 case OPC2_32_BO_LD_W_PREINC:
2547 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
2548 break;
2549 }
2550}
2551
2552static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
2553 DisasContext *ctx)
2554{
2555 uint32_t op2;
2556 uint32_t off10;
2557 int r1, r2;
2558
2559 TCGv temp, temp2, temp3;
2560
2561 r1 = MASK_OP_BO_S1D(ctx->opcode);
2562 r2 = MASK_OP_BO_S2(ctx->opcode);
2563 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2564 op2 = MASK_OP_BO_OP2(ctx->opcode);
2565
2566 temp = tcg_temp_new();
2567 temp2 = tcg_temp_new();
2568 temp3 = tcg_const_i32(off10);
2569
2570 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
2571 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2572
2573
2574 switch (op2) {
2575 case OPC2_32_BO_LD_A_BR:
2576 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2577 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2578 break;
2579 case OPC2_32_BO_LD_A_CIRC:
2580 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2581 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2582 break;
2583 case OPC2_32_BO_LD_B_BR:
2584 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
2585 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2586 break;
2587 case OPC2_32_BO_LD_B_CIRC:
2588 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
2589 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2590 break;
2591 case OPC2_32_BO_LD_BU_BR:
2592 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2593 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2594 break;
2595 case OPC2_32_BO_LD_BU_CIRC:
2596 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
2597 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2598 break;
2599 case OPC2_32_BO_LD_D_BR:
2600 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
2601 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2602 break;
2603 case OPC2_32_BO_LD_D_CIRC:
2604 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2605 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2606 tcg_gen_addi_tl(temp, temp, 4);
2607 tcg_gen_rem_tl(temp, temp, temp2);
2608 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2609 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2610 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2611 break;
2612 case OPC2_32_BO_LD_DA_BR:
2613 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
2614 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2615 break;
2616 case OPC2_32_BO_LD_DA_CIRC:
2617 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
2618 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
2619 tcg_gen_addi_tl(temp, temp, 4);
2620 tcg_gen_rem_tl(temp, temp, temp2);
2621 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2622 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
2623 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2624 break;
2625 case OPC2_32_BO_LD_H_BR:
2626 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
2627 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2628 break;
2629 case OPC2_32_BO_LD_H_CIRC:
2630 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
2631 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2632 break;
2633 case OPC2_32_BO_LD_HU_BR:
2634 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2635 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2636 break;
2637 case OPC2_32_BO_LD_HU_CIRC:
2638 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2639 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2640 break;
2641 case OPC2_32_BO_LD_Q_BR:
2642 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2643 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2644 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2645 break;
2646 case OPC2_32_BO_LD_Q_CIRC:
2647 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
2648 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
2649 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2650 break;
2651 case OPC2_32_BO_LD_W_BR:
2652 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2653 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2654 break;
2655 case OPC2_32_BO_LD_W_CIRC:
2656 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
2657 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2658 break;
2659 }
2660 tcg_temp_free(temp);
2661 tcg_temp_free(temp2);
2662 tcg_temp_free(temp3);
2663}
2664
2665static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
2666 DisasContext *ctx)
2667{
2668 uint32_t op2;
2669 uint32_t off10;
2670 int r1, r2;
2671
2672 TCGv temp, temp2;
2673
2674 r1 = MASK_OP_BO_S1D(ctx->opcode);
2675 r2 = MASK_OP_BO_S2(ctx->opcode);
2676 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2677 op2 = MASK_OP_BO_OP2(ctx->opcode);
2678
2679
2680 temp = tcg_temp_new();
2681 temp2 = tcg_temp_new();
2682
2683 switch (op2) {
2684 case OPC2_32_BO_LDLCX_SHORTOFF:
2685 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2686 gen_helper_ldlcx(cpu_env, temp);
2687 break;
2688 case OPC2_32_BO_LDMST_SHORTOFF:
2689 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2690 gen_ldmst(ctx, r1, temp);
2691 break;
2692 case OPC2_32_BO_LDMST_POSTINC:
2693 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
2694 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2695 break;
2696 case OPC2_32_BO_LDMST_PREINC:
2697 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2698 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
2699 break;
2700 case OPC2_32_BO_LDUCX_SHORTOFF:
2701 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2702 gen_helper_lducx(cpu_env, temp);
2703 break;
2704 case OPC2_32_BO_LEA_SHORTOFF:
2705 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
2706 break;
2707 case OPC2_32_BO_STLCX_SHORTOFF:
2708 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2709 gen_helper_stlcx(cpu_env, temp);
2710 break;
2711 case OPC2_32_BO_STUCX_SHORTOFF:
2712 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2713 gen_helper_stucx(cpu_env, temp);
2714 break;
2715 case OPC2_32_BO_SWAP_W_SHORTOFF:
2716 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
2717 gen_swap(ctx, r1, temp);
2718 break;
2719 case OPC2_32_BO_SWAP_W_POSTINC:
2720 gen_swap(ctx, r1, cpu_gpr_a[r2]);
2721 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2722 break;
2723 case OPC2_32_BO_SWAP_W_PREINC:
2724 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
2725 gen_swap(ctx, r1, cpu_gpr_a[r2]);
2726 break;
2727 }
2728 tcg_temp_free(temp);
2729 tcg_temp_free(temp2);
2730}
2731
2732static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
2733 DisasContext *ctx)
2734{
2735 uint32_t op2;
2736 uint32_t off10;
2737 int r1, r2;
2738
2739 TCGv temp, temp2, temp3;
2740
2741 r1 = MASK_OP_BO_S1D(ctx->opcode);
2742 r2 = MASK_OP_BO_S2(ctx->opcode);
2743 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
2744 op2 = MASK_OP_BO_OP2(ctx->opcode);
2745
2746 temp = tcg_temp_new();
2747 temp2 = tcg_temp_new();
2748 temp3 = tcg_const_i32(off10);
2749
2750 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
2751 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
2752
2753 switch (op2) {
2754 case OPC2_32_BO_LDMST_BR:
2755 gen_ldmst(ctx, r1, temp2);
2756 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2757 break;
2758 case OPC2_32_BO_LDMST_CIRC:
2759 gen_ldmst(ctx, r1, temp2);
2760 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2761 break;
2762 case OPC2_32_BO_SWAP_W_BR:
2763 gen_swap(ctx, r1, temp2);
2764 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
2765 break;
2766 case OPC2_32_BO_SWAP_W_CIRC:
2767 gen_swap(ctx, r1, temp2);
2768 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
2769 break;
2770 }
2771 tcg_temp_free(temp);
2772 tcg_temp_free(temp2);
2773 tcg_temp_free(temp3);
2774}
2775
3fb763cb
BK		 2776static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
2777{
2778 int r1, r2;
2779 int32_t address;
2780 TCGv temp;
2781
2782 r1 = MASK_OP_BOL_S1D(ctx->opcode);
2783 r2 = MASK_OP_BOL_S2(ctx->opcode);
2784 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
2785
2786 switch (op1) {
2787 case OPC1_32_BOL_LD_A_LONGOFF:
2788 temp = tcg_temp_new();
2789 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
2790 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
2791 tcg_temp_free(temp);
2792 break;
2793 case OPC1_32_BOL_LD_W_LONFOFF:
2794 temp = tcg_temp_new();
2795 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
2796 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
2797 tcg_temp_free(temp);
2798 break;
2799 case OPC1_32_BOL_LEA_LONGOFF:
2800 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
2801 break;
2802 case OPC1_32_BOL_ST_A_LONGOFF:
2803 if (tricore_feature(env, TRICORE_FEATURE_16)) {
2804 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
2805 } else {
2806 /* raise illegal opcode trap */
2807 }
2808 break;
2809 case OPC1_32_BOL_ST_W_LONGOFF:
2810 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
2811 break;
2812 }
2813
2814}
2815
0974257e
BK		 2816/* RC format */
2817static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
2818{
2819 uint32_t op2;
2820 int r1, r2;
2821 int32_t const9;
2822 TCGv temp;
2823
2824 r2 = MASK_OP_RC_D(ctx->opcode);
2825 r1 = MASK_OP_RC_S1(ctx->opcode);
2826 const9 = MASK_OP_RC_CONST9(ctx->opcode);
2827 op2 = MASK_OP_RC_OP2(ctx->opcode);
2828
2829 temp = tcg_temp_new();
2830
2831 switch (op2) {
2832 case OPC2_32_RC_AND:
2833 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2834 break;
2835 case OPC2_32_RC_ANDN:
2836 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
2837 break;
2838 case OPC2_32_RC_NAND:
2839 tcg_gen_movi_tl(temp, const9);
2840 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
2841 break;
2842 case OPC2_32_RC_NOR:
2843 tcg_gen_movi_tl(temp, const9);
2844 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
2845 break;
2846 case OPC2_32_RC_OR:
2847 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2848 break;
2849 case OPC2_32_RC_ORN:
2850 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
2851 break;
2852 case OPC2_32_RC_SH:
2853 const9 = sextract32(const9, 0, 6);
2854 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2855 break;
2856 case OPC2_32_RC_SH_H:
2857 const9 = sextract32(const9, 0, 5);
2858 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2859 break;
2860 case OPC2_32_RC_SHA:
2861 const9 = sextract32(const9, 0, 6);
2862 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2863 break;
2864 case OPC2_32_RC_SHA_H:
2865 const9 = sextract32(const9, 0, 5);
2866 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2867 break;
2868 case OPC2_32_RC_SHAS:
2869 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2870 break;
2871 case OPC2_32_RC_XNOR:
2872 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2873 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
2874 break;
2875 case OPC2_32_RC_XOR:
2876 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2877 break;
2878 }
2879 tcg_temp_free(temp);
2880}
2881
2882static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
2883{
2884 uint32_t op2;
2885 int r1, r2;
2886 int16_t const9;
2887
2888 TCGv temp;
2889
2890 r2 = MASK_OP_RC_D(ctx->opcode);
2891 r1 = MASK_OP_RC_S1(ctx->opcode);
2892 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
2893
2894 op2 = MASK_OP_RC_OP2(ctx->opcode);
2895
2896 temp = tcg_temp_new();
2897
2898 switch (op2) {
2899 case OPC2_32_RC_ABSDIF:
2900 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2901 break;
2902 case OPC2_32_RC_ABSDIFS:
2903 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2904 break;
2905 case OPC2_32_RC_ADD:
2906 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2907 break;
2908 case OPC2_32_RC_ADDC:
2909 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2910 break;
2911 case OPC2_32_RC_ADDS:
2912 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2913 break;
2914 case OPC2_32_RC_ADDS_U:
2915 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2916 break;
2917 case OPC2_32_RC_ADDX:
2918 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2919 break;
2920 case OPC2_32_RC_AND_EQ:
2921 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
2922 const9, &tcg_gen_and_tl);
2923 break;
2924 case OPC2_32_RC_AND_GE:
2925 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
2926 const9, &tcg_gen_and_tl);
2927 break;
2928 case OPC2_32_RC_AND_GE_U:
2929 const9 = MASK_OP_RC_CONST9(ctx->opcode);
2930 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
2931 const9, &tcg_gen_and_tl);
2932 break;
2933 case OPC2_32_RC_AND_LT:
2934 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
2935 const9, &tcg_gen_and_tl);
2936 break;
2937 case OPC2_32_RC_AND_LT_U:
2938 const9 = MASK_OP_RC_CONST9(ctx->opcode);
2939 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
2940 const9, &tcg_gen_and_tl);
2941 break;
2942 case OPC2_32_RC_AND_NE:
2943 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
2944 const9, &tcg_gen_and_tl);
2945 break;
2946 case OPC2_32_RC_EQ:
2947 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2948 break;
2949 case OPC2_32_RC_EQANY_B:
2950 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2951 break;
2952 case OPC2_32_RC_EQANY_H:
2953 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2954 break;
2955 case OPC2_32_RC_GE:
2956 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2957 break;
2958 case OPC2_32_RC_GE_U:
2959 const9 = MASK_OP_RC_CONST9(ctx->opcode);
2960 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2961 break;
2962 case OPC2_32_RC_LT:
2963 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2964 break;
2965 case OPC2_32_RC_LT_U:
2966 const9 = MASK_OP_RC_CONST9(ctx->opcode);
2967 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2968 break;
2969 case OPC2_32_RC_MAX:
2970 tcg_gen_movi_tl(temp, const9);
2971 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
2972 cpu_gpr_d[r1], temp);
2973 break;
2974 case OPC2_32_RC_MAX_U:
2975 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
2976 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
2977 cpu_gpr_d[r1], temp);
2978 break;
2979 case OPC2_32_RC_MIN:
2980 tcg_gen_movi_tl(temp, const9);
2981 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
2982 cpu_gpr_d[r1], temp);
2983 break;
2984 case OPC2_32_RC_MIN_U:
2985 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
2986 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
2987 cpu_gpr_d[r1], temp);
2988 break;
2989 case OPC2_32_RC_NE:
2990 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
2991 break;
2992 case OPC2_32_RC_OR_EQ:
2993 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
2994 const9, &tcg_gen_or_tl);
2995 break;
2996 case OPC2_32_RC_OR_GE:
2997 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
2998 const9, &tcg_gen_or_tl);
2999 break;
3000 case OPC2_32_RC_OR_GE_U:
3001 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3002 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3003 const9, &tcg_gen_or_tl);
3004 break;
3005 case OPC2_32_RC_OR_LT:
3006 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
3007 const9, &tcg_gen_or_tl);
3008 break;
3009 case OPC2_32_RC_OR_LT_U:
3010 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3011 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3012 const9, &tcg_gen_or_tl);
3013 break;
3014 case OPC2_32_RC_OR_NE:
3015 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
3016 const9, &tcg_gen_or_tl);
3017 break;
3018 case OPC2_32_RC_RSUB:
3019 tcg_gen_movi_tl(temp, const9);
3020 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
3021 break;
3022 case OPC2_32_RC_RSUBS:
3023 tcg_gen_movi_tl(temp, const9);
3024 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
3025 break;
3026 case OPC2_32_RC_RSUBS_U:
3027 tcg_gen_movi_tl(temp, const9);
3028 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
3029 break;
3030 case OPC2_32_RC_SH_EQ:
3031 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3032 break;
3033 case OPC2_32_RC_SH_GE:
3034 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3035 break;
3036 case OPC2_32_RC_SH_GE_U:
3037 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3038 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3039 break;
3040 case OPC2_32_RC_SH_LT:
3041 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3042 break;
3043 case OPC2_32_RC_SH_LT_U:
3044 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3045 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3046 break;
3047 case OPC2_32_RC_SH_NE:
3048 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3049 break;
3050 case OPC2_32_RC_XOR_EQ:
3051 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
3052 const9, &tcg_gen_xor_tl);
3053 break;
3054 case OPC2_32_RC_XOR_GE:
3055 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
3056 const9, &tcg_gen_xor_tl);
3057 break;
3058 case OPC2_32_RC_XOR_GE_U:
3059 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3060 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3061 const9, &tcg_gen_xor_tl);
3062 break;
3063 case OPC2_32_RC_XOR_LT:
3064 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
3065 const9, &tcg_gen_xor_tl);
3066 break;
3067 case OPC2_32_RC_XOR_LT_U:
3068 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3069 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
3070 const9, &tcg_gen_xor_tl);
3071 break;
3072 case OPC2_32_RC_XOR_NE:
3073 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
3074 const9, &tcg_gen_xor_tl);
3075 break;
3076 }
3077 tcg_temp_free(temp);
3078}
3079
3080static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
3081{
3082 uint32_t op2;
3083 uint32_t const9;
3084
3085 op2 = MASK_OP_RC_OP2(ctx->opcode);
3086 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3087
3088 switch (op2) {
3089 case OPC2_32_RC_BISR:
3090 gen_helper_1arg(bisr, const9);
3091 break;
3092 case OPC2_32_RC_SYSCALL:
3093 /* TODO: Add exception generation */
3094 break;
3095 }
3096}
3097
3098static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
3099{
3100 uint32_t op2;
3101 int r1, r2;
3102 int16_t const9;
3103
3104 r2 = MASK_OP_RC_D(ctx->opcode);
3105 r1 = MASK_OP_RC_S1(ctx->opcode);
3106 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
3107
3108 op2 = MASK_OP_RC_OP2(ctx->opcode);
3109
3110 switch (op2) {
3111 case OPC2_32_RC_MUL_32:
3112 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3113 break;
3114 case OPC2_32_RC_MUL_64:
3115 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
3116 break;
3117 case OPC2_32_RC_MULS_32:
3118 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3119 break;
3120 case OPC2_32_RC_MUL_U_64:
3121 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3122 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
3123 break;
3124 case OPC2_32_RC_MULS_U_32:
3125 const9 = MASK_OP_RC_CONST9(ctx->opcode);
3126 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
3127 break;
3128 }
3129}
3130
0aaeb118
BK		 3131static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
3132{
59543d4e 3133 int op1;
a68e0d54 3134 int32_t r1, r2;
59543d4e 3135 int32_t address;
fc2ef4a3 3136 int8_t b, const4;
59543d4e
BK		 3137 int32_t bpos;
3138 TCGv temp, temp2;
3139
3140 op1 = MASK_OP_MAJOR(ctx->opcode);
3141
83c1bb18
BK		 3142 /* handle JNZ.T opcode only being 6 bit long */
3143 if (unlikely((op1 & 0x3f) == OPCM_32_BRN_JTT)) {
3144 op1 = OPCM_32_BRN_JTT;
3145 }
3146
59543d4e
BK		 3147 switch (op1) {
3148/* ABS-format */
3149 case OPCM_32_ABS_LDW:
3150 decode_abs_ldw(env, ctx);
3151 break;
3152 case OPCM_32_ABS_LDB:
3153 decode_abs_ldb(env, ctx);
3154 break;
3155 case OPCM_32_ABS_LDMST_SWAP:
3156 decode_abs_ldst_swap(env, ctx);
3157 break;
3158 case OPCM_32_ABS_LDST_CONTEXT:
3159 decode_abs_ldst_context(env, ctx);
3160 break;
3161 case OPCM_32_ABS_STORE:
3162 decode_abs_store(env, ctx);
3163 break;
3164 case OPCM_32_ABS_STOREB_H:
3165 decode_abs_storeb_h(env, ctx);
3166 break;
3167 case OPC1_32_ABS_STOREQ:
3168 address = MASK_OP_ABS_OFF18(ctx->opcode);
3169 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3170 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3171 temp2 = tcg_temp_new();
3172
3173 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
3174 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
3175
3176 tcg_temp_free(temp2);
3177 tcg_temp_free(temp);
3178 break;
3179 case OPC1_32_ABS_LD_Q:
3180 address = MASK_OP_ABS_OFF18(ctx->opcode);
3181 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3182 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3183
3184 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3185 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
3186
3187 tcg_temp_free(temp);
3188 break;
3189 case OPC1_32_ABS_LEA:
3190 address = MASK_OP_ABS_OFF18(ctx->opcode);
3191 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3192 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
3193 break;
3194/* ABSB-format */
3195 case OPC1_32_ABSB_ST_T:
3196 address = MASK_OP_ABS_OFF18(ctx->opcode);
3197 b = MASK_OP_ABSB_B(ctx->opcode);
3198 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
3199
3200 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3201 temp2 = tcg_temp_new();
3202
3203 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
3204 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
3205 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
3206 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
3207
3208 tcg_temp_free(temp);
3209 tcg_temp_free(temp2);
3210 break;
f718b0bb
BK		 3211/* B-format */
3212 case OPC1_32_B_CALL:
3213 case OPC1_32_B_CALLA:
3214 case OPC1_32_B_J:
3215 case OPC1_32_B_JA:
3216 case OPC1_32_B_JL:
3217 case OPC1_32_B_JLA:
3218 address = MASK_OP_B_DISP24(ctx->opcode);
3219 gen_compute_branch(ctx, op1, 0, 0, 0, address);
3220 break;
b74f2b5b
BK		 3221/* Bit-format */
3222 case OPCM_32_BIT_ANDACC:
3223 decode_bit_andacc(env, ctx);
3224 break;
3225 case OPCM_32_BIT_LOGICAL_T1:
3226 decode_bit_logical_t(env, ctx);
3227 break;
3228 case OPCM_32_BIT_INSERT:
3229 decode_bit_insert(env, ctx);
3230 break;
3231 case OPCM_32_BIT_LOGICAL_T2:
3232 decode_bit_logical_t2(env, ctx);
3233 break;
3234 case OPCM_32_BIT_ORAND:
3235 decode_bit_orand(env, ctx);
3236 break;
3237 case OPCM_32_BIT_SH_LOGIC1:
3238 decode_bit_sh_logic1(env, ctx);
3239 break;
3240 case OPCM_32_BIT_SH_LOGIC2:
3241 decode_bit_sh_logic2(env, ctx);
3242 break;
3a16ecb0
BK		 3243 /* BO Format */
3244 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
3245 decode_bo_addrmode_post_pre_base(env, ctx);
3246 break;
3247 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
3248 decode_bo_addrmode_bitreverse_circular(env, ctx);
3249 break;
3250 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
3251 decode_bo_addrmode_ld_post_pre_base(env, ctx);
3252 break;
3253 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
3254 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
3255 break;
3256 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
3257 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
3258 break;
3259 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
3260 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
3261 break;
3fb763cb
BK		 3262/* BOL-format */
3263 case OPC1_32_BOL_LD_A_LONGOFF:
3264 case OPC1_32_BOL_LD_W_LONFOFF:
3265 case OPC1_32_BOL_LEA_LONGOFF:
3266 case OPC1_32_BOL_ST_W_LONGOFF:
3267 case OPC1_32_BOL_ST_A_LONGOFF:
3268 decode_bol_opc(env, ctx, op1);
3269 break;
fc2ef4a3
BK		 3270/* BRC Format */
3271 case OPCM_32_BRC_EQ_NEQ:
3272 case OPCM_32_BRC_GE:
3273 case OPCM_32_BRC_JLT:
3274 case OPCM_32_BRC_JNE:
3275 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
3276 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
3277 r1 = MASK_OP_BRC_S1(ctx->opcode);
3278 gen_compute_branch(ctx, op1, r1, 0, const4, address);
3279 break;
83c1bb18
BK		 3280/* BRN Format */
3281 case OPCM_32_BRN_JTT:
3282 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
3283 r1 = MASK_OP_BRN_S1(ctx->opcode);
3284 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3285 break;
a68e0d54
BK		 3286/* BRR Format */
3287 case OPCM_32_BRR_EQ_NEQ:
3288 case OPCM_32_BRR_ADDR_EQ_NEQ:
3289 case OPCM_32_BRR_GE:
3290 case OPCM_32_BRR_JLT:
3291 case OPCM_32_BRR_JNE:
3292 case OPCM_32_BRR_JNZ:
3293 case OPCM_32_BRR_LOOP:
3294 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
3295 r2 = MASK_OP_BRR_S2(ctx->opcode);
3296 r1 = MASK_OP_BRR_S1(ctx->opcode);
3297 gen_compute_branch(ctx, op1, r1, r2, 0, address);
3298 break;
0974257e
BK		 3299/* RC Format */
3300 case OPCM_32_RC_LOGICAL_SHIFT:
3301 decode_rc_logical_shift(env, ctx);
3302 break;
3303 case OPCM_32_RC_ACCUMULATOR:
3304 decode_rc_accumulator(env, ctx);
3305 break;
3306 case OPCM_32_RC_SERVICEROUTINE:
3307 decode_rc_serviceroutine(env, ctx);
3308 break;
3309 case OPCM_32_RC_MUL:
3310 decode_rc_mul(env, ctx);
3311 break;
59543d4e 3312 }
0aaeb118
BK		 3313}
3314
3315static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
3316{
3317 /* 16-Bit Instruction */
3318 if ((ctx->opcode & 0x1) == 0) {
3319 ctx->next_pc = ctx->pc + 2;
3320 decode_16Bit_opc(env, ctx);
3321 /* 32-Bit Instruction */
3322 } else {
3323 ctx->next_pc = ctx->pc + 4;
3324 decode_32Bit_opc(env, ctx);
3325 }
3326}
3327
48e06fe0
BK		 3328static inline void
3329gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
3330 int search_pc)
3331{
0aaeb118
BK		 3332 CPUState *cs = CPU(cpu);
3333 CPUTriCoreState *env = &cpu->env;
3334 DisasContext ctx;
3335 target_ulong pc_start;
3336 int num_insns;
3337 uint16_t *gen_opc_end;
3338
3339 if (search_pc) {
3340 qemu_log("search pc %d\n", search_pc);
3341 }
3342
3343 num_insns = 0;
3344 pc_start = tb->pc;
3345 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
3346 ctx.pc = pc_start;
3347 ctx.saved_pc = -1;
3348 ctx.tb = tb;
3349 ctx.singlestep_enabled = cs->singlestep_enabled;
3350 ctx.bstate = BS_NONE;
3351 ctx.mem_idx = cpu_mmu_index(env);
3352
3353 tcg_clear_temp_count();
3354 gen_tb_start();
3355 while (ctx.bstate == BS_NONE) {
3356 ctx.opcode = cpu_ldl_code(env, ctx.pc);
3357 decode_opc(env, &ctx, 0);
3358
3359 num_insns++;
3360
3361 if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
9a31922b
BK		 3362 gen_save_pc(ctx.next_pc);
3363 tcg_gen_exit_tb(0);
0aaeb118
BK		 3364 break;
3365 }
3366 if (singlestep) {
9a31922b
BK		 3367 gen_save_pc(ctx.next_pc);
3368 tcg_gen_exit_tb(0);
0aaeb118
BK		 3369 break;
3370 }
3371 ctx.pc = ctx.next_pc;
3372 }
3373
3374 gen_tb_end(tb, num_insns);
3375 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3376 if (search_pc) {
3377 printf("done_generating search pc\n");
3378 } else {
3379 tb->size = ctx.pc - pc_start;
3380 tb->icount = num_insns;
3381 }
3382 if (tcg_check_temp_count()) {
3383 printf("LEAK at %08x\n", env->PC);
3384 }
3385
3386#ifdef DEBUG_DISAS
3387 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3388 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3389 log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
3390 qemu_log("\n");
3391 }
3392#endif
48e06fe0
BK		 3393}
3394
3395void
3396gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
3397{
3398 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
3399}
3400
3401void
3402gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
3403{
3404 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
3405}
3406
3407void
3408restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
3409{
3410 env->PC = tcg_ctx.gen_opc_pc[pc_pos];
3411}
3412/*
3413 *
3414 * Initialization
3415 *
3416 */
3417
3418void cpu_state_reset(CPUTriCoreState *env)
3419{
0aaeb118
BK		 3420 /* Reset Regs to Default Value */
3421 env->PSW = 0xb80;
3422}
3423
3424static void tricore_tcg_init_csfr(void)
3425{
3426 cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
3427 offsetof(CPUTriCoreState, PCXI), "PCXI");
3428 cpu_PSW = tcg_global_mem_new(TCG_AREG0,
3429 offsetof(CPUTriCoreState, PSW), "PSW");
3430 cpu_PC = tcg_global_mem_new(TCG_AREG0,
3431 offsetof(CPUTriCoreState, PC), "PC");
3432 cpu_ICR = tcg_global_mem_new(TCG_AREG0,
3433 offsetof(CPUTriCoreState, ICR), "ICR");
48e06fe0
BK		 3434}
3435
3436void tricore_tcg_init(void)
3437{
0aaeb118
BK		 3438 int i;
3439 static int inited;
3440 if (inited) {
3441 return;
3442 }
3443 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3444 /* reg init */
3445 for (i = 0 ; i < 16 ; i++) {
3446 cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
3447 offsetof(CPUTriCoreState, gpr_a[i]),
3448 regnames_a[i]);
3449 }
3450 for (i = 0 ; i < 16 ; i++) {
3451 cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
3452 offsetof(CPUTriCoreState, gpr_d[i]),
3453 regnames_d[i]);
3454 }
3455 tricore_tcg_init_csfr();
3456 /* init PSW flag cache */
3457 cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
3458 offsetof(CPUTriCoreState, PSW_USB_C),
3459 "PSW_C");
3460 cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
3461 offsetof(CPUTriCoreState, PSW_USB_V),
3462 "PSW_V");
3463 cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
3464 offsetof(CPUTriCoreState, PSW_USB_SV),
3465 "PSW_SV");
3466 cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
3467 offsetof(CPUTriCoreState, PSW_USB_AV),
3468 "PSW_AV");
3469 cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
3470 offsetof(CPUTriCoreState, PSW_USB_SAV),
3471 "PSW_SAV");
48e06fe0 3472}
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