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target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format
[mirror_qemu.git] / target-tricore / tricore-opcodes.h
CommitLineData
7c87d074
BK		 1/*
2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18/*
19 * Opcode Masks for Tricore
20 * Format MASK_OP_InstrFormatName_Field
21 */
22
23/* This creates a mask with bits start .. end set to 1 and applies it to op */
24#define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \
25 (end) - (start) + 1))
26#define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\
27 (end) - (start) + 1))
28
29/* new opcode masks */
30
31#define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
32
33/* 16-Bit Formats */
34#define MASK_OP_SB_DISP8(op) MASK_BITS_SHIFT(op, 8, 15)
35#define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15)
36
37#define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
38#define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
39#define MASK_OP_SBC_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
40
41#define MASK_OP_SBR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
42#define MASK_OP_SBR_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
43
44#define MASK_OP_SBRN_N(op) MASK_BITS_SHIFT(op, 12, 15)
45#define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
46
47#define MASK_OP_SC_CONST8(op) MASK_BITS_SHIFT(op, 8, 15)
48
49#define MASK_OP_SLR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
50#define MASK_OP_SLR_D(op) MASK_BITS_SHIFT(op, 8, 11)
51
52#define MASK_OP_SLRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
53#define MASK_OP_SLRO_D(op) MASK_BITS_SHIFT(op, 8, 11)
54
55#define MASK_OP_SR_OP2(op) MASK_BITS_SHIFT(op, 12, 15)
56#define MASK_OP_SR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
57
58#define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
59#define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
60#define MASK_OP_SRC_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
61
62#define MASK_OP_SRO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
63#define MASK_OP_SRO_OFF4(op) MASK_BITS_SHIFT(op, 8, 11)
64
65#define MASK_OP_SRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
66#define MASK_OP_SRR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
67
68#define MASK_OP_SRRS_S2(op) MASK_BITS_SHIFT(op, 12, 15)
69#define MASK_OP_SRRS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
70#define MASK_OP_SRRS_N(op) MASK_BITS_SHIFT(op, 6, 7)
71
72#define MASK_OP_SSR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
73#define MASK_OP_SSR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
74
75#define MASK_OP_SSRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
76#define MASK_OP_SSRO_S1(op) MASK_BITS_SHIFT(op, 8, 11)
77
78/* 32-Bit Formats */
79
80/* ABS Format */
81#define MASK_OP_ABS_OFF18(op) (MASK_BITS_SHIFT(op, 16, 21) + \
82 (MASK_BITS_SHIFT(op, 28, 31) << 6) + \
83 (MASK_BITS_SHIFT(op, 22, 25) << 10) +\
84 (MASK_BITS_SHIFT(op, 12, 15) << 14))
85#define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
86#define MASK_OP_ABS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
87
88/* ABSB Format */
89#define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
90#define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
91#define MASK_OP_ABSB_B(op) MASK_BITS_SHIFT(op, 11, 11)
030c58df 92#define MASK_OP_ABSB_BPOS(op) MASK_BITS_SHIFT(op, 8, 10)
7c87d074
BK		 93
94/* B Format */
95#define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
96 (MASK_BITS_SHIFT(op, 8, 15) << 16))
97/* BIT Format */
98#define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
99#define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
100#define MASK_OP_BIT_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
101#define MASK_OP_BIT_POS1(op) MASK_BITS_SHIFT(op, 16, 20)
102#define MASK_OP_BIT_S2(op) MASK_BITS_SHIFT(op, 12, 15)
103#define MASK_OP_BIT_S1(op) MASK_BITS_SHIFT(op, 8, 11)
104
105/* BO Format */
106#define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
107 (MASK_BITS_SHIFT(op, 28, 31) << 6))
3a16ecb0
BK		 108#define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \
109 (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
7c87d074
BK		 110#define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
111#define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
112#define MASK_OP_BO_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
113
114/* BOL Format */
115#define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
116 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
117 (MASK_BITS_SHIFT(op, 22, 27) >> 10))
3fb763cb
BK		 118#define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
119 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
120 (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
7c87d074
BK		 121#define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
122#define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
123
124/* BRC Format */
125#define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
126#define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
fc2ef4a3 127#define MASK_OP_BRC_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
7c87d074 128#define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
fc2ef4a3 129#define MASK_OP_BRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
7c87d074
BK		 130#define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11)
131
132/* BRN Format */
133#define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
134#define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
83c1bb18 135#define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
7c87d074
BK		 136#define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
137 (MASK_BITS_SHIFT(op, 7, 7) << 4))
138#define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)
139/* BRR Format */
140#define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
141#define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
a68e0d54 142#define MASK_OP_BRR_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
7c87d074
BK		 143#define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
144#define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
145
146/* META MASK for similar instr Formats */
147#define MASK_OP_META_D(op) MASK_BITS_SHIFT(op, 28, 31)
148#define MASK_OP_META_S1(op) MASK_BITS_SHIFT(op, 8, 11)
149
150/* RC Format */
151#define MASK_OP_RC_D(op) MASK_OP_META_D(op)
152#define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
153#define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
0974257e 154#define MASK_OP_RC_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20)
7c87d074
BK		 155#define MASK_OP_RC_S1(op) MASK_OP_META_S1(op)
156
157/* RCPW Format */
158
159#define MASK_OP_RCPW_D(op) MASK_OP_META_D(op)
160#define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
161#define MASK_OP_RCPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
162#define MASK_OP_RCPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
163#define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
164#define MASK_OP_RCPW_S1(op) MASK_OP_META_S1(op)
165
166/* RCR Format */
167
168#define MASK_OP_RCR_D(op) MASK_OP_META_D(op)
169#define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
170#define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
171#define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
172#define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op)
173
174/* RCRR Format */
175
176#define MASK_OP_RCRR_D(op) MASK_OP_META_D(op)
177#define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
178#define MASK_OP_RCRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
179#define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
180#define MASK_OP_RCRR_S1(op) MASK_OP_META_S1(op)
181
182/* RCRW Format */
183
184#define MASK_OP_RCRW_D(op) MASK_OP_META_D(op)
185#define MASK_OP_RCRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
186#define MASK_OP_RCRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
187#define MASK_OP_RCRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
188#define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
189#define MASK_OP_RCRW_S1(op) MASK_OP_META_S1(op)
190
191/* RLC Format */
192
193#define MASK_OP_RLC_D(op) MASK_OP_META_D(op)
194#define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
195#define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op)
196
197/* RR Format */
198#define MASK_OP_RR_D(op) MASK_OP_META_D(op)
199#define MASK_OP_RR_OP2(op) MASK_BITS_SHIFT(op, 20, 27)
200#define MASK_OP_RR_N(op) MASK_BITS_SHIFT(op, 16, 17)
201#define MASK_OP_RR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
202#define MASK_OP_RR_S1(op) MASK_OP_META_S1(op)
203
204/* RR1 Format */
205#define MASK_OP_RR1_D(op) MASK_OP_META_D(op)
206#define MASK_OP_RR1_OP2(op) MASK_BITS_SHIFT(op, 18, 27)
207#define MASK_OP_RR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
208#define MASK_OP_RR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
209#define MASK_OP_RR1_S1(op) MASK_OP_META_S1(op)
210
211/* RR2 Format */
212#define MASK_OP_RR2_D(op) MASK_OP_META_D(op)
213#define MASK_OP_RR2_OP2(op) MASK_BITS_SHIFT(op, 16, 27)
214#define MASK_OP_RR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
215#define MASK_OP_RR2_S1(op) MASK_OP_META_S1(op)
216
217/* RRPW Format */
218#define MASK_OP_RRPW_D(op) MASK_OP_META_D(op)
219#define MASK_OP_RRPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
220#define MASK_OP_RRPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
221#define MASK_OP_RRPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
222#define MASK_OP_RRPW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
223#define MASK_OP_RRPW_S1(op) MASK_OP_META_S1(op)
224
225/* RRR Format */
226#define MASK_OP_RRR_D(op) MASK_OP_META_D(op)
227#define MASK_OP_RRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
228#define MASK_OP_RRR_OP2(op) MASK_BITS_SHIFT(op, 20, 23)
229#define MASK_OP_RRR_N(op) MASK_BITS_SHIFT(op, 16, 17)
230#define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
231#define MASK_OP_RRR_S1(op) MASK_OP_META_S1(op)
232
233/* RRR1 Format */
234#define MASK_OP_RRR1_D(op) MASK_OP_META_D(op)
235#define MASK_OP_RRR1_S3(op) MASK_BITS_SHIFT(op, 24, 27)
236#define MASK_OP_RRR1_OP2(op) MASK_BITS_SHIFT(op, 18, 23)
237#define MASK_OP_RRR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
238#define MASK_OP_RRR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
239#define MASK_OP_RRR1_S1(op) MASK_OP_META_S1(op)
240
241/* RRR2 Format */
242#define MASK_OP_RRR2_D(op) MASK_OP_META_D(op)
243#define MASK_OP_RRR2_S3(op) MASK_BITS_SHIFT(op, 24, 27)
244#define MASK_OP_RRR2_OP2(op) MASK_BITS_SHIFT(op, 16, 23)
245#define MASK_OP_RRR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
246#define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op)
247
248/* RRRR Format */
249#define MASK_OP_RRRR_D(op) MASK_OP_META_D(op)
250#define MASK_OP_RRRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
251#define MASK_OP_RRRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
252#define MASK_OP_RRRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
253#define MASK_OP_RRRR_S1(op) MASK_OP_META_S1(op)
254
255/* RRRW Format */
256#define MASK_OP_RRRW_D(op) MASK_OP_META_D(op)
257#define MASK_OP_RRRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
258#define MASK_OP_RRRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
259#define MASK_OP_RRRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
260#define MASK_OP_RRRW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
261#define MASK_OP_RRRW_S1(op) MASK_OP_META_S1(op)
262
263/* SYS Format */
264#define MASK_OP_SYS_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
265#define MASK_OP_SYS_S1D(op) MASK_OP_META_S1(op)
266
267
268
269/*
270 * Tricore Opcodes Enums
271 *
272 * Format: OPC(1|2|M)_InstrLen_Name
273 * OPC1 = only op1 field is used
274 * OPC2 = op1 and op2 field used part of OPCM
275 * OPCM = op1 field used to group Instr
276 * InstrLen = 16|32
277 * Name = Name of Instr
278 */
279
280/* 16-Bit */
281enum {
282
283 OPCM_16_SR_SYSTEM = 0x00,
284 OPCM_16_SR_ACCU = 0x32,
285
286 OPC1_16_SRC_ADD = 0xc2,
287 OPC1_16_SRC_ADD_A15 = 0x92,
288 OPC1_16_SRC_ADD_15A = 0x9a,
289 OPC1_16_SRR_ADD = 0x42,
290 OPC1_16_SRR_ADD_A15 = 0x12,
291 OPC1_16_SRR_ADD_15A = 0x1a,
292 OPC1_16_SRC_ADD_A = 0xb0,
293 OPC1_16_SRR_ADD_A = 0x30,
294 OPC1_16_SRR_ADDS = 0x22,
295 OPC1_16_SRRS_ADDSC_A = 0x10,
296 OPC1_16_SC_AND = 0x16,
297 OPC1_16_SRR_AND = 0x26,
298 OPC1_16_SC_BISR = 0xe0,
299 OPC1_16_SRC_CADD = 0x8a,
300 OPC1_16_SRC_CADDN = 0xca,
301 OPC1_16_SB_CALL = 0x5c,
302 OPC1_16_SRC_CMOV = 0xaa,
303 OPC1_16_SRR_CMOV = 0x2a,
304 OPC1_16_SRC_CMOVN = 0xea,
305 OPC1_16_SRR_CMOVN = 0x6a,
306 OPC1_16_SRC_EQ = 0xba,
307 OPC1_16_SRR_EQ = 0x3a,
308 OPC1_16_SB_J = 0x3c,
309 OPC1_16_SBC_JEQ = 0x1e,
310 OPC1_16_SBR_JEQ = 0x3e,
311 OPC1_16_SBR_JGEZ = 0xce,
312 OPC1_16_SBR_JGTZ = 0x4e,
313 OPC1_16_SR_JI = 0xdc,
314 OPC1_16_SBR_JLEZ = 0x8e,
315 OPC1_16_SBR_JLTZ = 0x0e,
316 OPC1_16_SBC_JNE = 0x5e,
317 OPC1_16_SBR_JNE = 0x7e,
318 OPC1_16_SB_JNZ = 0xee,
319 OPC1_16_SBR_JNZ = 0xf6,
320 OPC1_16_SBR_JNZ_A = 0x7c,
321 OPC1_16_SBRN_JNZ_T = 0xae,
322 OPC1_16_SB_JZ = 0x6e,
323 OPC1_16_SBR_JZ = 0x76,
324 OPC1_16_SBR_JZ_A = 0xbc,
325 OPC1_16_SBRN_JZ_T = 0x2e,
326 OPC1_16_SC_LD_A = 0xd8,
327 OPC1_16_SLR_LD_A = 0xd4,
328 OPC1_16_SLR_LD_A_POSTINC = 0xc4,
329 OPC1_16_SLRO_LD_A = 0xc8,
330 OPC1_16_SRO_LD_A = 0xcc,
331 OPC1_16_SLR_LD_BU = 0x14,
332 OPC1_16_SLR_LD_BU_POSTINC = 0x04,
333 OPC1_16_SLRO_LD_BU = 0x08,
334 OPC1_16_SRO_LD_BU = 0x0c,
335 OPC1_16_SLR_LD_H = 0x94,
336 OPC1_16_SLR_LD_H_POSTINC = 0x84,
337 OPC1_16_SLRO_LD_H = 0x88,
338 OPC1_16_SRO_LD_H = 0x8c,
339 OPC1_16_SC_LD_W = 0x58,
340 OPC1_16_SLR_LD_W = 0x54,
341 OPC1_16_SLR_LD_W_POSTINC = 0x44,
342 OPC1_16_SLRO_LD_W = 0x48,
343 OPC1_16_SRO_LD_W = 0x4c,
344 OPC1_16_SBR_LOOP = 0xfc,
345 OPC1_16_SRC_LT = 0xfa,
346 OPC1_16_SRR_LT = 0x7a,
347 OPC1_16_SC_MOV = 0xda,
348 OPC1_16_SRC_MOV = 0x82,
349 OPC1_16_SRR_MOV = 0x02,
350 OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */
351 OPC1_16_SRC_MOV_A = 0xa0,
352 OPC1_16_SRR_MOV_A = 0x60,
353 OPC1_16_SRR_MOV_AA = 0x40,
354 OPC1_16_SRR_MOV_D = 0x80,
355 OPC1_16_SRR_MUL = 0xe2,
356 OPC1_16_SR_NOT = 0x46,
357 OPC1_16_SC_OR = 0x96,
358 OPC1_16_SRR_OR = 0xa6,
359 OPC1_16_SRC_SH = 0x06,
360 OPC1_16_SRC_SHA = 0x86,
361 OPC1_16_SC_ST_A = 0xf8,
362 OPC1_16_SRO_ST_A = 0xec,
363 OPC1_16_SSR_ST_A = 0xf4,
364 OPC1_16_SSR_ST_A_POSTINC = 0xe4,
365 OPC1_16_SSRO_ST_A = 0xe8,
366 OPC1_16_SRO_ST_B = 0x2c,
367 OPC1_16_SSR_ST_B = 0x34,
368 OPC1_16_SSR_ST_B_POSTINC = 0x24,
369 OPC1_16_SSRO_ST_B = 0x28,
370 OPC1_16_SRO_ST_H = 0xac,
371 OPC1_16_SSR_ST_H = 0xb4,
372 OPC1_16_SSR_ST_H_POSTINC = 0xa4,
373 OPC1_16_SSRO_ST_H = 0xa8,
374 OPC1_16_SC_ST_W = 0x78,
375 OPC1_16_SRO_ST_W = 0x6c,
376 OPC1_16_SSR_ST_W = 0x74,
377 OPC1_16_SSR_ST_W_POSTINC = 0x64,
378 OPC1_16_SSRO_ST_W = 0x68,
379 OPC1_16_SRR_SUB = 0xa2,
380 OPC1_16_SRR_SUB_A15B = 0x52,
381 OPC1_16_SRR_SUB_15AB = 0x5a,
382 OPC1_16_SC_SUB_A = 0x20,
383 OPC1_16_SRR_SUBS = 0x62,
384 OPC1_16_SRR_XOR = 0xc6,
385
386};
387
388/*
389 * SR Format
390 */
391/* OPCM_16_SR_SYSTEM */
392enum {
393
394 OPC2_16_SR_NOP = 0x00,
395 OPC2_16_SR_RET = 0x09,
396 OPC2_16_SR_RFE = 0x08,
397 OPC2_16_SR_DEBUG = 0x0a,
398};
399/* OPCM_16_SR_ACCU */
400enum {
401 OPC2_16_SR_RSUB = 0x05,
402 OPC2_16_SR_SAT_B = 0x00,
403 OPC2_16_SR_SAT_BU = 0x01,
404 OPC2_16_SR_SAT_H = 0x02,
405 OPC2_16_SR_SAT_HU = 0x03,
406
407};
408
409/* 32-Bit */
410
411enum {
412/* ABS Format 1, M */
413 OPCM_32_ABS_LDW = 0x85,
414 OPCM_32_ABS_LDB = 0x05,
415 OPCM_32_ABS_LDMST_SWAP = 0xe5,
416 OPCM_32_ABS_LDST_CONTEXT = 0x15,
417 OPCM_32_ABS_STORE = 0xa5,
418 OPCM_32_ABS_STOREB_H = 0x25,
419 OPC1_32_ABS_STOREQ = 0x65,
420 OPC1_32_ABS_LD_Q = 0x45,
421 OPC1_32_ABS_LEA = 0xc5,
422/* ABSB Format */
423 OPC1_32_ABSB_ST_T = 0xd5,
424/* B Format */
425 OPC1_32_B_CALL = 0x6d,
426 OPC1_32_B_CALLA = 0xed,
427 OPC1_32_B_J = 0x1d,
428 OPC1_32_B_JA = 0x9d,
429 OPC1_32_B_JL = 0x5d,
430 OPC1_32_B_JLA = 0xdd,
431/* Bit Format */
432 OPCM_32_BIT_ANDACC = 0x47,
433 OPCM_32_BIT_LOGICAL_T1 = 0x87,
434 OPCM_32_BIT_INSERT = 0x67,
435 OPCM_32_BIT_LOGICAL_T2 = 0x07,
436 OPCM_32_BIT_ORAND = 0xc7,
437 OPCM_32_BIT_SH_LOGIC1 = 0x27,
438 OPCM_32_BIT_SH_LOGIC2 = 0xa7,
439/* BO Format */
440 OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89,
441 OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9,
442 OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09,
443 OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29,
444 OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49,
445 OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
446/* BOL Format */
447 OPC1_32_BOL_LD_A_LONGOFF = 0x99,
448 OPC1_32_BOL_LD_W_LONFOFF = 0x19,
449 OPC1_32_BOL_LEA_LONGOFF = 0xd9,
450 OPC1_32_BOL_ST_W_LONGOFF = 0x59,
451 OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
452/* BRC Format */
453 OPCM_32_BRC_EQ_NEQ = 0xdf,
454 OPCM_32_BRC_GE = 0xff,
455 OPCM_32_BRC_JLT = 0xbf,
456 OPCM_32_BRC_JNE = 0x9f,
457/* BRN Format */
458 OPCM_32_BRN_JTT = 0x6f,
459/* BRR Format */
460 OPCM_32_BRR_EQ_NEQ = 0x5f,
461 OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d,
462 OPCM_32_BRR_GE = 0x7f,
463 OPCM_32_BRR_JLT = 0x3f,
464 OPCM_32_BRR_JNE = 0x1f,
465 OPCM_32_BRR_JNZ = 0xbd,
466 OPCM_32_BRR_LOOP = 0xfd,
467/* RC Format */
468 OPCM_32_RC_LOGICAL_SHIFT = 0x8f,
469 OPCM_32_RC_ACCUMULATOR = 0x8b,
470 OPCM_32_RC_SERVICEROUTINE = 0xad,
471 OPCM_32_RC_MUL = 0x53,
472/* RCPW Format */
473 OPCM_32_RCPW_MASK_INSERT = 0xb7,
474/* RCR Format */
475 OPCM_32_RCR_COND_SELECT = 0xab,
476 OPCM_32_RCR_MADD = 0x13,
477 OPCM_32_RCR_MSUB = 0x33,
478/* RCRR Format */
479 OPC1_32_RCRR_INSERT = 0x97,
480/* RCRW Format */
481 OPCM_32_RCRW_MASK_INSERT = 0xd7,
482/* RLC Format */
483 OPC1_32_RLC_ADDI = 0x1b,
484 OPC1_32_RLC_ADDIH = 0x9b,
485 OPC1_32_RLC_ADDIH_A = 0x11,
486 OPC1_32_RLC_MFCR = 0x4d,
487 OPC1_32_RLC_MOV = 0x3b,
488 OPC1_32_RLC_MOV_U = 0xbb,
489 OPC1_32_RLC_MOV_H = 0x7b,
490 OPC1_32_RLC_MOVH_A = 0x91,
491 OPC1_32_RLC_MTCR = 0xcd,
492/* RR Format */
493 OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
494 OPCM_32_RR_ACCUMULATOR = 0x0b,
495 OPCM_32_RR_ADRESS = 0x01,
496 OPCM_32_RR_FLOAT = 0x4b,
497 OPCM_32_RR_IDIRECT = 0x2d,
498/* RR1 Format */
499 OPCM_32_RR1_MUL = 0xb3,
500 OPCM_32_RR1_MULQ = 0x93,
501/* RR2 Format */
502 OPCM_32_RR2_MUL = 0x73,
503/* RRPW Format */
504 OPCM_32_RRPW_EXTRACT_INSERT = 0x37,
505 OPC1_32_RRPW_DEXTR = 0x77,
506/* RRR Format */
507 OPCM_32_RRR_COND_SELECT = 0x2b,
508 OPCM_32_RRR_FLOAT = 0x6b,
509/* RRR1 Format */
510 OPCM_32_RRR1_MADD = 0x83,
511 OPCM_32_RRR1_MADDQ_H = 0x43,
512 OPCM_32_RRR1_MADDSU_H = 0xc3,
513 OPCM_32_RRR1_MSUB_H = 0xa3,
514 OPCM_32_RRR1_MSUB_Q = 0x63,
515 OPCM_32_RRR1_MSUBADS_H = 0xe3,
516/* RRR2 Format */
517 OPCM_32_RRR2_MADD = 0x03,
518 OPCM_32_RRR2_MSUB = 0x23,
519/* RRRR Format */
520 OPCM_32_RRRR_EXTRACT_INSERT = 0x17,
521/* RRRW Format */
522 OPCM_32_RRRW_EXTRACT_INSERT = 0x57,
523/* SYS Format */
524 OPCM_32_SYS_INTERRUPTS = 0x0d,
525 OPC1_32_SYS_RSTV = 0x2f,
526};
527
528
529
530/*
531 * ABS Format
532 */
533
534/* OPCM_32_ABS_LDW */
535enum {
536
537 OPC2_32_ABS_LD_A = 0x02,
538 OPC2_32_ABS_LD_D = 0x01,
539 OPC2_32_ABS_LD_DA = 0x03,
540 OPC2_32_ABS_LD_W = 0x00,
541};
542
543/* OPCM_32_ABS_LDB */
544enum {
545 OPC2_32_ABS_LD_B = 0x00,
546 OPC2_32_ABS_LD_BU = 0x01,
547 OPC2_32_ABS_LD_H = 0x02,
548 OPC2_32_ABS_LD_HU = 0x03,
549};
550/* OPCM_32_ABS_LDMST_SWAP */
551enum {
552 OPC2_32_ABS_LDMST = 0x01,
553 OPC2_32_ABS_SWAP_W = 0x00,
554};
555/* OPCM_32_ABS_LDST_CONTEXT */
556enum {
557 OPC2_32_ABS_LDLCX = 0x02,
558 OPC2_32_ABS_LDUCX = 0x03,
559 OPC2_32_ABS_STLCX = 0x00,
560 OPC2_32_ABS_STUCX = 0x01,
561};
562/* OPCM_32_ABS_STORE */
563enum {
564 OPC2_32_ABS_ST_A = 0x02,
565 OPC2_32_ABS_ST_D = 0x01,
566 OPC2_32_ABS_ST_DA = 0x03,
567 OPC2_32_ABS_ST_W = 0x00,
568};
569/* OPCM_32_ABS_STOREB_H */
570enum {
571 OPC2_32_ABS_ST_B = 0x00,
572 OPC2_32_ABS_ST_H = 0x02,
573};
574/*
575 * Bit Format
576 */
577/* OPCM_32_BIT_ANDACC */
578enum {
579 OPC2_32_BIT_AND_AND_T = 0x00,
580 OPC2_32_BIT_AND_ANDN_T = 0x03,
581 OPC2_32_BIT_AND_NOR_T = 0x02,
582 OPC2_32_BIT_AND_OR_T = 0x01,
583};
584/* OPCM_32_BIT_LOGICAL_T */
585enum {
586 OPC2_32_BIT_AND_T = 0x00,
587 OPC2_32_BIT_ANDN_T = 0x03,
588 OPC2_32_BIT_NOR_T = 0x02,
589 OPC2_32_BIT_OR_T = 0x01,
590};
591/* OPCM_32_BIT_INSERT */
592enum {
593 OPC2_32_BIT_INS_T = 0x00,
594 OPC2_32_BIT_INSN_T = 0x01,
595};
596/* OPCM_32_BIT_LOGICAL_T2 */
597enum {
598 OPC2_32_BIT_NAND_T = 0x00,
599 OPC2_32_BIT_ORN_T = 0x01,
600 OPC2_32_BIT_XNOR_T = 0x02,
601 OPC2_32_BIT_XOR_T = 0x03,
602};
603/* OPCM_32_BIT_ORAND */
604enum {
605 OPC2_32_BIT_OR_AND_T = 0x00,
606 OPC2_32_BIT_OR_ANDN_T = 0x03,
607 OPC2_32_BIT_OR_NOR_T = 0x02,
608 OPC2_32_BIT_OR_OR_T = 0x01,
609};
610/*OPCM_32_BIT_SH_LOGIC1 */
611enum {
612 OPC2_32_BIT_SH_AND_T = 0x00,
613 OPC2_32_BIT_SH_ANDN_T = 0x03,
614 OPC2_32_BIT_SH_NOR_T = 0x02,
615 OPC2_32_BIT_SH_OR_T = 0x01,
616};
617/* OPCM_32_BIT_SH_LOGIC2 */
618enum {
619 OPC2_32_BIT_SH_NAND_T = 0x00,
620 OPC2_32_BIT_SH_ORN_T = 0x01,
621 OPC2_32_BIT_SH_XNOR_T = 0x02,
622 OPC2_32_BIT_SH_XOR_T = 0x03,
623};
624/*
625 * BO Format
626 */
627/* OPCM_32_BO_ADDRMODE_POST_PRE_BASE */
628enum {
629 OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e,
630 OPC2_32_BO_CACHEA_I_POSTINC = 0x0e,
631 OPC2_32_BO_CACHEA_I_PREINC = 0x1e,
632 OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c,
633 OPC2_32_BO_CACHEA_W_POSTINC = 0x0c,
634 OPC2_32_BO_CACHEA_W_PREINC = 0x1c,
635 OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d,
636 OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d,
637 OPC2_32_BO_CACHEA_WI_PREINC = 0x1d,
638 /* 1.3.1 only */
639 OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b,
640 OPC2_32_BO_CACHEI_W_POSTINC = 0x0b,
641 OPC2_32_BO_CACHEI_W_PREINC = 0x1b,
642 OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f,
643 OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f,
644 OPC2_32_BO_CACHEI_WI_PREINC = 0x1f,
645 /* end 1.3.1 only */
646 OPC2_32_BO_ST_A_SHORTOFF = 0x26,
647 OPC2_32_BO_ST_A_POSTINC = 0x06,
648 OPC2_32_BO_ST_A_PREINC = 0x16,
649 OPC2_32_BO_ST_B_SHORTOFF = 0x20,
650 OPC2_32_BO_ST_B_POSTINC = 0x00,
651 OPC2_32_BO_ST_B_PREINC = 0x10,
652 OPC2_32_BO_ST_D_SHORTOFF = 0x25,
653 OPC2_32_BO_ST_D_POSTINC = 0x05,
654 OPC2_32_BO_ST_D_PREINC = 0x15,
655 OPC2_32_BO_ST_DA_SHORTOFF = 0x27,
656 OPC2_32_BO_ST_DA_POSTINC = 0x07,
657 OPC2_32_BO_ST_DA_PREINC = 0x17,
658 OPC2_32_BO_ST_H_SHORTOFF = 0x22,
659 OPC2_32_BO_ST_H_POSTINC = 0x02,
660 OPC2_32_BO_ST_H_PREINC = 0x12,
661 OPC2_32_BO_ST_Q_SHORTOFF = 0x28,
662 OPC2_32_BO_ST_Q_POSTINC = 0x08,
663 OPC2_32_BO_ST_Q_PREINC = 0x18,
664 OPC2_32_BO_ST_W_SHORTOFF = 0x24,
665 OPC2_32_BO_ST_W_POSTINC = 0x04,
666 OPC2_32_BO_ST_W_PREINC = 0x14,
667};
668/* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR */
669enum {
670 OPC2_32_BO_CACHEA_I_BR = 0x0e,
671 OPC2_32_BO_CACHEA_I_CIRC = 0x1e,
672 OPC2_32_BO_CACHEA_W_BR = 0x0c,
673 OPC2_32_BO_CACHEA_W_CIRC = 0x1c,
674 OPC2_32_BO_CACHEA_WI_BR = 0x0d,
675 OPC2_32_BO_CACHEA_WI_CIRC = 0x1d,
676 OPC2_32_BO_ST_A_BR = 0x06,
677 OPC2_32_BO_ST_A_CIRC = 0x16,
678 OPC2_32_BO_ST_B_BR = 0x00,
679 OPC2_32_BO_ST_B_CIRC = 0x10,
680 OPC2_32_BO_ST_D_BR = 0x05,
681 OPC2_32_BO_ST_D_CIRC = 0x15,
682 OPC2_32_BO_ST_DA_BR = 0x07,
683 OPC2_32_BO_ST_DA_CIRC = 0x17,
684 OPC2_32_BO_ST_H_BR = 0x02,
685 OPC2_32_BO_ST_H_CIRC = 0x12,
686 OPC2_32_BO_ST_Q_BR = 0x08,
687 OPC2_32_BO_ST_Q_CIRC = 0x18,
688 OPC2_32_BO_ST_W_BR = 0x04,
689 OPC2_32_BO_ST_W_CIRC = 0x14,
690};
691/* OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE */
692enum {
693 OPC2_32_BO_LD_A_SHORTOFF = 0x26,
694 OPC2_32_BO_LD_A_POSTINC = 0x06,
695 OPC2_32_BO_LD_A_PREINC = 0x16,
696 OPC2_32_BO_LD_B_SHORTOFF = 0x20,
697 OPC2_32_BO_LD_B_POSTINC = 0x00,
698 OPC2_32_BO_LD_B_PREINC = 0x10,
699 OPC2_32_BO_LD_BU_SHORTOFF = 0x21,
700 OPC2_32_BO_LD_BU_POSTINC = 0x01,
701 OPC2_32_BO_LD_BU_PREINC = 0x11,
702 OPC2_32_BO_LD_D_SHORTOFF = 0x25,
703 OPC2_32_BO_LD_D_POSTINC = 0x05,
704 OPC2_32_BO_LD_D_PREINC = 0x15,
705 OPC2_32_BO_LD_DA_SHORTOFF = 0x27,
706 OPC2_32_BO_LD_DA_POSTINC = 0x07,
707 OPC2_32_BO_LD_DA_PREINC = 0x17,
708 OPC2_32_BO_LD_H_SHORTOFF = 0x22,
709 OPC2_32_BO_LD_H_POSTINC = 0x02,
710 OPC2_32_BO_LD_H_PREINC = 0x12,
711 OPC2_32_BO_LD_HU_SHORTOFF = 0x23,
712 OPC2_32_BO_LD_HU_POSTINC = 0x03,
713 OPC2_32_BO_LD_HU_PREINC = 0x13,
714 OPC2_32_BO_LD_Q_SHORTOFF = 0x28,
715 OPC2_32_BO_LD_Q_POSTINC = 0x08,
716 OPC2_32_BO_LD_Q_PREINC = 0x18,
717 OPC2_32_BO_LD_W_SHORTOFF = 0x24,
718 OPC2_32_BO_LD_W_POSTINC = 0x04,
719 OPC2_32_BO_LD_W_PREINC = 0x14,
720};
721/* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR */
722enum {
723 OPC2_32_BO_LD_A_BR = 0x06,
724 OPC2_32_BO_LD_A_CIRC = 0x16,
725 OPC2_32_BO_LD_B_BR = 0x00,
726 OPC2_32_BO_LD_B_CIRC = 0x10,
727 OPC2_32_BO_LD_BU_BR = 0x01,
728 OPC2_32_BO_LD_BU_CIRC = 0x11,
729 OPC2_32_BO_LD_D_BR = 0x05,
730 OPC2_32_BO_LD_D_CIRC = 0x15,
731 OPC2_32_BO_LD_DA_BR = 0x07,
732 OPC2_32_BO_LD_DA_CIRC = 0x17,
733 OPC2_32_BO_LD_H_BR = 0x02,
734 OPC2_32_BO_LD_H_CIRC = 0x12,
735 OPC2_32_BO_LD_HU_BR = 0x03,
736 OPC2_32_BO_LD_HU_CIRC = 0x13,
737 OPC2_32_BO_LD_Q_BR = 0x08,
738 OPC2_32_BO_LD_Q_CIRC = 0x18,
739 OPC2_32_BO_LD_W_BR = 0x04,
740 OPC2_32_BO_LD_W_CIRC = 0x14,
741};
742/* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE */
743enum {
744 OPC2_32_BO_LDLCX_SHORTOFF = 0x24,
745 OPC2_32_BO_LDMST_SHORTOFF = 0x21,
746 OPC2_32_BO_LDMST_POSTINC = 0x01,
747 OPC2_32_BO_LDMST_PREINC = 0x11,
748 OPC2_32_BO_LDUCX_SHORTOFF = 0x25,
749 OPC2_32_BO_LEA_SHORTOFF = 0x28,
750 OPC2_32_BO_STLCX_SHORTOFF = 0x26,
751 OPC2_32_BO_STUCX_SHORTOFF = 0x27,
752 OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
753 OPC2_32_BO_SWAP_W_POSTINC = 0x00,
754 OPC2_32_BO_SWAP_W_PREINC = 0x10,
755};
756/*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
757enum {
758 OPC2_32_BO_LDMST_BR = 0x01,
759 OPC2_32_BO_LDMST_CIRC = 0x11,
760 OPC2_32_BO_SWAP_W_BR = 0x00,
761 OPC2_32_BO_SWAP_W_CIRC = 0x10,
762};
763/*
764 * BRC Format
765 */
766/*OPCM_32_BRC_EQ_NEQ */
767enum {
768 OPC2_32_BRC_JEQ = 0x00,
769 OPC2_32_BRC_JNE = 0x01,
770};
771/* OPCM_32_BRC_GE */
772enum {
fc2ef4a3
BK		 773 OP2_32_BRC_JGE = 0x00,
774 OPC_32_BRC_JGE_U = 0x01,
7c87d074
BK		 775};
776/* OPCM_32_BRC_JLT */
777enum {
778 OPC2_32_BRC_JLT = 0x00,
779 OPC2_32_BRC_JLT_U = 0x01,
780};
781/* OPCM_32_BRC_JNE */
782enum {
783 OPC2_32_BRC_JNED = 0x01,
784 OPC2_32_BRC_JNEI = 0x00,
785};
786/*
787 * BRN Format
788 */
789/* OPCM_32_BRN_JTT */
790enum {
791 OPC2_32_BRN_JNZ_T = 0x01,
792 OPC2_32_BRN_JZ_T = 0x00,
793};
794/*
795 * BRR Format
796 */
797/* OPCM_32_BRR_EQ_NEQ */
798enum {
799 OPC2_32_BRR_JEQ = 0x00,
800 OPC2_32_BRR_JNE = 0x01,
801};
802/* OPCM_32_BRR_ADDR_EQ_NEQ */
803enum {
804 OPC2_32_BRR_JEQ_A = 0x00,
805 OPC2_32_BRR_JNE_A = 0x01,
806};
807/*OPCM_32_BRR_GE */
808enum {
809 OPC2_32_BRR_JGE = 0x00,
810 OPC2_32_BRR_JGE_U = 0x01,
811};
812/* OPCM_32_BRR_JLT */
813enum {
814 OPC2_32_BRR_JLT = 0x00,
815 OPC2_32_BRR_JLT_U = 0x01,
816};
817/* OPCM_32_BRR_JNE */
818enum {
819 OPC2_32_BRR_JNED = 0x01,
820 OPC2_32_BRR_JNEI = 0x00,
821};
822/* OPCM_32_BRR_JNZ */
823enum {
824 OPC2_32_BRR_JNZ_A = 0x01,
825 OPC2_32_BRR_JZ_A = 0x00,
826};
827/* OPCM_32_BRR_LOOP */
828enum {
829 OPC2_32_BRR_LOOP = 0x00,
830 OPC2_32_BRR_LOOPU = 0x01,
831};
832/*
833 * RC Format
834 */
835/* OPCM_32_RC_LOGICAL_SHIFT */
836enum {
837 OPC2_32_RC_AND = 0x08,
838 OPC2_32_RC_ANDN = 0x0e,
839 OPC2_32_RC_NAND = 0x09,
840 OPC2_32_RC_NOR = 0x0b,
841 OPC2_32_RC_OR = 0x0a,
842 OPC2_32_RC_ORN = 0x0f,
843 OPC2_32_RC_SH = 0x00,
844 OPC2_32_RC_SH_H = 0x40,
845 OPC2_32_RC_SHA = 0x01,
846 OPC2_32_RC_SHA_H = 0x41,
847 OPC2_32_RC_SHAS = 0x02,
848 OPC2_32_RC_XNOR = 0x0d,
849 OPC2_32_RC_XOR = 0x0c,
850};
851/* OPCM_32_RC_ACCUMULATOR */
852enum {
853 OPC2_32_RC_ABSDIF = 0x0e,
854 OPC2_32_RC_ABSDIFS = 0x0f,
855 OPC2_32_RC_ADD = 0x00,
856 OPC2_32_RC_ADDC = 0x05,
857 OPC2_32_RC_ADDS = 0x02,
858 OPC2_32_RC_ADDS_U = 0x03,
859 OPC2_32_RC_ADDX = 0x04,
860 OPC2_32_RC_AND_EQ = 0x20,
861 OPC2_32_RC_AND_GE = 0x24,
862 OPC2_32_RC_AND_GE_U = 0x25,
863 OPC2_32_RC_AND_LT = 0x22,
864 OPC2_32_RC_AND_LT_U = 0x23,
865 OPC2_32_RC_AND_NE = 0x21,
866 OPC2_32_RC_EQ = 0x10,
867 OPC2_32_RC_EQANY_B = 0x56,
868 OPC2_32_RC_EQANY_H = 0x76,
869 OPC2_32_RC_GE = 0x14,
870 OPC2_32_RC_GE_U = 0x15,
871 OPC2_32_RC_LT = 0x12,
872 OPC2_32_RC_LT_U = 0x13,
873 OPC2_32_RC_MAX = 0x1a,
874 OPC2_32_RC_MAX_U = 0x1b,
875 OPC2_32_RC_MIN = 0x18,
876 OPC2_32_RC_MIN_U = 0x19,
877 OPC2_32_RC_NE = 0x11,
878 OPC2_32_RC_OR_EQ = 0x27,
879 OPC2_32_RC_OR_GE = 0x2b,
880 OPC2_32_RC_OR_GE_U = 0x2c,
881 OPC2_32_RC_OR_LT = 0x29,
882 OPC2_32_RC_OR_LT_U = 0x2a,
883 OPC2_32_RC_OR_NE = 0x28,
884 OPC2_32_RC_RSUB = 0x08,
885 OPC2_32_RC_RSUBS = 0x0a,
886 OPC2_32_RC_RSUBS_U = 0x0b,
887 OPC2_32_RC_SH_EQ = 0x37,
888 OPC2_32_RC_SH_GE = 0x3b,
889 OPC2_32_RC_SH_GE_U = 0x3c,
890 OPC2_32_RC_SH_LT = 0x39,
891 OPC2_32_RC_SH_LT_U = 0x3a,
892 OPC2_32_RC_SH_NE = 0x38,
893 OPC2_32_RC_XOR_EQ = 0x2f,
894 OPC2_32_RC_XOR_GE = 0x33,
895 OPC2_32_RC_XOR_GE_U = 0x34,
896 OPC2_32_RC_XOR_LT = 0x31,
897 OPC2_32_RC_XOR_LT_U = 0x32,
898 OPC2_32_RC_XOR_NE = 0x30,
899};
900/* OPCM_32_RC_SERVICEROUTINE */
901enum {
902 OPC2_32_RC_BISR = 0x00,
903 OPC2_32_RC_SYSCALL = 0x04,
904};
905/* OPCM_32_RC_MUL */
906enum {
907 OPC2_32_RC_MUL_32 = 0x01,
908 OPC2_32_RC_MUL_64 = 0x03,
909 OPC2_32_RC_MULS_32 = 0x05,
910 OPC2_32_RC_MUL_U_64 = 0x02,
911 OPC2_32_RC_MULS_U_32 = 0x04,
912};
913/*
914 * RCPW Format
915 */
916/* OPCM_32_RCPW_MASK_INSERT */
917enum {
918 OPC2_32_RCPW_IMASK = 0x01,
919 OPC2_32_RCPW_INSERT = 0x00,
920};
921/*
922 * RCR Format
923 */
924/* OPCM_32_RCR_COND_SELECT */
925enum {
926 OPC2_32_RCR_CADD = 0x00,
927 OPC2_32_RCR_CADDN = 0x01,
928 OPC2_32_RCR_SEL = 0x04,
929 OPC2_32_RCR_SELN = 0x05,
930};
931/* OPCM_32_RCR_MADD */
932enum {
933 OPC2_32_RCR_MADD_32 = 0x01,
934 OPC2_32_RCR_MADD_64 = 0x03,
935 OPC2_32_RCR_MADDS_32 = 0x05,
936 OPC2_32_RCR_MADDS_64 = 0x07,
937 OPC2_32_RCR_MADD_U_64 = 0x02,
938 OPC2_32_RCR_MADDS_U_32 = 0x04,
939 OPC2_32_RCR_MADDS_U_64 = 0x06,
940};
941/* OPCM_32_RCR_MSUB */
942enum {
943 OPC2_32_RCR_MSUB_32 = 0x01,
944 OPC2_32_RCR_MSUB_64 = 0x03,
945 OPC2_32_RCR_MSUBS_32 = 0x05,
946 OPC2_32_RCR_MSUBS_64 = 0x07,
947 OPC2_32_RCR_MSUB_U_32 = 0x02,
948 OPC2_32_RCR_MSUBS_U_32 = 0x04,
949 OPC2_32_RCR_MSUBS_U_64 = 0x06,
950};
951/*
952 * RCRW Format
953 */
954/* OPCM_32_RCRW_MASK_INSERT */
955enum {
956 OPC2_32_RCRW_IMASK = 0x01,
957 OPC2_32_RCRW_INSERT = 0x00,
958};
959
960/*
961 * RR Format
962 */
963/* OPCM_32_RR_LOGICAL_SHIFT */
964enum {
965 OPC2_32_RR_AND = 0x08,
966 OPC2_32_RR_ANDN = 0x0e,
967 OPC2_32_RR_CLO = 0x1c,
968 OPC2_32_RR_CLO_H = 0x7d,
969 OPC2_32_RR_CLS = 0x1d,
970 OPC2_32_RR_CLS_H = 0x7e,
971 OPC2_32_RR_CLZ = 0x1b,
972 OPC2_32_RR_CLZ_H = 0x7c,
973 OPC2_32_RR_NAND = 0x09,
974 OPC2_32_RR_NOR = 0x0b,
975 OPC2_32_RR_OR = 0x0a,
976 OPC2_32_RR_ORN = 0x0f,
977 OPC2_32_RR_SH = 0x00,
978 OPC2_32_RR_SH_H = 0x40,
979 OPC2_32_RR_SHA = 0x01,
980 OPC2_32_RR_SHA_H = 0x41,
981 OPC2_32_RR_SHAS = 0x02,
982 OPC2_32_RR_XNOR = 0x0d,
983 OPC2_32_RR_XOR = 0x0c,
984};
985/* OPCM_32_RR_ACCUMULATOR */
986enum {
987 OPC2_32_RR_ABS = 0x1c,
988 OPC2_32_RR_ABS_B = 0x5c,
989 OPC2_32_RR_ABS_H = 0x7c,
990 OPC2_32_RR_ABSDIF = 0x0e,
991 OPC2_32_RR_ABSDIF_B = 0x4e,
992 OPC2_32_RR_ABSDIF_H = 0x6e,
993 OPC2_32_RR_ABSDIFS = 0x0f,
994 OPC2_32_RR_ABSDIFS_H = 0x6f,
995 OPC2_32_RR_ABSS = 0x1d,
996 OPC2_32_RR_ABSS_H = 0x7d,
997 OPC2_32_RR_ADD = 0x00,
998 OPC2_32_RR_ADD_B = 0x40,
999 OPC2_32_RR_ADD_H = 0x60,
1000 OPC2_32_RR_ADDC = 0x05,
1001 OPC2_32_RR_ADDS = 0x02,
1002 OPC2_32_RR_ADDS_H = 0x62,
1003 OPC2_32_RR_ADDS_HU = 0x63,
1004 OPC2_32_RR_ADDS_U = 0x03,
1005 OPC2_32_RR_ADDX = 0x04,
1006 OPC2_32_RR_AND_EQ = 0x20,
1007 OPC2_32_RR_AND_GE = 0x24,
1008 OPC2_32_RR_AND_GE_U = 0x25,
1009 OPC2_32_RR_AND_LT = 0x22,
1010 OPC2_32_RR_AND_LT_U = 0x23,
1011 OPC2_32_RR_AND_NE = 0x21,
1012 OPC2_32_RR_EQ = 0x10,
1013 OPC2_32_RR_EQ_B = 0x50,
1014 OPC2_32_RR_EQ_H = 0x70,
1015 OPC2_32_RR_EQ_W = 0x90,
1016 OPC2_32_RR_EQANY_B = 0x56,
1017 OPC2_32_RR_EQANY_H = 0x76,
1018 OPC2_32_RR_GE = 0x14,
1019 OPC2_32_RR_GE_U = 0x15,
1020 OPC2_32_RR_LT = 0x12,
1021 OPC2_32_RR_LT_U = 0x13,
1022 OPC2_32_RR_LT_B = 0x52,
1023 OPC2_32_RR_LT_BU = 0x53,
1024 OPC2_32_RR_LT_H = 0x72,
1025 OPC2_32_RR_LT_HU = 0x73,
1026 OPC2_32_RR_LT_W = 0x92,
1027 OPC2_32_RR_LT_WU = 0x93,
1028 OPC2_32_RR_MAX = 0x1a,
1029 OPC2_32_RR_MAX_U = 0x1b,
1030 OPC2_32_RR_MAX_B = 0x5a,
1031 OPC2_32_RR_MAX_BU = 0x5b,
1032 OPC2_32_RR_MAX_H = 0x7a,
1033 OPC2_32_RR_MAX_HU = 0x7b,
1034 OPC2_32_RR_MIN = 0x19,
1035 OPC2_32_RR_MIN_U = 0x18,
1036 OPC2_32_RR_MIN_B = 0x58,
1037 OPC2_32_RR_MIN_BU = 0x59,
1038 OPC2_32_RR_MIN_H = 0x78,
1039 OPC2_32_RR_MIN_HU = 0x79,
1040 OPC2_32_RR_MOV = 0x1f,
1041 OPC2_32_RR_NE = 0x11,
1042 OPC2_32_RR_OR_EQ = 0x27,
1043 OPC2_32_RR_OR_GE = 0x2b,
1044 OPC2_32_RR_OR_GE_U = 0x2c,
1045 OPC2_32_RR_OR_LT = 0x29,
1046 OPC2_32_RR_OR_LT_U = 0x2a,
1047 OPC2_32_RR_OR_NE = 0x28,
1048 OPC2_32_RR_SAT_B = 0x5e,
1049 OPC2_32_RR_SAT_BU = 0x5f,
1050 OPC2_32_RR_SAT_H = 0x7e,
1051 OPC2_32_RR_SAT_HU = 0x7f,
1052 OPC2_32_RR_SH_EQ = 0x37,
1053 OPC2_32_RR_SH_GE = 0x3b,
1054 OPC2_32_RR_SH_GE_U = 0x3c,
1055 OPC2_32_RR_SH_LT = 0x39,
1056 OPC2_32_RR_SH_LT_U = 0x3a,
1057 OPC2_32_RR_SH_NE = 0x38,
1058 OPC2_32_RR_SUB = 0x08,
1059 OPC2_32_RR_SUB_B = 0x48,
1060 OPC2_32_RR_SUB_H = 0x68,
1061 OPC2_32_RR_SUBC = 0x0d,
1062 OPC2_32_RR_SUBS = 0x0a,
1063 OPC2_32_RR_SUBS_U = 0x0b,
1064 OPC2_32_RR_SUBS_H = 0x6a,
1065 OPC2_32_RR_SUBS_HU = 0x6b,
1066 OPC2_32_RR_SUBX = 0x0c,
1067 OPC2_32_RR_XOR_EQ = 0x2f,
1068 OPC2_32_RR_XOR_GE = 0x33,
1069 OPC2_32_RR_XOR_GE_U = 0x34,
1070 OPC2_32_RR_XOR_LT = 0x31,
1071 OPC2_32_RR_XOR_LT_U = 0x32,
1072 OPC2_32_RR_XOR_NE = 0x30,
1073};
1074/* OPCM_32_RR_ADRESS */
1075enum {
1076 OPC2_32_RR_ADD_A = 0x01,
1077 OPC2_32_RR_ADDSC_A = 0x60,
1078 OPC2_32_RR_ADDSC_AT = 0x62,
1079 OPC2_32_RR_EQ_A = 0x40,
1080 OPC2_32_RR_EQZ = 0x48,
1081 OPC2_32_RR_GE_A = 0x43,
1082 OPC2_32_RR_LT_A = 0x42,
1083 OPC2_32_RR_MOV_A = 0x63,
1084 OPC2_32_RR_MOV_AA = 0x00,
1085 OPC2_32_RR_MOV_D = 0x4c,
1086 OPC2_32_RR_NE_A = 0x41,
1087 OPC2_32_RR_NEZ_A = 0x49,
1088 OPC2_32_RR_SUB_A = 0x02,
1089};
1090/* OPCM_32_RR_FLOAT */
1091enum {
1092 OPC2_32_RR_BMERGE = 0x01,
1093 OPC2_32_RR_BSPLIT = 0x09,
1094 OPC2_32_RR_DVINIT_B = 0x5a,
1095 OPC2_32_RR_DVINIT_BU = 0x4a,
1096 OPC2_32_RR_DVINIT_H = 0x3a,
1097 OPC2_32_RR_DVINIT_HU = 0x2a,
1098 OPC2_32_RR_DVINIT = 0x1a,
1099 OPC2_32_RR_DVINIT_U = 0x0a,
1100 OPC2_32_RR_PARITY = 0x02,
1101 OPC2_32_RR_UNPACK = 0x08,
1102};
1103/* OPCM_32_RR_IDIRECT */
1104enum {
1105 OPC2_32_RR_JI = 0x03,
1106 OPC2_32_RR_JLI = 0x02,
1107 OPC2_32_RR_CALLI = 0x00,
1108};
1109/*
1110 * RR1 Format
1111 */
1112/* OPCM_32_RR1_MUL */
1113enum {
1114 OPC2_32_RR1_MUL_H_32_LL = 0x1a,
1115 OPC2_32_RR1_MUL_H_32_LU = 0x19,
1116 OPC2_32_RR1_MUL_H_32_UL = 0x18,
1117 OPC2_32_RR1_MUL_H_32_UU = 0x1b,
1118 OPC2_32_RR1_MULM_H_64_LL = 0x1e,
1119 OPC2_32_RR1_MULM_H_64_LU = 0x1d,
1120 OPC2_32_RR1_MULM_H_64_UL = 0x1c,
1121 OPC2_32_RR1_MULM_H_64_UU = 0x1f,
1122 OPC2_32_RR1_MULR_H_16_LL = 0x0e,
1123 OPC2_32_RR1_MULR_H_16_LU = 0x0d,
1124 OPC2_32_RR1_MULR_H_16_UL = 0x0c,
1125 OPC2_32_RR1_MULR_H_16_UU = 0x0f,
1126};
1127/* OPCM_32_RR1_MULQ */
1128enum {
1129 OPC2_32_RR1_MUL_Q_32 = 0x02,
1130 OPC2_32_RR1_MUL_Q_64 = 0x1b,
1131 OPC2_32_RR1_MUL_Q_32_L = 0x01,
1132 OPC2_32_RR1_MUL_Q_64_L = 0x19,
1133 OPC2_32_RR1_MUL_Q_32_U = 0x00,
1134 OPC2_32_RR1_MUL_Q_64_U = 0x18,
1135 OPC2_32_RR1_MUL_Q_32_LL = 0x05,
1136 OPC2_32_RR1_MUL_Q_32_UU = 0x04,
1137 OPC2_32_RR1_MULR_Q_32_L = 0x07,
1138 OPC2_32_RR1_MULR_Q_32_U = 0x06,
1139};
1140/*
1141 * RR2 Format
1142 */
1143/* OPCM_32_RR2_MUL */
1144enum {
1145 OPC2_32_RR2_MUL_32 = 0x0a,
1146 OPC2_32_RR2_MUL_64 = 0x6a,
1147 OPC2_32_RR2_MULS_32 = 0x8a,
1148 OPC2_32_RR2_MUL_U_64 = 0x68,
1149 OPC2_32_RR2_MULS_U_32 = 0x88,
1150};
1151/*
1152 * RRPW Format
1153 */
1154/* OPCM_32_RRPW_EXTRACT_INSERT */
1155enum {
1156
1157 OPC2_32_RRPW_EXTR = 0x02,
1158 OPC2_32_RRPW_EXTR_U = 0x03,
1159 OPC2_32_RRPW_IMASK = 0x01,
1160 OPC2_32_RRPW_INSERT = 0x00,
1161};
1162/*
1163 * RRR Format
1164 */
1165/* OPCM_32_RRR_COND_SELECT */
1166enum {
1167 OPC2_32_RRR_CADD = 0x00,
1168 OPC2_32_RRR_CADDN = 0x01,
1169 OPC2_32_RRR_CSUB = 0x02,
1170 OPC2_32_RRR_CSUBN = 0x03,
1171 OPC2_32_RRR_SEL = 0x04,
1172 OPC2_32_RRR_SELN = 0x05,
1173};
1174/* OPCM_32_RRR_FLOAT */
1175enum {
1176 OPC2_32_RRR_DVADJ = 0x0d,
1177 OPC2_32_RRR_DVSTEP = 0x0f,
1178 OPC2_32_RRR_DVSTEP_U = 0x0e,
1179 OPC2_32_RRR_IXMAX = 0x0a,
1180 OPC2_32_RRR_IXMAX_U = 0x0b,
1181 OPC2_32_RRR_IXMIN = 0x08,
1182 OPC2_32_RRR_IXMIN_U = 0x09,
1183 OPC2_32_RRR_PACK = 0x00,
1184};
1185/*
1186 * RRR1 Format
1187 */
1188/* OPCM_32_RRR1_MADD */
1189enum {
1190 OPC2_32_RRR1_MADD_H_LL = 0x1a,
1191 OPC2_32_RRR1_MADD_H_LU = 0x19,
1192 OPC2_32_RRR1_MADD_H_UL = 0x18,
1193 OPC2_32_RRR1_MADD_H_UU = 0x1b,
1194 OPC2_32_RRR1_MADDS_H_LL = 0x3a,
1195 OPC2_32_RRR1_MADDS_H_LU = 0x39,
1196 OPC2_32_RRR1_MADDS_H_UL = 0x38,
1197 OPC2_32_RRR1_MADDS_H_UU = 0x3b,
1198 OPC2_32_RRR1_MADDM_H_LL = 0x1e,
1199 OPC2_32_RRR1_MADDM_H_LU = 0x1d,
1200 OPC2_32_RRR1_MADDM_H_UL = 0x1c,
1201 OPC2_32_RRR1_MADDM_H_UU = 0x1f,
1202 OPC2_32_RRR1_MADDMS_H_LL = 0x3e,
1203 OPC2_32_RRR1_MADDMS_H_LU = 0x3d,
1204 OPC2_32_RRR1_MADDMS_H_UL = 0x3c,
1205 OPC2_32_RRR1_MADDMS_H_UU = 0x3f,
1206 OPC2_32_RRR1_MADDR_H_LL = 0x0e,
1207 OPC2_32_RRR1_MADDR_H_LU = 0x0d,
1208 OPC2_32_RRR1_MADDR_H_UL = 0x0c,
1209 OPC2_32_RRR1_MADDR_H_UU = 0x0f,
1210 OPC2_32_RRR1_MADDRS_H_LL = 0x2e,
1211 OPC2_32_RRR1_MADDRS_H_LU = 0x2d,
1212 OPC2_32_RRR1_MADDRS_H_UL = 0x2c,
1213 OPC2_32_RRR1_MADDRS_H_UU = 0x2f,
1214};
1215/* OPCM_32_RRR1_MADDQ_H */
1216enum {
1217 OPC2_32_RRR1_MADD_Q_32 = 0x02,
1218 OPC2_32_RRR1_MADD_Q_64 = 0x1b,
1219 OPC2_32_RRR1_MADD_Q_32_L = 0x01,
1220 OPC2_32_RRR1_MADD_Q_64_L = 0x19,
1221 OPC2_32_RRR1_MADD_Q_32_U = 0x00,
1222 OPC2_32_RRR1_MADD_Q_64_U = 0x18,
1223 OPC2_32_RRR1_MADD_Q_32_LL = 0x05,
1224 OPC2_32_RRR1_MADD_Q_64_LL = 0x1d,
1225 OPC2_32_RRR1_MADD_Q_32_UU = 0x04,
1226 OPC2_32_RRR1_MADD_Q_64_UU = 0x1c,
1227 OPC2_32_RRR1_MADDS_Q_32 = 0x22,
1228 OPC2_32_RRR1_MADDS_Q_64 = 0x3b,
1229 OPC2_32_RRR1_MADDS_Q_32_L = 0x21,
1230 OPC2_32_RRR1_MADDS_Q_64_L = 0x39,
1231 OPC2_32_RRR1_MADDS_Q_32_U = 0x20,
1232 OPC2_32_RRR1_MADDS_Q_64_U = 0x38,
1233 OPC2_32_RRR1_MADDS_Q_32_LL = 0x25,
1234 OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
1235 OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
1236 OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
1237 OPC2_32_RRR1_MADDR_H_16_UL = 0x1e,
1238 OPC2_32_RRR1_MADDRS_H_16_UL = 0x3e,
1239 OPC2_32_RRR1_MADDR_Q_32_L = 0x07,
1240 OPC2_32_RRR1_MADDR_Q_32_U = 0x06,
1241 OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
1242 OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
1243};
1244/* OPCM_32_RRR1_MADDSU_H */
1245enum {
1246 OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a,
1247 OPC2_32_RRR1_MADDSU_H_32_LU = 0x19,
1248 OPC2_32_RRR1_MADDSU_H_32_UL = 0x18,
1249 OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b,
1250 OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a,
1251 OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39,
1252 OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38,
1253 OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b,
1254 OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e,
1255 OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d,
1256 OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c,
1257 OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f,
1258 OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e,
1259 OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d,
1260 OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c,
1261 OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f,
1262 OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e,
1263 OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d,
1264 OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c,
1265 OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f,
1266 OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e,
1267 OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d,
1268 OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c,
1269 OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f,
1270};
1271/* OPCM_32_RRR1_MSUB_H */
1272enum {
1273 OPC2_32_RRR1_MSUB_H_32_LL = 0x1a,
1274 OPC2_32_RRR1_MSUB_H_32_LU = 0x19,
1275 OPC2_32_RRR1_MSUB_H_32_UL = 0x18,
1276 OPC2_32_RRR1_MSUB_H_32_UU = 0x1b,
1277 OPC2_32_RRR1_MSUBS_H_32_LL = 0x3a,
1278 OPC2_32_RRR1_MSUBS_H_32_LU = 0x39,
1279 OPC2_32_RRR1_MSUBS_H_32_UL = 0x38,
1280 OPC2_32_RRR1_MSUBS_H_32_UU = 0x3b,
1281 OPC2_32_RRR1_MSUBM_H_64_LL = 0x1e,
1282 OPC2_32_RRR1_MSUBM_H_64_LU = 0x1d,
1283 OPC2_32_RRR1_MSUBM_H_64_UL = 0x1c,
1284 OPC2_32_RRR1_MSUBM_H_64_UU = 0x1f,
1285 OPC2_32_RRR1_MSUBMS_H_64_LL = 0x3e,
1286 OPC2_32_RRR1_MSUBMS_H_64_LU = 0x3d,
1287 OPC2_32_RRR1_MSUBMS_H_64_UL = 0x3c,
1288 OPC2_32_RRR1_MSUBMS_H_64_UU = 0x3f,
1289 OPC2_32_RRR1_MSUBR_H_16_LL = 0x0e,
1290 OPC2_32_RRR1_MSUBR_H_16_LU = 0x0d,
1291 OPC2_32_RRR1_MSUBR_H_16_UL = 0x0c,
1292 OPC2_32_RRR1_MSUBR_H_16_UU = 0x0f,
1293 OPC2_32_RRR1_MSUBRS_H_16_LL = 0x2e,
1294 OPC2_32_RRR1_MSUBRS_H_16_LU = 0x2d,
1295 OPC2_32_RRR1_MSUBRS_H_16_UL = 0x2c,
1296 OPC2_32_RRR1_MSUBRS_H_16_UU = 0x2f,
1297};
1298/* OPCM_32_RRR1_MSUB_Q */
1299enum {
1300 OPC2_32_RRR1_MSUB_Q_32 = 0x02,
1301 OPC2_32_RRR1_MSUB_Q_64 = 0x1b,
1302 OPC2_32_RRR1_MSUB_Q_32_L = 0x01,
1303 OPC2_32_RRR1_MSUB_Q_64_L = 0x19,
1304 OPC2_32_RRR1_MSUB_Q_32_U = 0x00,
1305 OPC2_32_RRR1_MSUB_Q_64_U = 0x18,
1306 OPC2_32_RRR1_MSUB_Q_32_LL = 0x05,
1307 OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d,
1308 OPC2_32_RRR1_MSUB_Q_32_UU = 0x04,
1309 OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c,
1310 OPC2_32_RRR1_MSUBS_Q_32 = 0x22,
1311 OPC2_32_RRR1_MSUBS_Q_64 = 0x3b,
1312 OPC2_32_RRR1_MSUBS_Q_32_L = 0x21,
1313 OPC2_32_RRR1_MSUBS_Q_64_L = 0x39,
1314 OPC2_32_RRR1_MSUBS_Q_32_U = 0x20,
1315 OPC2_32_RRR1_MSUBS_Q_64_U = 0x38,
1316 OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25,
1317 OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d,
1318 OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24,
1319 OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c,
1320 OPC2_32_RRR1_MSUBR_H_32_UL = 0x1e,
1321 OPC2_32_RRR1_MSUBRS_H_32_UL = 0x3e,
1322 OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07,
1323 OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06,
1324 OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27,
1325 OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26,
1326};
1327/* OPCM_32_RRR1_MSUBADS_H */
1328enum {
1329 OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a,
1330 OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19,
1331 OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18,
1332 OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b,
1333 OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a,
1334 OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39,
1335 OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38,
1336 OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b,
1337 OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e,
1338 OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d,
1339 OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c,
1340 OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f,
1341 OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e,
1342 OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d,
1343 OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c,
1344 OPC2_32_RRR1_MSUBADMS_H_16_UU = 0x3f,
1345 OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e,
1346 OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d,
1347 OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c,
1348 OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f,
1349 OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e,
1350 OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d,
1351 OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c,
1352 OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f,
1353};
1354/*
1355 * RRR2 Format
1356 */
1357/* OPCM_32_RRR2_MADD */
1358enum {
1359 OPC2_32_RRR2_MADD_32 = 0x0a,
1360 OPC2_32_RRR2_MADD_64 = 0x6a,
1361 OPC2_32_RRR2_MADDS_32 = 0x8a,
1362 OPC2_32_RRR2_MADDS_64 = 0xea,
1363 OPC2_32_RRR2_MADD_U_32 = 0x68,
1364 OPC2_32_RRR2_MADDS_U_32 = 0x88,
1365 OPC2_32_RRR2_MADDS_U_64 = 0xe8,
1366};
1367/* OPCM_32_RRR2_MSUB */
1368enum {
1369 OPC2_32_RRR2_MSUB_32 = 0x0a,
1370 OPC2_32_RRR2_MSUB_64 = 0x6a,
1371 OPC2_32_RRR2_MSUBS_32 = 0x8a,
1372 OPC2_32_RRR2_MSUBS_64 = 0xea,
1373 OPC2_32_RRR2_MSUB_U_64 = 0x68,
1374 OPC2_32_RRR2_MSUBS_U_32 = 0x88,
1375 OPC2_32_RRR2_MSUBS_U_64 = 0xe8,
1376};
1377/*
1378 * RRRR Format
1379 */
1380/* OPCM_32_RRRR_EXTRACT_INSERT */
1381enum {
1382 OPC2_32_RRRR_DEXTR = 0x04,
1383 OPC2_32_RRRR_EXTR = 0x02,
1384 OPC2_32_RRRR_EXTR_U = 0x03,
1385 OPC2_32_RRRR_INSERT = 0x00,
1386};
1387/*
1388 * RRRW Format
1389 */
1390/* OPCM_32_RRRW_EXTRACT_INSERT */
1391enum {
1392 OPC2_32_RRRW_EXTR = 0x02,
1393 OPC2_32_RRRW_EXTR_U = 0x03,
1394 OPC2_32_RRRW_IMASK = 0x01,
1395 OPC2_32_RRRW_INSERT = 0x00,
1396};
1397/*
1398 * SYS Format
1399 */
1400/* OPCM_32_SYS_INTERRUPTS */
1401enum {
1402 OPC2_32_SYS_DEBUG = 0x04,
1403 OPC2_32_SYS_DISABLE = 0x0d,
1404 OPC2_32_SYS_DSYNC = 0x12,
1405 OPC2_32_SYS_ENABLE = 0x0c,
1406 OPC2_32_SYS_ISYNC = 0x13,
1407 OPC2_32_SYS_NOP = 0x00,
1408 OPC2_32_SYS_RET = 0x06,
1409 OPC2_32_SYS_RFE = 0x07,
1410 OPC2_32_SYS_RFM = 0x05,
1411 OPC2_32_SYS_RSLCX = 0x09,
1412 OPC2_32_SYS_SVLCX = 0x08,
1413 OPC2_32_SYS_TRAPSV = 0x15,
1414 OPC2_32_SYS_TRAPV = 0x14,
1415};
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