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6e64da3c GX |
1 | /* |
2 | * UniCore32 virtual CPU header | |
3 | * | |
4 | * Copyright (C) 2010-2011 GUAN Xue-tao | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
2b3bc6c0 AF |
8 | * published by the Free Software Foundation, or (at your option) any |
9 | * later version. See the COPYING file in the top-level directory. | |
6e64da3c GX |
10 | */ |
11 | #ifndef __CPU_UC32_H__ | |
12 | #define __CPU_UC32_H__ | |
13 | ||
14 | #define TARGET_LONG_BITS 32 | |
15 | #define TARGET_PAGE_BITS 12 | |
16 | ||
17 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
18 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
19 | ||
20 | #define ELF_MACHINE EM_UNICORE32 | |
21 | ||
9349b4f9 | 22 | #define CPUArchState struct CPUUniCore32State |
6e64da3c | 23 | |
8141905a SW |
24 | #include "config.h" |
25 | #include "qemu-common.h" | |
6e64da3c GX |
26 | #include "cpu-defs.h" |
27 | #include "softfloat.h" | |
28 | ||
29 | #define NB_MMU_MODES 2 | |
30 | ||
15ecee74 | 31 | typedef struct CPUUniCore32State { |
6e64da3c GX |
32 | /* Regs for current mode. */ |
33 | uint32_t regs[32]; | |
34 | /* Frequently accessed ASR bits are stored separately for efficiently. | |
35 | This contains all the other bits. Use asr_{read,write} to access | |
36 | the whole ASR. */ | |
37 | uint32_t uncached_asr; | |
38 | uint32_t bsr; | |
39 | ||
40 | /* Banked registers. */ | |
41 | uint32_t banked_bsr[6]; | |
42 | uint32_t banked_r29[6]; | |
43 | uint32_t banked_r30[6]; | |
44 | ||
45 | /* asr flag cache for faster execution */ | |
46 | uint32_t CF; /* 0 or 1 */ | |
47 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ | |
48 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ | |
49 | uint32_t ZF; /* Z set if zero. */ | |
50 | ||
51 | /* System control coprocessor (cp0) */ | |
52 | struct { | |
53 | uint32_t c0_cpuid; | |
54 | uint32_t c0_cachetype; | |
55 | uint32_t c1_sys; /* System control register. */ | |
56 | uint32_t c2_base; /* MMU translation table base. */ | |
57 | uint32_t c3_faultstatus; /* Fault status registers. */ | |
58 | uint32_t c4_faultaddr; /* Fault address registers. */ | |
59 | uint32_t c5_cacheop; /* Cache operation registers. */ | |
60 | uint32_t c6_tlbop; /* TLB operation registers. */ | |
61 | } cp0; | |
62 | ||
63 | /* UniCore-F64 coprocessor state. */ | |
64 | struct { | |
65 | float64 regs[16]; | |
66 | uint32_t xregs[32]; | |
67 | float_status fp_status; | |
68 | } ucf64; | |
69 | ||
70 | CPU_COMMON | |
71 | ||
72 | /* Internal CPU feature flags. */ | |
73 | uint32_t features; | |
74 | ||
15ecee74 | 75 | } CPUUniCore32State; |
6e64da3c GX |
76 | |
77 | #define ASR_M (0x1f) | |
78 | #define ASR_MODE_USER (0x10) | |
79 | #define ASR_MODE_INTR (0x12) | |
80 | #define ASR_MODE_PRIV (0x13) | |
81 | #define ASR_MODE_TRAP (0x17) | |
82 | #define ASR_MODE_EXTN (0x1b) | |
83 | #define ASR_MODE_SUSR (0x1f) | |
84 | #define ASR_I (1 << 7) | |
85 | #define ASR_V (1 << 28) | |
86 | #define ASR_C (1 << 29) | |
87 | #define ASR_Z (1 << 30) | |
88 | #define ASR_N (1 << 31) | |
89 | #define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V) | |
90 | #define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV)) | |
91 | ||
92 | #define UC32_EXCP_PRIV (ASR_MODE_PRIV) | |
93 | #define UC32_EXCP_TRAP (ASR_MODE_TRAP) | |
94 | ||
95 | /* Return the current ASR value. */ | |
eb23b556 | 96 | target_ulong cpu_asr_read(CPUUniCore32State *env1); |
6e64da3c | 97 | /* Set the ASR. Note that some bits of mask must be all-set or all-clear. */ |
eb23b556 | 98 | void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask); |
6e64da3c GX |
99 | |
100 | /* UniCore-F64 system registers. */ | |
101 | #define UC32_UCF64_FPSCR (31) | |
102 | #define UCF64_FPSCR_MASK (0x27ffffff) | |
103 | #define UCF64_FPSCR_RND_MASK (0x7) | |
104 | #define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK) | |
105 | #define UCF64_FPSCR_TRAPEN_MASK (0x7f) | |
106 | #define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK) | |
107 | #define UCF64_FPSCR_FLAG_MASK (0x3ff) | |
108 | #define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK) | |
109 | #define UCF64_FPSCR_FLAG_ZERO (1 << 17) | |
110 | #define UCF64_FPSCR_FLAG_INFINITY (1 << 18) | |
111 | #define UCF64_FPSCR_FLAG_INVALID (1 << 19) | |
112 | #define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20) | |
113 | #define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21) | |
114 | #define UCF64_FPSCR_FLAG_INEXACT (1 << 22) | |
115 | #define UCF64_FPSCR_FLAG_HUGEINT (1 << 23) | |
116 | #define UCF64_FPSCR_FLAG_DENORMAL (1 << 24) | |
117 | #define UCF64_FPSCR_FLAG_UNIMP (1 << 25) | |
118 | #define UCF64_FPSCR_FLAG_DIVZERO (1 << 26) | |
119 | ||
120 | #define UC32_HWCAP_CMOV 4 /* 1 << 2 */ | |
121 | #define UC32_HWCAP_UCF64 8 /* 1 << 3 */ | |
122 | ||
123 | #define UC32_CPUID(env) (env->cp0.c0_cpuid) | |
124 | #define UC32_CPUID_UCV2 0x40010863 | |
125 | #define UC32_CPUID_ANY 0xffffffff | |
126 | ||
127 | #define cpu_init uc32_cpu_init | |
128 | #define cpu_exec uc32_cpu_exec | |
129 | #define cpu_signal_handler uc32_cpu_signal_handler | |
130 | #define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault | |
131 | ||
eb23b556 AF |
132 | CPUUniCore32State *uc32_cpu_init(const char *cpu_model); |
133 | int uc32_cpu_exec(CPUUniCore32State *s); | |
6e64da3c | 134 | int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc); |
eb23b556 | 135 | int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw, |
97b348e7 | 136 | int mmu_idx); |
6e64da3c GX |
137 | |
138 | #define CPU_SAVE_VERSION 2 | |
139 | ||
140 | /* MMU modes definitions */ | |
141 | #define MMU_MODE0_SUFFIX _kernel | |
142 | #define MMU_MODE1_SUFFIX _user | |
143 | #define MMU_USER_IDX 1 | |
eb23b556 | 144 | static inline int cpu_mmu_index(CPUUniCore32State *env) |
6e64da3c GX |
145 | { |
146 | return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0; | |
147 | } | |
148 | ||
eb23b556 | 149 | static inline void cpu_clone_regs(CPUUniCore32State *env, target_ulong newsp) |
6e64da3c GX |
150 | { |
151 | if (newsp) { | |
152 | env->regs[29] = newsp; | |
153 | } | |
154 | env->regs[0] = 0; | |
155 | } | |
156 | ||
eb23b556 | 157 | static inline void cpu_set_tls(CPUUniCore32State *env, target_ulong newtls) |
6e64da3c GX |
158 | { |
159 | env->regs[16] = newtls; | |
160 | } | |
161 | ||
162 | #include "cpu-all.h" | |
ae0f5e9e | 163 | #include "cpu-qom.h" |
6e64da3c GX |
164 | #include "exec-all.h" |
165 | ||
eb23b556 | 166 | static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb) |
6e64da3c GX |
167 | { |
168 | env->regs[31] = tb->pc; | |
169 | } | |
170 | ||
eb23b556 | 171 | static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc, |
6e64da3c GX |
172 | target_ulong *cs_base, int *flags) |
173 | { | |
174 | *pc = env->regs[31]; | |
175 | *cs_base = 0; | |
176 | *flags = 0; | |
177 | if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) { | |
178 | *flags |= (1 << 6); | |
179 | } | |
180 | } | |
181 | ||
182 | void uc32_translate_init(void); | |
eb23b556 | 183 | void do_interrupt(CPUUniCore32State *); |
15ecee74 | 184 | void switch_mode(CPUUniCore32State *, int); |
6e64da3c | 185 | |
eb23b556 | 186 | static inline bool cpu_has_work(CPUUniCore32State *env) |
f081c76c BS |
187 | { |
188 | return env->interrupt_request & | |
189 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); | |
190 | } | |
191 | ||
6e64da3c | 192 | #endif /* __CPU_UC32_H__ */ |