[mirror_qemu.git] / target-unicore32 / helper.c

/*
 * Copyright (C) 2010-2012 Guan Xuetao
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Contributions from 2012-04-01 on are considered under GPL version 2,
 * or (at your option) any later version.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/gdbstub.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#ifndef CONFIG_USER_ONLY
#include "ui/console.h"
#endif

#undef DEBUG_UC32

#ifdef DEBUG_UC32
#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif

UniCore32CPU *uc32_cpu_init(const char *cpu_model)
{
    return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
}

uint32_t HELPER(clo)(uint32_t x)
{
    return clo32(x);
}

uint32_t HELPER(clz)(uint32_t x)
{
    return clz32(x);
}

#ifndef CONFIG_USER_ONLY
void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
        uint32_t cop)
{
    UniCore32CPU *cpu = uc32_env_get_cpu(env);

    /*
     * movc pp.nn, rn, #imm9
     *      rn: UCOP_REG_D
     *      nn: UCOP_REG_N
     *          1: sys control reg.
     *          2: page table base reg.
     *          3: data fault status reg.
     *          4: insn fault status reg.
     *          5: cache op. reg.
     *          6: tlb op. reg.
     *      imm9: split UCOP_IMM10 with bit5 is 0
     */
    switch (creg) {
    case 1:
        if (cop != 0) {
            goto unrecognized;
        }
        env->cp0.c1_sys = val;
        break;
    case 2:
        if (cop != 0) {
            goto unrecognized;
        }
        env->cp0.c2_base = val;
        break;
    case 3:
        if (cop != 0) {
            goto unrecognized;
        }
        env->cp0.c3_faultstatus = val;
        break;
    case 4:
        if (cop != 0) {
            goto unrecognized;
        }
        env->cp0.c4_faultaddr = val;
        break;
    case 5:
        switch (cop) {
        case 28:
            DPRINTF("Invalidate Entire I&D cache\n");
            return;
        case 20:
            DPRINTF("Invalidate Entire Icache\n");
            return;
        case 12:
            DPRINTF("Invalidate Entire Dcache\n");
            return;
        case 10:
            DPRINTF("Clean Entire Dcache\n");
            return;
        case 14:
            DPRINTF("Flush Entire Dcache\n");
            return;
        case 13:
            DPRINTF("Invalidate Dcache line\n");
            return;
        case 11:
            DPRINTF("Clean Dcache line\n");
            return;
        case 15:
            DPRINTF("Flush Dcache line\n");
            return;
        }
        break;
    case 6:
        if ((cop <= 6) && (cop >= 2)) {
            /* invalid all tlb */
            tlb_flush(CPU(cpu), 1);
            return;
        }
        break;
    default:
        goto unrecognized;
    }
    return;
unrecognized:
    DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
            creg, cop);
}

uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
{
    /*
     * movc rd, pp.nn, #imm9
     *      rd: UCOP_REG_D
     *      nn: UCOP_REG_N
     *          0: cpuid and cachetype
     *          1: sys control reg.
     *          2: page table base reg.
     *          3: data fault status reg.
     *          4: insn fault status reg.
     *      imm9: split UCOP_IMM10 with bit5 is 0
     */
    switch (creg) {
    case 0:
        switch (cop) {
        case 0:
            return env->cp0.c0_cpuid;
        case 1:
            return env->cp0.c0_cachetype;
        }
        break;
    case 1:
        if (cop == 0) {
            return env->cp0.c1_sys;
        }
        break;
    case 2:
        if (cop == 0) {
            return env->cp0.c2_base;
        }
        break;
    case 3:
        if (cop == 0) {
            return env->cp0.c3_faultstatus;
        }
        break;
    case 4:
        if (cop == 0) {
            return env->cp0.c4_faultaddr;
        }
        break;
    }
    DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
            creg, cop);
    return 0;
}

#ifdef CONFIG_CURSES
/*
 * FIXME:
 *     1. curses windows will be blank when switching back
 *     2. backspace is not handled yet
 */
static void putc_on_screen(unsigned char ch)
{
    static WINDOW *localwin;
    static int init;

    if (!init) {
        /* Assume 80 * 30 screen to minimize the implementation */
        localwin = newwin(30, 80, 0, 0);
        scrollok(localwin, TRUE);
        init = TRUE;
    }

    if (isprint(ch)) {
        wprintw(localwin, "%c", ch);
    } else {
        switch (ch) {
        case '\n':
            wprintw(localwin, "%c", ch);
            break;
        case '\r':
            /* If '\r' is put before '\n', the curses window will destroy the
             * last print line. And meanwhile, '\n' implifies '\r' inside. */
            break;
        default: /* Not handled, so just print it hex code */
            wprintw(localwin, "-- 0x%x --", ch);
        }
    }

    wrefresh(localwin);
}
#else
#define putc_on_screen(c)               do { } while (0)
#endif

void helper_cp1_putc(target_ulong x)
{
    putc_on_screen((unsigned char)x);   /* Output to screen */
    DPRINTF("%c", x);                   /* Output to stdout */
}
#endif

#ifdef CONFIG_USER_ONLY
void switch_mode(CPUUniCore32State *env, int mode)
{
    UniCore32CPU *cpu = uc32_env_get_cpu(env);

    if (mode != ASR_MODE_USER) {
        cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
    }
}

void uc32_cpu_do_interrupt(CPUState *cs)
{
    cpu_abort(cs, "NO interrupt in user mode\n");
}

int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
                              int access_type, int mmu_idx)
{
    cpu_abort(cs, "NO mmu fault in user mode\n");
    return 1;
}
#endif

bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
    if (interrupt_request & CPU_INTERRUPT_HARD) {
        UniCore32CPU *cpu = UNICORE32_CPU(cs);
        CPUUniCore32State *env = &cpu->env;

        if (!(env->uncached_asr & ASR_I)) {
            cs->exception_index = UC32_EXCP_INTR;
            uc32_cpu_do_interrupt(cs);
            return true;
        }
    }
    return false;
}
Commit	Line	Data
6e64da3c	1	/*
4f23a1e6	2	* Copyright (C) 2010-2012 Guan Xuetao
6e64da3c GX	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
c3a8baa9 AF	7	*
	8	* Contributions from 2012-04-01 on are considered under GPL version 2,
	9	* or (at your option) any later version.
6e64da3c	10	*/
6e64da3c	11
5af98cc5	12	#include "qemu/osdep.h"
6e64da3c	13	#include "cpu.h"
63c91552	14	#include "exec/exec-all.h"
022c62cb	15	#include "exec/gdbstub.h"
2ef6175a	16	#include "exec/helper-proto.h"
1de7afc9	17	#include "qemu/host-utils.h"
74880fe2	18	#ifndef CONFIG_USER_ONLY
28ecbaee	19	#include "ui/console.h"
74880fe2	20	#endif
6e64da3c	21
527d9979 GX	22	#undef DEBUG_UC32
	23
	24	#ifdef DEBUG_UC32
	25	#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
	26	#else
	27	#define DPRINTF(fmt, ...) do {} while (0)
	28	#endif
	29
41979669	30	UniCore32CPU uc32_cpu_init(const char cpu_model)
6e64da3c	31	{
41979669	32	return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
6e64da3c GX	33	}
	34
	35	uint32_t HELPER(clo)(uint32_t x)
	36	{
	37	return clo32(x);
	38	}
	39
	40	uint32_t HELPER(clz)(uint32_t x)
	41	{
	42	return clz32(x);
	43	}
	44
527d9979 GX	45	#ifndef CONFIG_USER_ONLY
	46	void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
	47	uint32_t cop)
4f23a1e6	48	{
00c8cb0a AF	49	UniCore32CPU *cpu = uc32_env_get_cpu(env);
00c8cb0a AF	50
527d9979 GX	51	/*
	52	* movc pp.nn, rn, #imm9
	53	* rn: UCOP_REG_D
	54	* nn: UCOP_REG_N
	55	* 1: sys control reg.
	56	* 2: page table base reg.
	57	* 3: data fault status reg.
	58	* 4: insn fault status reg.
	59	* 5: cache op. reg.
	60	* 6: tlb op. reg.
	61	* imm9: split UCOP_IMM10 with bit5 is 0
	62	*/
	63	switch (creg) {
	64	case 1:
	65	if (cop != 0) {
	66	goto unrecognized;
	67	}
	68	env->cp0.c1_sys = val;
	69	break;
	70	case 2:
	71	if (cop != 0) {
	72	goto unrecognized;
	73	}
	74	env->cp0.c2_base = val;
	75	break;
	76	case 3:
	77	if (cop != 0) {
	78	goto unrecognized;
	79	}
	80	env->cp0.c3_faultstatus = val;
	81	break;
	82	case 4:
	83	if (cop != 0) {
	84	goto unrecognized;
	85	}
	86	env->cp0.c4_faultaddr = val;
	87	break;
	88	case 5:
	89	switch (cop) {
	90	case 28:
	91	DPRINTF("Invalidate Entire I&D cache\n");
	92	return;
	93	case 20:
	94	DPRINTF("Invalidate Entire Icache\n");
	95	return;
	96	case 12:
	97	DPRINTF("Invalidate Entire Dcache\n");
	98	return;
	99	case 10:
	100	DPRINTF("Clean Entire Dcache\n");
	101	return;
	102	case 14:
	103	DPRINTF("Flush Entire Dcache\n");
	104	return;
	105	case 13:
	106	DPRINTF("Invalidate Dcache line\n");
	107	return;
	108	case 11:
	109	DPRINTF("Clean Dcache line\n");
	110	return;
	111	case 15:
	112	DPRINTF("Flush Dcache line\n");
	113	return;
	114	}
115	break;
116	case 6:
117	if ((cop <= 6) && (cop >= 2)) {
118	/* invalid all tlb */
00c8cb0a	119	tlb_flush(CPU(cpu), 1);
527d9979 GX	120	return;
	121	}
	122	break;
	123	default:
	124	goto unrecognized;
4f23a1e6	125	}
6e64da3c	126	return;
527d9979 GX	127	unrecognized:
	128	DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
	129	creg, cop);
6e64da3c GX	130	}
6e64da3c GX	131
527d9979	132	uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
6e64da3c	133	{
527d9979 GX	134	/*
	135	* movc rd, pp.nn, #imm9
	136	* rd: UCOP_REG_D
	137	* nn: UCOP_REG_N
	138	* 0: cpuid and cachetype
	139	* 1: sys control reg.
	140	* 2: page table base reg.
	141	* 3: data fault status reg.
	142	* 4: insn fault status reg.
	143	* imm9: split UCOP_IMM10 with bit5 is 0
	144	*/
	145	switch (creg) {
	146	case 0:
	147	switch (cop) {
	148	case 0:
	149	return env->cp0.c0_cpuid;
	150	case 1:
	151	return env->cp0.c0_cachetype;
	152	}
	153	break;
	154	case 1:
	155	if (cop == 0) {
	156	return env->cp0.c1_sys;
	157	}
	158	break;
	159	case 2:
	160	if (cop == 0) {
	161	return env->cp0.c2_base;
	162	}
	163	break;
	164	case 3:
	165	if (cop == 0) {
	166	return env->cp0.c3_faultstatus;
	167	}
	168	break;
	169	case 4:
	170	if (cop == 0) {
	171	return env->cp0.c4_faultaddr;
	172	}
	173	break;
	174	}
	175	DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
	176	creg, cop);
6e64da3c GX	177	return 0;
	178	}
	179
ff5928d0 GX	180	#ifdef CONFIG_CURSES
	181	/*
	182	* FIXME:
	183	* 1. curses windows will be blank when switching back
	184	* 2. backspace is not handled yet
	185	*/
	186	static void putc_on_screen(unsigned char ch)
	187	{
	188	static WINDOW *localwin;
	189	static int init;
	190
	191	if (!init) {
	192	/* Assume 80 * 30 screen to minimize the implementation */
	193	localwin = newwin(30, 80, 0, 0);
	194	scrollok(localwin, TRUE);
	195	init = TRUE;
	196	}
	197
	198	if (isprint(ch)) {
	199	wprintw(localwin, "%c", ch);
	200	} else {
	201	switch (ch) {
	202	case '\n':
	203	wprintw(localwin, "%c", ch);
	204	break;
	205	case '\r':
	206	/* If '\r' is put before '\n', the curses window will destroy the
	207	* last print line. And meanwhile, '\n' implifies '\r' inside. */
	208	break;
	209	default: /* Not handled, so just print it hex code */
	210	wprintw(localwin, "-- 0x%x --", ch);
	211	}
	212	}
	213
	214	wrefresh(localwin);
	215	}
	216	#else
	217	#define putc_on_screen(c) do { } while (0)
	218	#endif
	219
527d9979	220	void helper_cp1_putc(target_ulong x)
6e64da3c	221	{
ff5928d0 GX	222	putc_on_screen((unsigned char)x); /* Output to screen */
ff5928d0 GX	223	DPRINTF("%c", x); /* Output to stdout */
6e64da3c	224	}
527d9979	225	#endif
6e64da3c	226
527d9979 GX	227	#ifdef CONFIG_USER_ONLY
527d9979 GX	228	void switch_mode(CPUUniCore32State *env, int mode)
6e64da3c	229	{
a47dddd7 AF	230	UniCore32CPU *cpu = uc32_env_get_cpu(env);
a47dddd7 AF	231
527d9979	232	if (mode != ASR_MODE_USER) {
a47dddd7	233	cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
527d9979	234	}
6e64da3c GX	235	}
6e64da3c GX	236
97a8ea5a	237	void uc32_cpu_do_interrupt(CPUState *cs)
6e64da3c	238	{
a47dddd7	239	cpu_abort(cs, "NO interrupt in user mode\n");
6e64da3c GX	240	}
6e64da3c GX	241
7510454e	242	int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
527d9979	243	int access_type, int mmu_idx)
6e64da3c	244	{
a47dddd7	245	cpu_abort(cs, "NO mmu fault in user mode\n");
527d9979	246	return 1;
6e64da3c	247	}
527d9979	248	#endif
d8bb9159 RH	249
	250	bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
	251	{
	252	if (interrupt_request & CPU_INTERRUPT_HARD) {
	253	UniCore32CPU *cpu = UNICORE32_CPU(cs);
	254	CPUUniCore32State *env = &cpu->env;
	255
	256	if (!(env->uncached_asr & ASR_I)) {
	257	cs->exception_index = UC32_EXCP_INTR;
	258	uc32_cpu_do_interrupt(cs);
	259	return true;
	260	}
	261	}
	262	return false;
	263	}