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softmmu: introduce cpu_ldst.h
[mirror_qemu.git] / target-unicore32 / translate.c
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6e64da3c
GX		 1/*
2 * UniCore32 translation
3 *
527d9979 4 * Copyright (C) 2010-2012 Guan Xuetao
6e64da3c
GX		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
2b3bc6c0
AF		 8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
6e64da3c
GX		 10 */
11#include <stdarg.h>
12#include <stdlib.h>
13#include <stdio.h>
14#include <string.h>
15#include <inttypes.h>
16
17#include "cpu.h"
76cad711 18#include "disas/disas.h"
6e64da3c 19#include "tcg-op.h"
1de7afc9 20#include "qemu/log.h"
f08b6170 21#include "exec/cpu_ldst.h"
6e64da3c 22
2ef6175a
RH		 23#include "exec/helper-proto.h"
24#include "exec/helper-gen.h"
6e64da3c
GX		 25
26/* internal defines */
27typedef struct DisasContext {
28 target_ulong pc;
29 int is_jmp;
30 /* Nonzero if this instruction has been conditionally skipped. */
31 int condjmp;
32 /* The label that will be jumped to when the instruction is skipped. */
33 int condlabel;
34 struct TranslationBlock *tb;
35 int singlestep_enabled;
ef03168a
GX		 36#ifndef CONFIG_USER_ONLY
37 int user;
38#endif
6e64da3c
GX		 39} DisasContext;
40
ef03168a
GX		 41#ifndef CONFIG_USER_ONLY
42#define IS_USER(s) (s->user)
43#else
44#define IS_USER(s) 1
45#endif
6e64da3c
GX		 46
47/* These instructions trap after executing, so defer them until after the
48 conditional executions state has been updated. */
49#define DISAS_SYSCALL 5
50
51static TCGv_ptr cpu_env;
52static TCGv_i32 cpu_R[32];
53
54/* FIXME: These should be removed. */
55static TCGv cpu_F0s, cpu_F1s;
56static TCGv_i64 cpu_F0d, cpu_F1d;
57
022c62cb 58#include "exec/gen-icount.h"
6e64da3c
GX		 59
60static const char *regnames[] = {
61 "r00", "r01", "r02", "r03", "r04", "r05", "r06", "r07",
62 "r08", "r09", "r10", "r11", "r12", "r13", "r14", "r15",
63 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
64 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "pc" };
65
66/* initialize TCG globals. */
67void uc32_translate_init(void)
68{
69 int i;
70
71 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
72
73 for (i = 0; i < 32; i++) {
74 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
eb23b556 75 offsetof(CPUUniCore32State, regs[i]), regnames[i]);
6e64da3c 76 }
6e64da3c
GX		 77}
78
79static int num_temps;
80
81/* Allocate a temporary variable. */
82static TCGv_i32 new_tmp(void)
83{
84 num_temps++;
85 return tcg_temp_new_i32();
86}
87
88/* Release a temporary variable. */
89static void dead_tmp(TCGv tmp)
90{
91 tcg_temp_free(tmp);
92 num_temps--;
93}
94
95static inline TCGv load_cpu_offset(int offset)
96{
97 TCGv tmp = new_tmp();
98 tcg_gen_ld_i32(tmp, cpu_env, offset);
99 return tmp;
100}
101
eb23b556 102#define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
6e64da3c
GX		 103
104static inline void store_cpu_offset(TCGv var, int offset)
105{
106 tcg_gen_st_i32(var, cpu_env, offset);
107 dead_tmp(var);
108}
109
110#define store_cpu_field(var, name) \
eb23b556 111 store_cpu_offset(var, offsetof(CPUUniCore32State, name))
6e64da3c
GX		 112
113/* Set a variable to the value of a CPU register. */
114static void load_reg_var(DisasContext *s, TCGv var, int reg)
115{
116 if (reg == 31) {
117 uint32_t addr;
118 /* normaly, since we updated PC */
119 addr = (long)s->pc;
120 tcg_gen_movi_i32(var, addr);
121 } else {
122 tcg_gen_mov_i32(var, cpu_R[reg]);
123 }
124}
125
126/* Create a new temporary and set it to the value of a CPU register. */
127static inline TCGv load_reg(DisasContext *s, int reg)
128{
129 TCGv tmp = new_tmp();
130 load_reg_var(s, tmp, reg);
131 return tmp;
132}
133
134/* Set a CPU register. The source must be a temporary and will be
135 marked as dead. */
136static void store_reg(DisasContext *s, int reg, TCGv var)
137{
138 if (reg == 31) {
139 tcg_gen_andi_i32(var, var, ~3);
140 s->is_jmp = DISAS_JUMP;
141 }
142 tcg_gen_mov_i32(cpu_R[reg], var);
143 dead_tmp(var);
144}
145
146/* Value extensions. */
147#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
148#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
149#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
150#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
151
152#define UCOP_REG_M (((insn) >> 0) & 0x1f)
153#define UCOP_REG_N (((insn) >> 19) & 0x1f)
154#define UCOP_REG_D (((insn) >> 14) & 0x1f)
155#define UCOP_REG_S (((insn) >> 9) & 0x1f)
156#define UCOP_REG_LO (((insn) >> 14) & 0x1f)
157#define UCOP_REG_HI (((insn) >> 9) & 0x1f)
158#define UCOP_SH_OP (((insn) >> 6) & 0x03)
159#define UCOP_SH_IM (((insn) >> 9) & 0x1f)
160#define UCOP_OPCODES (((insn) >> 25) & 0x0f)
161#define UCOP_IMM_9 (((insn) >> 0) & 0x1ff)
162#define UCOP_IMM10 (((insn) >> 0) & 0x3ff)
163#define UCOP_IMM14 (((insn) >> 0) & 0x3fff)
164#define UCOP_COND (((insn) >> 25) & 0x0f)
165#define UCOP_CMOV_COND (((insn) >> 19) & 0x0f)
166#define UCOP_CPNUM (((insn) >> 10) & 0x0f)
167#define UCOP_UCF64_FMT (((insn) >> 24) & 0x03)
168#define UCOP_UCF64_FUNC (((insn) >> 6) & 0x0f)
169#define UCOP_UCF64_COND (((insn) >> 6) & 0x0f)
170
171#define UCOP_SET(i) ((insn) & (1 << (i)))
172#define UCOP_SET_P UCOP_SET(28)
173#define UCOP_SET_U UCOP_SET(27)
174#define UCOP_SET_B UCOP_SET(26)
175#define UCOP_SET_W UCOP_SET(25)
176#define UCOP_SET_L UCOP_SET(24)
177#define UCOP_SET_S UCOP_SET(24)
178
a47dddd7 179#define ILLEGAL cpu_abort(CPU(cpu), \
6e64da3c
GX		 180 "Illegal UniCore32 instruction %x at line %d!", \
181 insn, __LINE__)
182
527d9979
GX		 183#ifndef CONFIG_USER_ONLY
184static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
185 uint32_t insn)
186{
a47dddd7 187 UniCore32CPU *cpu = uc32_env_get_cpu(env);
527d9979
GX		 188 TCGv tmp, tmp2, tmp3;
189 if ((insn & 0xfe000000) == 0xe0000000) {
190 tmp2 = new_tmp();
191 tmp3 = new_tmp();
192 tcg_gen_movi_i32(tmp2, UCOP_REG_N);
193 tcg_gen_movi_i32(tmp3, UCOP_IMM10);
194 if (UCOP_SET_L) {
195 tmp = new_tmp();
196 gen_helper_cp0_get(tmp, cpu_env, tmp2, tmp3);
197 store_reg(s, UCOP_REG_D, tmp);
198 } else {
199 tmp = load_reg(s, UCOP_REG_D);
200 gen_helper_cp0_set(cpu_env, tmp, tmp2, tmp3);
201 dead_tmp(tmp);
202 }
203 dead_tmp(tmp2);
204 dead_tmp(tmp3);
205 return;
206 }
207 ILLEGAL;
208}
209
210static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
211 uint32_t insn)
212{
a47dddd7 213 UniCore32CPU *cpu = uc32_env_get_cpu(env);
527d9979
GX		 214 TCGv tmp;
215
216 if ((insn & 0xff003fff) == 0xe1000400) {
217 /*
218 * movc rd, pp.nn, #imm9
219 * rd: UCOP_REG_D
220 * nn: UCOP_REG_N (must be 0)
221 * imm9: 0
222 */
223 if (UCOP_REG_N == 0) {
224 tmp = new_tmp();
225 tcg_gen_movi_i32(tmp, 0);
226 store_reg(s, UCOP_REG_D, tmp);
227 return;
228 } else {
229 ILLEGAL;
230 }
231 }
232 if ((insn & 0xff003fff) == 0xe0000401) {
233 /*
234 * movc pp.nn, rn, #imm9
235 * rn: UCOP_REG_D
236 * nn: UCOP_REG_N (must be 1)
237 * imm9: 1
238 */
239 if (UCOP_REG_N == 1) {
240 tmp = load_reg(s, UCOP_REG_D);
241 gen_helper_cp1_putc(tmp);
242 dead_tmp(tmp);
243 return;
244 } else {
245 ILLEGAL;
246 }
247 }
248 ILLEGAL;
249}
250#endif
251
6e64da3c
GX		 252static inline void gen_set_asr(TCGv var, uint32_t mask)
253{
254 TCGv tmp_mask = tcg_const_i32(mask);
04a130ea 255 gen_helper_asr_write(cpu_env, var, tmp_mask);
6e64da3c
GX		 256 tcg_temp_free_i32(tmp_mask);
257}
258/* Set NZCV flags from the high 4 bits of var. */
259#define gen_set_nzcv(var) gen_set_asr(var, ASR_NZCV)
260
261static void gen_exception(int excp)
262{
263 TCGv tmp = new_tmp();
264 tcg_gen_movi_i32(tmp, excp);
04a130ea 265 gen_helper_exception(cpu_env, tmp);
6e64da3c
GX		 266 dead_tmp(tmp);
267}
268
eb23b556 269#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
6e64da3c
GX		 270
271/* Set CF to the top bit of var. */
272static void gen_set_CF_bit31(TCGv var)
273{
274 TCGv tmp = new_tmp();
275 tcg_gen_shri_i32(tmp, var, 31);
276 gen_set_CF(tmp);
277 dead_tmp(tmp);
278}
279
280/* Set N and Z flags from var. */
281static inline void gen_logic_CC(TCGv var)
282{
eb23b556
AF		 283 tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, NF));
284 tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, ZF));
6e64da3c
GX		 285}
286
287/* dest = T0 + T1 + CF. */
288static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
289{
290 TCGv tmp;
291 tcg_gen_add_i32(dest, t0, t1);
292 tmp = load_cpu_field(CF);
293 tcg_gen_add_i32(dest, dest, tmp);
294 dead_tmp(tmp);
295}
296
297/* dest = T0 - T1 + CF - 1. */
298static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
299{
300 TCGv tmp;
301 tcg_gen_sub_i32(dest, t0, t1);
302 tmp = load_cpu_field(CF);
303 tcg_gen_add_i32(dest, dest, tmp);
304 tcg_gen_subi_i32(dest, dest, 1);
305 dead_tmp(tmp);
306}
307
308static void shifter_out_im(TCGv var, int shift)
309{
310 TCGv tmp = new_tmp();
311 if (shift == 0) {
312 tcg_gen_andi_i32(tmp, var, 1);
313 } else {
314 tcg_gen_shri_i32(tmp, var, shift);
315 if (shift != 31) {
316 tcg_gen_andi_i32(tmp, tmp, 1);
317 }
318 }
319 gen_set_CF(tmp);
320 dead_tmp(tmp);
321}
322
323/* Shift by immediate. Includes special handling for shift == 0. */
324static inline void gen_uc32_shift_im(TCGv var, int shiftop, int shift,
325 int flags)
326{
327 switch (shiftop) {
328 case 0: /* LSL */
329 if (shift != 0) {
330 if (flags) {
331 shifter_out_im(var, 32 - shift);
332 }
333 tcg_gen_shli_i32(var, var, shift);
334 }
335 break;
336 case 1: /* LSR */
337 if (shift == 0) {
338 if (flags) {
339 tcg_gen_shri_i32(var, var, 31);
340 gen_set_CF(var);
341 }
342 tcg_gen_movi_i32(var, 0);
343 } else {
344 if (flags) {
345 shifter_out_im(var, shift - 1);
346 }
347 tcg_gen_shri_i32(var, var, shift);
348 }
349 break;
350 case 2: /* ASR */
351 if (shift == 0) {
352 shift = 32;
353 }
354 if (flags) {
355 shifter_out_im(var, shift - 1);
356 }
357 if (shift == 32) {
358 shift = 31;
359 }
360 tcg_gen_sari_i32(var, var, shift);
361 break;
362 case 3: /* ROR/RRX */
363 if (shift != 0) {
364 if (flags) {
365 shifter_out_im(var, shift - 1);
366 }
367 tcg_gen_rotri_i32(var, var, shift); break;
368 } else {
369 TCGv tmp = load_cpu_field(CF);
370 if (flags) {
371 shifter_out_im(var, 0);
372 }
373 tcg_gen_shri_i32(var, var, 1);
374 tcg_gen_shli_i32(tmp, tmp, 31);
375 tcg_gen_or_i32(var, var, tmp);
376 dead_tmp(tmp);
377 }
378 }
379};
380
381static inline void gen_uc32_shift_reg(TCGv var, int shiftop,
382 TCGv shift, int flags)
383{
384 if (flags) {
385 switch (shiftop) {
386 case 0:
04a130ea 387 gen_helper_shl_cc(var, cpu_env, var, shift);
6e64da3c
GX		 388 break;
389 case 1:
04a130ea 390 gen_helper_shr_cc(var, cpu_env, var, shift);
6e64da3c
GX		 391 break;
392 case 2:
04a130ea 393 gen_helper_sar_cc(var, cpu_env, var, shift);
6e64da3c
GX		 394 break;
395 case 3:
04a130ea 396 gen_helper_ror_cc(var, cpu_env, var, shift);
6e64da3c
GX		 397 break;
398 }
399 } else {
400 switch (shiftop) {
401 case 0:
402 gen_helper_shl(var, var, shift);
403 break;
404 case 1:
405 gen_helper_shr(var, var, shift);
406 break;
407 case 2:
408 gen_helper_sar(var, var, shift);
409 break;
410 case 3:
411 tcg_gen_andi_i32(shift, shift, 0x1f);
412 tcg_gen_rotr_i32(var, var, shift);
413 break;
414 }
415 }
416 dead_tmp(shift);
417}
418
419static void gen_test_cc(int cc, int label)
420{
421 TCGv tmp;
422 TCGv tmp2;
423 int inv;
424
425 switch (cc) {
426 case 0: /* eq: Z */
427 tmp = load_cpu_field(ZF);
428 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
429 break;
430 case 1: /* ne: !Z */
431 tmp = load_cpu_field(ZF);
432 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
433 break;
434 case 2: /* cs: C */
435 tmp = load_cpu_field(CF);
436 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
437 break;
438 case 3: /* cc: !C */
439 tmp = load_cpu_field(CF);
440 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
441 break;
442 case 4: /* mi: N */
443 tmp = load_cpu_field(NF);
444 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
445 break;
446 case 5: /* pl: !N */
447 tmp = load_cpu_field(NF);
448 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
449 break;
450 case 6: /* vs: V */
451 tmp = load_cpu_field(VF);
452 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
453 break;
454 case 7: /* vc: !V */
455 tmp = load_cpu_field(VF);
456 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
457 break;
458 case 8: /* hi: C && !Z */
459 inv = gen_new_label();
460 tmp = load_cpu_field(CF);
461 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
462 dead_tmp(tmp);
463 tmp = load_cpu_field(ZF);
464 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
465 gen_set_label(inv);
466 break;
467 case 9: /* ls: !C || Z */
468 tmp = load_cpu_field(CF);
469 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
470 dead_tmp(tmp);
471 tmp = load_cpu_field(ZF);
472 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
473 break;
474 case 10: /* ge: N == V -> N ^ V == 0 */
475 tmp = load_cpu_field(VF);
476 tmp2 = load_cpu_field(NF);
477 tcg_gen_xor_i32(tmp, tmp, tmp2);
478 dead_tmp(tmp2);
479 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
480 break;
481 case 11: /* lt: N != V -> N ^ V != 0 */
482 tmp = load_cpu_field(VF);
483 tmp2 = load_cpu_field(NF);
484 tcg_gen_xor_i32(tmp, tmp, tmp2);
485 dead_tmp(tmp2);
486 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
487 break;
488 case 12: /* gt: !Z && N == V */
489 inv = gen_new_label();
490 tmp = load_cpu_field(ZF);
491 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
492 dead_tmp(tmp);
493 tmp = load_cpu_field(VF);
494 tmp2 = load_cpu_field(NF);
495 tcg_gen_xor_i32(tmp, tmp, tmp2);
496 dead_tmp(tmp2);
497 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
498 gen_set_label(inv);
499 break;
500 case 13: /* le: Z || N != V */
501 tmp = load_cpu_field(ZF);
502 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
503 dead_tmp(tmp);
504 tmp = load_cpu_field(VF);
505 tmp2 = load_cpu_field(NF);
506 tcg_gen_xor_i32(tmp, tmp, tmp2);
507 dead_tmp(tmp2);
508 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
509 break;
510 default:
511 fprintf(stderr, "Bad condition code 0x%x\n", cc);
512 abort();
513 }
514 dead_tmp(tmp);
515}
516
517static const uint8_t table_logic_cc[16] = {
518 1, /* and */ 1, /* xor */ 0, /* sub */ 0, /* rsb */
519 0, /* add */ 0, /* adc */ 0, /* sbc */ 0, /* rsc */
520 1, /* andl */ 1, /* xorl */ 0, /* cmp */ 0, /* cmn */
521 1, /* orr */ 1, /* mov */ 1, /* bic */ 1, /* mvn */
522};
523
524/* Set PC state from an immediate address. */
525static inline void gen_bx_im(DisasContext *s, uint32_t addr)
526{
527 s->is_jmp = DISAS_UPDATE;
528 tcg_gen_movi_i32(cpu_R[31], addr & ~3);
529}
530
531/* Set PC state from var. var is marked as dead. */
532static inline void gen_bx(DisasContext *s, TCGv var)
533{
534 s->is_jmp = DISAS_UPDATE;
535 tcg_gen_andi_i32(cpu_R[31], var, ~3);
536 dead_tmp(var);
537}
538
539static inline void store_reg_bx(DisasContext *s, int reg, TCGv var)
540{
541 store_reg(s, reg, var);
542}
543
544static inline TCGv gen_ld8s(TCGv addr, int index)
545{
546 TCGv tmp = new_tmp();
547 tcg_gen_qemu_ld8s(tmp, addr, index);
548 return tmp;
549}
550
551static inline TCGv gen_ld8u(TCGv addr, int index)
552{
553 TCGv tmp = new_tmp();
554 tcg_gen_qemu_ld8u(tmp, addr, index);
555 return tmp;
556}
557
558static inline TCGv gen_ld16s(TCGv addr, int index)
559{
560 TCGv tmp = new_tmp();
561 tcg_gen_qemu_ld16s(tmp, addr, index);
562 return tmp;
563}
564
565static inline TCGv gen_ld16u(TCGv addr, int index)
566{
567 TCGv tmp = new_tmp();
568 tcg_gen_qemu_ld16u(tmp, addr, index);
569 return tmp;
570}
571
572static inline TCGv gen_ld32(TCGv addr, int index)
573{
574 TCGv tmp = new_tmp();
575 tcg_gen_qemu_ld32u(tmp, addr, index);
576 return tmp;
577}
578
579static inline TCGv_i64 gen_ld64(TCGv addr, int index)
580{
581 TCGv_i64 tmp = tcg_temp_new_i64();
582 tcg_gen_qemu_ld64(tmp, addr, index);
583 return tmp;
584}
585
586static inline void gen_st8(TCGv val, TCGv addr, int index)
587{
588 tcg_gen_qemu_st8(val, addr, index);
589 dead_tmp(val);
590}
591
592static inline void gen_st16(TCGv val, TCGv addr, int index)
593{
594 tcg_gen_qemu_st16(val, addr, index);
595 dead_tmp(val);
596}
597
598static inline void gen_st32(TCGv val, TCGv addr, int index)
599{
600 tcg_gen_qemu_st32(val, addr, index);
601 dead_tmp(val);
602}
603
604static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
605{
606 tcg_gen_qemu_st64(val, addr, index);
607 tcg_temp_free_i64(val);
608}
609
610static inline void gen_set_pc_im(uint32_t val)
611{
612 tcg_gen_movi_i32(cpu_R[31], val);
613}
614
615/* Force a TB lookup after an instruction that changes the CPU state. */
616static inline void gen_lookup_tb(DisasContext *s)
617{
618 tcg_gen_movi_i32(cpu_R[31], s->pc & ~1);
619 s->is_jmp = DISAS_UPDATE;
620}
621
622static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
623 TCGv var)
624{
625 int val;
626 TCGv offset;
627
628 if (UCOP_SET(29)) {
629 /* immediate */
630 val = UCOP_IMM14;
631 if (!UCOP_SET_U) {
632 val = -val;
633 }
634 if (val != 0) {
635 tcg_gen_addi_i32(var, var, val);
636 }
637 } else {
638 /* shift/register */
639 offset = load_reg(s, UCOP_REG_M);
640 gen_uc32_shift_im(offset, UCOP_SH_OP, UCOP_SH_IM, 0);
641 if (!UCOP_SET_U) {
642 tcg_gen_sub_i32(var, var, offset);
643 } else {
644 tcg_gen_add_i32(var, var, offset);
645 }
646 dead_tmp(offset);
647 }
648}
649
650static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
651 TCGv var)
652{
653 int val;
654 TCGv offset;
655
656 if (UCOP_SET(26)) {
657 /* immediate */
658 val = (insn & 0x1f) | ((insn >> 4) & 0x3e0);
659 if (!UCOP_SET_U) {
660 val = -val;
661 }
662 if (val != 0) {
663 tcg_gen_addi_i32(var, var, val);
664 }
665 } else {
666 /* register */
667 offset = load_reg(s, UCOP_REG_M);
668 if (!UCOP_SET_U) {
669 tcg_gen_sub_i32(var, var, offset);
670 } else {
671 tcg_gen_add_i32(var, var, offset);
672 }
673 dead_tmp(offset);
674 }
675}
676
677static inline long ucf64_reg_offset(int reg)
678{
679 if (reg & 1) {
eb23b556 680 return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
6e64da3c
GX		 681 + offsetof(CPU_DoubleU, l.upper);
682 } else {
eb23b556 683 return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
6e64da3c
GX		 684 + offsetof(CPU_DoubleU, l.lower);
685 }
686}
687
688#define ucf64_gen_ld32(reg) load_cpu_offset(ucf64_reg_offset(reg))
689#define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
690
691/* UniCore-F64 single load/store I_offset */
eb23b556 692static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 693{
a47dddd7 694 UniCore32CPU *cpu = uc32_env_get_cpu(env);
6e64da3c
GX		 695 int offset;
696 TCGv tmp;
697 TCGv addr;
698
699 addr = load_reg(s, UCOP_REG_N);
700 if (!UCOP_SET_P && !UCOP_SET_W) {
701 ILLEGAL;
702 }
703
704 if (UCOP_SET_P) {
705 offset = UCOP_IMM10 << 2;
706 if (!UCOP_SET_U) {
707 offset = -offset;
708 }
709 if (offset != 0) {
710 tcg_gen_addi_i32(addr, addr, offset);
711 }
712 }
713
714 if (UCOP_SET_L) { /* load */
715 tmp = gen_ld32(addr, IS_USER(s));
716 ucf64_gen_st32(tmp, UCOP_REG_D);
717 } else { /* store */
718 tmp = ucf64_gen_ld32(UCOP_REG_D);
719 gen_st32(tmp, addr, IS_USER(s));
720 }
721
722 if (!UCOP_SET_P) {
723 offset = UCOP_IMM10 << 2;
724 if (!UCOP_SET_U) {
725 offset = -offset;
726 }
727 if (offset != 0) {
728 tcg_gen_addi_i32(addr, addr, offset);
729 }
730 }
731 if (UCOP_SET_W) {
732 store_reg(s, UCOP_REG_N, addr);
733 } else {
734 dead_tmp(addr);
735 }
736}
737
738/* UniCore-F64 load/store multiple words */
eb23b556 739static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 740{
a47dddd7 741 UniCore32CPU *cpu = uc32_env_get_cpu(env);
6e64da3c
GX		 742 unsigned int i;
743 int j, n, freg;
744 TCGv tmp;
745 TCGv addr;
746
747 if (UCOP_REG_D != 0) {
748 ILLEGAL;
749 }
750 if (UCOP_REG_N == 31) {
751 ILLEGAL;
752 }
753 if ((insn << 24) == 0) {
754 ILLEGAL;
755 }
756
757 addr = load_reg(s, UCOP_REG_N);
758
759 n = 0;
760 for (i = 0; i < 8; i++) {
761 if (UCOP_SET(i)) {
762 n++;
763 }
764 }
765
766 if (UCOP_SET_U) {
767 if (UCOP_SET_P) { /* pre increment */
768 tcg_gen_addi_i32(addr, addr, 4);
769 } /* unnecessary to do anything when post increment */
770 } else {
771 if (UCOP_SET_P) { /* pre decrement */
772 tcg_gen_addi_i32(addr, addr, -(n * 4));
773 } else { /* post decrement */
774 if (n != 1) {
775 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
776 }
777 }
778 }
779
780 freg = ((insn >> 8) & 3) << 3; /* freg should be 0, 8, 16, 24 */
781
782 for (i = 0, j = 0; i < 8; i++, freg++) {
783 if (!UCOP_SET(i)) {
784 continue;
785 }
786
787 if (UCOP_SET_L) { /* load */
788 tmp = gen_ld32(addr, IS_USER(s));
789 ucf64_gen_st32(tmp, freg);
790 } else { /* store */
791 tmp = ucf64_gen_ld32(freg);
792 gen_st32(tmp, addr, IS_USER(s));
793 }
794
795 j++;
796 /* unnecessary to add after the last transfer */
797 if (j != n) {
798 tcg_gen_addi_i32(addr, addr, 4);
799 }
800 }
801
802 if (UCOP_SET_W) { /* write back */
803 if (UCOP_SET_U) {
804 if (!UCOP_SET_P) { /* post increment */
805 tcg_gen_addi_i32(addr, addr, 4);
806 } /* unnecessary to do anything when pre increment */
807 } else {
808 if (UCOP_SET_P) {
809 /* pre decrement */
810 if (n != 1) {
811 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
812 }
813 } else {
814 /* post decrement */
815 tcg_gen_addi_i32(addr, addr, -(n * 4));
816 }
817 }
818 store_reg(s, UCOP_REG_N, addr);
819 } else {
820 dead_tmp(addr);
821 }
822}
823
824/* UniCore-F64 mrc/mcr */
eb23b556 825static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 826{
a47dddd7 827 UniCore32CPU *cpu = uc32_env_get_cpu(env);
6e64da3c
GX		 828 TCGv tmp;
829
830 if ((insn & 0xfe0003ff) == 0xe2000000) {
831 /* control register */
832 if ((UCOP_REG_N != UC32_UCF64_FPSCR) || (UCOP_REG_D == 31)) {
833 ILLEGAL;
834 }
835 if (UCOP_SET(24)) {
836 /* CFF */
837 tmp = new_tmp();
838 gen_helper_ucf64_get_fpscr(tmp, cpu_env);
839 store_reg(s, UCOP_REG_D, tmp);
840 } else {
841 /* CTF */
842 tmp = load_reg(s, UCOP_REG_D);
843 gen_helper_ucf64_set_fpscr(cpu_env, tmp);
844 dead_tmp(tmp);
845 gen_lookup_tb(s);
846 }
847 return;
848 }
849 if ((insn & 0xfe0003ff) == 0xe0000000) {
850 /* general register */
851 if (UCOP_REG_D == 31) {
852 ILLEGAL;
853 }
854 if (UCOP_SET(24)) { /* MFF */
855 tmp = ucf64_gen_ld32(UCOP_REG_N);
856 store_reg(s, UCOP_REG_D, tmp);
857 } else { /* MTF */
858 tmp = load_reg(s, UCOP_REG_D);
859 ucf64_gen_st32(tmp, UCOP_REG_N);
860 }
861 return;
862 }
863 if ((insn & 0xfb000000) == 0xe9000000) {
864 /* MFFC */
865 if (UCOP_REG_D != 31) {
866 ILLEGAL;
867 }
868 if (UCOP_UCF64_COND & 0x8) {
869 ILLEGAL;
870 }
871
872 tmp = new_tmp();
873 tcg_gen_movi_i32(tmp, UCOP_UCF64_COND);
874 if (UCOP_SET(26)) {
875 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_N));
876 tcg_gen_ld_i64(cpu_F1d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
877 gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, tmp, cpu_env);
878 } else {
879 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_N));
880 tcg_gen_ld_i32(cpu_F1s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
881 gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, tmp, cpu_env);
882 }
883 dead_tmp(tmp);
884 return;
885 }
886 ILLEGAL;
887}
888
889/* UniCore-F64 convert instructions */
eb23b556 890static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 891{
a47dddd7
AF		 892 UniCore32CPU *cpu = uc32_env_get_cpu(env);
893
6e64da3c
GX		 894 if (UCOP_UCF64_FMT == 3) {
895 ILLEGAL;
896 }
897 if (UCOP_REG_N != 0) {
898 ILLEGAL;
899 }
900 switch (UCOP_UCF64_FUNC) {
901 case 0: /* cvt.s */
902 switch (UCOP_UCF64_FMT) {
903 case 1 /* d */:
904 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
905 gen_helper_ucf64_df2sf(cpu_F0s, cpu_F0d, cpu_env);
906 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
907 break;
908 case 2 /* w */:
909 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
910 gen_helper_ucf64_si2sf(cpu_F0s, cpu_F0s, cpu_env);
911 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
912 break;
913 default /* s */:
914 ILLEGAL;
915 break;
916 }
917 break;
918 case 1: /* cvt.d */
919 switch (UCOP_UCF64_FMT) {
920 case 0 /* s */:
921 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
922 gen_helper_ucf64_sf2df(cpu_F0d, cpu_F0s, cpu_env);
923 tcg_gen_st_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_D));
924 break;
925 case 2 /* w */:
926 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
927 gen_helper_ucf64_si2df(cpu_F0d, cpu_F0s, cpu_env);
928 tcg_gen_st_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_D));
929 break;
930 default /* d */:
931 ILLEGAL;
932 break;
933 }
934 break;
935 case 4: /* cvt.w */
936 switch (UCOP_UCF64_FMT) {
937 case 0 /* s */:
938 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
939 gen_helper_ucf64_sf2si(cpu_F0s, cpu_F0s, cpu_env);
940 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
941 break;
942 case 1 /* d */:
943 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
944 gen_helper_ucf64_df2si(cpu_F0s, cpu_F0d, cpu_env);
945 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
946 break;
947 default /* w */:
948 ILLEGAL;
949 break;
950 }
951 break;
952 default:
953 ILLEGAL;
954 }
955}
956
957/* UniCore-F64 compare instructions */
eb23b556 958static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 959{
a47dddd7
AF		 960 UniCore32CPU *cpu = uc32_env_get_cpu(env);
961
6e64da3c
GX		 962 if (UCOP_SET(25)) {
963 ILLEGAL;
964 }
965 if (UCOP_REG_D != 0) {
966 ILLEGAL;
967 }
968
969 ILLEGAL; /* TODO */
970 if (UCOP_SET(24)) {
971 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_N));
972 tcg_gen_ld_i64(cpu_F1d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
973 /* gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, cpu_env); */
974 } else {
975 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_N));
976 tcg_gen_ld_i32(cpu_F1s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
977 /* gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, cpu_env); */
978 }
979}
980
981#define gen_helper_ucf64_movs(x, y) do { } while (0)
982#define gen_helper_ucf64_movd(x, y) do { } while (0)
983
984#define UCF64_OP1(name) do { \
985 if (UCOP_REG_N != 0) { \
986 ILLEGAL; \
987 } \
988 switch (UCOP_UCF64_FMT) { \
989 case 0 /* s */: \
990 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
991 ucf64_reg_offset(UCOP_REG_M)); \
992 gen_helper_ucf64_##name##s(cpu_F0s, cpu_F0s); \
993 tcg_gen_st_i32(cpu_F0s, cpu_env, \
994 ucf64_reg_offset(UCOP_REG_D)); \
995 break; \
996 case 1 /* d */: \
997 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
998 ucf64_reg_offset(UCOP_REG_M)); \
999 gen_helper_ucf64_##name##d(cpu_F0d, cpu_F0d); \
1000 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1001 ucf64_reg_offset(UCOP_REG_D)); \
1002 break; \
1003 case 2 /* w */: \
1004 ILLEGAL; \
1005 break; \
1006 } \
1007 } while (0)
1008
1009#define UCF64_OP2(name) do { \
1010 switch (UCOP_UCF64_FMT) { \
1011 case 0 /* s */: \
1012 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
1013 ucf64_reg_offset(UCOP_REG_N)); \
1014 tcg_gen_ld_i32(cpu_F1s, cpu_env, \
1015 ucf64_reg_offset(UCOP_REG_M)); \
1016 gen_helper_ucf64_##name##s(cpu_F0s, \
1017 cpu_F0s, cpu_F1s, cpu_env); \
1018 tcg_gen_st_i32(cpu_F0s, cpu_env, \
1019 ucf64_reg_offset(UCOP_REG_D)); \
1020 break; \
1021 case 1 /* d */: \
1022 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
1023 ucf64_reg_offset(UCOP_REG_N)); \
1024 tcg_gen_ld_i64(cpu_F1d, cpu_env, \
1025 ucf64_reg_offset(UCOP_REG_M)); \
1026 gen_helper_ucf64_##name##d(cpu_F0d, \
1027 cpu_F0d, cpu_F1d, cpu_env); \
1028 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1029 ucf64_reg_offset(UCOP_REG_D)); \
1030 break; \
1031 case 2 /* w */: \
1032 ILLEGAL; \
1033 break; \
1034 } \
1035 } while (0)
1036
1037/* UniCore-F64 data processing */
eb23b556 1038static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1039{
a47dddd7
AF		 1040 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1041
6e64da3c
GX		 1042 if (UCOP_UCF64_FMT == 3) {
1043 ILLEGAL;
1044 }
1045 switch (UCOP_UCF64_FUNC) {
1046 case 0: /* add */
1047 UCF64_OP2(add);
1048 break;
1049 case 1: /* sub */
1050 UCF64_OP2(sub);
1051 break;
1052 case 2: /* mul */
1053 UCF64_OP2(mul);
1054 break;
1055 case 4: /* div */
1056 UCF64_OP2(div);
1057 break;
1058 case 5: /* abs */
1059 UCF64_OP1(abs);
1060 break;
1061 case 6: /* mov */
1062 UCF64_OP1(mov);
1063 break;
1064 case 7: /* neg */
1065 UCF64_OP1(neg);
1066 break;
1067 default:
1068 ILLEGAL;
1069 }
1070}
1071
1072/* Disassemble an F64 instruction */
eb23b556 1073static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1074{
a47dddd7
AF		 1075 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1076
6e64da3c
GX		 1077 if (!UCOP_SET(29)) {
1078 if (UCOP_SET(26)) {
1079 do_ucf64_ldst_m(env, s, insn);
1080 } else {
1081 do_ucf64_ldst_i(env, s, insn);
1082 }
1083 } else {
1084 if (UCOP_SET(5)) {
1085 switch ((insn >> 26) & 0x3) {
1086 case 0:
1087 do_ucf64_datap(env, s, insn);
1088 break;
1089 case 1:
1090 ILLEGAL;
1091 break;
1092 case 2:
1093 do_ucf64_fcvt(env, s, insn);
1094 break;
1095 case 3:
1096 do_ucf64_fcmp(env, s, insn);
1097 break;
1098 }
1099 } else {
1100 do_ucf64_trans(env, s, insn);
1101 }
1102 }
1103}
1104
1105static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
1106{
1107 TranslationBlock *tb;
1108
1109 tb = s->tb;
1110 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1111 tcg_gen_goto_tb(n);
1112 gen_set_pc_im(dest);
8cfd0495 1113 tcg_gen_exit_tb((uintptr_t)tb + n);
6e64da3c
GX		 1114 } else {
1115 gen_set_pc_im(dest);
1116 tcg_gen_exit_tb(0);
1117 }
1118}
1119
1120static inline void gen_jmp(DisasContext *s, uint32_t dest)
1121{
1122 if (unlikely(s->singlestep_enabled)) {
1123 /* An indirect jump so that we still trigger the debug exception. */
1124 gen_bx_im(s, dest);
1125 } else {
1126 gen_goto_tb(s, 0, dest);
1127 s->is_jmp = DISAS_TB_JUMP;
1128 }
1129}
1130
1131static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
1132{
1133 if (x) {
1134 tcg_gen_sari_i32(t0, t0, 16);
1135 } else {
1136 gen_sxth(t0);
1137 }
1138 if (y) {
1139 tcg_gen_sari_i32(t1, t1, 16);
1140 } else {
1141 gen_sxth(t1);
1142 }
1143 tcg_gen_mul_i32(t0, t0, t1);
1144}
1145
1146/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
1147static int gen_set_psr(DisasContext *s, uint32_t mask, int bsr, TCGv t0)
1148{
1149 TCGv tmp;
1150 if (bsr) {
1151 /* ??? This is also undefined in system mode. */
1152 if (IS_USER(s)) {
1153 return 1;
1154 }
1155
1156 tmp = load_cpu_field(bsr);
1157 tcg_gen_andi_i32(tmp, tmp, ~mask);
1158 tcg_gen_andi_i32(t0, t0, mask);
1159 tcg_gen_or_i32(tmp, tmp, t0);
1160 store_cpu_field(tmp, bsr);
1161 } else {
1162 gen_set_asr(t0, mask);
1163 }
1164 dead_tmp(t0);
1165 gen_lookup_tb(s);
1166 return 0;
1167}
1168
1169/* Generate an old-style exception return. Marks pc as dead. */
1170static void gen_exception_return(DisasContext *s, TCGv pc)
1171{
1172 TCGv tmp;
1173 store_reg(s, 31, pc);
1174 tmp = load_cpu_field(bsr);
1175 gen_set_asr(tmp, 0xffffffff);
1176 dead_tmp(tmp);
1177 s->is_jmp = DISAS_UPDATE;
1178}
1179
527d9979
GX		 1180static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
1181 uint32_t insn)
6e64da3c 1182{
a47dddd7
AF		 1183 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1184
6e64da3c 1185 switch (UCOP_CPNUM) {
527d9979
GX		 1186#ifndef CONFIG_USER_ONLY
1187 case 0:
1188 disas_cp0_insn(env, s, insn);
1189 break;
1190 case 1:
1191 disas_ocd_insn(env, s, insn);
1192 break;
1193#endif
6e64da3c
GX		 1194 case 2:
1195 disas_ucf64_insn(env, s, insn);
1196 break;
1197 default:
1198 /* Unknown coprocessor. */
a47dddd7 1199 cpu_abort(CPU(cpu), "Unknown coprocessor!");
6e64da3c
GX		 1200 }
1201}
1202
6e64da3c 1203/* data processing instructions */
eb23b556 1204static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1205{
a47dddd7 1206 UniCore32CPU *cpu = uc32_env_get_cpu(env);
6e64da3c
GX		 1207 TCGv tmp;
1208 TCGv tmp2;
1209 int logic_cc;
1210
1211 if (UCOP_OPCODES == 0x0f || UCOP_OPCODES == 0x0d) {
1212 if (UCOP_SET(23)) { /* CMOV instructions */
1213 if ((UCOP_CMOV_COND == 0xe) || (UCOP_CMOV_COND == 0xf)) {
1214 ILLEGAL;
1215 }
1216 /* if not always execute, we generate a conditional jump to
1217 next instruction */
1218 s->condlabel = gen_new_label();
1219 gen_test_cc(UCOP_CMOV_COND ^ 1, s->condlabel);
1220 s->condjmp = 1;
1221 }
1222 }
1223
1224 logic_cc = table_logic_cc[UCOP_OPCODES] & (UCOP_SET_S >> 24);
1225
1226 if (UCOP_SET(29)) {
1227 unsigned int val;
1228 /* immediate operand */
1229 val = UCOP_IMM_9;
1230 if (UCOP_SH_IM) {
1231 val = (val >> UCOP_SH_IM) | (val << (32 - UCOP_SH_IM));
1232 }
1233 tmp2 = new_tmp();
1234 tcg_gen_movi_i32(tmp2, val);
1235 if (logic_cc && UCOP_SH_IM) {
1236 gen_set_CF_bit31(tmp2);
1237 }
1238 } else {
1239 /* register */
1240 tmp2 = load_reg(s, UCOP_REG_M);
1241 if (UCOP_SET(5)) {
1242 tmp = load_reg(s, UCOP_REG_S);
1243 gen_uc32_shift_reg(tmp2, UCOP_SH_OP, tmp, logic_cc);
1244 } else {
1245 gen_uc32_shift_im(tmp2, UCOP_SH_OP, UCOP_SH_IM, logic_cc);
1246 }
1247 }
1248
1249 if (UCOP_OPCODES != 0x0f && UCOP_OPCODES != 0x0d) {
1250 tmp = load_reg(s, UCOP_REG_N);
1251 } else {
1252 TCGV_UNUSED(tmp);
1253 }
1254
1255 switch (UCOP_OPCODES) {
1256 case 0x00:
1257 tcg_gen_and_i32(tmp, tmp, tmp2);
1258 if (logic_cc) {
1259 gen_logic_CC(tmp);
1260 }
1261 store_reg_bx(s, UCOP_REG_D, tmp);
1262 break;
1263 case 0x01:
1264 tcg_gen_xor_i32(tmp, tmp, tmp2);
1265 if (logic_cc) {
1266 gen_logic_CC(tmp);
1267 }
1268 store_reg_bx(s, UCOP_REG_D, tmp);
1269 break;
1270 case 0x02:
1271 if (UCOP_SET_S && UCOP_REG_D == 31) {
1272 /* SUBS r31, ... is used for exception return. */
1273 if (IS_USER(s)) {
1274 ILLEGAL;
1275 }
04a130ea 1276 gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
6e64da3c
GX		 1277 gen_exception_return(s, tmp);
1278 } else {
1279 if (UCOP_SET_S) {
04a130ea 1280 gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
6e64da3c
GX		 1281 } else {
1282 tcg_gen_sub_i32(tmp, tmp, tmp2);
1283 }
1284 store_reg_bx(s, UCOP_REG_D, tmp);
1285 }
1286 break;
1287 case 0x03:
1288 if (UCOP_SET_S) {
04a130ea 1289 gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
6e64da3c
GX		 1290 } else {
1291 tcg_gen_sub_i32(tmp, tmp2, tmp);
1292 }
1293 store_reg_bx(s, UCOP_REG_D, tmp);
1294 break;
1295 case 0x04:
1296 if (UCOP_SET_S) {
04a130ea 1297 gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
6e64da3c
GX		 1298 } else {
1299 tcg_gen_add_i32(tmp, tmp, tmp2);
1300 }
1301 store_reg_bx(s, UCOP_REG_D, tmp);
1302 break;
1303 case 0x05:
1304 if (UCOP_SET_S) {
04a130ea 1305 gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
6e64da3c
GX		 1306 } else {
1307 gen_add_carry(tmp, tmp, tmp2);
1308 }
1309 store_reg_bx(s, UCOP_REG_D, tmp);
1310 break;
1311 case 0x06:
1312 if (UCOP_SET_S) {
04a130ea 1313 gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
6e64da3c
GX		 1314 } else {
1315 gen_sub_carry(tmp, tmp, tmp2);
1316 }
1317 store_reg_bx(s, UCOP_REG_D, tmp);
1318 break;
1319 case 0x07:
1320 if (UCOP_SET_S) {
04a130ea 1321 gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
6e64da3c
GX		 1322 } else {
1323 gen_sub_carry(tmp, tmp2, tmp);
1324 }
1325 store_reg_bx(s, UCOP_REG_D, tmp);
1326 break;
1327 case 0x08:
1328 if (UCOP_SET_S) {
1329 tcg_gen_and_i32(tmp, tmp, tmp2);
1330 gen_logic_CC(tmp);
1331 }
1332 dead_tmp(tmp);
1333 break;
1334 case 0x09:
1335 if (UCOP_SET_S) {
1336 tcg_gen_xor_i32(tmp, tmp, tmp2);
1337 gen_logic_CC(tmp);
1338 }
1339 dead_tmp(tmp);
1340 break;
1341 case 0x0a:
1342 if (UCOP_SET_S) {
04a130ea 1343 gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
6e64da3c
GX		 1344 }
1345 dead_tmp(tmp);
1346 break;
1347 case 0x0b:
1348 if (UCOP_SET_S) {
04a130ea 1349 gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
6e64da3c
GX		 1350 }
1351 dead_tmp(tmp);
1352 break;
1353 case 0x0c:
1354 tcg_gen_or_i32(tmp, tmp, tmp2);
1355 if (logic_cc) {
1356 gen_logic_CC(tmp);
1357 }
1358 store_reg_bx(s, UCOP_REG_D, tmp);
1359 break;
1360 case 0x0d:
1361 if (logic_cc && UCOP_REG_D == 31) {
1362 /* MOVS r31, ... is used for exception return. */
1363 if (IS_USER(s)) {
1364 ILLEGAL;
1365 }
1366 gen_exception_return(s, tmp2);
1367 } else {
1368 if (logic_cc) {
1369 gen_logic_CC(tmp2);
1370 }
1371 store_reg_bx(s, UCOP_REG_D, tmp2);
1372 }
1373 break;
1374 case 0x0e:
1375 tcg_gen_andc_i32(tmp, tmp, tmp2);
1376 if (logic_cc) {
1377 gen_logic_CC(tmp);
1378 }
1379 store_reg_bx(s, UCOP_REG_D, tmp);
1380 break;
1381 default:
1382 case 0x0f:
1383 tcg_gen_not_i32(tmp2, tmp2);
1384 if (logic_cc) {
1385 gen_logic_CC(tmp2);
1386 }
1387 store_reg_bx(s, UCOP_REG_D, tmp2);
1388 break;
1389 }
1390 if (UCOP_OPCODES != 0x0f && UCOP_OPCODES != 0x0d) {
1391 dead_tmp(tmp2);
1392 }
1393}
1394
1395/* multiply */
eb23b556 1396static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1397{
d1f8cd83 1398 TCGv tmp, tmp2, tmp3, tmp4;
6e64da3c
GX		 1399
1400 if (UCOP_SET(27)) {
1401 /* 64 bit mul */
1402 tmp = load_reg(s, UCOP_REG_M);
1403 tmp2 = load_reg(s, UCOP_REG_N);
1404 if (UCOP_SET(26)) {
d1f8cd83 1405 tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2);
6e64da3c 1406 } else {
d1f8cd83 1407 tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2);
6e64da3c
GX		 1408 }
1409 if (UCOP_SET(25)) { /* mult accumulate */
d1f8cd83
RH		 1410 tmp3 = load_reg(s, UCOP_REG_LO);
1411 tmp4 = load_reg(s, UCOP_REG_HI);
1412 tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, tmp3, tmp4);
1413 dead_tmp(tmp3);
1414 dead_tmp(tmp4);
1415 }
1416 store_reg(s, UCOP_REG_LO, tmp);
1417 store_reg(s, UCOP_REG_HI, tmp2);
6e64da3c
GX		 1418 } else {
1419 /* 32 bit mul */
1420 tmp = load_reg(s, UCOP_REG_M);
1421 tmp2 = load_reg(s, UCOP_REG_N);
1422 tcg_gen_mul_i32(tmp, tmp, tmp2);
1423 dead_tmp(tmp2);
1424 if (UCOP_SET(25)) {
1425 /* Add */
1426 tmp2 = load_reg(s, UCOP_REG_S);
1427 tcg_gen_add_i32(tmp, tmp, tmp2);
1428 dead_tmp(tmp2);
1429 }
1430 if (UCOP_SET_S) {
1431 gen_logic_CC(tmp);
1432 }
1433 store_reg(s, UCOP_REG_D, tmp);
1434 }
1435}
1436
1437/* miscellaneous instructions */
eb23b556 1438static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1439{
a47dddd7 1440 UniCore32CPU *cpu = uc32_env_get_cpu(env);
6e64da3c
GX		 1441 unsigned int val;
1442 TCGv tmp;
1443
1444 if ((insn & 0xffffffe0) == 0x10ffc120) {
1445 /* Trivial implementation equivalent to bx. */
1446 tmp = load_reg(s, UCOP_REG_M);
1447 gen_bx(s, tmp);
1448 return;
1449 }
1450
1451 if ((insn & 0xfbffc000) == 0x30ffc000) {
1452 /* PSR = immediate */
1453 val = UCOP_IMM_9;
1454 if (UCOP_SH_IM) {
1455 val = (val >> UCOP_SH_IM) | (val << (32 - UCOP_SH_IM));
1456 }
1457 tmp = new_tmp();
1458 tcg_gen_movi_i32(tmp, val);
1459 if (gen_set_psr(s, ~ASR_RESERVED, UCOP_SET_B, tmp)) {
1460 ILLEGAL;
1461 }
1462 return;
1463 }
1464
1465 if ((insn & 0xfbffffe0) == 0x12ffc020) {
1466 /* PSR.flag = reg */
1467 tmp = load_reg(s, UCOP_REG_M);
1468 if (gen_set_psr(s, ASR_NZCV, UCOP_SET_B, tmp)) {
1469 ILLEGAL;
1470 }
1471 return;
1472 }
1473
1474 if ((insn & 0xfbffffe0) == 0x10ffc020) {
1475 /* PSR = reg */
1476 tmp = load_reg(s, UCOP_REG_M);
1477 if (gen_set_psr(s, ~ASR_RESERVED, UCOP_SET_B, tmp)) {
1478 ILLEGAL;
1479 }
1480 return;
1481 }
1482
1483 if ((insn & 0xfbf83fff) == 0x10f80000) {
1484 /* reg = PSR */
1485 if (UCOP_SET_B) {
1486 if (IS_USER(s)) {
1487 ILLEGAL;
1488 }
1489 tmp = load_cpu_field(bsr);
1490 } else {
1491 tmp = new_tmp();
04a130ea 1492 gen_helper_asr_read(tmp, cpu_env);
6e64da3c
GX		 1493 }
1494 store_reg(s, UCOP_REG_D, tmp);
1495 return;
1496 }
1497
1498 if ((insn & 0xfbf83fe0) == 0x12f80120) {
1499 /* clz */
1500 tmp = load_reg(s, UCOP_REG_M);
1501 if (UCOP_SET(26)) {
1502 gen_helper_clo(tmp, tmp);
1503 } else {
1504 gen_helper_clz(tmp, tmp);
1505 }
1506 store_reg(s, UCOP_REG_D, tmp);
1507 return;
1508 }
1509
1510 /* otherwise */
1511 ILLEGAL;
1512}
1513
1514/* load/store I_offset and R_offset */
eb23b556 1515static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1516{
ef03168a 1517 unsigned int mmu_idx;
6e64da3c
GX		 1518 TCGv tmp;
1519 TCGv tmp2;
1520
1521 tmp2 = load_reg(s, UCOP_REG_N);
ef03168a 1522 mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
6e64da3c
GX		 1523
1524 /* immediate */
1525 if (UCOP_SET_P) {
1526 gen_add_data_offset(s, insn, tmp2);
1527 }
1528
1529 if (UCOP_SET_L) {
1530 /* load */
1531 if (UCOP_SET_B) {
ef03168a 1532 tmp = gen_ld8u(tmp2, mmu_idx);
6e64da3c 1533 } else {
ef03168a 1534 tmp = gen_ld32(tmp2, mmu_idx);
6e64da3c
GX		 1535 }
1536 } else {
1537 /* store */
1538 tmp = load_reg(s, UCOP_REG_D);
1539 if (UCOP_SET_B) {
ef03168a 1540 gen_st8(tmp, tmp2, mmu_idx);
6e64da3c 1541 } else {
ef03168a 1542 gen_st32(tmp, tmp2, mmu_idx);
6e64da3c
GX		 1543 }
1544 }
1545 if (!UCOP_SET_P) {
1546 gen_add_data_offset(s, insn, tmp2);
1547 store_reg(s, UCOP_REG_N, tmp2);
1548 } else if (UCOP_SET_W) {
1549 store_reg(s, UCOP_REG_N, tmp2);
1550 } else {
1551 dead_tmp(tmp2);
1552 }
1553 if (UCOP_SET_L) {
1554 /* Complete the load. */
1555 if (UCOP_REG_D == 31) {
1556 gen_bx(s, tmp);
1557 } else {
1558 store_reg(s, UCOP_REG_D, tmp);
1559 }
1560 }
1561}
1562
1563/* SWP instruction */
eb23b556 1564static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1565{
a47dddd7 1566 UniCore32CPU *cpu = uc32_env_get_cpu(env);
6e64da3c
GX		 1567 TCGv addr;
1568 TCGv tmp;
1569 TCGv tmp2;
1570
1571 if ((insn & 0xff003fe0) != 0x40000120) {
1572 ILLEGAL;
1573 }
1574
1575 /* ??? This is not really atomic. However we know
1576 we never have multiple CPUs running in parallel,
1577 so it is good enough. */
1578 addr = load_reg(s, UCOP_REG_N);
1579 tmp = load_reg(s, UCOP_REG_M);
1580 if (UCOP_SET_B) {
1581 tmp2 = gen_ld8u(addr, IS_USER(s));
1582 gen_st8(tmp, addr, IS_USER(s));
1583 } else {
1584 tmp2 = gen_ld32(addr, IS_USER(s));
1585 gen_st32(tmp, addr, IS_USER(s));
1586 }
1587 dead_tmp(addr);
1588 store_reg(s, UCOP_REG_D, tmp2);
1589}
1590
1591/* load/store hw/sb */
eb23b556 1592static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1593{
a47dddd7 1594 UniCore32CPU *cpu = uc32_env_get_cpu(env);
6e64da3c
GX		 1595 TCGv addr;
1596 TCGv tmp;
1597
1598 if (UCOP_SH_OP == 0) {
1599 do_swap(env, s, insn);
1600 return;
1601 }
1602
1603 addr = load_reg(s, UCOP_REG_N);
1604 if (UCOP_SET_P) {
1605 gen_add_datah_offset(s, insn, addr);
1606 }
1607
1608 if (UCOP_SET_L) { /* load */
1609 switch (UCOP_SH_OP) {
1610 case 1:
1611 tmp = gen_ld16u(addr, IS_USER(s));
1612 break;
1613 case 2:
1614 tmp = gen_ld8s(addr, IS_USER(s));
1615 break;
1616 default: /* see do_swap */
1617 case 3:
1618 tmp = gen_ld16s(addr, IS_USER(s));
1619 break;
1620 }
1621 } else { /* store */
1622 if (UCOP_SH_OP != 1) {
1623 ILLEGAL;
1624 }
1625 tmp = load_reg(s, UCOP_REG_D);
1626 gen_st16(tmp, addr, IS_USER(s));
1627 }
1628 /* Perform base writeback before the loaded value to
1629 ensure correct behavior with overlapping index registers. */
1630 if (!UCOP_SET_P) {
1631 gen_add_datah_offset(s, insn, addr);
1632 store_reg(s, UCOP_REG_N, addr);
1633 } else if (UCOP_SET_W) {
1634 store_reg(s, UCOP_REG_N, addr);
1635 } else {
1636 dead_tmp(addr);
1637 }
1638 if (UCOP_SET_L) {
1639 /* Complete the load. */
1640 store_reg(s, UCOP_REG_D, tmp);
1641 }
1642}
1643
1644/* load/store multiple words */
eb23b556 1645static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1646{
a47dddd7 1647 UniCore32CPU *cpu = uc32_env_get_cpu(env);
ef03168a 1648 unsigned int val, i, mmu_idx;
6e64da3c
GX		 1649 int j, n, reg, user, loaded_base;
1650 TCGv tmp;
1651 TCGv tmp2;
1652 TCGv addr;
1653 TCGv loaded_var;
1654
1655 if (UCOP_SET(7)) {
1656 ILLEGAL;
1657 }
1658 /* XXX: store correct base if write back */
1659 user = 0;
1660 if (UCOP_SET_B) { /* S bit in instruction table */
1661 if (IS_USER(s)) {
1662 ILLEGAL; /* only usable in supervisor mode */
1663 }
1664 if (UCOP_SET(18) == 0) { /* pc reg */
1665 user = 1;
1666 }
1667 }
1668
ef03168a 1669 mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
6e64da3c
GX		 1670 addr = load_reg(s, UCOP_REG_N);
1671
1672 /* compute total size */
1673 loaded_base = 0;
1674 TCGV_UNUSED(loaded_var);
1675 n = 0;
1676 for (i = 0; i < 6; i++) {
1677 if (UCOP_SET(i)) {
1678 n++;
1679 }
1680 }
1681 for (i = 9; i < 19; i++) {
1682 if (UCOP_SET(i)) {
1683 n++;
1684 }
1685 }
1686 /* XXX: test invalid n == 0 case ? */
1687 if (UCOP_SET_U) {
1688 if (UCOP_SET_P) {
1689 /* pre increment */
1690 tcg_gen_addi_i32(addr, addr, 4);
1691 } else {
1692 /* post increment */
1693 }
1694 } else {
1695 if (UCOP_SET_P) {
1696 /* pre decrement */
1697 tcg_gen_addi_i32(addr, addr, -(n * 4));
1698 } else {
1699 /* post decrement */
1700 if (n != 1) {
1701 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
1702 }
1703 }
1704 }
1705
1706 j = 0;
1707 reg = UCOP_SET(6) ? 16 : 0;
1708 for (i = 0; i < 19; i++, reg++) {
1709 if (i == 6) {
1710 i = i + 3;
1711 }
1712 if (UCOP_SET(i)) {
1713 if (UCOP_SET_L) { /* load */
ef03168a 1714 tmp = gen_ld32(addr, mmu_idx);
6e64da3c
GX		 1715 if (reg == 31) {
1716 gen_bx(s, tmp);
1717 } else if (user) {
1718 tmp2 = tcg_const_i32(reg);
04a130ea 1719 gen_helper_set_user_reg(cpu_env, tmp2, tmp);
6e64da3c
GX		 1720 tcg_temp_free_i32(tmp2);
1721 dead_tmp(tmp);
1722 } else if (reg == UCOP_REG_N) {
1723 loaded_var = tmp;
1724 loaded_base = 1;
1725 } else {
1726 store_reg(s, reg, tmp);
1727 }
1728 } else { /* store */
1729 if (reg == 31) {
1730 /* special case: r31 = PC + 4 */
1731 val = (long)s->pc;
1732 tmp = new_tmp();
1733 tcg_gen_movi_i32(tmp, val);
1734 } else if (user) {
1735 tmp = new_tmp();
1736 tmp2 = tcg_const_i32(reg);
04a130ea 1737 gen_helper_get_user_reg(tmp, cpu_env, tmp2);
6e64da3c
GX		 1738 tcg_temp_free_i32(tmp2);
1739 } else {
1740 tmp = load_reg(s, reg);
1741 }
ef03168a 1742 gen_st32(tmp, addr, mmu_idx);
6e64da3c
GX		 1743 }
1744 j++;
1745 /* no need to add after the last transfer */
1746 if (j != n) {
1747 tcg_gen_addi_i32(addr, addr, 4);
1748 }
1749 }
1750 }
1751 if (UCOP_SET_W) { /* write back */
1752 if (UCOP_SET_U) {
1753 if (UCOP_SET_P) {
1754 /* pre increment */
1755 } else {
1756 /* post increment */
1757 tcg_gen_addi_i32(addr, addr, 4);
1758 }
1759 } else {
1760 if (UCOP_SET_P) {
1761 /* pre decrement */
1762 if (n != 1) {
1763 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
1764 }
1765 } else {
1766 /* post decrement */
1767 tcg_gen_addi_i32(addr, addr, -(n * 4));
1768 }
1769 }
1770 store_reg(s, UCOP_REG_N, addr);
1771 } else {
1772 dead_tmp(addr);
1773 }
1774 if (loaded_base) {
1775 store_reg(s, UCOP_REG_N, loaded_var);
1776 }
1777 if (UCOP_SET_B && !user) {
1778 /* Restore ASR from BSR. */
1779 tmp = load_cpu_field(bsr);
1780 gen_set_asr(tmp, 0xffffffff);
1781 dead_tmp(tmp);
1782 s->is_jmp = DISAS_UPDATE;
1783 }
1784}
1785
1786/* branch (and link) */
eb23b556 1787static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
6e64da3c 1788{
a47dddd7 1789 UniCore32CPU *cpu = uc32_env_get_cpu(env);
6e64da3c
GX		 1790 unsigned int val;
1791 int32_t offset;
1792 TCGv tmp;
1793
1794 if (UCOP_COND == 0xf) {
1795 ILLEGAL;
1796 }
1797
1798 if (UCOP_COND != 0xe) {
1799 /* if not always execute, we generate a conditional jump to
1800 next instruction */
1801 s->condlabel = gen_new_label();
1802 gen_test_cc(UCOP_COND ^ 1, s->condlabel);
1803 s->condjmp = 1;
1804 }
1805
1806 val = (int32_t)s->pc;
1807 if (UCOP_SET_L) {
1808 tmp = new_tmp();
1809 tcg_gen_movi_i32(tmp, val);
1810 store_reg(s, 30, tmp);
1811 }
1812 offset = (((int32_t)insn << 8) >> 8);
1813 val += (offset << 2); /* unicore is pc+4 */
1814 gen_jmp(s, val);
1815}
1816
eb23b556 1817static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
6e64da3c 1818{
a47dddd7 1819 UniCore32CPU *cpu = uc32_env_get_cpu(env);
6e64da3c
GX		 1820 unsigned int insn;
1821
daa47c34
RH		 1822 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1823 tcg_gen_debug_insn_start(s->pc);
1824 }
1825
04a130ea 1826 insn = cpu_ldl_code(env, s->pc);
6e64da3c
GX		 1827 s->pc += 4;
1828
1829 /* UniCore instructions class:
1830 * AAAB BBBC xxxx xxxx xxxx xxxD xxEx xxxx
1831 * AAA : see switch case
1832 * BBBB : opcodes or cond or PUBW
1833 * C : S OR L
1834 * D : 8
1835 * E : 5
1836 */
1837 switch (insn >> 29) {
fa4e49c0 1838 case 0x0:
6e64da3c
GX		 1839 if (UCOP_SET(5) && UCOP_SET(8) && !UCOP_SET(28)) {
1840 do_mult(env, s, insn);
1841 break;
1842 }
1843
1844 if (UCOP_SET(8)) {
1845 do_misc(env, s, insn);
1846 break;
1847 }
fa4e49c0 1848 case 0x1:
6e64da3c
GX		 1849 if (((UCOP_OPCODES >> 2) == 2) && !UCOP_SET_S) {
1850 do_misc(env, s, insn);
1851 break;
1852 }
1853 do_datap(env, s, insn);
1854 break;
1855
fa4e49c0 1856 case 0x2:
6e64da3c
GX		 1857 if (UCOP_SET(8) && UCOP_SET(5)) {
1858 do_ldst_hwsb(env, s, insn);
1859 break;
1860 }
1861 if (UCOP_SET(8) || UCOP_SET(5)) {
1862 ILLEGAL;
1863 }
fa4e49c0 1864 case 0x3:
6e64da3c
GX		 1865 do_ldst_ir(env, s, insn);
1866 break;
1867
fa4e49c0 1868 case 0x4:
6e64da3c
GX		 1869 if (UCOP_SET(8)) {
1870 ILLEGAL; /* extended instructions */
1871 }
1872 do_ldst_m(env, s, insn);
1873 break;
fa4e49c0 1874 case 0x5:
6e64da3c
GX		 1875 do_branch(env, s, insn);
1876 break;
fa4e49c0 1877 case 0x6:
6e64da3c
GX		 1878 /* Coprocessor. */
1879 disas_coproc_insn(env, s, insn);
1880 break;
fa4e49c0 1881 case 0x7:
6e64da3c
GX		 1882 if (!UCOP_SET(28)) {
1883 disas_coproc_insn(env, s, insn);
1884 break;
1885 }
1886 if ((insn & 0xff000000) == 0xff000000) { /* syscall */
1887 gen_set_pc_im(s->pc);
1888 s->is_jmp = DISAS_SYSCALL;
1889 break;
1890 }
1891 ILLEGAL;
1892 }
6e64da3c
GX		 1893}
1894
1895/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
1896 basic block 'tb'. If search_pc is TRUE, also generate PC
1897 information for each intermediate instruction. */
62a80559
AF		 1898static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
1899 TranslationBlock *tb, bool search_pc)
6e64da3c 1900{
ed2803da 1901 CPUState *cs = CPU(cpu);
62a80559 1902 CPUUniCore32State *env = &cpu->env;
6e64da3c
GX		 1903 DisasContext dc1, *dc = &dc1;
1904 CPUBreakpoint *bp;
1905 uint16_t *gen_opc_end;
1906 int j, lj;
1907 target_ulong pc_start;
1908 uint32_t next_page_start;
1909 int num_insns;
1910 int max_insns;
1911
1912 /* generate intermediate code */
1913 num_temps = 0;
1914
1915 pc_start = tb->pc;
1916
1917 dc->tb = tb;
1918
92414b31 1919 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
6e64da3c
GX		 1920
1921 dc->is_jmp = DISAS_NEXT;
1922 dc->pc = pc_start;
ed2803da 1923 dc->singlestep_enabled = cs->singlestep_enabled;
6e64da3c
GX		 1924 dc->condjmp = 0;
1925 cpu_F0s = tcg_temp_new_i32();
1926 cpu_F1s = tcg_temp_new_i32();
1927 cpu_F0d = tcg_temp_new_i64();
1928 cpu_F1d = tcg_temp_new_i64();
1929 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1930 lj = -1;
1931 num_insns = 0;
1932 max_insns = tb->cflags & CF_COUNT_MASK;
1933 if (max_insns == 0) {
1934 max_insns = CF_COUNT_MASK;
1935 }
1936
ef03168a
GX		 1937#ifndef CONFIG_USER_ONLY
1938 if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
1939 dc->user = 1;
1940 } else {
1941 dc->user = 0;
1942 }
1943#endif
1944
806f352d 1945 gen_tb_start();
6e64da3c 1946 do {
f0c3c505
AF		 1947 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
1948 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
6e64da3c
GX		 1949 if (bp->pc == dc->pc) {
1950 gen_set_pc_im(dc->pc);
1951 gen_exception(EXCP_DEBUG);
1952 dc->is_jmp = DISAS_JUMP;
1953 /* Advance PC so that clearing the breakpoint will
1954 invalidate this TB. */
1955 dc->pc += 2; /* FIXME */
1956 goto done_generating;
6e64da3c
GX		 1957 }
1958 }
1959 }
1960 if (search_pc) {
92414b31 1961 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
6e64da3c
GX		 1962 if (lj < j) {
1963 lj++;
1964 while (lj < j) {
ab1103de 1965 tcg_ctx.gen_opc_instr_start[lj++] = 0;
6e64da3c
GX		 1966 }
1967 }
25983cad 1968 tcg_ctx.gen_opc_pc[lj] = dc->pc;
ab1103de 1969 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 1970 tcg_ctx.gen_opc_icount[lj] = num_insns;
6e64da3c
GX		 1971 }
1972
1973 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
1974 gen_io_start();
1975 }
1976
1977 disas_uc32_insn(env, dc);
1978
1979 if (num_temps) {
1980 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
1981 num_temps = 0;
1982 }
1983
1984 if (dc->condjmp && !dc->is_jmp) {
1985 gen_set_label(dc->condlabel);
1986 dc->condjmp = 0;
1987 }
1988 /* Translation stops when a conditional branch is encountered.
1989 * Otherwise the subsequent code could get translated several times.
1990 * Also stop translation when a page boundary is reached. This
1991 * ensures prefetch aborts occur at the right place. */
1992 num_insns++;
efd7f486 1993 } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
ed2803da 1994 !cs->singlestep_enabled &&
6e64da3c
GX		 1995 !singlestep &&
1996 dc->pc < next_page_start &&
1997 num_insns < max_insns);
1998
1999 if (tb->cflags & CF_LAST_IO) {
2000 if (dc->condjmp) {
2001 /* FIXME: This can theoretically happen with self-modifying
2002 code. */
a47dddd7 2003 cpu_abort(cs, "IO on conditional branch instruction");
6e64da3c
GX		 2004 }
2005 gen_io_end();
2006 }
2007
2008 /* At this stage dc->condjmp will only be set when the skipped
2009 instruction was a conditional branch or trap, and the PC has
2010 already been written. */
ed2803da 2011 if (unlikely(cs->singlestep_enabled)) {
6e64da3c
GX		 2012 /* Make sure the pc is updated, and raise a debug exception. */
2013 if (dc->condjmp) {
2014 if (dc->is_jmp == DISAS_SYSCALL) {
2015 gen_exception(UC32_EXCP_PRIV);
2016 } else {
2017 gen_exception(EXCP_DEBUG);
2018 }
2019 gen_set_label(dc->condlabel);
2020 }
2021 if (dc->condjmp || !dc->is_jmp) {
2022 gen_set_pc_im(dc->pc);
2023 dc->condjmp = 0;
2024 }
2025 if (dc->is_jmp == DISAS_SYSCALL && !dc->condjmp) {
2026 gen_exception(UC32_EXCP_PRIV);
2027 } else {
2028 gen_exception(EXCP_DEBUG);
2029 }
2030 } else {
2031 /* While branches must always occur at the end of an IT block,
2032 there are a few other things that can cause us to terminate
2033 the TB in the middel of an IT block:
2034 - Exception generating instructions (bkpt, swi, undefined).
2035 - Page boundaries.
2036 - Hardware watchpoints.
2037 Hardware breakpoints have already been handled and skip this code.
2038 */
2039 switch (dc->is_jmp) {
2040 case DISAS_NEXT:
2041 gen_goto_tb(dc, 1, dc->pc);
2042 break;
2043 default:
2044 case DISAS_JUMP:
2045 case DISAS_UPDATE:
2046 /* indicate that the hash table must be used to find the next TB */
2047 tcg_gen_exit_tb(0);
2048 break;
2049 case DISAS_TB_JUMP:
2050 /* nothing more to generate */
2051 break;
2052 case DISAS_SYSCALL:
2053 gen_exception(UC32_EXCP_PRIV);
2054 break;
2055 }
2056 if (dc->condjmp) {
2057 gen_set_label(dc->condlabel);
2058 gen_goto_tb(dc, 1, dc->pc);
2059 dc->condjmp = 0;
2060 }
2061 }
2062
2063done_generating:
806f352d 2064 gen_tb_end(tb, num_insns);
efd7f486 2065 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
6e64da3c
GX		 2066
2067#ifdef DEBUG_DISAS
2068 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
2069 qemu_log("----------------\n");
2070 qemu_log("IN: %s\n", lookup_symbol(pc_start));
f4359b9f 2071 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
6e64da3c
GX		 2072 qemu_log("\n");
2073 }
2074#endif
2075 if (search_pc) {
92414b31 2076 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
6e64da3c
GX		 2077 lj++;
2078 while (lj <= j) {
ab1103de 2079 tcg_ctx.gen_opc_instr_start[lj++] = 0;
6e64da3c
GX		 2080 }
2081 } else {
2082 tb->size = dc->pc - pc_start;
2083 tb->icount = num_insns;
2084 }
2085}
2086
eb23b556 2087void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
6e64da3c 2088{
62a80559 2089 gen_intermediate_code_internal(uc32_env_get_cpu(env), tb, false);
6e64da3c
GX		 2090}
2091
eb23b556 2092void gen_intermediate_code_pc(CPUUniCore32State *env, TranslationBlock *tb)
6e64da3c 2093{
62a80559 2094 gen_intermediate_code_internal(uc32_env_get_cpu(env), tb, true);
6e64da3c
GX		 2095}
2096
2097static const char *cpu_mode_names[16] = {
2098 "USER", "REAL", "INTR", "PRIV", "UM14", "UM15", "UM16", "TRAP",
2099 "UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
2100};
2101
1e5cdaa1 2102#undef UCF64_DUMP_STATE
c5240d82
GX		 2103#ifdef UCF64_DUMP_STATE
2104static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
2105 fprintf_function cpu_fprintf, int flags)
6e64da3c
GX		 2106{
2107 int i;
6e64da3c
GX		 2108 union {
2109 uint32_t i;
2110 float s;
2111 } s0, s1;
2112 CPU_DoubleU d;
2113 /* ??? This assumes float64 and double have the same layout.
2114 Oh well, it's only debug dumps. */
2115 union {
2116 float64 f64;
2117 double d;
2118 } d0;
c5240d82
GX		 2119
2120 for (i = 0; i < 16; i++) {
2121 d.d = env->ucf64.regs[i];
2122 s0.i = d.l.lower;
2123 s1.i = d.l.upper;
2124 d0.f64 = d.d;
2125 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
2126 i * 2, (int)s0.i, s0.s,
2127 i * 2 + 1, (int)s1.i, s1.s);
2128 cpu_fprintf(f, " d%02d=%" PRIx64 "(%8g)\n",
2129 i, (uint64_t)d0.f64, d0.d);
2130 }
2131 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
2132}
2133#else
2134#define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
6e64da3c 2135#endif
c5240d82 2136
878096ee
AF		 2137void uc32_cpu_dump_state(CPUState *cs, FILE *f,
2138 fprintf_function cpu_fprintf, int flags)
c5240d82 2139{
878096ee
AF		 2140 UniCore32CPU *cpu = UNICORE32_CPU(cs);
2141 CPUUniCore32State *env = &cpu->env;
c5240d82 2142 int i;
6e64da3c
GX		 2143 uint32_t psr;
2144
2145 for (i = 0; i < 32; i++) {
2146 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2147 if ((i % 4) == 3) {
2148 cpu_fprintf(f, "\n");
2149 } else {
2150 cpu_fprintf(f, " ");
2151 }
2152 }
2153 psr = cpu_asr_read(env);
2154 cpu_fprintf(f, "PSR=%08x %c%c%c%c %s\n",
2155 psr,
2156 psr & (1 << 31) ? 'N' : '-',
2157 psr & (1 << 30) ? 'Z' : '-',
2158 psr & (1 << 29) ? 'C' : '-',
2159 psr & (1 << 28) ? 'V' : '-',
2160 cpu_mode_names[psr & 0xf]);
2161
c5240d82 2162 cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
6e64da3c
GX		 2163}
2164
eb23b556 2165void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int pc_pos)
6e64da3c 2166{
25983cad 2167 env->regs[31] = tcg_ctx.gen_opc_pc[pc_pos];
6e64da3c 2168}
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