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1/*
2 * QEMU Xtensa CPU
3 *
5087a72c 4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
15be3171 31#include "cpu.h"
a4633e16 32#include "qemu-common.h"
004a5690 33#include "migration/vmstate.h"
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34
35
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36static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
37{
38 XtensaCPU *cpu = XTENSA_CPU(cs);
39
40 cpu->env.pc = value;
41}
42
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43static bool xtensa_cpu_has_work(CPUState *cs)
44{
45 XtensaCPU *cpu = XTENSA_CPU(cs);
46
47 return cpu->env.pending_irq_level;
48}
49
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50/* CPUClass::reset() */
51static void xtensa_cpu_reset(CPUState *s)
52{
53 XtensaCPU *cpu = XTENSA_CPU(s);
54 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
55 CPUXtensaState *env = &cpu->env;
56
57 xcc->parent_reset(s);
58
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59 env->exception_taken = 0;
60 env->pc = env->config->exception_vector[EXC_RESET];
61 env->sregs[LITBASE] &= ~1;
62 env->sregs[PS] = xtensa_option_enabled(env->config,
63 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
64 env->sregs[VECBASE] = env->config->vecbase;
65 env->sregs[IBREAKENABLE] = 0;
4e41d2f5 66 env->sregs[CACHEATTR] = 0x22222222;
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67 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
68 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
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69 env->sregs[CONFIGID0] = env->config->configid[0];
70 env->sregs[CONFIGID1] = env->config->configid[1];
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71
72 env->pending_irq_level = 0;
73 reset_mmu(env);
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74}
75
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76static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
77{
78 ObjectClass *oc;
79 char *typename;
80
81 if (cpu_model == NULL) {
82 return NULL;
83 }
84
85 typename = g_strdup_printf("%s-" TYPE_XTENSA_CPU, cpu_model);
86 oc = object_class_by_name(typename);
87 g_free(typename);
88 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
89 object_class_is_abstract(oc)) {
90 return NULL;
91 }
92 return oc;
93}
94
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95static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
96{
a0e372f0 97 CPUState *cs = CPU(dev);
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98 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
99
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100 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
101
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102 qemu_init_vcpu(cs);
103
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104 xcc->parent_realize(dev, errp);
105}
106
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107static void xtensa_cpu_initfn(Object *obj)
108{
c05efcb1 109 CPUState *cs = CPU(obj);
e554bbc6 110 XtensaCPU *cpu = XTENSA_CPU(obj);
67cce561 111 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
e554bbc6 112 CPUXtensaState *env = &cpu->env;
25733ead 113 static bool tcg_inited;
e554bbc6 114
c05efcb1 115 cs->env_ptr = env;
67cce561 116 env->config = xcc->config;
4bad9e39 117 cpu_exec_init(cs, &error_abort);
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118
119 if (tcg_enabled() && !tcg_inited) {
120 tcg_inited = true;
121 xtensa_translate_init();
25733ead 122 }
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123}
124
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125static const VMStateDescription vmstate_xtensa_cpu = {
126 .name = "cpu",
127 .unmigratable = 1,
128};
129
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130static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
131{
004a5690 132 DeviceClass *dc = DEVICE_CLASS(oc);
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133 CPUClass *cc = CPU_CLASS(oc);
134 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
135
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136 xcc->parent_realize = dc->realize;
137 dc->realize = xtensa_cpu_realizefn;
138
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139 xcc->parent_reset = cc->reset;
140 cc->reset = xtensa_cpu_reset;
004a5690 141
67cce561 142 cc->class_by_name = xtensa_cpu_class_by_name;
8c2e1b00 143 cc->has_work = xtensa_cpu_has_work;
97a8ea5a 144 cc->do_interrupt = xtensa_cpu_do_interrupt;
37f3616a 145 cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
878096ee 146 cc->dump_state = xtensa_cpu_dump_state;
f45748f1 147 cc->set_pc = xtensa_cpu_set_pc;
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148 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
149 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
2472b6c0 150 cc->gdb_stop_before_watchpoint = true;
00b941e5 151#ifndef CONFIG_USER_ONLY
93e22326 152 cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
00b941e5 153 cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
4246e225 154 cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
00b941e5 155#endif
86025ee4 156 cc->debug_excp_handler = xtensa_breakpoint_handler;
004a5690 157 dc->vmsd = &vmstate_xtensa_cpu;
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158
159 /*
160 * Reason: xtensa_cpu_initfn() calls cpu_exec_init(), which saves
161 * the object in cpus -> dangling pointer after final
162 * object_unref().
163 */
164 dc->cannot_destroy_with_object_finalize_yet = true;
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165}
166
167static const TypeInfo xtensa_cpu_type_info = {
168 .name = TYPE_XTENSA_CPU,
169 .parent = TYPE_CPU,
170 .instance_size = sizeof(XtensaCPU),
e554bbc6 171 .instance_init = xtensa_cpu_initfn,
67cce561 172 .abstract = true,
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173 .class_size = sizeof(XtensaCPUClass),
174 .class_init = xtensa_cpu_class_init,
175};
176
177static void xtensa_cpu_register_types(void)
178{
179 type_register_static(&xtensa_cpu_type_info);
180}
181
182type_init(xtensa_cpu_register_types)