[mirror_qemu.git] / target-xtensa / cpu.h

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef XTENSA_CPU_H
#define XTENSA_CPU_H

#define ALIGNED_ONLY
#define TARGET_LONG_BITS 32

#define CPUArchState struct CPUXtensaState

#include "qemu-common.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"

#define NB_MMU_MODES 4

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_PAGE_BITS 12

enum {
    /* Additional instructions */
    XTENSA_OPTION_CODE_DENSITY,
    XTENSA_OPTION_LOOP,
    XTENSA_OPTION_EXTENDED_L32R,
    XTENSA_OPTION_16_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL_HIGH,
    XTENSA_OPTION_32_BIT_IDIV,
    XTENSA_OPTION_MAC16,
    XTENSA_OPTION_MISC_OP_NSA,
    XTENSA_OPTION_MISC_OP_MINMAX,
    XTENSA_OPTION_MISC_OP_SEXT,
    XTENSA_OPTION_MISC_OP_CLAMPS,
    XTENSA_OPTION_COPROCESSOR,
    XTENSA_OPTION_BOOLEAN,
    XTENSA_OPTION_FP_COPROCESSOR,
    XTENSA_OPTION_MP_SYNCHRO,
    XTENSA_OPTION_CONDITIONAL_STORE,
    XTENSA_OPTION_ATOMCTL,
    XTENSA_OPTION_DEPBITS,

    /* Interrupts and exceptions */
    XTENSA_OPTION_EXCEPTION,
    XTENSA_OPTION_RELOCATABLE_VECTOR,
    XTENSA_OPTION_UNALIGNED_EXCEPTION,
    XTENSA_OPTION_INTERRUPT,
    XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
    XTENSA_OPTION_TIMER_INTERRUPT,

    /* Local memory */
    XTENSA_OPTION_ICACHE,
    XTENSA_OPTION_ICACHE_TEST,
    XTENSA_OPTION_ICACHE_INDEX_LOCK,
    XTENSA_OPTION_DCACHE,
    XTENSA_OPTION_DCACHE_TEST,
    XTENSA_OPTION_DCACHE_INDEX_LOCK,
    XTENSA_OPTION_IRAM,
    XTENSA_OPTION_IROM,
    XTENSA_OPTION_DRAM,
    XTENSA_OPTION_DROM,
    XTENSA_OPTION_XLMI,
    XTENSA_OPTION_HW_ALIGNMENT,
    XTENSA_OPTION_MEMORY_ECC_PARITY,

    /* Memory protection and translation */
    XTENSA_OPTION_REGION_PROTECTION,
    XTENSA_OPTION_REGION_TRANSLATION,
    XTENSA_OPTION_MMU,
    XTENSA_OPTION_CACHEATTR,

    /* Other */
    XTENSA_OPTION_WINDOWED_REGISTER,
    XTENSA_OPTION_PROCESSOR_INTERFACE,
    XTENSA_OPTION_MISC_SR,
    XTENSA_OPTION_THREAD_POINTER,
    XTENSA_OPTION_PROCESSOR_ID,
    XTENSA_OPTION_DEBUG,
    XTENSA_OPTION_TRACE_PORT,
};

enum {
    THREADPTR = 231,
    FCR = 232,
    FSR = 233,
};

enum {
    LBEG = 0,
    LEND = 1,
    LCOUNT = 2,
    SAR = 3,
    BR = 4,
    LITBASE = 5,
    SCOMPARE1 = 12,
    ACCLO = 16,
    ACCHI = 17,
    MR = 32,
    WINDOW_BASE = 72,
    WINDOW_START = 73,
    PTEVADDR = 83,
    RASID = 90,
    ITLBCFG = 91,
    DTLBCFG = 92,
    IBREAKENABLE = 96,
    CACHEATTR = 98,
    ATOMCTL = 99,
    IBREAKA = 128,
    DBREAKA = 144,
    DBREAKC = 160,
    CONFIGID0 = 176,
    EPC1 = 177,
    DEPC = 192,
    EPS2 = 194,
    CONFIGID1 = 208,
    EXCSAVE1 = 209,
    CPENABLE = 224,
    INTSET = 226,
    INTCLEAR = 227,
    INTENABLE = 228,
    PS = 230,
    VECBASE = 231,
    EXCCAUSE = 232,
    DEBUGCAUSE = 233,
    CCOUNT = 234,
    PRID = 235,
    ICOUNT = 236,
    ICOUNTLEVEL = 237,
    EXCVADDR = 238,
    CCOMPARE = 240,
    MISC = 244,
};

#define PS_INTLEVEL 0xf
#define PS_INTLEVEL_SHIFT 0

#define PS_EXCM 0x10
#define PS_UM 0x20

#define PS_RING 0xc0
#define PS_RING_SHIFT 6

#define PS_OWB 0xf00
#define PS_OWB_SHIFT 8

#define PS_CALLINC 0x30000
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_LEN 2

#define PS_WOE 0x40000

#define DEBUGCAUSE_IC 0x1
#define DEBUGCAUSE_IB 0x2
#define DEBUGCAUSE_DB 0x4
#define DEBUGCAUSE_BI 0x8
#define DEBUGCAUSE_BN 0x10
#define DEBUGCAUSE_DI 0x20
#define DEBUGCAUSE_DBNUM 0xf00
#define DEBUGCAUSE_DBNUM_SHIFT 8

#define DBREAKC_SB 0x80000000
#define DBREAKC_LB 0x40000000
#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
#define DBREAKC_MASK 0x3f

#define MAX_NAREG 64
#define MAX_NINTERRUPT 32
#define MAX_NLEVEL 6
#define MAX_NNMI 1
#define MAX_NCCOMPARE 3
#define MAX_TLB_WAY_SIZE 8
#define MAX_NDBREAK 2

#define REGION_PAGE_MASK 0xe0000000

#define PAGE_CACHE_MASK    0x700
#define PAGE_CACHE_SHIFT   8
#define PAGE_CACHE_INVALID 0x000
#define PAGE_CACHE_BYPASS  0x100
#define PAGE_CACHE_WT      0x200
#define PAGE_CACHE_WB      0x400
#define PAGE_CACHE_ISOLATE 0x600

enum {
    /* Static vectors */
    EXC_RESET,
    EXC_MEMORY_ERROR,

    /* Dynamic vectors */
    EXC_WINDOW_OVERFLOW4,
    EXC_WINDOW_UNDERFLOW4,
    EXC_WINDOW_OVERFLOW8,
    EXC_WINDOW_UNDERFLOW8,
    EXC_WINDOW_OVERFLOW12,
    EXC_WINDOW_UNDERFLOW12,
    EXC_IRQ,
    EXC_KERNEL,
    EXC_USER,
    EXC_DOUBLE,
    EXC_DEBUG,
    EXC_MAX
};

enum {
    ILLEGAL_INSTRUCTION_CAUSE = 0,
    SYSCALL_CAUSE,
    INSTRUCTION_FETCH_ERROR_CAUSE,
    LOAD_STORE_ERROR_CAUSE,
    LEVEL1_INTERRUPT_CAUSE,
    ALLOCA_CAUSE,
    INTEGER_DIVIDE_BY_ZERO_CAUSE,
    PRIVILEGED_CAUSE = 8,
    LOAD_STORE_ALIGNMENT_CAUSE,

    INSTR_PIF_DATA_ERROR_CAUSE = 12,
    LOAD_STORE_PIF_DATA_ERROR_CAUSE,
    INSTR_PIF_ADDR_ERROR_CAUSE,
    LOAD_STORE_PIF_ADDR_ERROR_CAUSE,

    INST_TLB_MISS_CAUSE,
    INST_TLB_MULTI_HIT_CAUSE,
    INST_FETCH_PRIVILEGE_CAUSE,
    INST_FETCH_PROHIBITED_CAUSE = 20,
    LOAD_STORE_TLB_MISS_CAUSE = 24,
    LOAD_STORE_TLB_MULTI_HIT_CAUSE,
    LOAD_STORE_PRIVILEGE_CAUSE,
    LOAD_PROHIBITED_CAUSE = 28,
    STORE_PROHIBITED_CAUSE,

    COPROCESSOR0_DISABLED = 32,
};

typedef enum {
    INTTYPE_LEVEL,
    INTTYPE_EDGE,
    INTTYPE_NMI,
    INTTYPE_SOFTWARE,
    INTTYPE_TIMER,
    INTTYPE_DEBUG,
    INTTYPE_WRITE_ERR,
    INTTYPE_PROFILING,
    INTTYPE_MAX
} interrupt_type;

typedef struct xtensa_tlb_entry {
    uint32_t vaddr;
    uint32_t paddr;
    uint8_t asid;
    uint8_t attr;
    bool variable;
} xtensa_tlb_entry;

typedef struct xtensa_tlb {
    unsigned nways;
    const unsigned way_size[10];
    bool varway56;
    unsigned nrefillentries;
} xtensa_tlb;

typedef struct XtensaGdbReg {
    int targno;
    int type;
    int group;
    unsigned size;
} XtensaGdbReg;

typedef struct XtensaGdbRegmap {
    int num_regs;
    int num_core_regs;
    /* PC + a + ar + sr + ur */
    XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
} XtensaGdbRegmap;

struct XtensaConfig {
    const char *name;
    uint64_t options;
    XtensaGdbRegmap gdb_regmap;
    unsigned nareg;
    int excm_level;
    int ndepc;
    uint32_t vecbase;
    uint32_t exception_vector[EXC_MAX];
    unsigned ninterrupt;
    unsigned nlevel;
    uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t inttype_mask[INTTYPE_MAX];
    struct {
        uint32_t level;
        interrupt_type inttype;
    } interrupt[MAX_NINTERRUPT];
    unsigned nccompare;
    uint32_t timerint[MAX_NCCOMPARE];
    unsigned nextint;
    unsigned extint[MAX_NINTERRUPT];

    unsigned debug_level;
    unsigned nibreak;
    unsigned ndbreak;

    uint32_t configid[2];

    uint32_t clock_freq_khz;

    xtensa_tlb itlb;
    xtensa_tlb dtlb;
};

typedef struct XtensaConfigList {
    const XtensaConfig *config;
    struct XtensaConfigList *next;
} XtensaConfigList;

#ifdef HOST_WORDS_BIGENDIAN
enum {
    FP_F32_HIGH,
    FP_F32_LOW,
};
#else
enum {
    FP_F32_LOW,
    FP_F32_HIGH,
};
#endif

typedef struct CPUXtensaState {
    const XtensaConfig *config;
    uint32_t regs[16];
    uint32_t pc;
    uint32_t sregs[256];
    uint32_t uregs[256];
    uint32_t phys_regs[MAX_NAREG];
    union {
        float32 f32[2];
        float64 f64;
    } fregs[16];
    float_status fp_status;

    xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
    xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
    unsigned autorefill_idx;

    int pending_irq_level; /* level of last raised IRQ */
    void **irq_inputs;
    QEMUTimer *ccompare_timer;
    uint32_t wake_ccount;
    int64_t halt_clock;

    int exception_taken;

    /* Watchpoints for DBREAK registers */
    struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];

    CPU_COMMON
} CPUXtensaState;

/**
 * XtensaCPU:
 * @env: #CPUXtensaState
 *
 * An Xtensa CPU.
 */
struct XtensaCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUXtensaState env;
};

static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
{
    return container_of(env, XtensaCPU, env);
}

#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))

#define ENV_OFFSET offsetof(XtensaCPU, env)

void xtensa_cpu_do_interrupt(CPUState *cpu);
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
                                     bool is_write, bool is_exec, int opaque,
                                     unsigned size);
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
                           fprintf_function cpu_fprintf, int flags);
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
                                    MMUAccessType access_type,
                                    int mmu_idx, uintptr_t retaddr);

#define cpu_signal_handler cpu_xtensa_signal_handler
#define cpu_list xtensa_cpu_list

#ifdef TARGET_WORDS_BIGENDIAN
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
#else
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
#endif

XtensaCPU *cpu_xtensa_init(const char *cpu_model);

#define cpu_init(cpu_model) CPU(cpu_xtensa_init(cpu_model))

void xtensa_translate_init(void);
void xtensa_breakpoint_handler(CPUState *cs);
void xtensa_finalize_config(XtensaConfig *config);
void xtensa_register_core(XtensaConfigList *node);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void xtensa_sync_window_from_phys(CPUXtensaState *env);
void xtensa_sync_phys_from_window(CPUXtensaState *env);
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
        uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
        uint32_t *pwi, uint32_t *pei, uint8_t *pring);
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
        xtensa_tlb_entry *entry, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
        uint32_t vaddr, int is_write, int mmu_idx,
        uint32_t *paddr, uint32_t *page_size, unsigned *access);
void reset_mmu(CPUXtensaState *env);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);


#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
#define XTENSA_OPTION_ALL (~(uint64_t)0)

static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
        uint64_t opt)
{
    return (config->options & opt) != 0;
}

static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
{
    return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
}

static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
{
    int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
    if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
        level = env->config->excm_level;
    }
    return level;
}

static inline int xtensa_get_ring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline int xtensa_get_cring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
            (env->sregs[PS] & PS_EXCM) == 0) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
        bool dtlb, unsigned wi, unsigned ei)
{
    return dtlb ?
        env->dtlb[wi] + ei :
        env->itlb[wi] + ei;
}

static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
{
    return env->sregs[WINDOW_START] |
        (env->sregs[WINDOW_START] << env->config->nareg / 4);
}

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _ring0
#define MMU_MODE1_SUFFIX _ring1
#define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3

static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
{
    return xtensa_get_cring(env);
}

#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
#define XTENSA_TBFLAG_DEBUG 0x10
#define XTENSA_TBFLAG_ICOUNT 0x20
#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
#define XTENSA_TBFLAG_EXCEPTION 0x4000
#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
#define XTENSA_TBFLAG_WINDOW_SHIFT 15

static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
        target_ulong *cs_base, uint32_t *flags)
{
    CPUState *cs = CPU(xtensa_env_get_cpu(env));

    *pc = env->pc;
    *cs_base = 0;
    *flags = 0;
    *flags |= xtensa_get_ring(env);
    if (env->sregs[PS] & PS_EXCM) {
        *flags |= XTENSA_TBFLAG_EXCM;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
            (env->sregs[LITBASE] & 1)) {
        *flags |= XTENSA_TBFLAG_LITBASE;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
        if (xtensa_get_cintlevel(env) < env->config->debug_level) {
            *flags |= XTENSA_TBFLAG_DEBUG;
        }
        if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
            *flags |= XTENSA_TBFLAG_ICOUNT;
        }
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
        *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
    }
    if (cs->singlestep_enabled && env->exception_taken) {
        *flags |= XTENSA_TBFLAG_EXCEPTION;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
        (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
        uint32_t windowstart = xtensa_replicate_windowstart(env) >>
            (env->sregs[WINDOW_BASE] + 1);
        uint32_t w = ctz32(windowstart | 0x8);

        *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
    } else {
        *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
    }
}

#include "exec/cpu-all.h"

#endif
Commit	Line	Data
2328826b MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
07f5a258 MA	28	#ifndef XTENSA_CPU_H
07f5a258 MA	29	#define XTENSA_CPU_H
2328826b	30
d94f0a8e	31	#define ALIGNED_ONLY
2328826b	32	#define TARGET_LONG_BITS 32
2328826b	33
9349b4f9	34	#define CPUArchState struct CPUXtensaState
2328826b	35
2328826b	36	#include "qemu-common.h"
da374261	37	#include "cpu-qom.h"
022c62cb	38	#include "exec/cpu-defs.h"
dd519cbe	39	#include "fpu/softfloat.h"
2328826b	40
2328826b MF	41	#define NB_MMU_MODES 4
	42
	43	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	44	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	45	#define TARGET_PAGE_BITS 12
	46
dedc5eae MF	47	enum {
	48	/* Additional instructions */
	49	XTENSA_OPTION_CODE_DENSITY,
	50	XTENSA_OPTION_LOOP,
	51	XTENSA_OPTION_EXTENDED_L32R,
	52	XTENSA_OPTION_16_BIT_IMUL,
	53	XTENSA_OPTION_32_BIT_IMUL,
7f65f4b0	54	XTENSA_OPTION_32_BIT_IMUL_HIGH,
dedc5eae MF	55	XTENSA_OPTION_32_BIT_IDIV,
dedc5eae MF	56	XTENSA_OPTION_MAC16,
7f65f4b0 MF	57	XTENSA_OPTION_MISC_OP_NSA,
	58	XTENSA_OPTION_MISC_OP_MINMAX,
	59	XTENSA_OPTION_MISC_OP_SEXT,
	60	XTENSA_OPTION_MISC_OP_CLAMPS,
dedc5eae MF	61	XTENSA_OPTION_COPROCESSOR,
	62	XTENSA_OPTION_BOOLEAN,
	63	XTENSA_OPTION_FP_COPROCESSOR,
	64	XTENSA_OPTION_MP_SYNCHRO,
	65	XTENSA_OPTION_CONDITIONAL_STORE,
fcc803d1	66	XTENSA_OPTION_ATOMCTL,
5eeb40c5	67	XTENSA_OPTION_DEPBITS,
dedc5eae MF	68
	69	/* Interrupts and exceptions */
	70	XTENSA_OPTION_EXCEPTION,
	71	XTENSA_OPTION_RELOCATABLE_VECTOR,
	72	XTENSA_OPTION_UNALIGNED_EXCEPTION,
	73	XTENSA_OPTION_INTERRUPT,
	74	XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
	75	XTENSA_OPTION_TIMER_INTERRUPT,
	76
	77	/* Local memory */
	78	XTENSA_OPTION_ICACHE,
	79	XTENSA_OPTION_ICACHE_TEST,
	80	XTENSA_OPTION_ICACHE_INDEX_LOCK,
	81	XTENSA_OPTION_DCACHE,
	82	XTENSA_OPTION_DCACHE_TEST,
	83	XTENSA_OPTION_DCACHE_INDEX_LOCK,
	84	XTENSA_OPTION_IRAM,
	85	XTENSA_OPTION_IROM,
	86	XTENSA_OPTION_DRAM,
	87	XTENSA_OPTION_DROM,
	88	XTENSA_OPTION_XLMI,
	89	XTENSA_OPTION_HW_ALIGNMENT,
	90	XTENSA_OPTION_MEMORY_ECC_PARITY,
	91
	92	/* Memory protection and translation */
	93	XTENSA_OPTION_REGION_PROTECTION,
	94	XTENSA_OPTION_REGION_TRANSLATION,
	95	XTENSA_OPTION_MMU,
4e41d2f5	96	XTENSA_OPTION_CACHEATTR,
dedc5eae MF	97
	98	/* Other */
	99	XTENSA_OPTION_WINDOWED_REGISTER,
	100	XTENSA_OPTION_PROCESSOR_INTERFACE,
	101	XTENSA_OPTION_MISC_SR,
	102	XTENSA_OPTION_THREAD_POINTER,
	103	XTENSA_OPTION_PROCESSOR_ID,
	104	XTENSA_OPTION_DEBUG,
	105	XTENSA_OPTION_TRACE_PORT,
	106	};
	107
2af3da91 MF	108	enum {
	109	THREADPTR = 231,
	110	FCR = 232,
	111	FSR = 233,
	112	};
	113
3580ecad	114	enum {
797d780b MF	115	LBEG = 0,
	116	LEND = 1,
	117	LCOUNT = 2,
3580ecad	118	SAR = 3,
4dd85b6b	119	BR = 4,
6ad6dbf7	120	LITBASE = 5,
809377aa	121	SCOMPARE1 = 12,
6825b6c3 MF	122	ACCLO = 16,
	123	ACCHI = 17,
	124	MR = 32,
553e44f9 MF	125	WINDOW_BASE = 72,
553e44f9 MF	126	WINDOW_START = 73,
b67ea0cd MF	127	PTEVADDR = 83,
	128	RASID = 90,
	129	ITLBCFG = 91,
	130	DTLBCFG = 92,
e61dc8f7	131	IBREAKENABLE = 96,
4e41d2f5	132	CACHEATTR = 98,
fcc803d1	133	ATOMCTL = 99,
e61dc8f7	134	IBREAKA = 128,
f14c4b5f MF	135	DBREAKA = 144,
f14c4b5f MF	136	DBREAKC = 160,
604e1f9c	137	CONFIGID0 = 176,
40643d7c MF	138	EPC1 = 177,
40643d7c MF	139	DEPC = 192,
b994e91b	140	EPS2 = 194,
604e1f9c	141	CONFIGID1 = 208,
40643d7c	142	EXCSAVE1 = 209,
f3df4c04	143	CPENABLE = 224,
b994e91b MF	144	INTSET = 226,
	145	INTCLEAR = 227,
	146	INTENABLE = 228,
f0a548b9	147	PS = 230,
97836cee	148	VECBASE = 231,
40643d7c	149	EXCCAUSE = 232,
ab58c5b4	150	DEBUGCAUSE = 233,
b994e91b	151	CCOUNT = 234,
f3df4c04	152	PRID = 235,
35b5c044 MF	153	ICOUNT = 236,
35b5c044 MF	154	ICOUNTLEVEL = 237,
40643d7c	155	EXCVADDR = 238,
b994e91b	156	CCOMPARE = 240,
b7909d81	157	MISC = 244,
3580ecad MF	158	};
3580ecad MF	159
f0a548b9 MF	160	#define PS_INTLEVEL 0xf
	161	#define PS_INTLEVEL_SHIFT 0
	162
	163	#define PS_EXCM 0x10
	164	#define PS_UM 0x20
	165
	166	#define PS_RING 0xc0
	167	#define PS_RING_SHIFT 6
	168
	169	#define PS_OWB 0xf00
	170	#define PS_OWB_SHIFT 8
	171
	172	#define PS_CALLINC 0x30000
	173	#define PS_CALLINC_SHIFT 16
	174	#define PS_CALLINC_LEN 2
	175
	176	#define PS_WOE 0x40000
	177
ab58c5b4 MF	178	#define DEBUGCAUSE_IC 0x1
	179	#define DEBUGCAUSE_IB 0x2
	180	#define DEBUGCAUSE_DB 0x4
	181	#define DEBUGCAUSE_BI 0x8
	182	#define DEBUGCAUSE_BN 0x10
	183	#define DEBUGCAUSE_DI 0x20
	184	#define DEBUGCAUSE_DBNUM 0xf00
	185	#define DEBUGCAUSE_DBNUM_SHIFT 8
	186
f14c4b5f MF	187	#define DBREAKC_SB 0x80000000
	188	#define DBREAKC_LB 0x40000000
	189	#define DBREAKC_SB_LB (DBREAKC_SB \| DBREAKC_LB)
	190	#define DBREAKC_MASK 0x3f
	191
553e44f9	192	#define MAX_NAREG 64
b994e91b MF	193	#define MAX_NINTERRUPT 32
	194	#define MAX_NLEVEL 6
	195	#define MAX_NNMI 1
	196	#define MAX_NCCOMPARE 3
b67ea0cd	197	#define MAX_TLB_WAY_SIZE 8
f14c4b5f	198	#define MAX_NDBREAK 2
b67ea0cd MF	199
b67ea0cd MF	200	#define REGION_PAGE_MASK 0xe0000000
553e44f9	201
fcc803d1 MF	202	#define PAGE_CACHE_MASK 0x700
	203	#define PAGE_CACHE_SHIFT 8
	204	#define PAGE_CACHE_INVALID 0x000
	205	#define PAGE_CACHE_BYPASS 0x100
	206	#define PAGE_CACHE_WT 0x200
	207	#define PAGE_CACHE_WB 0x400
	208	#define PAGE_CACHE_ISOLATE 0x600
	209
40643d7c MF	210	enum {
	211	/* Static vectors */
	212	EXC_RESET,
	213	EXC_MEMORY_ERROR,
	214
	215	/* Dynamic vectors */
	216	EXC_WINDOW_OVERFLOW4,
	217	EXC_WINDOW_UNDERFLOW4,
	218	EXC_WINDOW_OVERFLOW8,
	219	EXC_WINDOW_UNDERFLOW8,
	220	EXC_WINDOW_OVERFLOW12,
	221	EXC_WINDOW_UNDERFLOW12,
	222	EXC_IRQ,
	223	EXC_KERNEL,
	224	EXC_USER,
	225	EXC_DOUBLE,
e61dc8f7	226	EXC_DEBUG,
40643d7c MF	227	EXC_MAX
	228	};
	229
	230	enum {
	231	ILLEGAL_INSTRUCTION_CAUSE = 0,
	232	SYSCALL_CAUSE,
	233	INSTRUCTION_FETCH_ERROR_CAUSE,
	234	LOAD_STORE_ERROR_CAUSE,
	235	LEVEL1_INTERRUPT_CAUSE,
	236	ALLOCA_CAUSE,
	237	INTEGER_DIVIDE_BY_ZERO_CAUSE,
	238	PRIVILEGED_CAUSE = 8,
	239	LOAD_STORE_ALIGNMENT_CAUSE,
	240
	241	INSTR_PIF_DATA_ERROR_CAUSE = 12,
	242	LOAD_STORE_PIF_DATA_ERROR_CAUSE,
	243	INSTR_PIF_ADDR_ERROR_CAUSE,
	244	LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
	245
	246	INST_TLB_MISS_CAUSE,
	247	INST_TLB_MULTI_HIT_CAUSE,
	248	INST_FETCH_PRIVILEGE_CAUSE,
	249	INST_FETCH_PROHIBITED_CAUSE = 20,
	250	LOAD_STORE_TLB_MISS_CAUSE = 24,
	251	LOAD_STORE_TLB_MULTI_HIT_CAUSE,
	252	LOAD_STORE_PRIVILEGE_CAUSE,
	253	LOAD_PROHIBITED_CAUSE = 28,
	254	STORE_PROHIBITED_CAUSE,
	255
	256	COPROCESSOR0_DISABLED = 32,
	257	};
	258
b994e91b MF	259	typedef enum {
	260	INTTYPE_LEVEL,
	261	INTTYPE_EDGE,
	262	INTTYPE_NMI,
	263	INTTYPE_SOFTWARE,
	264	INTTYPE_TIMER,
	265	INTTYPE_DEBUG,
	266	INTTYPE_WRITE_ERR,
dec71d2d	267	INTTYPE_PROFILING,
b994e91b MF	268	INTTYPE_MAX
	269	} interrupt_type;
	270
b67ea0cd MF	271	typedef struct xtensa_tlb_entry {
	272	uint32_t vaddr;
	273	uint32_t paddr;
	274	uint8_t asid;
	275	uint8_t attr;
	276	bool variable;
	277	} xtensa_tlb_entry;
	278
	279	typedef struct xtensa_tlb {
	280	unsigned nways;
	281	const unsigned way_size[10];
	282	bool varway56;
	283	unsigned nrefillentries;
	284	} xtensa_tlb;
	285
ccfcaba6 MF	286	typedef struct XtensaGdbReg {
	287	int targno;
	288	int type;
	289	int group;
ddd44279	290	unsigned size;
ccfcaba6 MF	291	} XtensaGdbReg;
	292
	293	typedef struct XtensaGdbRegmap {
	294	int num_regs;
	295	int num_core_regs;
	296	/* PC + a + ar + sr + ur */
	297	XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
	298	} XtensaGdbRegmap;
	299
da374261	300	struct XtensaConfig {
dedc5eae MF	301	const char *name;
dedc5eae MF	302	uint64_t options;
ccfcaba6	303	XtensaGdbRegmap gdb_regmap;
553e44f9	304	unsigned nareg;
40643d7c MF	305	int excm_level;
40643d7c MF	306	int ndepc;
97836cee	307	uint32_t vecbase;
40643d7c	308	uint32_t exception_vector[EXC_MAX];
b994e91b MF	309	unsigned ninterrupt;
	310	unsigned nlevel;
	311	uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
	312	uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
	313	uint32_t inttype_mask[INTTYPE_MAX];
	314	struct {
	315	uint32_t level;
	316	interrupt_type inttype;
	317	} interrupt[MAX_NINTERRUPT];
	318	unsigned nccompare;
	319	uint32_t timerint[MAX_NCCOMPARE];
b8929a54 MF	320	unsigned nextint;
b8929a54 MF	321	unsigned extint[MAX_NINTERRUPT];
ab58c5b4 MF	322
	323	unsigned debug_level;
	324	unsigned nibreak;
	325	unsigned ndbreak;
	326
604e1f9c MF	327	uint32_t configid[2];
604e1f9c MF	328
b994e91b	329	uint32_t clock_freq_khz;
b67ea0cd MF	330
	331	xtensa_tlb itlb;
	332	xtensa_tlb dtlb;
da374261	333	};
dedc5eae	334
ac8b7db4 MF	335	typedef struct XtensaConfigList {
	336	const XtensaConfig *config;
	337	struct XtensaConfigList *next;
	338	} XtensaConfigList;
	339
ddd44279 MF	340	#ifdef HOST_WORDS_BIGENDIAN
	341	enum {
	342	FP_F32_HIGH,
	343	FP_F32_LOW,
	344	};
	345	#else
	346	enum {
	347	FP_F32_LOW,
	348	FP_F32_HIGH,
	349	};
	350	#endif
	351
2328826b	352	typedef struct CPUXtensaState {
dedc5eae	353	const XtensaConfig *config;
2328826b MF	354	uint32_t regs[16];
	355	uint32_t pc;
	356	uint32_t sregs[256];
2af3da91	357	uint32_t uregs[256];
553e44f9	358	uint32_t phys_regs[MAX_NAREG];
ddd44279 MF	359	union {
	360	float32 f32[2];
	361	float64 f64;
	362	} fregs[16];
dd519cbe	363	float_status fp_status;
2328826b	364
b67ea0cd MF	365	xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
	366	xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
	367	unsigned autorefill_idx;
	368
b994e91b MF	369	int pending_irq_level; /* level of last raised IRQ */
	370	void **irq_inputs;
	371	QEMUTimer *ccompare_timer;
	372	uint32_t wake_ccount;
	373	int64_t halt_clock;
	374
40643d7c MF	375	int exception_taken;
40643d7c MF	376
f14c4b5f	377	/* Watchpoints for DBREAK registers */
ff4700b0	378	struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
f14c4b5f	379
2328826b MF	380	CPU_COMMON
	381	} CPUXtensaState;
	382
da374261 PB	383	/**
	384	* XtensaCPU:
	385	* @env: #CPUXtensaState
	386	*
	387	* An Xtensa CPU.
	388	*/
	389	struct XtensaCPU {
	390	/< private >/
	391	CPUState parent_obj;
	392	/< public >/
	393
	394	CPUXtensaState env;
	395	};
	396
	397	static inline XtensaCPU xtensa_env_get_cpu(const CPUXtensaState env)
	398	{
	399	return container_of(env, XtensaCPU, env);
	400	}
	401
	402	#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
	403
	404	#define ENV_OFFSET offsetof(XtensaCPU, env)
	405
	406	void xtensa_cpu_do_interrupt(CPUState *cpu);
	407	bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
	408	void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
	409	bool is_write, bool is_exec, int opaque,
	410	unsigned size);
	411	void xtensa_cpu_dump_state(CPUState cpu, FILE f,
	412	fprintf_function cpu_fprintf, int flags);
	413	hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	414	int xtensa_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
	415	int xtensa_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	416	void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
b35399bb SS	417	MMUAccessType access_type,
b35399bb SS	418	int mmu_idx, uintptr_t retaddr);
15be3171	419
2328826b MF	420	#define cpu_signal_handler cpu_xtensa_signal_handler
	421	#define cpu_list xtensa_cpu_list
	422
e38077ff MF	423	#ifdef TARGET_WORDS_BIGENDIAN
	424	#define XTENSA_DEFAULT_CPU_MODEL "fsf"
	425	#else
	426	#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
	427	#endif
	428
15be3171 AF	429	XtensaCPU cpu_xtensa_init(const char cpu_model);
15be3171 AF	430
2994fd96	431	#define cpu_init(cpu_model) CPU(cpu_xtensa_init(cpu_model))
15be3171	432
2328826b	433	void xtensa_translate_init(void);
86025ee4	434	void xtensa_breakpoint_handler(CPUState *cs);
1479073b	435	void xtensa_finalize_config(XtensaConfig *config);
ac8b7db4	436	void xtensa_register_core(XtensaConfigList *node);
b994e91b	437	void check_interrupts(CPUXtensaState *s);
97129ac8 AF	438	void xtensa_irq_init(CPUXtensaState *env);
	439	void xtensa_get_extint(CPUXtensaState env, unsigned extint);
	440	void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
	441	void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
	442	void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
2328826b MF	443	int cpu_xtensa_signal_handler(int host_signum, void pinfo, void puc);
2328826b MF	444	void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
97129ac8 AF	445	void xtensa_sync_window_from_phys(CPUXtensaState *env);
	446	void xtensa_sync_phys_from_window(CPUXtensaState *env);
	447	uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
	448	void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
b67ea0cd	449	uint32_t vpn, uint32_t wi, uint32_t ei);
97129ac8	450	int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
b67ea0cd	451	uint32_t pwi, uint32_t pei, uint8_t *pring);
16bde77a MF	452	void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
	453	xtensa_tlb_entry *entry, bool dtlb,
	454	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
97129ac8	455	void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
b67ea0cd	456	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
ae4e7982	457	int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
b67ea0cd MF	458	uint32_t vaddr, int is_write, int mmu_idx,
b67ea0cd MF	459	uint32_t paddr, uint32_t page_size, unsigned *access);
5087a72c	460	void reset_mmu(CPUXtensaState *env);
97129ac8 AF	461	void dump_mmu(FILE f, fprintf_function cpu_fprintf, CPUXtensaState env);
97129ac8 AF	462	void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
b67ea0cd	463
2328826b	464
dedc5eae	465	#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
fe0bd475	466	#define XTENSA_OPTION_ALL (~(uint64_t)0)
dedc5eae	467
b67ea0cd MF	468	static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
	469	uint64_t opt)
	470	{
	471	return (config->options & opt) != 0;
	472	}
	473
dedc5eae MF	474	static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
dedc5eae MF	475	{
b67ea0cd	476	return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
dedc5eae MF	477	}
dedc5eae MF	478
97129ac8	479	static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
40643d7c MF	480	{
	481	int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
	482	if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
	483	level = env->config->excm_level;
	484	}
	485	return level;
	486	}
	487
97129ac8	488	static inline int xtensa_get_ring(const CPUXtensaState *env)
f0a548b9 MF	489	{
	490	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
	491	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	492	} else {
	493	return 0;
	494	}
	495	}
	496
97129ac8	497	static inline int xtensa_get_cring(const CPUXtensaState *env)
f0a548b9 MF	498	{
	499	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
	500	(env->sregs[PS] & PS_EXCM) == 0) {
	501	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	502	} else {
	503	return 0;
	504	}
	505	}
	506
97129ac8	507	static inline xtensa_tlb_entry xtensa_tlb_get_entry(CPUXtensaState env,
b67ea0cd MF	508	bool dtlb, unsigned wi, unsigned ei)
	509	{
	510	return dtlb ?
	511	env->dtlb[wi] + ei :
	512	env->itlb[wi] + ei;
	513	}
	514
1b3e71f8 MF	515	static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
	516	{
	517	return env->sregs[WINDOW_START] \|
	518	(env->sregs[WINDOW_START] << env->config->nareg / 4);
	519	}
	520
f0a548b9 MF	521	/* MMU modes definitions */
	522	#define MMU_MODE0_SUFFIX _ring0
	523	#define MMU_MODE1_SUFFIX _ring1
	524	#define MMU_MODE2_SUFFIX _ring2
	525	#define MMU_MODE3_SUFFIX _ring3
	526
97ed5ccd	527	static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
2328826b	528	{
f0a548b9	529	return xtensa_get_cring(env);
2328826b MF	530	}
2328826b MF	531
f0a548b9 MF	532	#define XTENSA_TBFLAG_RING_MASK 0x3
f0a548b9 MF	533	#define XTENSA_TBFLAG_EXCM 0x4
6ad6dbf7	534	#define XTENSA_TBFLAG_LITBASE 0x8
e61dc8f7	535	#define XTENSA_TBFLAG_DEBUG 0x10
35b5c044	536	#define XTENSA_TBFLAG_ICOUNT 0x20
ef04a846 MF	537	#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
ef04a846 MF	538	#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
a00817cc	539	#define XTENSA_TBFLAG_EXCEPTION 0x4000
2db59a76 MF	540	#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
2db59a76 MF	541	#define XTENSA_TBFLAG_WINDOW_SHIFT 15
f0a548b9	542
97129ac8	543	static inline void cpu_get_tb_cpu_state(CPUXtensaState env, target_ulong pc,
89fee74a	544	target_ulong cs_base, uint32_t flags)
2328826b	545	{
1cf5ccbc AF	546	CPUState *cs = CPU(xtensa_env_get_cpu(env));
1cf5ccbc AF	547
2328826b MF	548	*pc = env->pc;
	549	*cs_base = 0;
	550	*flags = 0;
f0a548b9 MF	551	*flags \|= xtensa_get_ring(env);
	552	if (env->sregs[PS] & PS_EXCM) {
	553	*flags \|= XTENSA_TBFLAG_EXCM;
	554	}
6ad6dbf7 MF	555	if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
	556	(env->sregs[LITBASE] & 1)) {
	557	*flags \|= XTENSA_TBFLAG_LITBASE;
	558	}
e61dc8f7 MF	559	if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
	560	if (xtensa_get_cintlevel(env) < env->config->debug_level) {
	561	*flags \|= XTENSA_TBFLAG_DEBUG;
	562	}
35b5c044 MF	563	if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
	564	*flags \|= XTENSA_TBFLAG_ICOUNT;
	565	}
e61dc8f7	566	}
ef04a846 MF	567	if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
	568	*flags \|= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
	569	}
1cf5ccbc	570	if (cs->singlestep_enabled && env->exception_taken) {
a00817cc MF	571	*flags \|= XTENSA_TBFLAG_EXCEPTION;
a00817cc MF	572	}
2db59a76 MF	573	if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
	574	(env->sregs[PS] & (PS_WOE \| PS_EXCM)) == PS_WOE) {
	575	uint32_t windowstart = xtensa_replicate_windowstart(env) >>
	576	(env->sregs[WINDOW_BASE] + 1);
	577	uint32_t w = ctz32(windowstart \| 0x8);
	578
	579	*flags \|= w << XTENSA_TBFLAG_WINDOW_SHIFT;
	580	} else {
	581	*flags \|= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
	582	}
2328826b MF	583	}
2328826b MF	584
022c62cb	585	#include "exec/cpu-all.h"
2328826b	586
2328826b	587	#endif