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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #ifndef CPU_XTENSA_H | |
29 | #define CPU_XTENSA_H | |
30 | ||
31 | #define TARGET_LONG_BITS 32 | |
32 | #define ELF_MACHINE EM_XTENSA | |
33 | ||
34 | #define CPUState struct CPUXtensaState | |
35 | ||
36 | #include "config.h" | |
37 | #include "qemu-common.h" | |
38 | #include "cpu-defs.h" | |
39 | ||
40 | #define TARGET_HAS_ICE 1 | |
41 | ||
42 | #define NB_MMU_MODES 4 | |
43 | ||
44 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
45 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
46 | #define TARGET_PAGE_BITS 12 | |
47 | ||
dedc5eae MF |
48 | enum { |
49 | /* Additional instructions */ | |
50 | XTENSA_OPTION_CODE_DENSITY, | |
51 | XTENSA_OPTION_LOOP, | |
52 | XTENSA_OPTION_EXTENDED_L32R, | |
53 | XTENSA_OPTION_16_BIT_IMUL, | |
54 | XTENSA_OPTION_32_BIT_IMUL, | |
55 | XTENSA_OPTION_32_BIT_IDIV, | |
56 | XTENSA_OPTION_MAC16, | |
57 | XTENSA_OPTION_MISC_OP, | |
58 | XTENSA_OPTION_COPROCESSOR, | |
59 | XTENSA_OPTION_BOOLEAN, | |
60 | XTENSA_OPTION_FP_COPROCESSOR, | |
61 | XTENSA_OPTION_MP_SYNCHRO, | |
62 | XTENSA_OPTION_CONDITIONAL_STORE, | |
63 | ||
64 | /* Interrupts and exceptions */ | |
65 | XTENSA_OPTION_EXCEPTION, | |
66 | XTENSA_OPTION_RELOCATABLE_VECTOR, | |
67 | XTENSA_OPTION_UNALIGNED_EXCEPTION, | |
68 | XTENSA_OPTION_INTERRUPT, | |
69 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, | |
70 | XTENSA_OPTION_TIMER_INTERRUPT, | |
71 | ||
72 | /* Local memory */ | |
73 | XTENSA_OPTION_ICACHE, | |
74 | XTENSA_OPTION_ICACHE_TEST, | |
75 | XTENSA_OPTION_ICACHE_INDEX_LOCK, | |
76 | XTENSA_OPTION_DCACHE, | |
77 | XTENSA_OPTION_DCACHE_TEST, | |
78 | XTENSA_OPTION_DCACHE_INDEX_LOCK, | |
79 | XTENSA_OPTION_IRAM, | |
80 | XTENSA_OPTION_IROM, | |
81 | XTENSA_OPTION_DRAM, | |
82 | XTENSA_OPTION_DROM, | |
83 | XTENSA_OPTION_XLMI, | |
84 | XTENSA_OPTION_HW_ALIGNMENT, | |
85 | XTENSA_OPTION_MEMORY_ECC_PARITY, | |
86 | ||
87 | /* Memory protection and translation */ | |
88 | XTENSA_OPTION_REGION_PROTECTION, | |
89 | XTENSA_OPTION_REGION_TRANSLATION, | |
90 | XTENSA_OPTION_MMU, | |
91 | ||
92 | /* Other */ | |
93 | XTENSA_OPTION_WINDOWED_REGISTER, | |
94 | XTENSA_OPTION_PROCESSOR_INTERFACE, | |
95 | XTENSA_OPTION_MISC_SR, | |
96 | XTENSA_OPTION_THREAD_POINTER, | |
97 | XTENSA_OPTION_PROCESSOR_ID, | |
98 | XTENSA_OPTION_DEBUG, | |
99 | XTENSA_OPTION_TRACE_PORT, | |
100 | }; | |
101 | ||
2af3da91 MF |
102 | enum { |
103 | THREADPTR = 231, | |
104 | FCR = 232, | |
105 | FSR = 233, | |
106 | }; | |
107 | ||
3580ecad | 108 | enum { |
797d780b MF |
109 | LBEG = 0, |
110 | LEND = 1, | |
111 | LCOUNT = 2, | |
3580ecad | 112 | SAR = 3, |
6ad6dbf7 | 113 | LITBASE = 5, |
809377aa | 114 | SCOMPARE1 = 12, |
553e44f9 MF |
115 | WINDOW_BASE = 72, |
116 | WINDOW_START = 73, | |
40643d7c MF |
117 | EPC1 = 177, |
118 | DEPC = 192, | |
b994e91b | 119 | EPS2 = 194, |
40643d7c | 120 | EXCSAVE1 = 209, |
f3df4c04 | 121 | CPENABLE = 224, |
b994e91b MF |
122 | INTSET = 226, |
123 | INTCLEAR = 227, | |
124 | INTENABLE = 228, | |
f0a548b9 | 125 | PS = 230, |
97836cee | 126 | VECBASE = 231, |
40643d7c | 127 | EXCCAUSE = 232, |
b994e91b | 128 | CCOUNT = 234, |
f3df4c04 | 129 | PRID = 235, |
40643d7c | 130 | EXCVADDR = 238, |
b994e91b | 131 | CCOMPARE = 240, |
3580ecad MF |
132 | }; |
133 | ||
f0a548b9 MF |
134 | #define PS_INTLEVEL 0xf |
135 | #define PS_INTLEVEL_SHIFT 0 | |
136 | ||
137 | #define PS_EXCM 0x10 | |
138 | #define PS_UM 0x20 | |
139 | ||
140 | #define PS_RING 0xc0 | |
141 | #define PS_RING_SHIFT 6 | |
142 | ||
143 | #define PS_OWB 0xf00 | |
144 | #define PS_OWB_SHIFT 8 | |
145 | ||
146 | #define PS_CALLINC 0x30000 | |
147 | #define PS_CALLINC_SHIFT 16 | |
148 | #define PS_CALLINC_LEN 2 | |
149 | ||
150 | #define PS_WOE 0x40000 | |
151 | ||
553e44f9 | 152 | #define MAX_NAREG 64 |
b994e91b MF |
153 | #define MAX_NINTERRUPT 32 |
154 | #define MAX_NLEVEL 6 | |
155 | #define MAX_NNMI 1 | |
156 | #define MAX_NCCOMPARE 3 | |
553e44f9 | 157 | |
40643d7c MF |
158 | enum { |
159 | /* Static vectors */ | |
160 | EXC_RESET, | |
161 | EXC_MEMORY_ERROR, | |
162 | ||
163 | /* Dynamic vectors */ | |
164 | EXC_WINDOW_OVERFLOW4, | |
165 | EXC_WINDOW_UNDERFLOW4, | |
166 | EXC_WINDOW_OVERFLOW8, | |
167 | EXC_WINDOW_UNDERFLOW8, | |
168 | EXC_WINDOW_OVERFLOW12, | |
169 | EXC_WINDOW_UNDERFLOW12, | |
170 | EXC_IRQ, | |
171 | EXC_KERNEL, | |
172 | EXC_USER, | |
173 | EXC_DOUBLE, | |
174 | EXC_MAX | |
175 | }; | |
176 | ||
177 | enum { | |
178 | ILLEGAL_INSTRUCTION_CAUSE = 0, | |
179 | SYSCALL_CAUSE, | |
180 | INSTRUCTION_FETCH_ERROR_CAUSE, | |
181 | LOAD_STORE_ERROR_CAUSE, | |
182 | LEVEL1_INTERRUPT_CAUSE, | |
183 | ALLOCA_CAUSE, | |
184 | INTEGER_DIVIDE_BY_ZERO_CAUSE, | |
185 | PRIVILEGED_CAUSE = 8, | |
186 | LOAD_STORE_ALIGNMENT_CAUSE, | |
187 | ||
188 | INSTR_PIF_DATA_ERROR_CAUSE = 12, | |
189 | LOAD_STORE_PIF_DATA_ERROR_CAUSE, | |
190 | INSTR_PIF_ADDR_ERROR_CAUSE, | |
191 | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, | |
192 | ||
193 | INST_TLB_MISS_CAUSE, | |
194 | INST_TLB_MULTI_HIT_CAUSE, | |
195 | INST_FETCH_PRIVILEGE_CAUSE, | |
196 | INST_FETCH_PROHIBITED_CAUSE = 20, | |
197 | LOAD_STORE_TLB_MISS_CAUSE = 24, | |
198 | LOAD_STORE_TLB_MULTI_HIT_CAUSE, | |
199 | LOAD_STORE_PRIVILEGE_CAUSE, | |
200 | LOAD_PROHIBITED_CAUSE = 28, | |
201 | STORE_PROHIBITED_CAUSE, | |
202 | ||
203 | COPROCESSOR0_DISABLED = 32, | |
204 | }; | |
205 | ||
b994e91b MF |
206 | typedef enum { |
207 | INTTYPE_LEVEL, | |
208 | INTTYPE_EDGE, | |
209 | INTTYPE_NMI, | |
210 | INTTYPE_SOFTWARE, | |
211 | INTTYPE_TIMER, | |
212 | INTTYPE_DEBUG, | |
213 | INTTYPE_WRITE_ERR, | |
214 | INTTYPE_MAX | |
215 | } interrupt_type; | |
216 | ||
dedc5eae MF |
217 | typedef struct XtensaConfig { |
218 | const char *name; | |
219 | uint64_t options; | |
553e44f9 | 220 | unsigned nareg; |
40643d7c MF |
221 | int excm_level; |
222 | int ndepc; | |
97836cee | 223 | uint32_t vecbase; |
40643d7c | 224 | uint32_t exception_vector[EXC_MAX]; |
b994e91b MF |
225 | unsigned ninterrupt; |
226 | unsigned nlevel; | |
227 | uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; | |
228 | uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; | |
229 | uint32_t inttype_mask[INTTYPE_MAX]; | |
230 | struct { | |
231 | uint32_t level; | |
232 | interrupt_type inttype; | |
233 | } interrupt[MAX_NINTERRUPT]; | |
234 | unsigned nccompare; | |
235 | uint32_t timerint[MAX_NCCOMPARE]; | |
236 | uint32_t clock_freq_khz; | |
dedc5eae MF |
237 | } XtensaConfig; |
238 | ||
2328826b | 239 | typedef struct CPUXtensaState { |
dedc5eae | 240 | const XtensaConfig *config; |
2328826b MF |
241 | uint32_t regs[16]; |
242 | uint32_t pc; | |
243 | uint32_t sregs[256]; | |
2af3da91 | 244 | uint32_t uregs[256]; |
553e44f9 | 245 | uint32_t phys_regs[MAX_NAREG]; |
2328826b | 246 | |
b994e91b MF |
247 | int pending_irq_level; /* level of last raised IRQ */ |
248 | void **irq_inputs; | |
249 | QEMUTimer *ccompare_timer; | |
250 | uint32_t wake_ccount; | |
251 | int64_t halt_clock; | |
252 | ||
40643d7c MF |
253 | int exception_taken; |
254 | ||
2328826b MF |
255 | CPU_COMMON |
256 | } CPUXtensaState; | |
257 | ||
258 | #define cpu_init cpu_xtensa_init | |
259 | #define cpu_exec cpu_xtensa_exec | |
260 | #define cpu_gen_code cpu_xtensa_gen_code | |
261 | #define cpu_signal_handler cpu_xtensa_signal_handler | |
262 | #define cpu_list xtensa_cpu_list | |
263 | ||
264 | CPUXtensaState *cpu_xtensa_init(const char *cpu_model); | |
265 | void xtensa_translate_init(void); | |
266 | int cpu_xtensa_exec(CPUXtensaState *s); | |
267 | void do_interrupt(CPUXtensaState *s); | |
b994e91b MF |
268 | void check_interrupts(CPUXtensaState *s); |
269 | void xtensa_irq_init(CPUState *env); | |
270 | void xtensa_advance_ccount(CPUState *env, uint32_t d); | |
271 | void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active); | |
2328826b MF |
272 | int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); |
273 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
553e44f9 MF |
274 | void xtensa_sync_window_from_phys(CPUState *env); |
275 | void xtensa_sync_phys_from_window(CPUState *env); | |
2328826b | 276 | |
dedc5eae MF |
277 | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) |
278 | ||
279 | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) | |
280 | { | |
281 | return (config->options & XTENSA_OPTION_BIT(opt)) != 0; | |
282 | } | |
283 | ||
40643d7c MF |
284 | static inline int xtensa_get_cintlevel(const CPUState *env) |
285 | { | |
286 | int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; | |
287 | if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { | |
288 | level = env->config->excm_level; | |
289 | } | |
290 | return level; | |
291 | } | |
292 | ||
f0a548b9 MF |
293 | static inline int xtensa_get_ring(const CPUState *env) |
294 | { | |
295 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
296 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
297 | } else { | |
298 | return 0; | |
299 | } | |
300 | } | |
301 | ||
302 | static inline int xtensa_get_cring(const CPUState *env) | |
303 | { | |
304 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && | |
305 | (env->sregs[PS] & PS_EXCM) == 0) { | |
306 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
307 | } else { | |
308 | return 0; | |
309 | } | |
310 | } | |
311 | ||
312 | /* MMU modes definitions */ | |
313 | #define MMU_MODE0_SUFFIX _ring0 | |
314 | #define MMU_MODE1_SUFFIX _ring1 | |
315 | #define MMU_MODE2_SUFFIX _ring2 | |
316 | #define MMU_MODE3_SUFFIX _ring3 | |
317 | ||
2328826b MF |
318 | static inline int cpu_mmu_index(CPUState *env) |
319 | { | |
f0a548b9 | 320 | return xtensa_get_cring(env); |
2328826b MF |
321 | } |
322 | ||
f0a548b9 MF |
323 | #define XTENSA_TBFLAG_RING_MASK 0x3 |
324 | #define XTENSA_TBFLAG_EXCM 0x4 | |
6ad6dbf7 | 325 | #define XTENSA_TBFLAG_LITBASE 0x8 |
f0a548b9 | 326 | |
2328826b MF |
327 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
328 | target_ulong *cs_base, int *flags) | |
329 | { | |
330 | *pc = env->pc; | |
331 | *cs_base = 0; | |
332 | *flags = 0; | |
f0a548b9 MF |
333 | *flags |= xtensa_get_ring(env); |
334 | if (env->sregs[PS] & PS_EXCM) { | |
335 | *flags |= XTENSA_TBFLAG_EXCM; | |
336 | } | |
6ad6dbf7 MF |
337 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && |
338 | (env->sregs[LITBASE] & 1)) { | |
339 | *flags |= XTENSA_TBFLAG_LITBASE; | |
340 | } | |
2328826b MF |
341 | } |
342 | ||
343 | #include "cpu-all.h" | |
344 | #include "exec-all.h" | |
345 | ||
346 | static inline int cpu_has_work(CPUState *env) | |
347 | { | |
b994e91b | 348 | return env->pending_irq_level; |
2328826b MF |
349 | } |
350 | ||
351 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) | |
352 | { | |
353 | env->pc = tb->pc; | |
354 | } | |
355 | ||
356 | #endif |