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1/*
2 * Xtensa gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
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20#include "config.h"
21#include "qemu-common.h"
22#include "exec/gdbstub.h"
25d8ac0e 23
5b50e790 24int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
25d8ac0e 25{
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26 XtensaCPU *cpu = XTENSA_CPU(cs);
27 CPUXtensaState *env = &cpu->env;
25d8ac0e 28 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
ddd44279 29 unsigned i;
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30
31 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
32 return 0;
33 }
34
35 switch (reg->type) {
36 case 9: /*pc*/
986a2998 37 return gdb_get_reg32(mem_buf, env->pc);
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38
39 case 1: /*ar*/
40 xtensa_sync_phys_from_window(env);
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41 return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff)
42 % env->config->nareg]);
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43
44 case 2: /*SR*/
986a2998 45 return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);
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46
47 case 3: /*UR*/
986a2998 48 return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
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49
50 case 4: /*f*/
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51 i = reg->targno & 0x0f;
52 switch (reg->size) {
53 case 4:
54 return gdb_get_reg32(mem_buf,
55 float32_val(env->fregs[i].f32[FP_F32_LOW]));
56 case 8:
57 return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64));
58 default:
59 return 0;
60 }
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61
62 case 8: /*a*/
986a2998 63 return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
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64
65 default:
66 qemu_log("%s from reg %d of unsupported type %d\n",
67 __func__, n, reg->type);
68 return 0;
69 }
70}
71
5b50e790 72int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
25d8ac0e 73{
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74 XtensaCPU *cpu = XTENSA_CPU(cs);
75 CPUXtensaState *env = &cpu->env;
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76 uint32_t tmp;
77 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
78
79 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
80 return 0;
81 }
82
83 tmp = ldl_p(mem_buf);
84
85 switch (reg->type) {
86 case 9: /*pc*/
87 env->pc = tmp;
88 break;
89
90 case 1: /*ar*/
91 env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
92 xtensa_sync_window_from_phys(env);
93 break;
94
95 case 2: /*SR*/
96 env->sregs[reg->targno & 0xff] = tmp;
97 break;
98
99 case 3: /*UR*/
100 env->uregs[reg->targno & 0xff] = tmp;
101 break;
102
103 case 4: /*f*/
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104 switch (reg->size) {
105 case 4:
106 env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp);
107 return 4;
108 case 8:
109 env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp);
110 return 8;
111 default:
112 return 0;
113 }
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114
115 case 8: /*a*/
116 env->regs[reg->targno & 0x0f] = tmp;
117 break;
118
119 default:
120 qemu_log("%s to reg %d of unsupported type %d\n",
121 __func__, n, reg->type);
122 return 0;
123 }
124
125 return 4;
126}