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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #include "cpu.h" | |
16c1deae | 29 | #include "helper.h" |
1de7afc9 | 30 | #include "qemu/host-utils.h" |
b1669e5e | 31 | #include "exec/softmmu_exec.h" |
29d8ec7b | 32 | #include "exec/address-spaces.h" |
2328826b | 33 | |
f492b82d MF |
34 | static void do_unaligned_access(CPUXtensaState *env, |
35 | target_ulong addr, int is_write, int is_user, uintptr_t retaddr); | |
5b4e481b MF |
36 | |
37 | #define ALIGNED_ONLY | |
2328826b MF |
38 | #define MMUSUFFIX _mmu |
39 | ||
40 | #define SHIFT 0 | |
022c62cb | 41 | #include "exec/softmmu_template.h" |
2328826b MF |
42 | |
43 | #define SHIFT 1 | |
022c62cb | 44 | #include "exec/softmmu_template.h" |
2328826b MF |
45 | |
46 | #define SHIFT 2 | |
022c62cb | 47 | #include "exec/softmmu_template.h" |
2328826b MF |
48 | |
49 | #define SHIFT 3 | |
022c62cb | 50 | #include "exec/softmmu_template.h" |
2328826b | 51 | |
f492b82d MF |
52 | static void do_unaligned_access(CPUXtensaState *env, |
53 | target_ulong addr, int is_write, int is_user, uintptr_t retaddr) | |
5b4e481b MF |
54 | { |
55 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && | |
56 | !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { | |
a8a826a3 | 57 | cpu_restore_state(env, retaddr); |
f492b82d | 58 | HELPER(exception_cause_vaddr)(env, |
5b4e481b MF |
59 | env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); |
60 | } | |
61 | } | |
62 | ||
f492b82d MF |
63 | void tlb_fill(CPUXtensaState *env, |
64 | target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) | |
2328826b | 65 | { |
f492b82d MF |
66 | uint32_t paddr; |
67 | uint32_t page_size; | |
68 | unsigned access; | |
69 | int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx, | |
70 | &paddr, &page_size, &access); | |
b67ea0cd | 71 | |
f492b82d MF |
72 | qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__, |
73 | vaddr, is_write, mmu_idx, paddr, ret); | |
b67ea0cd | 74 | |
f492b82d MF |
75 | if (ret == 0) { |
76 | tlb_set_page(env, | |
77 | vaddr & TARGET_PAGE_MASK, | |
78 | paddr & TARGET_PAGE_MASK, | |
79 | access, mmu_idx, page_size); | |
80 | } else { | |
a8a826a3 | 81 | cpu_restore_state(env, retaddr); |
f492b82d | 82 | HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); |
b67ea0cd | 83 | } |
2328826b | 84 | } |
dedc5eae | 85 | |
3d0be8a5 MF |
86 | static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) |
87 | { | |
88 | uint32_t paddr; | |
89 | uint32_t page_size; | |
90 | unsigned access; | |
ae4e7982 | 91 | int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, |
3d0be8a5 MF |
92 | &paddr, &page_size, &access); |
93 | if (ret == 0) { | |
29d8ec7b | 94 | tb_invalidate_phys_addr(&address_space_memory, paddr); |
3d0be8a5 MF |
95 | } |
96 | } | |
97 | ||
f492b82d | 98 | void HELPER(exception)(CPUXtensaState *env, uint32_t excp) |
dedc5eae | 99 | { |
27103424 AF |
100 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); |
101 | ||
102 | cs->exception_index = excp; | |
a00817cc MF |
103 | if (excp == EXCP_DEBUG) { |
104 | env->exception_taken = 0; | |
105 | } | |
dedc5eae MF |
106 | cpu_loop_exit(env); |
107 | } | |
3580ecad | 108 | |
f492b82d | 109 | void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) |
40643d7c MF |
110 | { |
111 | uint32_t vector; | |
112 | ||
113 | env->pc = pc; | |
114 | if (env->sregs[PS] & PS_EXCM) { | |
115 | if (env->config->ndepc) { | |
116 | env->sregs[DEPC] = pc; | |
117 | } else { | |
118 | env->sregs[EPC1] = pc; | |
119 | } | |
120 | vector = EXC_DOUBLE; | |
121 | } else { | |
122 | env->sregs[EPC1] = pc; | |
123 | vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; | |
124 | } | |
125 | ||
126 | env->sregs[EXCCAUSE] = cause; | |
127 | env->sregs[PS] |= PS_EXCM; | |
128 | ||
f492b82d | 129 | HELPER(exception)(env, vector); |
40643d7c MF |
130 | } |
131 | ||
f492b82d MF |
132 | void HELPER(exception_cause_vaddr)(CPUXtensaState *env, |
133 | uint32_t pc, uint32_t cause, uint32_t vaddr) | |
40643d7c MF |
134 | { |
135 | env->sregs[EXCVADDR] = vaddr; | |
f492b82d | 136 | HELPER(exception_cause)(env, pc, cause); |
40643d7c MF |
137 | } |
138 | ||
f492b82d | 139 | void debug_exception_env(CPUXtensaState *env, uint32_t cause) |
f14c4b5f | 140 | { |
f492b82d MF |
141 | if (xtensa_get_cintlevel(env) < env->config->debug_level) { |
142 | HELPER(debug_exception)(env, env->pc, cause); | |
f14c4b5f MF |
143 | } |
144 | } | |
145 | ||
f492b82d | 146 | void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause) |
e61dc8f7 MF |
147 | { |
148 | unsigned level = env->config->debug_level; | |
149 | ||
150 | env->pc = pc; | |
151 | env->sregs[DEBUGCAUSE] = cause; | |
152 | env->sregs[EPC1 + level - 1] = pc; | |
153 | env->sregs[EPS2 + level - 2] = env->sregs[PS]; | |
154 | env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM | | |
155 | (level << PS_INTLEVEL_SHIFT); | |
f492b82d | 156 | HELPER(exception)(env, EXC_DEBUG); |
e61dc8f7 MF |
157 | } |
158 | ||
3580ecad MF |
159 | uint32_t HELPER(nsa)(uint32_t v) |
160 | { | |
161 | if (v & 0x80000000) { | |
162 | v = ~v; | |
163 | } | |
164 | return v ? clz32(v) - 1 : 31; | |
165 | } | |
166 | ||
167 | uint32_t HELPER(nsau)(uint32_t v) | |
168 | { | |
169 | return v ? clz32(v) : 32; | |
170 | } | |
553e44f9 | 171 | |
97129ac8 | 172 | static void copy_window_from_phys(CPUXtensaState *env, |
553e44f9 MF |
173 | uint32_t window, uint32_t phys, uint32_t n) |
174 | { | |
175 | assert(phys < env->config->nareg); | |
176 | if (phys + n <= env->config->nareg) { | |
177 | memcpy(env->regs + window, env->phys_regs + phys, | |
178 | n * sizeof(uint32_t)); | |
179 | } else { | |
180 | uint32_t n1 = env->config->nareg - phys; | |
181 | memcpy(env->regs + window, env->phys_regs + phys, | |
182 | n1 * sizeof(uint32_t)); | |
183 | memcpy(env->regs + window + n1, env->phys_regs, | |
184 | (n - n1) * sizeof(uint32_t)); | |
185 | } | |
186 | } | |
187 | ||
97129ac8 | 188 | static void copy_phys_from_window(CPUXtensaState *env, |
553e44f9 MF |
189 | uint32_t phys, uint32_t window, uint32_t n) |
190 | { | |
191 | assert(phys < env->config->nareg); | |
192 | if (phys + n <= env->config->nareg) { | |
193 | memcpy(env->phys_regs + phys, env->regs + window, | |
194 | n * sizeof(uint32_t)); | |
195 | } else { | |
196 | uint32_t n1 = env->config->nareg - phys; | |
197 | memcpy(env->phys_regs + phys, env->regs + window, | |
198 | n1 * sizeof(uint32_t)); | |
199 | memcpy(env->phys_regs, env->regs + window + n1, | |
200 | (n - n1) * sizeof(uint32_t)); | |
201 | } | |
202 | } | |
203 | ||
204 | ||
97129ac8 | 205 | static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env) |
553e44f9 MF |
206 | { |
207 | return a & (env->config->nareg / 4 - 1); | |
208 | } | |
209 | ||
97129ac8 | 210 | static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env) |
553e44f9 MF |
211 | { |
212 | return 1 << windowbase_bound(a, env); | |
213 | } | |
214 | ||
97129ac8 | 215 | void xtensa_sync_window_from_phys(CPUXtensaState *env) |
553e44f9 MF |
216 | { |
217 | copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16); | |
218 | } | |
219 | ||
97129ac8 | 220 | void xtensa_sync_phys_from_window(CPUXtensaState *env) |
553e44f9 MF |
221 | { |
222 | copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); | |
223 | } | |
224 | ||
f492b82d | 225 | static void rotate_window_abs(CPUXtensaState *env, uint32_t position) |
553e44f9 MF |
226 | { |
227 | xtensa_sync_phys_from_window(env); | |
228 | env->sregs[WINDOW_BASE] = windowbase_bound(position, env); | |
229 | xtensa_sync_window_from_phys(env); | |
230 | } | |
231 | ||
f492b82d | 232 | static void rotate_window(CPUXtensaState *env, uint32_t delta) |
553e44f9 | 233 | { |
f492b82d | 234 | rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); |
553e44f9 MF |
235 | } |
236 | ||
f492b82d | 237 | void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) |
553e44f9 | 238 | { |
f492b82d | 239 | rotate_window_abs(env, v); |
553e44f9 MF |
240 | } |
241 | ||
f492b82d | 242 | void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) |
553e44f9 MF |
243 | { |
244 | int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT; | |
245 | if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { | |
246 | qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n", | |
247 | pc, env->sregs[PS]); | |
f492b82d | 248 | HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); |
553e44f9 MF |
249 | } else { |
250 | env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3); | |
f492b82d | 251 | rotate_window(env, callinc); |
553e44f9 MF |
252 | env->sregs[WINDOW_START] |= |
253 | windowstart_bit(env->sregs[WINDOW_BASE], env); | |
254 | } | |
255 | } | |
256 | ||
f492b82d | 257 | void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w) |
553e44f9 MF |
258 | { |
259 | uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); | |
260 | uint32_t windowstart = env->sregs[WINDOW_START]; | |
261 | uint32_t m, n; | |
262 | ||
263 | if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) { | |
264 | return; | |
265 | } | |
266 | ||
267 | for (n = 1; ; ++n) { | |
268 | if (n > w) { | |
269 | return; | |
270 | } | |
271 | if (windowstart & windowstart_bit(windowbase + n, env)) { | |
272 | break; | |
273 | } | |
274 | } | |
275 | ||
276 | m = windowbase_bound(windowbase + n, env); | |
f492b82d | 277 | rotate_window(env, n); |
553e44f9 MF |
278 | env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | |
279 | (windowbase << PS_OWB_SHIFT) | PS_EXCM; | |
280 | env->sregs[EPC1] = env->pc = pc; | |
281 | ||
282 | if (windowstart & windowstart_bit(m + 1, env)) { | |
f492b82d | 283 | HELPER(exception)(env, EXC_WINDOW_OVERFLOW4); |
553e44f9 | 284 | } else if (windowstart & windowstart_bit(m + 2, env)) { |
f492b82d | 285 | HELPER(exception)(env, EXC_WINDOW_OVERFLOW8); |
553e44f9 | 286 | } else { |
f492b82d | 287 | HELPER(exception)(env, EXC_WINDOW_OVERFLOW12); |
553e44f9 MF |
288 | } |
289 | } | |
290 | ||
f492b82d | 291 | uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) |
553e44f9 MF |
292 | { |
293 | int n = (env->regs[0] >> 30) & 0x3; | |
294 | int m = 0; | |
295 | uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); | |
296 | uint32_t windowstart = env->sregs[WINDOW_START]; | |
297 | uint32_t ret_pc = 0; | |
298 | ||
299 | if (windowstart & windowstart_bit(windowbase - 1, env)) { | |
300 | m = 1; | |
301 | } else if (windowstart & windowstart_bit(windowbase - 2, env)) { | |
302 | m = 2; | |
303 | } else if (windowstart & windowstart_bit(windowbase - 3, env)) { | |
304 | m = 3; | |
305 | } | |
306 | ||
307 | if (n == 0 || (m != 0 && m != n) || | |
308 | ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { | |
309 | qemu_log("Illegal retw instruction(pc = %08x), " | |
310 | "PS = %08x, m = %d, n = %d\n", | |
311 | pc, env->sregs[PS], m, n); | |
f492b82d | 312 | HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); |
553e44f9 MF |
313 | } else { |
314 | int owb = windowbase; | |
315 | ||
316 | ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); | |
317 | ||
f492b82d | 318 | rotate_window(env, -n); |
553e44f9 MF |
319 | if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) { |
320 | env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env); | |
321 | } else { | |
322 | /* window underflow */ | |
323 | env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | | |
324 | (windowbase << PS_OWB_SHIFT) | PS_EXCM; | |
325 | env->sregs[EPC1] = env->pc = pc; | |
326 | ||
327 | if (n == 1) { | |
f492b82d | 328 | HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4); |
553e44f9 | 329 | } else if (n == 2) { |
f492b82d | 330 | HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8); |
553e44f9 | 331 | } else if (n == 3) { |
f492b82d | 332 | HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12); |
553e44f9 MF |
333 | } |
334 | } | |
335 | } | |
336 | return ret_pc; | |
337 | } | |
338 | ||
f492b82d | 339 | void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) |
553e44f9 | 340 | { |
f492b82d | 341 | rotate_window(env, imm4); |
553e44f9 MF |
342 | } |
343 | ||
f492b82d | 344 | void HELPER(restore_owb)(CPUXtensaState *env) |
553e44f9 | 345 | { |
f492b82d | 346 | rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); |
553e44f9 MF |
347 | } |
348 | ||
f492b82d | 349 | void HELPER(movsp)(CPUXtensaState *env, uint32_t pc) |
553e44f9 MF |
350 | { |
351 | if ((env->sregs[WINDOW_START] & | |
352 | (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) | | |
353 | windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) | | |
354 | windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) { | |
f492b82d | 355 | HELPER(exception_cause)(env, pc, ALLOCA_CAUSE); |
553e44f9 MF |
356 | } |
357 | } | |
358 | ||
f492b82d | 359 | void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v) |
797d780b MF |
360 | { |
361 | if (env->sregs[LBEG] != v) { | |
3d0be8a5 | 362 | tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); |
797d780b MF |
363 | env->sregs[LBEG] = v; |
364 | } | |
365 | } | |
366 | ||
f492b82d | 367 | void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v) |
797d780b MF |
368 | { |
369 | if (env->sregs[LEND] != v) { | |
3d0be8a5 | 370 | tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); |
797d780b | 371 | env->sregs[LEND] = v; |
3d0be8a5 | 372 | tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); |
797d780b MF |
373 | } |
374 | } | |
375 | ||
f492b82d | 376 | void HELPER(dump_state)(CPUXtensaState *env) |
553e44f9 | 377 | { |
878096ee AF |
378 | XtensaCPU *cpu = xtensa_env_get_cpu(env); |
379 | ||
380 | cpu_dump_state(CPU(cpu), stderr, fprintf, 0); | |
553e44f9 | 381 | } |
b994e91b | 382 | |
f492b82d | 383 | void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) |
b994e91b | 384 | { |
259186a7 AF |
385 | CPUState *cpu; |
386 | ||
b994e91b MF |
387 | env->pc = pc; |
388 | env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | | |
389 | (intlevel << PS_INTLEVEL_SHIFT); | |
390 | check_interrupts(env); | |
391 | if (env->pending_irq_level) { | |
392 | cpu_loop_exit(env); | |
393 | return; | |
394 | } | |
395 | ||
259186a7 | 396 | cpu = CPU(xtensa_env_get_cpu(env)); |
bc72ad67 | 397 | env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
259186a7 | 398 | cpu->halted = 1; |
890c6333 MF |
399 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) { |
400 | xtensa_rearm_ccompare_timer(env); | |
401 | } | |
f492b82d | 402 | HELPER(exception)(env, EXCP_HLT); |
b994e91b MF |
403 | } |
404 | ||
f492b82d | 405 | void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active) |
b994e91b MF |
406 | { |
407 | xtensa_timer_irq(env, id, active); | |
408 | } | |
409 | ||
f492b82d | 410 | void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d) |
b994e91b MF |
411 | { |
412 | xtensa_advance_ccount(env, d); | |
413 | } | |
414 | ||
97129ac8 | 415 | void HELPER(check_interrupts)(CPUXtensaState *env) |
b994e91b MF |
416 | { |
417 | check_interrupts(env); | |
418 | } | |
b67ea0cd | 419 | |
e848dd42 MF |
420 | void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) |
421 | { | |
422 | get_page_addr_code(env, vaddr); | |
423 | } | |
424 | ||
fcc803d1 MF |
425 | /*! |
426 | * Check vaddr accessibility/cache attributes and raise an exception if | |
427 | * specified by the ATOMCTL SR. | |
428 | * | |
429 | * Note: local memory exclusion is not implemented | |
430 | */ | |
431 | void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) | |
432 | { | |
433 | uint32_t paddr, page_size, access; | |
434 | uint32_t atomctl = env->sregs[ATOMCTL]; | |
435 | int rc = xtensa_get_physical_addr(env, true, vaddr, 1, | |
436 | xtensa_get_cring(env), &paddr, &page_size, &access); | |
437 | ||
438 | /* | |
439 | * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions, | |
440 | * see opcode description in the ISA | |
441 | */ | |
442 | if (rc == 0 && | |
443 | (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) { | |
444 | rc = STORE_PROHIBITED_CAUSE; | |
445 | } | |
446 | ||
447 | if (rc) { | |
448 | HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); | |
449 | } | |
450 | ||
451 | /* | |
452 | * When data cache is not configured use ATOMCTL bypass field. | |
453 | * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL) | |
454 | * under the Conditional Store Option. | |
455 | */ | |
456 | if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { | |
457 | access = PAGE_CACHE_BYPASS; | |
458 | } | |
459 | ||
460 | switch (access & PAGE_CACHE_MASK) { | |
461 | case PAGE_CACHE_WB: | |
462 | atomctl >>= 2; | |
5739006b | 463 | /* fall through */ |
fcc803d1 MF |
464 | case PAGE_CACHE_WT: |
465 | atomctl >>= 2; | |
5739006b | 466 | /* fall through */ |
fcc803d1 MF |
467 | case PAGE_CACHE_BYPASS: |
468 | if ((atomctl & 0x3) == 0) { | |
469 | HELPER(exception_cause_vaddr)(env, pc, | |
470 | LOAD_STORE_ERROR_CAUSE, vaddr); | |
471 | } | |
472 | break; | |
473 | ||
474 | case PAGE_CACHE_ISOLATE: | |
475 | HELPER(exception_cause_vaddr)(env, pc, | |
476 | LOAD_STORE_ERROR_CAUSE, vaddr); | |
477 | break; | |
478 | ||
479 | default: | |
480 | break; | |
481 | } | |
482 | } | |
483 | ||
f492b82d | 484 | void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) |
b67ea0cd MF |
485 | { |
486 | v = (v & 0xffffff00) | 0x1; | |
487 | if (v != env->sregs[RASID]) { | |
488 | env->sregs[RASID] = v; | |
489 | tlb_flush(env, 1); | |
490 | } | |
491 | } | |
492 | ||
97129ac8 | 493 | static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way) |
b67ea0cd MF |
494 | { |
495 | uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; | |
496 | ||
497 | switch (way) { | |
498 | case 4: | |
499 | return (tlbcfg >> 16) & 0x3; | |
500 | ||
501 | case 5: | |
502 | return (tlbcfg >> 20) & 0x1; | |
503 | ||
504 | case 6: | |
505 | return (tlbcfg >> 24) & 0x1; | |
506 | ||
507 | default: | |
508 | return 0; | |
509 | } | |
510 | } | |
511 | ||
512 | /*! | |
513 | * Get bit mask for the virtual address bits translated by the TLB way | |
514 | */ | |
97129ac8 | 515 | uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) |
b67ea0cd MF |
516 | { |
517 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
518 | bool varway56 = dtlb ? | |
519 | env->config->dtlb.varway56 : | |
520 | env->config->itlb.varway56; | |
521 | ||
522 | switch (way) { | |
523 | case 4: | |
524 | return 0xfff00000 << get_page_size(env, dtlb, way) * 2; | |
525 | ||
526 | case 5: | |
527 | if (varway56) { | |
528 | return 0xf8000000 << get_page_size(env, dtlb, way); | |
529 | } else { | |
530 | return 0xf8000000; | |
531 | } | |
532 | ||
533 | case 6: | |
534 | if (varway56) { | |
535 | return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); | |
536 | } else { | |
537 | return 0xf0000000; | |
538 | } | |
539 | ||
540 | default: | |
541 | return 0xfffff000; | |
542 | } | |
543 | } else { | |
544 | return REGION_PAGE_MASK; | |
545 | } | |
546 | } | |
547 | ||
548 | /*! | |
549 | * Get bit mask for the 'VPN without index' field. | |
550 | * See ISA, 4.6.5.6, data format for RxTLB0 | |
551 | */ | |
97129ac8 | 552 | static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) |
b67ea0cd MF |
553 | { |
554 | if (way < 4) { | |
555 | bool is32 = (dtlb ? | |
556 | env->config->dtlb.nrefillentries : | |
557 | env->config->itlb.nrefillentries) == 32; | |
558 | return is32 ? 0xffff8000 : 0xffffc000; | |
559 | } else if (way == 4) { | |
560 | return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; | |
561 | } else if (way <= 6) { | |
562 | uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); | |
563 | bool varway56 = dtlb ? | |
564 | env->config->dtlb.varway56 : | |
565 | env->config->itlb.varway56; | |
566 | ||
567 | if (varway56) { | |
568 | return mask << (way == 5 ? 2 : 3); | |
569 | } else { | |
570 | return mask << 1; | |
571 | } | |
572 | } else { | |
573 | return 0xfffff000; | |
574 | } | |
575 | } | |
576 | ||
577 | /*! | |
578 | * Split virtual address into VPN (with index) and entry index | |
579 | * for the given TLB way | |
580 | */ | |
97129ac8 | 581 | void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, |
b67ea0cd MF |
582 | uint32_t *vpn, uint32_t wi, uint32_t *ei) |
583 | { | |
584 | bool varway56 = dtlb ? | |
585 | env->config->dtlb.varway56 : | |
586 | env->config->itlb.varway56; | |
587 | ||
588 | if (!dtlb) { | |
589 | wi &= 7; | |
590 | } | |
591 | ||
592 | if (wi < 4) { | |
593 | bool is32 = (dtlb ? | |
594 | env->config->dtlb.nrefillentries : | |
595 | env->config->itlb.nrefillentries) == 32; | |
596 | *ei = (v >> 12) & (is32 ? 0x7 : 0x3); | |
597 | } else { | |
598 | switch (wi) { | |
599 | case 4: | |
600 | { | |
601 | uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; | |
602 | *ei = (v >> eibase) & 0x3; | |
603 | } | |
604 | break; | |
605 | ||
606 | case 5: | |
607 | if (varway56) { | |
608 | uint32_t eibase = 27 + get_page_size(env, dtlb, wi); | |
609 | *ei = (v >> eibase) & 0x3; | |
610 | } else { | |
611 | *ei = (v >> 27) & 0x1; | |
612 | } | |
613 | break; | |
614 | ||
615 | case 6: | |
616 | if (varway56) { | |
617 | uint32_t eibase = 29 - get_page_size(env, dtlb, wi); | |
618 | *ei = (v >> eibase) & 0x7; | |
619 | } else { | |
620 | *ei = (v >> 28) & 0x1; | |
621 | } | |
622 | break; | |
623 | ||
624 | default: | |
625 | *ei = 0; | |
626 | break; | |
627 | } | |
628 | } | |
629 | *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); | |
630 | } | |
631 | ||
632 | /*! | |
633 | * Split TLB address into TLB way, entry index and VPN (with index). | |
634 | * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format | |
635 | */ | |
f492b82d | 636 | static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, |
b67ea0cd MF |
637 | uint32_t *vpn, uint32_t *wi, uint32_t *ei) |
638 | { | |
639 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
640 | *wi = v & (dtlb ? 0xf : 0x7); | |
641 | split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); | |
642 | } else { | |
643 | *vpn = v & REGION_PAGE_MASK; | |
644 | *wi = 0; | |
645 | *ei = (v >> 29) & 0x7; | |
646 | } | |
647 | } | |
648 | ||
f492b82d MF |
649 | static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, |
650 | uint32_t v, bool dtlb, uint32_t *pwi) | |
b67ea0cd MF |
651 | { |
652 | uint32_t vpn; | |
653 | uint32_t wi; | |
654 | uint32_t ei; | |
655 | ||
f492b82d | 656 | split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); |
b67ea0cd MF |
657 | if (pwi) { |
658 | *pwi = wi; | |
659 | } | |
660 | return xtensa_tlb_get_entry(env, dtlb, wi, ei); | |
661 | } | |
662 | ||
f492b82d | 663 | uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
664 | { |
665 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
666 | uint32_t wi; | |
f492b82d | 667 | const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); |
b67ea0cd MF |
668 | return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; |
669 | } else { | |
670 | return v & REGION_PAGE_MASK; | |
671 | } | |
672 | } | |
673 | ||
f492b82d | 674 | uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd | 675 | { |
f492b82d | 676 | const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); |
b67ea0cd MF |
677 | return entry->paddr | entry->attr; |
678 | } | |
679 | ||
f492b82d | 680 | void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
681 | { |
682 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
683 | uint32_t wi; | |
f492b82d | 684 | xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); |
b67ea0cd MF |
685 | if (entry->variable && entry->asid) { |
686 | tlb_flush_page(env, entry->vaddr); | |
687 | entry->asid = 0; | |
688 | } | |
689 | } | |
690 | } | |
691 | ||
f492b82d | 692 | uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
693 | { |
694 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
695 | uint32_t wi; | |
696 | uint32_t ei; | |
697 | uint8_t ring; | |
698 | int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); | |
699 | ||
700 | switch (res) { | |
701 | case 0: | |
702 | if (ring >= xtensa_get_ring(env)) { | |
703 | return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); | |
704 | } | |
705 | break; | |
706 | ||
707 | case INST_TLB_MULTI_HIT_CAUSE: | |
708 | case LOAD_STORE_TLB_MULTI_HIT_CAUSE: | |
f492b82d | 709 | HELPER(exception_cause_vaddr)(env, env->pc, res, v); |
b67ea0cd MF |
710 | break; |
711 | } | |
712 | return 0; | |
713 | } else { | |
714 | return (v & REGION_PAGE_MASK) | 0x1; | |
715 | } | |
716 | } | |
717 | ||
16bde77a MF |
718 | void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, |
719 | xtensa_tlb_entry *entry, bool dtlb, | |
720 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) | |
721 | { | |
722 | entry->vaddr = vpn; | |
723 | entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); | |
724 | entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; | |
725 | entry->attr = pte & 0xf; | |
726 | } | |
727 | ||
97129ac8 | 728 | void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, |
b67ea0cd MF |
729 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) |
730 | { | |
731 | xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); | |
732 | ||
733 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
734 | if (entry->variable) { | |
735 | if (entry->asid) { | |
736 | tlb_flush_page(env, entry->vaddr); | |
737 | } | |
16bde77a | 738 | xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); |
e323bdef | 739 | tlb_flush_page(env, entry->vaddr); |
b67ea0cd MF |
740 | } else { |
741 | qemu_log("%s %d, %d, %d trying to set immutable entry\n", | |
742 | __func__, dtlb, wi, ei); | |
743 | } | |
744 | } else { | |
745 | tlb_flush_page(env, entry->vaddr); | |
746 | if (xtensa_option_enabled(env->config, | |
747 | XTENSA_OPTION_REGION_TRANSLATION)) { | |
748 | entry->paddr = pte & REGION_PAGE_MASK; | |
749 | } | |
750 | entry->attr = pte & 0xf; | |
751 | } | |
752 | } | |
753 | ||
f492b82d | 754 | void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
755 | { |
756 | uint32_t vpn; | |
757 | uint32_t wi; | |
758 | uint32_t ei; | |
f492b82d | 759 | split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); |
b67ea0cd MF |
760 | xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); |
761 | } | |
e61dc8f7 MF |
762 | |
763 | ||
f492b82d | 764 | void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) |
e61dc8f7 MF |
765 | { |
766 | uint32_t change = v ^ env->sregs[IBREAKENABLE]; | |
767 | unsigned i; | |
768 | ||
769 | for (i = 0; i < env->config->nibreak; ++i) { | |
770 | if (change & (1 << i)) { | |
3d0be8a5 | 771 | tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); |
e61dc8f7 MF |
772 | } |
773 | } | |
774 | env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1); | |
775 | } | |
776 | ||
f492b82d | 777 | void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) |
e61dc8f7 MF |
778 | { |
779 | if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) { | |
3d0be8a5 MF |
780 | tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); |
781 | tb_invalidate_virtual_addr(env, v); | |
e61dc8f7 MF |
782 | } |
783 | env->sregs[IBREAKA + i] = v; | |
784 | } | |
f14c4b5f | 785 | |
f492b82d MF |
786 | static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, |
787 | uint32_t dbreakc) | |
f14c4b5f MF |
788 | { |
789 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
790 | uint32_t mask = dbreakc | ~DBREAKC_MASK; | |
791 | ||
792 | if (env->cpu_watchpoint[i]) { | |
793 | cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); | |
794 | } | |
795 | if (dbreakc & DBREAKC_SB) { | |
796 | flags |= BP_MEM_WRITE; | |
797 | } | |
798 | if (dbreakc & DBREAKC_LB) { | |
799 | flags |= BP_MEM_READ; | |
800 | } | |
801 | /* contiguous mask after inversion is one less than some power of 2 */ | |
802 | if ((~mask + 1) & ~mask) { | |
803 | qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc); | |
804 | /* cut mask after the first zero bit */ | |
805 | mask = 0xffffffff << (32 - clo32(mask)); | |
806 | } | |
807 | if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1, | |
808 | flags, &env->cpu_watchpoint[i])) { | |
809 | env->cpu_watchpoint[i] = NULL; | |
810 | qemu_log("Failed to set data breakpoint at 0x%08x/%d\n", | |
811 | dbreaka & mask, ~mask + 1); | |
812 | } | |
813 | } | |
814 | ||
f492b82d | 815 | void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) |
f14c4b5f MF |
816 | { |
817 | uint32_t dbreakc = env->sregs[DBREAKC + i]; | |
818 | ||
819 | if ((dbreakc & DBREAKC_SB_LB) && | |
820 | env->sregs[DBREAKA + i] != v) { | |
f492b82d | 821 | set_dbreak(env, i, v, dbreakc); |
f14c4b5f MF |
822 | } |
823 | env->sregs[DBREAKA + i] = v; | |
824 | } | |
825 | ||
f492b82d | 826 | void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) |
f14c4b5f MF |
827 | { |
828 | if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) { | |
829 | if (v & DBREAKC_SB_LB) { | |
f492b82d | 830 | set_dbreak(env, i, env->sregs[DBREAKA + i], v); |
f14c4b5f MF |
831 | } else { |
832 | if (env->cpu_watchpoint[i]) { | |
833 | cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); | |
834 | env->cpu_watchpoint[i] = NULL; | |
835 | } | |
836 | } | |
837 | } | |
838 | env->sregs[DBREAKC + i] = v; | |
839 | } | |
dd519cbe MF |
840 | |
841 | void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) | |
842 | { | |
843 | static const int rounding_mode[] = { | |
844 | float_round_nearest_even, | |
845 | float_round_to_zero, | |
846 | float_round_up, | |
847 | float_round_down, | |
848 | }; | |
849 | ||
850 | env->uregs[FCR] = v & 0xfffff07f; | |
851 | set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); | |
852 | } | |
0b6df838 MF |
853 | |
854 | float32 HELPER(abs_s)(float32 v) | |
855 | { | |
856 | return float32_abs(v); | |
857 | } | |
858 | ||
859 | float32 HELPER(neg_s)(float32 v) | |
860 | { | |
861 | return float32_chs(v); | |
862 | } | |
863 | ||
864 | float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) | |
865 | { | |
866 | return float32_add(a, b, &env->fp_status); | |
867 | } | |
868 | ||
869 | float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) | |
870 | { | |
871 | return float32_sub(a, b, &env->fp_status); | |
872 | } | |
873 | ||
874 | float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) | |
875 | { | |
876 | return float32_mul(a, b, &env->fp_status); | |
877 | } | |
878 | ||
879 | float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) | |
880 | { | |
881 | return float32_muladd(b, c, a, 0, | |
882 | &env->fp_status); | |
883 | } | |
884 | ||
885 | float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) | |
886 | { | |
887 | return float32_muladd(b, c, a, float_muladd_negate_product, | |
888 | &env->fp_status); | |
889 | } | |
b7ee8c6a MF |
890 | |
891 | uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) | |
892 | { | |
893 | float_status fp_status = {0}; | |
894 | ||
895 | set_float_rounding_mode(rounding_mode, &fp_status); | |
896 | return float32_to_int32( | |
897 | float32_scalbn(v, scale, &fp_status), &fp_status); | |
898 | } | |
899 | ||
900 | uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) | |
901 | { | |
902 | float_status fp_status = {0}; | |
903 | float32 res; | |
904 | ||
905 | set_float_rounding_mode(rounding_mode, &fp_status); | |
906 | ||
907 | res = float32_scalbn(v, scale, &fp_status); | |
908 | ||
909 | if (float32_is_neg(v) && !float32_is_any_nan(v)) { | |
910 | return float32_to_int32(res, &fp_status); | |
911 | } else { | |
912 | return float32_to_uint32(res, &fp_status); | |
913 | } | |
914 | } | |
915 | ||
916 | float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) | |
917 | { | |
918 | return float32_scalbn(int32_to_float32(v, &env->fp_status), | |
919 | (int32_t)scale, &env->fp_status); | |
920 | } | |
921 | ||
922 | float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) | |
923 | { | |
924 | return float32_scalbn(uint32_to_float32(v, &env->fp_status), | |
925 | (int32_t)scale, &env->fp_status); | |
926 | } | |
4e273869 MF |
927 | |
928 | static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) | |
929 | { | |
930 | if (v) { | |
931 | env->sregs[BR] |= br; | |
932 | } else { | |
933 | env->sregs[BR] &= ~br; | |
934 | } | |
935 | } | |
936 | ||
937 | void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
938 | { | |
939 | set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); | |
940 | } | |
941 | ||
942 | void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
943 | { | |
944 | set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); | |
945 | } | |
946 | ||
947 | void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
948 | { | |
949 | int v = float32_compare_quiet(a, b, &env->fp_status); | |
950 | set_br(env, v == float_relation_equal || v == float_relation_unordered, br); | |
951 | } | |
952 | ||
953 | void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
954 | { | |
955 | set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); | |
956 | } | |
957 | ||
958 | void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
959 | { | |
960 | int v = float32_compare_quiet(a, b, &env->fp_status); | |
961 | set_br(env, v == float_relation_less || v == float_relation_unordered, br); | |
962 | } | |
963 | ||
964 | void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
965 | { | |
966 | set_br(env, float32_le_quiet(a, b, &env->fp_status), br); | |
967 | } | |
968 | ||
969 | void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
970 | { | |
971 | int v = float32_compare_quiet(a, b, &env->fp_status); | |
972 | set_br(env, v != float_relation_greater, br); | |
973 | } |