]> git.proxmox.com Git - mirror_qemu.git/blame - target-xtensa/op_helper.c
target-xtensa: implement extended L32R
[mirror_qemu.git] / target-xtensa / op_helper.c
CommitLineData
2328826b
MF
1/*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include "cpu.h"
29#include "dyngen-exec.h"
dedc5eae 30#include "helpers.h"
3580ecad 31#include "host-utils.h"
2328826b
MF
32
33#define MMUSUFFIX _mmu
34
35#define SHIFT 0
36#include "softmmu_template.h"
37
38#define SHIFT 1
39#include "softmmu_template.h"
40
41#define SHIFT 2
42#include "softmmu_template.h"
43
44#define SHIFT 3
45#include "softmmu_template.h"
46
47void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
48{
49 tlb_set_page(cpu_single_env,
50 addr & ~(TARGET_PAGE_SIZE - 1),
51 addr & ~(TARGET_PAGE_SIZE - 1),
52 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
53 mmu_idx, TARGET_PAGE_SIZE);
54}
dedc5eae
MF
55
56void HELPER(exception)(uint32_t excp)
57{
58 env->exception_index = excp;
59 cpu_loop_exit(env);
60}
3580ecad 61
40643d7c
MF
62void HELPER(exception_cause)(uint32_t pc, uint32_t cause)
63{
64 uint32_t vector;
65
66 env->pc = pc;
67 if (env->sregs[PS] & PS_EXCM) {
68 if (env->config->ndepc) {
69 env->sregs[DEPC] = pc;
70 } else {
71 env->sregs[EPC1] = pc;
72 }
73 vector = EXC_DOUBLE;
74 } else {
75 env->sregs[EPC1] = pc;
76 vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
77 }
78
79 env->sregs[EXCCAUSE] = cause;
80 env->sregs[PS] |= PS_EXCM;
81
82 HELPER(exception)(vector);
83}
84
85void HELPER(exception_cause_vaddr)(uint32_t pc, uint32_t cause, uint32_t vaddr)
86{
87 env->sregs[EXCVADDR] = vaddr;
88 HELPER(exception_cause)(pc, cause);
89}
90
3580ecad
MF
91uint32_t HELPER(nsa)(uint32_t v)
92{
93 if (v & 0x80000000) {
94 v = ~v;
95 }
96 return v ? clz32(v) - 1 : 31;
97}
98
99uint32_t HELPER(nsau)(uint32_t v)
100{
101 return v ? clz32(v) : 32;
102}
553e44f9
MF
103
104static void copy_window_from_phys(CPUState *env,
105 uint32_t window, uint32_t phys, uint32_t n)
106{
107 assert(phys < env->config->nareg);
108 if (phys + n <= env->config->nareg) {
109 memcpy(env->regs + window, env->phys_regs + phys,
110 n * sizeof(uint32_t));
111 } else {
112 uint32_t n1 = env->config->nareg - phys;
113 memcpy(env->regs + window, env->phys_regs + phys,
114 n1 * sizeof(uint32_t));
115 memcpy(env->regs + window + n1, env->phys_regs,
116 (n - n1) * sizeof(uint32_t));
117 }
118}
119
120static void copy_phys_from_window(CPUState *env,
121 uint32_t phys, uint32_t window, uint32_t n)
122{
123 assert(phys < env->config->nareg);
124 if (phys + n <= env->config->nareg) {
125 memcpy(env->phys_regs + phys, env->regs + window,
126 n * sizeof(uint32_t));
127 } else {
128 uint32_t n1 = env->config->nareg - phys;
129 memcpy(env->phys_regs + phys, env->regs + window,
130 n1 * sizeof(uint32_t));
131 memcpy(env->phys_regs, env->regs + window + n1,
132 (n - n1) * sizeof(uint32_t));
133 }
134}
135
136
137static inline unsigned windowbase_bound(unsigned a, const CPUState *env)
138{
139 return a & (env->config->nareg / 4 - 1);
140}
141
142static inline unsigned windowstart_bit(unsigned a, const CPUState *env)
143{
144 return 1 << windowbase_bound(a, env);
145}
146
147void xtensa_sync_window_from_phys(CPUState *env)
148{
149 copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
150}
151
152void xtensa_sync_phys_from_window(CPUState *env)
153{
154 copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
155}
156
157static void rotate_window_abs(uint32_t position)
158{
159 xtensa_sync_phys_from_window(env);
160 env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
161 xtensa_sync_window_from_phys(env);
162}
163
164static void rotate_window(uint32_t delta)
165{
166 rotate_window_abs(env->sregs[WINDOW_BASE] + delta);
167}
168
169void HELPER(wsr_windowbase)(uint32_t v)
170{
171 rotate_window_abs(v);
172}
173
174void HELPER(entry)(uint32_t pc, uint32_t s, uint32_t imm)
175{
176 int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
177 if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
178 qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
179 pc, env->sregs[PS]);
180 HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
181 } else {
182 env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
183 rotate_window(callinc);
184 env->sregs[WINDOW_START] |=
185 windowstart_bit(env->sregs[WINDOW_BASE], env);
186 }
187}
188
189void HELPER(window_check)(uint32_t pc, uint32_t w)
190{
191 uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
192 uint32_t windowstart = env->sregs[WINDOW_START];
193 uint32_t m, n;
194
195 if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
196 return;
197 }
198
199 for (n = 1; ; ++n) {
200 if (n > w) {
201 return;
202 }
203 if (windowstart & windowstart_bit(windowbase + n, env)) {
204 break;
205 }
206 }
207
208 m = windowbase_bound(windowbase + n, env);
209 rotate_window(n);
210 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
211 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
212 env->sregs[EPC1] = env->pc = pc;
213
214 if (windowstart & windowstart_bit(m + 1, env)) {
215 HELPER(exception)(EXC_WINDOW_OVERFLOW4);
216 } else if (windowstart & windowstart_bit(m + 2, env)) {
217 HELPER(exception)(EXC_WINDOW_OVERFLOW8);
218 } else {
219 HELPER(exception)(EXC_WINDOW_OVERFLOW12);
220 }
221}
222
223uint32_t HELPER(retw)(uint32_t pc)
224{
225 int n = (env->regs[0] >> 30) & 0x3;
226 int m = 0;
227 uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
228 uint32_t windowstart = env->sregs[WINDOW_START];
229 uint32_t ret_pc = 0;
230
231 if (windowstart & windowstart_bit(windowbase - 1, env)) {
232 m = 1;
233 } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
234 m = 2;
235 } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
236 m = 3;
237 }
238
239 if (n == 0 || (m != 0 && m != n) ||
240 ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
241 qemu_log("Illegal retw instruction(pc = %08x), "
242 "PS = %08x, m = %d, n = %d\n",
243 pc, env->sregs[PS], m, n);
244 HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
245 } else {
246 int owb = windowbase;
247
248 ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
249
250 rotate_window(-n);
251 if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
252 env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
253 } else {
254 /* window underflow */
255 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
256 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
257 env->sregs[EPC1] = env->pc = pc;
258
259 if (n == 1) {
260 HELPER(exception)(EXC_WINDOW_UNDERFLOW4);
261 } else if (n == 2) {
262 HELPER(exception)(EXC_WINDOW_UNDERFLOW8);
263 } else if (n == 3) {
264 HELPER(exception)(EXC_WINDOW_UNDERFLOW12);
265 }
266 }
267 }
268 return ret_pc;
269}
270
271void HELPER(rotw)(uint32_t imm4)
272{
273 rotate_window(imm4);
274}
275
276void HELPER(restore_owb)(void)
277{
278 rotate_window_abs((env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
279}
280
281void HELPER(movsp)(uint32_t pc)
282{
283 if ((env->sregs[WINDOW_START] &
284 (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
285 windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
286 windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
287 HELPER(exception_cause)(pc, ALLOCA_CAUSE);
288 }
289}
290
797d780b
MF
291void HELPER(wsr_lbeg)(uint32_t v)
292{
293 if (env->sregs[LBEG] != v) {
294 tb_invalidate_phys_page_range(
295 env->sregs[LEND] - 1, env->sregs[LEND], 0);
296 env->sregs[LBEG] = v;
297 }
298}
299
300void HELPER(wsr_lend)(uint32_t v)
301{
302 if (env->sregs[LEND] != v) {
303 tb_invalidate_phys_page_range(
304 env->sregs[LEND] - 1, env->sregs[LEND], 0);
305 env->sregs[LEND] = v;
306 tb_invalidate_phys_page_range(
307 env->sregs[LEND] - 1, env->sregs[LEND], 0);
308 }
309}
310
553e44f9
MF
311void HELPER(dump_state)(void)
312{
313 cpu_dump_state(env, stderr, fprintf, 0);
314}