[mirror_qemu.git] / target-xtensa / overlay_tool.h

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
        a1, a2, a3, a4, a5, a6) \
    { .targno = (no), .type = (typ), .group = (grp) },

#ifndef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#endif

#ifndef XCHAL_UNALIGNED_LOAD_HW
#define XCHAL_UNALIGNED_LOAD_HW 0
#endif

#ifndef XCHAL_HAVE_VECBASE
#define XCHAL_HAVE_VECBASE 0
#define XCHAL_VECBASE_RESET_VADDR 0
#endif

#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)

#define XTENSA_OPTIONS ( \
    XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
    XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
    XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
    XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
    XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
    XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
    XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
    XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
    XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
    XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
    XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
    XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
    XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
    XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
    XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
    XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
    /* Interrupts and exceptions */ \
    XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
    XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
    XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
        XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
    XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
    XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
        XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
    XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
    /* Local memory, TODO */ \
    XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \
    XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
            XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
    XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \
    XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
            XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
    XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
    /* Memory protection and translation */ \
    XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
            XTENSA_OPTION_REGION_PROTECTION) | \
    XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
            XTENSA_OPTION_REGION_TRANSLATION) | \
    XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
    /* Other, TODO */ \
    XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
    XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG))

#ifndef XCHAL_WINDOW_OF4_VECOFS
#define XCHAL_WINDOW_OF4_VECOFS         0x00000000
#define XCHAL_WINDOW_UF4_VECOFS         0x00000040
#define XCHAL_WINDOW_OF8_VECOFS         0x00000080
#define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS        0x00000100
#define XCHAL_WINDOW_UF12_VECOFS        0x00000140
#endif

#define EXCEPTION_VECTORS { \
        [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
        [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
            XCHAL_WINDOW_VECTORS_VADDR, \
        [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
        [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
        [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
        [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
    }

#define INTERRUPT_VECTORS { \
        0, \
        0, \
        XCHAL_INTLEVEL2_VECTOR_VADDR, \
        XCHAL_INTLEVEL3_VECTOR_VADDR, \
        XCHAL_INTLEVEL4_VECTOR_VADDR, \
        XCHAL_INTLEVEL5_VECTOR_VADDR, \
        XCHAL_INTLEVEL6_VECTOR_VADDR, \
        XCHAL_INTLEVEL7_VECTOR_VADDR, \
    }

#define LEVEL_MASKS { \
        [1] = XCHAL_INTLEVEL1_MASK, \
        [2] = XCHAL_INTLEVEL2_MASK, \
        [3] = XCHAL_INTLEVEL3_MASK, \
        [4] = XCHAL_INTLEVEL4_MASK, \
        [5] = XCHAL_INTLEVEL5_MASK, \
        [6] = XCHAL_INTLEVEL6_MASK, \
        [7] = XCHAL_INTLEVEL7_MASK, \
    }

#define INTTYPE_MASKS { \
        [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
        [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
        [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
    }

#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
#define XTHAL_INTTYPE_NMI INTTYPE_NMI
#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR


#define INTERRUPT(i) { \
        .level = XCHAL_INT ## i ## _LEVEL, \
        .inttype = XCHAL_INT ## i ## _TYPE, \
    }

#define INTERRUPTS { \
        [0] = INTERRUPT(0), \
        [1] = INTERRUPT(1), \
        [2] = INTERRUPT(2), \
        [3] = INTERRUPT(3), \
        [4] = INTERRUPT(4), \
        [5] = INTERRUPT(5), \
        [6] = INTERRUPT(6), \
        [7] = INTERRUPT(7), \
        [8] = INTERRUPT(8), \
        [9] = INTERRUPT(9), \
        [10] = INTERRUPT(10), \
        [11] = INTERRUPT(11), \
        [12] = INTERRUPT(12), \
        [13] = INTERRUPT(13), \
        [14] = INTERRUPT(14), \
        [15] = INTERRUPT(15), \
        [16] = INTERRUPT(16), \
        [17] = INTERRUPT(17), \
        [18] = INTERRUPT(18), \
        [19] = INTERRUPT(19), \
        [20] = INTERRUPT(20), \
        [21] = INTERRUPT(21), \
        [22] = INTERRUPT(22), \
        [23] = INTERRUPT(23), \
        [24] = INTERRUPT(24), \
        [25] = INTERRUPT(25), \
        [26] = INTERRUPT(26), \
        [27] = INTERRUPT(27), \
        [28] = INTERRUPT(28), \
        [29] = INTERRUPT(29), \
        [30] = INTERRUPT(30), \
        [31] = INTERRUPT(31), \
    }

#define TIMERINTS { \
        [0] = XCHAL_TIMER0_INTERRUPT, \
        [1] = XCHAL_TIMER1_INTERRUPT, \
        [2] = XCHAL_TIMER2_INTERRUPT, \
    }

#define EXTINTS { \
        [0] = XCHAL_EXTINT0_NUM, \
        [1] = XCHAL_EXTINT1_NUM, \
        [2] = XCHAL_EXTINT2_NUM, \
        [3] = XCHAL_EXTINT3_NUM, \
        [4] = XCHAL_EXTINT4_NUM, \
        [5] = XCHAL_EXTINT5_NUM, \
        [6] = XCHAL_EXTINT6_NUM, \
        [7] = XCHAL_EXTINT7_NUM, \
        [8] = XCHAL_EXTINT8_NUM, \
        [9] = XCHAL_EXTINT9_NUM, \
        [10] = XCHAL_EXTINT10_NUM, \
        [11] = XCHAL_EXTINT11_NUM, \
        [12] = XCHAL_EXTINT12_NUM, \
        [13] = XCHAL_EXTINT13_NUM, \
        [14] = XCHAL_EXTINT14_NUM, \
        [15] = XCHAL_EXTINT15_NUM, \
        [16] = XCHAL_EXTINT16_NUM, \
        [17] = XCHAL_EXTINT17_NUM, \
        [18] = XCHAL_EXTINT18_NUM, \
        [19] = XCHAL_EXTINT19_NUM, \
        [20] = XCHAL_EXTINT20_NUM, \
        [21] = XCHAL_EXTINT21_NUM, \
        [22] = XCHAL_EXTINT22_NUM, \
        [23] = XCHAL_EXTINT23_NUM, \
        [24] = XCHAL_EXTINT24_NUM, \
        [25] = XCHAL_EXTINT25_NUM, \
        [26] = XCHAL_EXTINT26_NUM, \
        [27] = XCHAL_EXTINT27_NUM, \
        [28] = XCHAL_EXTINT28_NUM, \
        [29] = XCHAL_EXTINT29_NUM, \
        [30] = XCHAL_EXTINT30_NUM, \
        [31] = XCHAL_EXTINT31_NUM, \
    }

#define EXCEPTIONS_SECTION \
    .excm_level = XCHAL_EXCM_LEVEL, \
    .vecbase = XCHAL_VECBASE_RESET_VADDR, \
    .exception_vector = EXCEPTION_VECTORS

#define INTERRUPTS_SECTION \
    .ninterrupt = XCHAL_NUM_INTERRUPTS, \
    .nlevel = XCHAL_NUM_INTLEVELS, \
    .interrupt_vector = INTERRUPT_VECTORS, \
    .level_mask = LEVEL_MASKS, \
    .inttype_mask = INTTYPE_MASKS, \
    .interrupt = INTERRUPTS, \
    .nccompare = XCHAL_NUM_TIMERS, \
    .timerint = TIMERINTS, \
    .nextint = XCHAL_NUM_EXTINTERRUPTS, \
    .extint = EXTINTS

#if XCHAL_HAVE_PTP_MMU

#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
        .nways = ways, \
        .way_size = { \
            (refill_way_size), (refill_way_size), \
            (refill_way_size), (refill_way_size), \
            4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
        }, \
        .varway56 = (way56), \
        .nrefillentries = (refill_way_size) * 4, \
    }

#define ITLB(varway56) \
    TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)

#define DTLB(varway56) \
    TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)

#define TLB_SECTION \
    .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
    .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)

#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR

#define TLB_TEMPLATE { \
        .nways = 1, \
        .way_size = { \
            8, \
        } \
    }

#define TLB_SECTION \
    .itlb = TLB_TEMPLATE, \
    .dtlb = TLB_TEMPLATE

#endif

#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
#define REGISTER_CORE(core) \
    static void __attribute__((constructor)) register_core(void) \
    { \
        static XtensaConfigList node = { \
            .config = &core, \
        }; \
        xtensa_register_core(&node); \
    }
#else
#define REGISTER_CORE(core)
#endif

#define DEBUG_SECTION \
    .debug_level = XCHAL_DEBUGLEVEL, \
    .nibreak = XCHAL_NUM_IBREAK, \
    .ndbreak = XCHAL_NUM_DBREAK

#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
#endif


#if XCHAL_NUM_INTERRUPTS <= 0
#define XCHAL_INT0_LEVEL 0
#define XCHAL_INT0_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 1
#define XCHAL_INT1_LEVEL 0
#define XCHAL_INT1_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 2
#define XCHAL_INT2_LEVEL 0
#define XCHAL_INT2_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 3
#define XCHAL_INT3_LEVEL 0
#define XCHAL_INT3_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 4
#define XCHAL_INT4_LEVEL 0
#define XCHAL_INT4_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 5
#define XCHAL_INT5_LEVEL 0
#define XCHAL_INT5_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 6
#define XCHAL_INT6_LEVEL 0
#define XCHAL_INT6_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 7
#define XCHAL_INT7_LEVEL 0
#define XCHAL_INT7_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 8
#define XCHAL_INT8_LEVEL 0
#define XCHAL_INT8_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 9
#define XCHAL_INT9_LEVEL 0
#define XCHAL_INT9_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 10
#define XCHAL_INT10_LEVEL 0
#define XCHAL_INT10_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 11
#define XCHAL_INT11_LEVEL 0
#define XCHAL_INT11_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 12
#define XCHAL_INT12_LEVEL 0
#define XCHAL_INT12_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 13
#define XCHAL_INT13_LEVEL 0
#define XCHAL_INT13_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 14
#define XCHAL_INT14_LEVEL 0
#define XCHAL_INT14_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 15
#define XCHAL_INT15_LEVEL 0
#define XCHAL_INT15_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 16
#define XCHAL_INT16_LEVEL 0
#define XCHAL_INT16_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 17
#define XCHAL_INT17_LEVEL 0
#define XCHAL_INT17_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 18
#define XCHAL_INT18_LEVEL 0
#define XCHAL_INT18_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 19
#define XCHAL_INT19_LEVEL 0
#define XCHAL_INT19_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 20
#define XCHAL_INT20_LEVEL 0
#define XCHAL_INT20_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 21
#define XCHAL_INT21_LEVEL 0
#define XCHAL_INT21_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 22
#define XCHAL_INT22_LEVEL 0
#define XCHAL_INT22_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 23
#define XCHAL_INT23_LEVEL 0
#define XCHAL_INT23_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 24
#define XCHAL_INT24_LEVEL 0
#define XCHAL_INT24_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 25
#define XCHAL_INT25_LEVEL 0
#define XCHAL_INT25_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 26
#define XCHAL_INT26_LEVEL 0
#define XCHAL_INT26_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 27
#define XCHAL_INT27_LEVEL 0
#define XCHAL_INT27_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 28
#define XCHAL_INT28_LEVEL 0
#define XCHAL_INT28_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 29
#define XCHAL_INT29_LEVEL 0
#define XCHAL_INT29_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 30
#define XCHAL_INT30_LEVEL 0
#define XCHAL_INT30_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 31
#define XCHAL_INT31_LEVEL 0
#define XCHAL_INT31_TYPE 0
#endif


#if XCHAL_NUM_EXTINTERRUPTS <= 0
#define XCHAL_EXTINT0_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 1
#define XCHAL_EXTINT1_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 2
#define XCHAL_EXTINT2_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 3
#define XCHAL_EXTINT3_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 4
#define XCHAL_EXTINT4_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 5
#define XCHAL_EXTINT5_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 6
#define XCHAL_EXTINT6_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 7
#define XCHAL_EXTINT7_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 8
#define XCHAL_EXTINT8_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 9
#define XCHAL_EXTINT9_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 10
#define XCHAL_EXTINT10_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 11
#define XCHAL_EXTINT11_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 12
#define XCHAL_EXTINT12_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 13
#define XCHAL_EXTINT13_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 14
#define XCHAL_EXTINT14_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 15
#define XCHAL_EXTINT15_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 16
#define XCHAL_EXTINT16_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 17
#define XCHAL_EXTINT17_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 18
#define XCHAL_EXTINT18_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 19
#define XCHAL_EXTINT19_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 20
#define XCHAL_EXTINT20_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 21
#define XCHAL_EXTINT21_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 22
#define XCHAL_EXTINT22_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 23
#define XCHAL_EXTINT23_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 24
#define XCHAL_EXTINT24_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 25
#define XCHAL_EXTINT25_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 26
#define XCHAL_EXTINT26_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 27
#define XCHAL_EXTINT27_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 28
#define XCHAL_EXTINT28_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 29
#define XCHAL_EXTINT29_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 30
#define XCHAL_EXTINT30_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 31
#define XCHAL_EXTINT31_NUM 0
#endif


#define XTHAL_TIMER_UNCONFIGURED 0
Commit	Line	Data
ac8b7db4 MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
	28	#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
	29	a1, a2, a3, a4, a5, a6) \
	30	{ .targno = (no), .type = (typ), .group = (grp) },
	31
	32	#ifndef XCHAL_HAVE_DIV32
	33	#define XCHAL_HAVE_DIV32 0
	34	#endif
	35
	36	#ifndef XCHAL_UNALIGNED_LOAD_HW
	37	#define XCHAL_UNALIGNED_LOAD_HW 0
	38	#endif
	39
	40	#ifndef XCHAL_HAVE_VECBASE
	41	#define XCHAL_HAVE_VECBASE 0
	42	#define XCHAL_VECBASE_RESET_VADDR 0
	43	#endif
	44
	45	#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
	46
	47	#define XTENSA_OPTIONS ( \
	48	XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) \| \
	49	XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) \| \
	50	XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) \| \
	51	XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) \| \
	52	XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) \| \
	53	XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) \| \
	54	XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) \| \
	55	XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) \| \
	56	XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) \| \
	57	XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) \| \
	58	XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) \| \
	59	XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) \| \
	60	XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) \| \
	61	XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) \| \
	62	XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) \| \
	63	XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) \| \
	64	/* Interrupts and exceptions */ \
65	XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) \| \
66	XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) \| \
67	XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
68	XTENSA_OPTION_UNALIGNED_EXCEPTION) \| \
69	XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) \| \
70	XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
71	XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) \| \
72	XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) \| \
73	/* Local memory, TODO */ \
0c852e17 MF	74	XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) \| \
	75	XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
	76	XTENSA_OPTION_ICACHE_INDEX_LOCK) \| \
	77	XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) \| \
	78	XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
	79	XTENSA_OPTION_DCACHE_INDEX_LOCK) \| \
ac8b7db4 MF	80	XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) \| \
	81	/* Memory protection and translation */ \
	82	XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
	83	XTENSA_OPTION_REGION_PROTECTION) \| \
	84	XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
	85	XTENSA_OPTION_REGION_TRANSLATION) \| \
	86	XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) \| \
	87	/* Other, TODO */ \
	88	XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) \| \
	89	XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG))
	90
	91	#ifndef XCHAL_WINDOW_OF4_VECOFS
	92	#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
	93	#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
	94	#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
	95	#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
	96	#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
	97	#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
	98	#endif
	99
	100	#define EXCEPTION_VECTORS { \
	101	[EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
	102	[EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
	103	XCHAL_WINDOW_VECTORS_VADDR, \
	104	[EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
	105	XCHAL_WINDOW_VECTORS_VADDR, \
	106	[EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
	107	XCHAL_WINDOW_VECTORS_VADDR, \
	108	[EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
	109	XCHAL_WINDOW_VECTORS_VADDR, \
	110	[EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
	111	XCHAL_WINDOW_VECTORS_VADDR, \
	112	[EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
	113	XCHAL_WINDOW_VECTORS_VADDR, \
	114	[EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
	115	[EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
	116	[EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
18da9326	117	[EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
ac8b7db4 MF	118	}
	119
	120	#define INTERRUPT_VECTORS { \
	121	0, \
	122	0, \
	123	XCHAL_INTLEVEL2_VECTOR_VADDR, \
	124	XCHAL_INTLEVEL3_VECTOR_VADDR, \
	125	XCHAL_INTLEVEL4_VECTOR_VADDR, \
	126	XCHAL_INTLEVEL5_VECTOR_VADDR, \
	127	XCHAL_INTLEVEL6_VECTOR_VADDR, \
	128	XCHAL_INTLEVEL7_VECTOR_VADDR, \
	129	}
	130
	131	#define LEVEL_MASKS { \
	132	[1] = XCHAL_INTLEVEL1_MASK, \
	133	[2] = XCHAL_INTLEVEL2_MASK, \
	134	[3] = XCHAL_INTLEVEL3_MASK, \
	135	[4] = XCHAL_INTLEVEL4_MASK, \
	136	[5] = XCHAL_INTLEVEL5_MASK, \
	137	[6] = XCHAL_INTLEVEL6_MASK, \
	138	[7] = XCHAL_INTLEVEL7_MASK, \
	139	}
	140
	141	#define INTTYPE_MASKS { \
	142	[INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
	143	[INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
	144	[INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
	145	}
	146
	147	#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
	148	#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
	149	#define XTHAL_INTTYPE_NMI INTTYPE_NMI
	150	#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
	151	#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
	152	#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
	153	#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
	154	#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
	155
	156
	157	#define INTERRUPT(i) { \
	158	.level = XCHAL_INT ## i ## _LEVEL, \
	159	.inttype = XCHAL_INT ## i ## _TYPE, \
	160	}
	161
	162	#define INTERRUPTS { \
	163	[0] = INTERRUPT(0), \
	164	[1] = INTERRUPT(1), \
	165	[2] = INTERRUPT(2), \
	166	[3] = INTERRUPT(3), \
	167	[4] = INTERRUPT(4), \
	168	[5] = INTERRUPT(5), \
	169	[6] = INTERRUPT(6), \
	170	[7] = INTERRUPT(7), \
	171	[8] = INTERRUPT(8), \
	172	[9] = INTERRUPT(9), \
	173	[10] = INTERRUPT(10), \
	174	[11] = INTERRUPT(11), \
	175	[12] = INTERRUPT(12), \
	176	[13] = INTERRUPT(13), \
	177	[14] = INTERRUPT(14), \
	178	[15] = INTERRUPT(15), \
	179	[16] = INTERRUPT(16), \
	180	[17] = INTERRUPT(17), \
	181	[18] = INTERRUPT(18), \
182	[19] = INTERRUPT(19), \
183	[20] = INTERRUPT(20), \
184	[21] = INTERRUPT(21), \
185	[22] = INTERRUPT(22), \
186	[23] = INTERRUPT(23), \
187	[24] = INTERRUPT(24), \
188	[25] = INTERRUPT(25), \
189	[26] = INTERRUPT(26), \
190	[27] = INTERRUPT(27), \
191	[28] = INTERRUPT(28), \
192	[29] = INTERRUPT(29), \
193	[30] = INTERRUPT(30), \
194	[31] = INTERRUPT(31), \
195	}
196
197	#define TIMERINTS { \
198	[0] = XCHAL_TIMER0_INTERRUPT, \
199	[1] = XCHAL_TIMER1_INTERRUPT, \
200	[2] = XCHAL_TIMER2_INTERRUPT, \
201	}
202
203	#define EXTINTS { \
204	[0] = XCHAL_EXTINT0_NUM, \
205	[1] = XCHAL_EXTINT1_NUM, \
206	[2] = XCHAL_EXTINT2_NUM, \
207	[3] = XCHAL_EXTINT3_NUM, \
208	[4] = XCHAL_EXTINT4_NUM, \
209	[5] = XCHAL_EXTINT5_NUM, \
210	[6] = XCHAL_EXTINT6_NUM, \
211	[7] = XCHAL_EXTINT7_NUM, \
212	[8] = XCHAL_EXTINT8_NUM, \
213	[9] = XCHAL_EXTINT9_NUM, \
214	[10] = XCHAL_EXTINT10_NUM, \
215	[11] = XCHAL_EXTINT11_NUM, \
216	[12] = XCHAL_EXTINT12_NUM, \
217	[13] = XCHAL_EXTINT13_NUM, \
218	[14] = XCHAL_EXTINT14_NUM, \
219	[15] = XCHAL_EXTINT15_NUM, \
220	[16] = XCHAL_EXTINT16_NUM, \
221	[17] = XCHAL_EXTINT17_NUM, \
222	[18] = XCHAL_EXTINT18_NUM, \
223	[19] = XCHAL_EXTINT19_NUM, \
224	[20] = XCHAL_EXTINT20_NUM, \
225	[21] = XCHAL_EXTINT21_NUM, \
226	[22] = XCHAL_EXTINT22_NUM, \
227	[23] = XCHAL_EXTINT23_NUM, \
228	[24] = XCHAL_EXTINT24_NUM, \
229	[25] = XCHAL_EXTINT25_NUM, \
230	[26] = XCHAL_EXTINT26_NUM, \
231	[27] = XCHAL_EXTINT27_NUM, \
232	[28] = XCHAL_EXTINT28_NUM, \
233	[29] = XCHAL_EXTINT29_NUM, \
234	[30] = XCHAL_EXTINT30_NUM, \
235	[31] = XCHAL_EXTINT31_NUM, \
236	}
237
238	#define EXCEPTIONS_SECTION \
239	.excm_level = XCHAL_EXCM_LEVEL, \
240	.vecbase = XCHAL_VECBASE_RESET_VADDR, \
241	.exception_vector = EXCEPTION_VECTORS
242
243	#define INTERRUPTS_SECTION \
244	.ninterrupt = XCHAL_NUM_INTERRUPTS, \
245	.nlevel = XCHAL_NUM_INTLEVELS, \
246	.interrupt_vector = INTERRUPT_VECTORS, \
247	.level_mask = LEVEL_MASKS, \
248	.inttype_mask = INTTYPE_MASKS, \
249	.interrupt = INTERRUPTS, \
250	.nccompare = XCHAL_NUM_TIMERS, \
251	.timerint = TIMERINTS, \
252	.nextint = XCHAL_NUM_EXTINTERRUPTS, \
253	.extint = EXTINTS
254
b96ac3e4 MF	255	#if XCHAL_HAVE_PTP_MMU
b96ac3e4 MF	256
ac8b7db4 MF	257	#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
	258	.nways = ways, \
	259	.way_size = { \
	260	(refill_way_size), (refill_way_size), \
	261	(refill_way_size), (refill_way_size), \
0fdd2e1d	262	4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
ac8b7db4 MF	263	}, \
	264	.varway56 = (way56), \
	265	.nrefillentries = (refill_way_size) * 4, \
	266	}
	267
	268	#define ITLB(varway56) \
	269	TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
	270
	271	#define DTLB(varway56) \
	272	TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
	273
ac8b7db4 MF	274	#define TLB_SECTION \
	275	.itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
	276	.dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
b96ac3e4 MF	277
	278	#elif XCHAL_HAVE_XLT_CACHEATTR \|\| XCHAL_HAVE_MIMIC_CACHEATTR
	279
	280	#define TLB_TEMPLATE { \
	281	.nways = 1, \
	282	.way_size = { \
	283	8, \
	284	} \
	285	}
	286
	287	#define TLB_SECTION \
	288	.itlb = TLB_TEMPLATE, \
	289	.dtlb = TLB_TEMPLATE
	290
ac8b7db4 MF	291	#endif
	292
	293	#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
	294	#define REGISTER_CORE(core) \
	295	static void __attribute__((constructor)) register_core(void) \
	296	{ \
	297	static XtensaConfigList node = { \
	298	.config = &core, \
	299	}; \
	300	xtensa_register_core(&node); \
	301	}
	302	#else
	303	#define REGISTER_CORE(core)
	304	#endif
	305
18da9326 MF	306	#define DEBUG_SECTION \
	307	.debug_level = XCHAL_DEBUGLEVEL, \
	308	.nibreak = XCHAL_NUM_IBREAK, \
	309	.ndbreak = XCHAL_NUM_DBREAK
ac8b7db4 MF	310
	311	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
	312	#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
	313	#endif
	314	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
	315	#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
	316	#endif
	317	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
	318	#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
	319	#endif
	320	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
	321	#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
	322	#endif
	323	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
	324	#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
	325	#endif
	326	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
	327	#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
	328	#endif
	329
	330
	331	#if XCHAL_NUM_INTERRUPTS <= 0
	332	#define XCHAL_INT0_LEVEL 0
	333	#define XCHAL_INT0_TYPE 0
	334	#endif
	335	#if XCHAL_NUM_INTERRUPTS <= 1
	336	#define XCHAL_INT1_LEVEL 0
	337	#define XCHAL_INT1_TYPE 0
	338	#endif
	339	#if XCHAL_NUM_INTERRUPTS <= 2
	340	#define XCHAL_INT2_LEVEL 0
	341	#define XCHAL_INT2_TYPE 0
	342	#endif
	343	#if XCHAL_NUM_INTERRUPTS <= 3
	344	#define XCHAL_INT3_LEVEL 0
	345	#define XCHAL_INT3_TYPE 0
	346	#endif
	347	#if XCHAL_NUM_INTERRUPTS <= 4
	348	#define XCHAL_INT4_LEVEL 0
	349	#define XCHAL_INT4_TYPE 0
	350	#endif
	351	#if XCHAL_NUM_INTERRUPTS <= 5
	352	#define XCHAL_INT5_LEVEL 0
	353	#define XCHAL_INT5_TYPE 0
	354	#endif
	355	#if XCHAL_NUM_INTERRUPTS <= 6
	356	#define XCHAL_INT6_LEVEL 0
	357	#define XCHAL_INT6_TYPE 0
	358	#endif
	359	#if XCHAL_NUM_INTERRUPTS <= 7
	360	#define XCHAL_INT7_LEVEL 0
	361	#define XCHAL_INT7_TYPE 0
	362	#endif
	363	#if XCHAL_NUM_INTERRUPTS <= 8
	364	#define XCHAL_INT8_LEVEL 0
	365	#define XCHAL_INT8_TYPE 0
	366	#endif
	367	#if XCHAL_NUM_INTERRUPTS <= 9
	368	#define XCHAL_INT9_LEVEL 0
	369	#define XCHAL_INT9_TYPE 0
	370	#endif
	371	#if XCHAL_NUM_INTERRUPTS <= 10
	372	#define XCHAL_INT10_LEVEL 0
	373	#define XCHAL_INT10_TYPE 0
374	#endif
375	#if XCHAL_NUM_INTERRUPTS <= 11
376	#define XCHAL_INT11_LEVEL 0
377	#define XCHAL_INT11_TYPE 0
378	#endif
379	#if XCHAL_NUM_INTERRUPTS <= 12
380	#define XCHAL_INT12_LEVEL 0
381	#define XCHAL_INT12_TYPE 0
382	#endif
383	#if XCHAL_NUM_INTERRUPTS <= 13
384	#define XCHAL_INT13_LEVEL 0
385	#define XCHAL_INT13_TYPE 0
386	#endif
387	#if XCHAL_NUM_INTERRUPTS <= 14
388	#define XCHAL_INT14_LEVEL 0
389	#define XCHAL_INT14_TYPE 0
390	#endif
391	#if XCHAL_NUM_INTERRUPTS <= 15
392	#define XCHAL_INT15_LEVEL 0
393	#define XCHAL_INT15_TYPE 0
394	#endif
395	#if XCHAL_NUM_INTERRUPTS <= 16
396	#define XCHAL_INT16_LEVEL 0
397	#define XCHAL_INT16_TYPE 0
398	#endif
399	#if XCHAL_NUM_INTERRUPTS <= 17
400	#define XCHAL_INT17_LEVEL 0
401	#define XCHAL_INT17_TYPE 0
402	#endif
403	#if XCHAL_NUM_INTERRUPTS <= 18
404	#define XCHAL_INT18_LEVEL 0
405	#define XCHAL_INT18_TYPE 0
406	#endif
407	#if XCHAL_NUM_INTERRUPTS <= 19
408	#define XCHAL_INT19_LEVEL 0
409	#define XCHAL_INT19_TYPE 0
410	#endif
411	#if XCHAL_NUM_INTERRUPTS <= 20
412	#define XCHAL_INT20_LEVEL 0
413	#define XCHAL_INT20_TYPE 0
414	#endif
415	#if XCHAL_NUM_INTERRUPTS <= 21
416	#define XCHAL_INT21_LEVEL 0
417	#define XCHAL_INT21_TYPE 0
418	#endif
419	#if XCHAL_NUM_INTERRUPTS <= 22
420	#define XCHAL_INT22_LEVEL 0
421	#define XCHAL_INT22_TYPE 0
422	#endif
423	#if XCHAL_NUM_INTERRUPTS <= 23
424	#define XCHAL_INT23_LEVEL 0
425	#define XCHAL_INT23_TYPE 0
426	#endif
427	#if XCHAL_NUM_INTERRUPTS <= 24
428	#define XCHAL_INT24_LEVEL 0
429	#define XCHAL_INT24_TYPE 0
430	#endif
431	#if XCHAL_NUM_INTERRUPTS <= 25
432	#define XCHAL_INT25_LEVEL 0
433	#define XCHAL_INT25_TYPE 0
434	#endif
435	#if XCHAL_NUM_INTERRUPTS <= 26
436	#define XCHAL_INT26_LEVEL 0
437	#define XCHAL_INT26_TYPE 0
438	#endif
439	#if XCHAL_NUM_INTERRUPTS <= 27
440	#define XCHAL_INT27_LEVEL 0
441	#define XCHAL_INT27_TYPE 0
442	#endif
443	#if XCHAL_NUM_INTERRUPTS <= 28
444	#define XCHAL_INT28_LEVEL 0
445	#define XCHAL_INT28_TYPE 0
446	#endif
447	#if XCHAL_NUM_INTERRUPTS <= 29
448	#define XCHAL_INT29_LEVEL 0
449	#define XCHAL_INT29_TYPE 0
450	#endif
451	#if XCHAL_NUM_INTERRUPTS <= 30
452	#define XCHAL_INT30_LEVEL 0
453	#define XCHAL_INT30_TYPE 0
454	#endif
455	#if XCHAL_NUM_INTERRUPTS <= 31
456	#define XCHAL_INT31_LEVEL 0
457	#define XCHAL_INT31_TYPE 0
458	#endif
459
460
461	#if XCHAL_NUM_EXTINTERRUPTS <= 0
462	#define XCHAL_EXTINT0_NUM 0
463	#endif
464	#if XCHAL_NUM_EXTINTERRUPTS <= 1
465	#define XCHAL_EXTINT1_NUM 0
466	#endif
467	#if XCHAL_NUM_EXTINTERRUPTS <= 2
468	#define XCHAL_EXTINT2_NUM 0
469	#endif
470	#if XCHAL_NUM_EXTINTERRUPTS <= 3
471	#define XCHAL_EXTINT3_NUM 0
472	#endif
473	#if XCHAL_NUM_EXTINTERRUPTS <= 4
474	#define XCHAL_EXTINT4_NUM 0
475	#endif
476	#if XCHAL_NUM_EXTINTERRUPTS <= 5
477	#define XCHAL_EXTINT5_NUM 0
478	#endif
479	#if XCHAL_NUM_EXTINTERRUPTS <= 6
480	#define XCHAL_EXTINT6_NUM 0
481	#endif
482	#if XCHAL_NUM_EXTINTERRUPTS <= 7
483	#define XCHAL_EXTINT7_NUM 0
484	#endif
485	#if XCHAL_NUM_EXTINTERRUPTS <= 8
486	#define XCHAL_EXTINT8_NUM 0
487	#endif
488	#if XCHAL_NUM_EXTINTERRUPTS <= 9
489	#define XCHAL_EXTINT9_NUM 0
490	#endif
491	#if XCHAL_NUM_EXTINTERRUPTS <= 10
492	#define XCHAL_EXTINT10_NUM 0
493	#endif
494	#if XCHAL_NUM_EXTINTERRUPTS <= 11
495	#define XCHAL_EXTINT11_NUM 0
496	#endif
497	#if XCHAL_NUM_EXTINTERRUPTS <= 12
498	#define XCHAL_EXTINT12_NUM 0
499	#endif
500	#if XCHAL_NUM_EXTINTERRUPTS <= 13
501	#define XCHAL_EXTINT13_NUM 0
502	#endif
503	#if XCHAL_NUM_EXTINTERRUPTS <= 14
504	#define XCHAL_EXTINT14_NUM 0
505	#endif
506	#if XCHAL_NUM_EXTINTERRUPTS <= 15
507	#define XCHAL_EXTINT15_NUM 0
508	#endif
509	#if XCHAL_NUM_EXTINTERRUPTS <= 16
510	#define XCHAL_EXTINT16_NUM 0
511	#endif
512	#if XCHAL_NUM_EXTINTERRUPTS <= 17
513	#define XCHAL_EXTINT17_NUM 0
514	#endif
515	#if XCHAL_NUM_EXTINTERRUPTS <= 18
516	#define XCHAL_EXTINT18_NUM 0
517	#endif
518	#if XCHAL_NUM_EXTINTERRUPTS <= 19
519	#define XCHAL_EXTINT19_NUM 0
520	#endif
521	#if XCHAL_NUM_EXTINTERRUPTS <= 20
522	#define XCHAL_EXTINT20_NUM 0
523	#endif
524	#if XCHAL_NUM_EXTINTERRUPTS <= 21
525	#define XCHAL_EXTINT21_NUM 0
526	#endif
527	#if XCHAL_NUM_EXTINTERRUPTS <= 22
528	#define XCHAL_EXTINT22_NUM 0
529	#endif
530	#if XCHAL_NUM_EXTINTERRUPTS <= 23
531	#define XCHAL_EXTINT23_NUM 0
532	#endif
533	#if XCHAL_NUM_EXTINTERRUPTS <= 24
534	#define XCHAL_EXTINT24_NUM 0
535	#endif
536	#if XCHAL_NUM_EXTINTERRUPTS <= 25
537	#define XCHAL_EXTINT25_NUM 0
538	#endif
539	#if XCHAL_NUM_EXTINTERRUPTS <= 26
540	#define XCHAL_EXTINT26_NUM 0
541	#endif
542	#if XCHAL_NUM_EXTINTERRUPTS <= 27
543	#define XCHAL_EXTINT27_NUM 0
544	#endif
545	#if XCHAL_NUM_EXTINTERRUPTS <= 28
546	#define XCHAL_EXTINT28_NUM 0
547	#endif
548	#if XCHAL_NUM_EXTINTERRUPTS <= 29
549	#define XCHAL_EXTINT29_NUM 0
550	#endif
551	#if XCHAL_NUM_EXTINTERRUPTS <= 30
552	#define XCHAL_EXTINT30_NUM 0
553	#endif
554	#if XCHAL_NUM_EXTINTERRUPTS <= 31
555	#define XCHAL_EXTINT31_NUM 0
556	#endif
557
558
559	#define XTHAL_TIMER_UNCONFIGURED 0