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2328826b MF |
1 | /* |
2 | * Xtensa ISA: | |
3 | * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm | |
4 | * | |
5 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
6 | * All rights reserved. | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | |
15 | * * Neither the name of the Open Source and Linux Lab nor the | |
16 | * names of its contributors may be used to endorse or promote products | |
17 | * derived from this software without specific prior written permission. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
09aae23d | 31 | #include "qemu/osdep.h" |
2328826b MF |
32 | |
33 | #include "cpu.h" | |
022c62cb | 34 | #include "exec/exec-all.h" |
76cad711 | 35 | #include "disas/disas.h" |
2328826b | 36 | #include "tcg-op.h" |
1de7afc9 | 37 | #include "qemu/log.h" |
9c17d615 | 38 | #include "sysemu/sysemu.h" |
63c91552 | 39 | #include "exec/exec-all.h" |
f08b6170 | 40 | #include "exec/cpu_ldst.h" |
cfe67cef | 41 | #include "exec/semihost.h" |
2328826b | 42 | |
2ef6175a RH |
43 | #include "exec/helper-proto.h" |
44 | #include "exec/helper-gen.h" | |
dedc5eae | 45 | |
a7e30d84 | 46 | #include "trace-tcg.h" |
508127e2 | 47 | #include "exec/log.h" |
a7e30d84 LV |
48 | |
49 | ||
dedc5eae MF |
50 | typedef struct DisasContext { |
51 | const XtensaConfig *config; | |
52 | TranslationBlock *tb; | |
53 | uint32_t pc; | |
54 | uint32_t next_pc; | |
f0a548b9 MF |
55 | int cring; |
56 | int ring; | |
797d780b MF |
57 | uint32_t lbeg; |
58 | uint32_t lend; | |
6ad6dbf7 | 59 | TCGv_i32 litbase; |
dedc5eae MF |
60 | int is_jmp; |
61 | int singlestep_enabled; | |
3580ecad MF |
62 | |
63 | bool sar_5bit; | |
64 | bool sar_m32_5bit; | |
65 | bool sar_m32_allocated; | |
66 | TCGv_i32 sar_m32; | |
b994e91b MF |
67 | |
68 | uint32_t ccount_delta; | |
2db59a76 | 69 | unsigned window; |
e61dc8f7 MF |
70 | |
71 | bool debug; | |
35b5c044 MF |
72 | bool icount; |
73 | TCGv_i32 next_icount; | |
ef04a846 MF |
74 | |
75 | unsigned cpenable; | |
dedc5eae MF |
76 | } DisasContext; |
77 | ||
1bcea73e | 78 | static TCGv_env cpu_env; |
dedc5eae MF |
79 | static TCGv_i32 cpu_pc; |
80 | static TCGv_i32 cpu_R[16]; | |
dd519cbe | 81 | static TCGv_i32 cpu_FR[16]; |
2af3da91 MF |
82 | static TCGv_i32 cpu_SR[256]; |
83 | static TCGv_i32 cpu_UR[256]; | |
dedc5eae | 84 | |
022c62cb | 85 | #include "exec/gen-icount.h" |
2328826b | 86 | |
fe0bd475 MF |
87 | typedef struct XtensaReg { |
88 | const char *name; | |
89 | uint64_t opt_bits; | |
53593e90 MF |
90 | enum { |
91 | SR_R = 1, | |
92 | SR_W = 2, | |
93 | SR_X = 4, | |
94 | SR_RW = 3, | |
95 | SR_RWX = 7, | |
96 | } access; | |
fe0bd475 MF |
97 | } XtensaReg; |
98 | ||
53593e90 | 99 | #define XTENSA_REG_ACCESS(regname, opt, acc) { \ |
fe0bd475 MF |
100 | .name = (regname), \ |
101 | .opt_bits = XTENSA_OPTION_BIT(opt), \ | |
53593e90 | 102 | .access = (acc), \ |
fe0bd475 MF |
103 | } |
104 | ||
53593e90 MF |
105 | #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX) |
106 | ||
604e1f9c | 107 | #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \ |
fe0bd475 MF |
108 | .name = (regname), \ |
109 | .opt_bits = (opt), \ | |
604e1f9c | 110 | .access = (acc), \ |
fe0bd475 MF |
111 | } |
112 | ||
604e1f9c MF |
113 | #define XTENSA_REG_BITS(regname, opt) \ |
114 | XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX) | |
115 | ||
fe0bd475 MF |
116 | static const XtensaReg sregnames[256] = { |
117 | [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP), | |
118 | [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP), | |
119 | [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP), | |
120 | [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL), | |
121 | [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN), | |
122 | [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R), | |
123 | [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE), | |
124 | [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16), | |
125 | [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16), | |
126 | [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16), | |
127 | [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), | |
128 | [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), | |
129 | [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), | |
130 | [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), | |
131 | [WINDOW_START] = XTENSA_REG("WINDOW_START", | |
132 | XTENSA_OPTION_WINDOWED_REGISTER), | |
133 | [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), | |
134 | [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), | |
135 | [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), | |
136 | [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), | |
137 | [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG), | |
138 | [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), | |
139 | [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), | |
140 | [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), | |
141 | [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), | |
142 | [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), | |
143 | [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG), | |
144 | [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG), | |
145 | [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG), | |
604e1f9c | 146 | [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R), |
fe0bd475 MF |
147 | [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION), |
148 | [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
149 | [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
150 | [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
151 | [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
152 | [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
153 | [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
154 | [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION), | |
155 | [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
156 | [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
157 | [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
158 | [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
159 | [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
160 | [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
604e1f9c | 161 | [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R), |
fe0bd475 MF |
162 | [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION), |
163 | [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2", | |
164 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
165 | [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3", | |
166 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
167 | [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4", | |
168 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
169 | [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5", | |
170 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
171 | [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6", | |
172 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
173 | [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7", | |
174 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
175 | [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR), | |
53593e90 MF |
176 | [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW), |
177 | [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W), | |
fe0bd475 MF |
178 | [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT), |
179 | [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL), | |
180 | [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR), | |
181 | [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION), | |
53593e90 | 182 | [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R), |
fe0bd475 | 183 | [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT), |
53593e90 | 184 | [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R), |
fe0bd475 MF |
185 | [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG), |
186 | [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG), | |
187 | [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION), | |
188 | [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT), | |
189 | [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1", | |
190 | XTENSA_OPTION_TIMER_INTERRUPT), | |
191 | [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", | |
192 | XTENSA_OPTION_TIMER_INTERRUPT), | |
b7909d81 MF |
193 | [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), |
194 | [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), | |
195 | [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), | |
196 | [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), | |
2af3da91 MF |
197 | }; |
198 | ||
fe0bd475 MF |
199 | static const XtensaReg uregnames[256] = { |
200 | [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), | |
201 | [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), | |
202 | [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), | |
2af3da91 MF |
203 | }; |
204 | ||
2328826b MF |
205 | void xtensa_translate_init(void) |
206 | { | |
dedc5eae MF |
207 | static const char * const regnames[] = { |
208 | "ar0", "ar1", "ar2", "ar3", | |
209 | "ar4", "ar5", "ar6", "ar7", | |
210 | "ar8", "ar9", "ar10", "ar11", | |
211 | "ar12", "ar13", "ar14", "ar15", | |
212 | }; | |
dd519cbe MF |
213 | static const char * const fregnames[] = { |
214 | "f0", "f1", "f2", "f3", | |
215 | "f4", "f5", "f6", "f7", | |
216 | "f8", "f9", "f10", "f11", | |
217 | "f12", "f13", "f14", "f15", | |
218 | }; | |
dedc5eae MF |
219 | int i; |
220 | ||
221 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
7c255043 | 222 | tcg_ctx.tcg_env = cpu_env; |
e1ccc054 | 223 | cpu_pc = tcg_global_mem_new_i32(cpu_env, |
97129ac8 | 224 | offsetof(CPUXtensaState, pc), "pc"); |
dedc5eae MF |
225 | |
226 | for (i = 0; i < 16; i++) { | |
e1ccc054 | 227 | cpu_R[i] = tcg_global_mem_new_i32(cpu_env, |
97129ac8 | 228 | offsetof(CPUXtensaState, regs[i]), |
dedc5eae MF |
229 | regnames[i]); |
230 | } | |
2af3da91 | 231 | |
dd519cbe | 232 | for (i = 0; i < 16; i++) { |
e1ccc054 | 233 | cpu_FR[i] = tcg_global_mem_new_i32(cpu_env, |
ddd44279 | 234 | offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]), |
dd519cbe MF |
235 | fregnames[i]); |
236 | } | |
237 | ||
2af3da91 | 238 | for (i = 0; i < 256; ++i) { |
fe0bd475 | 239 | if (sregnames[i].name) { |
e1ccc054 | 240 | cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, |
97129ac8 | 241 | offsetof(CPUXtensaState, sregs[i]), |
fe0bd475 | 242 | sregnames[i].name); |
2af3da91 MF |
243 | } |
244 | } | |
245 | ||
246 | for (i = 0; i < 256; ++i) { | |
fe0bd475 | 247 | if (uregnames[i].name) { |
e1ccc054 | 248 | cpu_UR[i] = tcg_global_mem_new_i32(cpu_env, |
97129ac8 | 249 | offsetof(CPUXtensaState, uregs[i]), |
fe0bd475 | 250 | uregnames[i].name); |
2af3da91 MF |
251 | } |
252 | } | |
dedc5eae MF |
253 | } |
254 | ||
b67ea0cd MF |
255 | static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt) |
256 | { | |
257 | return xtensa_option_bits_enabled(dc->config, opt); | |
258 | } | |
259 | ||
dedc5eae MF |
260 | static inline bool option_enabled(DisasContext *dc, int opt) |
261 | { | |
262 | return xtensa_option_enabled(dc->config, opt); | |
263 | } | |
264 | ||
6ad6dbf7 MF |
265 | static void init_litbase(DisasContext *dc) |
266 | { | |
267 | if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { | |
268 | dc->litbase = tcg_temp_local_new_i32(); | |
269 | tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000); | |
270 | } | |
271 | } | |
272 | ||
273 | static void reset_litbase(DisasContext *dc) | |
274 | { | |
275 | if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { | |
276 | tcg_temp_free(dc->litbase); | |
277 | } | |
278 | } | |
279 | ||
3580ecad MF |
280 | static void init_sar_tracker(DisasContext *dc) |
281 | { | |
282 | dc->sar_5bit = false; | |
283 | dc->sar_m32_5bit = false; | |
284 | dc->sar_m32_allocated = false; | |
285 | } | |
286 | ||
287 | static void reset_sar_tracker(DisasContext *dc) | |
288 | { | |
289 | if (dc->sar_m32_allocated) { | |
290 | tcg_temp_free(dc->sar_m32); | |
291 | } | |
292 | } | |
293 | ||
294 | static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) | |
295 | { | |
296 | tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); | |
297 | if (dc->sar_m32_5bit) { | |
298 | tcg_gen_discard_i32(dc->sar_m32); | |
299 | } | |
300 | dc->sar_5bit = true; | |
301 | dc->sar_m32_5bit = false; | |
302 | } | |
303 | ||
304 | static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) | |
305 | { | |
306 | TCGv_i32 tmp = tcg_const_i32(32); | |
307 | if (!dc->sar_m32_allocated) { | |
308 | dc->sar_m32 = tcg_temp_local_new_i32(); | |
309 | dc->sar_m32_allocated = true; | |
310 | } | |
311 | tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); | |
312 | tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32); | |
313 | dc->sar_5bit = false; | |
314 | dc->sar_m32_5bit = true; | |
315 | tcg_temp_free(tmp); | |
316 | } | |
317 | ||
2db59a76 | 318 | static void gen_advance_ccount(DisasContext *dc) |
b994e91b MF |
319 | { |
320 | if (dc->ccount_delta > 0) { | |
321 | TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta); | |
f492b82d | 322 | gen_helper_advance_ccount(cpu_env, tmp); |
b994e91b MF |
323 | tcg_temp_free(tmp); |
324 | } | |
908c67fc MF |
325 | dc->ccount_delta = 0; |
326 | } | |
327 | ||
b994e91b | 328 | static void gen_exception(DisasContext *dc, int excp) |
dedc5eae MF |
329 | { |
330 | TCGv_i32 tmp = tcg_const_i32(excp); | |
b994e91b | 331 | gen_advance_ccount(dc); |
f492b82d | 332 | gen_helper_exception(cpu_env, tmp); |
dedc5eae MF |
333 | tcg_temp_free(tmp); |
334 | } | |
335 | ||
40643d7c MF |
336 | static void gen_exception_cause(DisasContext *dc, uint32_t cause) |
337 | { | |
338 | TCGv_i32 tpc = tcg_const_i32(dc->pc); | |
339 | TCGv_i32 tcause = tcg_const_i32(cause); | |
b994e91b | 340 | gen_advance_ccount(dc); |
f492b82d | 341 | gen_helper_exception_cause(cpu_env, tpc, tcause); |
40643d7c MF |
342 | tcg_temp_free(tpc); |
343 | tcg_temp_free(tcause); | |
6b814719 MF |
344 | if (cause == ILLEGAL_INSTRUCTION_CAUSE || |
345 | cause == SYSCALL_CAUSE) { | |
346 | dc->is_jmp = DISAS_UPDATE; | |
347 | } | |
40643d7c MF |
348 | } |
349 | ||
5b4e481b MF |
350 | static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause, |
351 | TCGv_i32 vaddr) | |
352 | { | |
353 | TCGv_i32 tpc = tcg_const_i32(dc->pc); | |
354 | TCGv_i32 tcause = tcg_const_i32(cause); | |
b994e91b | 355 | gen_advance_ccount(dc); |
f492b82d | 356 | gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr); |
5b4e481b MF |
357 | tcg_temp_free(tpc); |
358 | tcg_temp_free(tcause); | |
359 | } | |
360 | ||
e61dc8f7 MF |
361 | static void gen_debug_exception(DisasContext *dc, uint32_t cause) |
362 | { | |
363 | TCGv_i32 tpc = tcg_const_i32(dc->pc); | |
364 | TCGv_i32 tcause = tcg_const_i32(cause); | |
365 | gen_advance_ccount(dc); | |
f492b82d | 366 | gen_helper_debug_exception(cpu_env, tpc, tcause); |
e61dc8f7 MF |
367 | tcg_temp_free(tpc); |
368 | tcg_temp_free(tcause); | |
369 | if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { | |
370 | dc->is_jmp = DISAS_UPDATE; | |
371 | } | |
372 | } | |
373 | ||
97e89ee9 | 374 | static bool gen_check_privilege(DisasContext *dc) |
40643d7c MF |
375 | { |
376 | if (dc->cring) { | |
377 | gen_exception_cause(dc, PRIVILEGED_CAUSE); | |
6b814719 | 378 | dc->is_jmp = DISAS_UPDATE; |
97e89ee9 | 379 | return false; |
40643d7c | 380 | } |
97e89ee9 | 381 | return true; |
40643d7c MF |
382 | } |
383 | ||
97e89ee9 | 384 | static bool gen_check_cpenable(DisasContext *dc, unsigned cp) |
ef04a846 MF |
385 | { |
386 | if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && | |
387 | !(dc->cpenable & (1 << cp))) { | |
388 | gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); | |
389 | dc->is_jmp = DISAS_UPDATE; | |
97e89ee9 | 390 | return false; |
ef04a846 | 391 | } |
97e89ee9 | 392 | return true; |
ef04a846 MF |
393 | } |
394 | ||
dedc5eae MF |
395 | static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) |
396 | { | |
397 | tcg_gen_mov_i32(cpu_pc, dest); | |
35b5c044 MF |
398 | gen_advance_ccount(dc); |
399 | if (dc->icount) { | |
400 | tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); | |
401 | } | |
dedc5eae | 402 | if (dc->singlestep_enabled) { |
b994e91b | 403 | gen_exception(dc, EXCP_DEBUG); |
dedc5eae MF |
404 | } else { |
405 | if (slot >= 0) { | |
406 | tcg_gen_goto_tb(slot); | |
8cfd0495 | 407 | tcg_gen_exit_tb((uintptr_t)dc->tb + slot); |
dedc5eae MF |
408 | } else { |
409 | tcg_gen_exit_tb(0); | |
410 | } | |
411 | } | |
412 | dc->is_jmp = DISAS_UPDATE; | |
413 | } | |
414 | ||
67882fd1 MF |
415 | static void gen_jump(DisasContext *dc, TCGv dest) |
416 | { | |
417 | gen_jump_slot(dc, dest, -1); | |
418 | } | |
419 | ||
dedc5eae MF |
420 | static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) |
421 | { | |
422 | TCGv_i32 tmp = tcg_const_i32(dest); | |
90aa39a1 | 423 | #ifndef CONFIG_USER_ONLY |
433d33c5 | 424 | if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { |
dedc5eae MF |
425 | slot = -1; |
426 | } | |
90aa39a1 | 427 | #endif |
dedc5eae MF |
428 | gen_jump_slot(dc, tmp, slot); |
429 | tcg_temp_free(tmp); | |
430 | } | |
431 | ||
553e44f9 MF |
432 | static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, |
433 | int slot) | |
434 | { | |
435 | TCGv_i32 tcallinc = tcg_const_i32(callinc); | |
436 | ||
437 | tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], | |
438 | tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN); | |
439 | tcg_temp_free(tcallinc); | |
440 | tcg_gen_movi_i32(cpu_R[callinc << 2], | |
441 | (callinc << 30) | (dc->next_pc & 0x3fffffff)); | |
442 | gen_jump_slot(dc, dest, slot); | |
443 | } | |
444 | ||
445 | static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest) | |
446 | { | |
447 | gen_callw_slot(dc, callinc, dest, -1); | |
448 | } | |
449 | ||
450 | static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) | |
451 | { | |
452 | TCGv_i32 tmp = tcg_const_i32(dest); | |
90aa39a1 | 453 | #ifndef CONFIG_USER_ONLY |
433d33c5 | 454 | if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { |
553e44f9 MF |
455 | slot = -1; |
456 | } | |
90aa39a1 | 457 | #endif |
553e44f9 MF |
458 | gen_callw_slot(dc, callinc, tmp, slot); |
459 | tcg_temp_free(tmp); | |
460 | } | |
461 | ||
797d780b MF |
462 | static bool gen_check_loop_end(DisasContext *dc, int slot) |
463 | { | |
464 | if (option_enabled(dc, XTENSA_OPTION_LOOP) && | |
465 | !(dc->tb->flags & XTENSA_TBFLAG_EXCM) && | |
466 | dc->next_pc == dc->lend) { | |
42a268c2 | 467 | TCGLabel *label = gen_new_label(); |
797d780b | 468 | |
d865f307 | 469 | gen_advance_ccount(dc); |
797d780b MF |
470 | tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); |
471 | tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); | |
472 | gen_jumpi(dc, dc->lbeg, slot); | |
473 | gen_set_label(label); | |
474 | gen_jumpi(dc, dc->next_pc, -1); | |
475 | return true; | |
476 | } | |
477 | return false; | |
478 | } | |
479 | ||
480 | static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) | |
481 | { | |
482 | if (!gen_check_loop_end(dc, slot)) { | |
483 | gen_jumpi(dc, dc->next_pc, slot); | |
484 | } | |
485 | } | |
486 | ||
bd57fb91 MF |
487 | static void gen_brcond(DisasContext *dc, TCGCond cond, |
488 | TCGv_i32 t0, TCGv_i32 t1, uint32_t offset) | |
489 | { | |
42a268c2 | 490 | TCGLabel *label = gen_new_label(); |
bd57fb91 | 491 | |
d865f307 | 492 | gen_advance_ccount(dc); |
bd57fb91 | 493 | tcg_gen_brcond_i32(cond, t0, t1, label); |
797d780b | 494 | gen_jumpi_check_loop_end(dc, 0); |
bd57fb91 MF |
495 | gen_set_label(label); |
496 | gen_jumpi(dc, dc->pc + offset, 1); | |
497 | } | |
498 | ||
499 | static void gen_brcondi(DisasContext *dc, TCGCond cond, | |
500 | TCGv_i32 t0, uint32_t t1, uint32_t offset) | |
501 | { | |
502 | TCGv_i32 tmp = tcg_const_i32(t1); | |
503 | gen_brcond(dc, cond, t0, tmp, offset); | |
504 | tcg_temp_free(tmp); | |
505 | } | |
506 | ||
0857a06e | 507 | static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) |
fe0bd475 MF |
508 | { |
509 | if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { | |
510 | if (sregnames[sr].name) { | |
c30f0d18 | 511 | qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name); |
fe0bd475 | 512 | } else { |
c30f0d18 | 513 | qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr); |
fe0bd475 MF |
514 | } |
515 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); | |
0857a06e | 516 | return false; |
53593e90 MF |
517 | } else if (!(sregnames[sr].access & access)) { |
518 | static const char * const access_text[] = { | |
519 | [SR_R] = "rsr", | |
520 | [SR_W] = "wsr", | |
521 | [SR_X] = "xsr", | |
522 | }; | |
523 | assert(access < ARRAY_SIZE(access_text) && access_text[access]); | |
c30f0d18 PB |
524 | qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name, |
525 | access_text[access]); | |
53593e90 | 526 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
0857a06e | 527 | return false; |
fe0bd475 | 528 | } |
0857a06e | 529 | return true; |
fe0bd475 MF |
530 | } |
531 | ||
b994e91b MF |
532 | static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
533 | { | |
534 | gen_advance_ccount(dc); | |
535 | tcg_gen_mov_i32(d, cpu_SR[sr]); | |
536 | } | |
537 | ||
b67ea0cd MF |
538 | static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
539 | { | |
540 | tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10); | |
541 | tcg_gen_or_i32(d, d, cpu_SR[sr]); | |
542 | tcg_gen_andi_i32(d, d, 0xfffffffc); | |
543 | } | |
544 | ||
b8132eff MF |
545 | static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
546 | { | |
547 | static void (* const rsr_handler[256])(DisasContext *dc, | |
548 | TCGv_i32 d, uint32_t sr) = { | |
b994e91b | 549 | [CCOUNT] = gen_rsr_ccount, |
b67ea0cd | 550 | [PTEVADDR] = gen_rsr_ptevaddr, |
b8132eff MF |
551 | }; |
552 | ||
fe0bd475 MF |
553 | if (rsr_handler[sr]) { |
554 | rsr_handler[sr](dc, d, sr); | |
b8132eff | 555 | } else { |
fe0bd475 | 556 | tcg_gen_mov_i32(d, cpu_SR[sr]); |
b8132eff MF |
557 | } |
558 | } | |
559 | ||
797d780b MF |
560 | static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
561 | { | |
f492b82d | 562 | gen_helper_wsr_lbeg(cpu_env, s); |
3d0be8a5 | 563 | gen_jumpi_check_loop_end(dc, 0); |
797d780b MF |
564 | } |
565 | ||
566 | static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s) | |
567 | { | |
f492b82d | 568 | gen_helper_wsr_lend(cpu_env, s); |
3d0be8a5 | 569 | gen_jumpi_check_loop_end(dc, 0); |
797d780b MF |
570 | } |
571 | ||
3580ecad MF |
572 | static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
573 | { | |
574 | tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f); | |
575 | if (dc->sar_m32_5bit) { | |
576 | tcg_gen_discard_i32(dc->sar_m32); | |
577 | } | |
578 | dc->sar_5bit = false; | |
579 | dc->sar_m32_5bit = false; | |
580 | } | |
581 | ||
4dd85b6b MF |
582 | static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
583 | { | |
584 | tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff); | |
585 | } | |
586 | ||
6ad6dbf7 MF |
587 | static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
588 | { | |
589 | tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001); | |
590 | /* This can change tb->flags, so exit tb */ | |
591 | gen_jumpi_check_loop_end(dc, -1); | |
592 | } | |
593 | ||
6825b6c3 MF |
594 | static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
595 | { | |
596 | tcg_gen_ext8s_i32(cpu_SR[sr], s); | |
597 | } | |
598 | ||
553e44f9 MF |
599 | static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
600 | { | |
f492b82d | 601 | gen_helper_wsr_windowbase(cpu_env, v); |
2db59a76 MF |
602 | /* This can change tb->flags, so exit tb */ |
603 | gen_jumpi_check_loop_end(dc, -1); | |
772177c1 MF |
604 | } |
605 | ||
606 | static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
607 | { | |
53a72dfd | 608 | tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); |
2db59a76 MF |
609 | /* This can change tb->flags, so exit tb */ |
610 | gen_jumpi_check_loop_end(dc, -1); | |
553e44f9 MF |
611 | } |
612 | ||
b67ea0cd MF |
613 | static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
614 | { | |
615 | tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000); | |
616 | } | |
617 | ||
618 | static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
619 | { | |
f492b82d | 620 | gen_helper_wsr_rasid(cpu_env, v); |
b67ea0cd MF |
621 | /* This can change tb->flags, so exit tb */ |
622 | gen_jumpi_check_loop_end(dc, -1); | |
623 | } | |
624 | ||
625 | static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
626 | { | |
627 | tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000); | |
628 | } | |
629 | ||
e61dc8f7 MF |
630 | static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
631 | { | |
f492b82d | 632 | gen_helper_wsr_ibreakenable(cpu_env, v); |
e61dc8f7 MF |
633 | gen_jumpi_check_loop_end(dc, 0); |
634 | } | |
635 | ||
fcc803d1 MF |
636 | static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
637 | { | |
638 | tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f); | |
639 | } | |
640 | ||
e61dc8f7 MF |
641 | static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
642 | { | |
643 | unsigned id = sr - IBREAKA; | |
644 | ||
645 | if (id < dc->config->nibreak) { | |
646 | TCGv_i32 tmp = tcg_const_i32(id); | |
f492b82d | 647 | gen_helper_wsr_ibreaka(cpu_env, tmp, v); |
e61dc8f7 MF |
648 | tcg_temp_free(tmp); |
649 | gen_jumpi_check_loop_end(dc, 0); | |
650 | } | |
651 | } | |
652 | ||
f14c4b5f MF |
653 | static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
654 | { | |
655 | unsigned id = sr - DBREAKA; | |
656 | ||
657 | if (id < dc->config->ndbreak) { | |
658 | TCGv_i32 tmp = tcg_const_i32(id); | |
f492b82d | 659 | gen_helper_wsr_dbreaka(cpu_env, tmp, v); |
f14c4b5f MF |
660 | tcg_temp_free(tmp); |
661 | } | |
662 | } | |
663 | ||
664 | static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
665 | { | |
666 | unsigned id = sr - DBREAKC; | |
667 | ||
668 | if (id < dc->config->ndbreak) { | |
669 | TCGv_i32 tmp = tcg_const_i32(id); | |
f492b82d | 670 | gen_helper_wsr_dbreakc(cpu_env, tmp, v); |
f14c4b5f MF |
671 | tcg_temp_free(tmp); |
672 | } | |
673 | } | |
674 | ||
ef04a846 MF |
675 | static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
676 | { | |
677 | tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); | |
678 | /* This can change tb->flags, so exit tb */ | |
679 | gen_jumpi_check_loop_end(dc, -1); | |
680 | } | |
681 | ||
b994e91b MF |
682 | static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
683 | { | |
684 | tcg_gen_andi_i32(cpu_SR[sr], v, | |
685 | dc->config->inttype_mask[INTTYPE_SOFTWARE]); | |
686 | gen_helper_check_interrupts(cpu_env); | |
687 | gen_jumpi_check_loop_end(dc, 0); | |
688 | } | |
689 | ||
690 | static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
691 | { | |
692 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
693 | ||
694 | tcg_gen_andi_i32(tmp, v, | |
695 | dc->config->inttype_mask[INTTYPE_EDGE] | | |
696 | dc->config->inttype_mask[INTTYPE_NMI] | | |
697 | dc->config->inttype_mask[INTTYPE_SOFTWARE]); | |
698 | tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp); | |
699 | tcg_temp_free(tmp); | |
700 | gen_helper_check_interrupts(cpu_env); | |
701 | } | |
702 | ||
703 | static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
704 | { | |
705 | tcg_gen_mov_i32(cpu_SR[sr], v); | |
706 | gen_helper_check_interrupts(cpu_env); | |
707 | gen_jumpi_check_loop_end(dc, 0); | |
708 | } | |
709 | ||
f0a548b9 MF |
710 | static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
711 | { | |
712 | uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | | |
713 | PS_UM | PS_EXCM | PS_INTLEVEL; | |
714 | ||
715 | if (option_enabled(dc, XTENSA_OPTION_MMU)) { | |
716 | mask |= PS_RING; | |
717 | } | |
718 | tcg_gen_andi_i32(cpu_SR[sr], v, mask); | |
b994e91b MF |
719 | gen_helper_check_interrupts(cpu_env); |
720 | /* This can change mmu index and tb->flags, so exit tb */ | |
797d780b | 721 | gen_jumpi_check_loop_end(dc, -1); |
f0a548b9 MF |
722 | } |
723 | ||
35b5c044 MF |
724 | static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
725 | { | |
726 | if (dc->icount) { | |
727 | tcg_gen_mov_i32(dc->next_icount, v); | |
728 | } else { | |
729 | tcg_gen_mov_i32(cpu_SR[sr], v); | |
730 | } | |
731 | } | |
732 | ||
733 | static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
734 | { | |
735 | tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); | |
736 | /* This can change tb->flags, so exit tb */ | |
737 | gen_jumpi_check_loop_end(dc, -1); | |
738 | } | |
739 | ||
b994e91b MF |
740 | static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
741 | { | |
742 | uint32_t id = sr - CCOMPARE; | |
743 | if (id < dc->config->nccompare) { | |
744 | uint32_t int_bit = 1 << dc->config->timerint[id]; | |
745 | gen_advance_ccount(dc); | |
746 | tcg_gen_mov_i32(cpu_SR[sr], v); | |
747 | tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); | |
748 | gen_helper_check_interrupts(cpu_env); | |
749 | } | |
750 | } | |
751 | ||
b8132eff MF |
752 | static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
753 | { | |
754 | static void (* const wsr_handler[256])(DisasContext *dc, | |
755 | uint32_t sr, TCGv_i32 v) = { | |
797d780b MF |
756 | [LBEG] = gen_wsr_lbeg, |
757 | [LEND] = gen_wsr_lend, | |
3580ecad | 758 | [SAR] = gen_wsr_sar, |
4dd85b6b | 759 | [BR] = gen_wsr_br, |
6ad6dbf7 | 760 | [LITBASE] = gen_wsr_litbase, |
6825b6c3 | 761 | [ACCHI] = gen_wsr_acchi, |
553e44f9 | 762 | [WINDOW_BASE] = gen_wsr_windowbase, |
772177c1 | 763 | [WINDOW_START] = gen_wsr_windowstart, |
b67ea0cd MF |
764 | [PTEVADDR] = gen_wsr_ptevaddr, |
765 | [RASID] = gen_wsr_rasid, | |
766 | [ITLBCFG] = gen_wsr_tlbcfg, | |
767 | [DTLBCFG] = gen_wsr_tlbcfg, | |
e61dc8f7 | 768 | [IBREAKENABLE] = gen_wsr_ibreakenable, |
fcc803d1 | 769 | [ATOMCTL] = gen_wsr_atomctl, |
e61dc8f7 MF |
770 | [IBREAKA] = gen_wsr_ibreaka, |
771 | [IBREAKA + 1] = gen_wsr_ibreaka, | |
f14c4b5f MF |
772 | [DBREAKA] = gen_wsr_dbreaka, |
773 | [DBREAKA + 1] = gen_wsr_dbreaka, | |
774 | [DBREAKC] = gen_wsr_dbreakc, | |
775 | [DBREAKC + 1] = gen_wsr_dbreakc, | |
ef04a846 | 776 | [CPENABLE] = gen_wsr_cpenable, |
b994e91b MF |
777 | [INTSET] = gen_wsr_intset, |
778 | [INTCLEAR] = gen_wsr_intclear, | |
779 | [INTENABLE] = gen_wsr_intenable, | |
f0a548b9 | 780 | [PS] = gen_wsr_ps, |
35b5c044 MF |
781 | [ICOUNT] = gen_wsr_icount, |
782 | [ICOUNTLEVEL] = gen_wsr_icountlevel, | |
b994e91b MF |
783 | [CCOMPARE] = gen_wsr_ccompare, |
784 | [CCOMPARE + 1] = gen_wsr_ccompare, | |
785 | [CCOMPARE + 2] = gen_wsr_ccompare, | |
b8132eff MF |
786 | }; |
787 | ||
fe0bd475 MF |
788 | if (wsr_handler[sr]) { |
789 | wsr_handler[sr](dc, sr, s); | |
b8132eff | 790 | } else { |
fe0bd475 | 791 | tcg_gen_mov_i32(cpu_SR[sr], s); |
b8132eff MF |
792 | } |
793 | } | |
794 | ||
dd519cbe MF |
795 | static void gen_wur(uint32_t ur, TCGv_i32 s) |
796 | { | |
797 | switch (ur) { | |
798 | case FCR: | |
799 | gen_helper_wur_fcr(cpu_env, s); | |
800 | break; | |
801 | ||
802 | case FSR: | |
803 | tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80); | |
804 | break; | |
805 | ||
806 | default: | |
807 | tcg_gen_mov_i32(cpu_UR[ur], s); | |
808 | break; | |
809 | } | |
810 | } | |
811 | ||
5b4e481b MF |
812 | static void gen_load_store_alignment(DisasContext *dc, int shift, |
813 | TCGv_i32 addr, bool no_hw_alignment) | |
814 | { | |
815 | if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { | |
816 | tcg_gen_andi_i32(addr, addr, ~0 << shift); | |
817 | } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) && | |
818 | no_hw_alignment) { | |
42a268c2 | 819 | TCGLabel *label = gen_new_label(); |
5b4e481b MF |
820 | TCGv_i32 tmp = tcg_temp_new_i32(); |
821 | tcg_gen_andi_i32(tmp, addr, ~(~0 << shift)); | |
822 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); | |
823 | gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr); | |
824 | gen_set_label(label); | |
825 | tcg_temp_free(tmp); | |
826 | } | |
827 | } | |
828 | ||
b994e91b MF |
829 | static void gen_waiti(DisasContext *dc, uint32_t imm4) |
830 | { | |
831 | TCGv_i32 pc = tcg_const_i32(dc->next_pc); | |
832 | TCGv_i32 intlevel = tcg_const_i32(imm4); | |
833 | gen_advance_ccount(dc); | |
f492b82d | 834 | gen_helper_waiti(cpu_env, pc, intlevel); |
b994e91b MF |
835 | tcg_temp_free(pc); |
836 | tcg_temp_free(intlevel); | |
837 | } | |
838 | ||
97e89ee9 | 839 | static bool gen_window_check1(DisasContext *dc, unsigned r1) |
772177c1 | 840 | { |
2db59a76 MF |
841 | if (r1 / 4 > dc->window) { |
842 | TCGv_i32 pc = tcg_const_i32(dc->pc); | |
843 | TCGv_i32 w = tcg_const_i32(r1 / 4); | |
908c67fc | 844 | |
2db59a76 MF |
845 | gen_advance_ccount(dc); |
846 | gen_helper_window_check(cpu_env, pc, w); | |
847 | dc->is_jmp = DISAS_UPDATE; | |
97e89ee9 | 848 | return false; |
772177c1 | 849 | } |
97e89ee9 | 850 | return true; |
772177c1 MF |
851 | } |
852 | ||
97e89ee9 | 853 | static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2) |
772177c1 | 854 | { |
97e89ee9 | 855 | return gen_window_check1(dc, r1 > r2 ? r1 : r2); |
772177c1 MF |
856 | } |
857 | ||
97e89ee9 | 858 | static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2, |
772177c1 MF |
859 | unsigned r3) |
860 | { | |
97e89ee9 | 861 | return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3); |
772177c1 MF |
862 | } |
863 | ||
6825b6c3 MF |
864 | static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) |
865 | { | |
866 | TCGv_i32 m = tcg_temp_new_i32(); | |
867 | ||
868 | if (hi) { | |
869 | (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16); | |
870 | } else { | |
871 | (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v); | |
872 | } | |
873 | return m; | |
874 | } | |
875 | ||
01673a34 MF |
876 | static inline unsigned xtensa_op0_insn_len(unsigned op0) |
877 | { | |
878 | return op0 >= 8 ? 2 : 3; | |
879 | } | |
880 | ||
0c4fabea | 881 | static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) |
dedc5eae | 882 | { |
b67ea0cd MF |
883 | #define HAS_OPTION_BITS(opt) do { \ |
884 | if (!option_bits_enabled(dc, opt)) { \ | |
c30f0d18 PB |
885 | qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \ |
886 | __FILE__, __LINE__); \ | |
dedc5eae MF |
887 | goto invalid_opcode; \ |
888 | } \ | |
889 | } while (0) | |
890 | ||
b67ea0cd MF |
891 | #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt)) |
892 | ||
c30f0d18 | 893 | #define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__) |
91a5bb76 | 894 | #define RESERVED() do { \ |
c30f0d18 PB |
895 | qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \ |
896 | dc->pc, b0, b1, b2, __FILE__, __LINE__); \ | |
91a5bb76 MF |
897 | goto invalid_opcode; \ |
898 | } while (0) | |
899 | ||
900 | ||
dedc5eae MF |
901 | #ifdef TARGET_WORDS_BIGENDIAN |
902 | #define OP0 (((b0) & 0xf0) >> 4) | |
903 | #define OP1 (((b2) & 0xf0) >> 4) | |
904 | #define OP2 ((b2) & 0xf) | |
905 | #define RRR_R ((b1) & 0xf) | |
906 | #define RRR_S (((b1) & 0xf0) >> 4) | |
907 | #define RRR_T ((b0) & 0xf) | |
908 | #else | |
909 | #define OP0 (((b0) & 0xf)) | |
910 | #define OP1 (((b2) & 0xf)) | |
911 | #define OP2 (((b2) & 0xf0) >> 4) | |
912 | #define RRR_R (((b1) & 0xf0) >> 4) | |
913 | #define RRR_S (((b1) & 0xf)) | |
914 | #define RRR_T (((b0) & 0xf0) >> 4) | |
915 | #endif | |
6825b6c3 MF |
916 | #define RRR_X ((RRR_R & 0x4) >> 2) |
917 | #define RRR_Y ((RRR_T & 0x4) >> 2) | |
918 | #define RRR_W (RRR_R & 0x3) | |
dedc5eae MF |
919 | |
920 | #define RRRN_R RRR_R | |
921 | #define RRRN_S RRR_S | |
922 | #define RRRN_T RRR_T | |
923 | ||
65026682 MF |
924 | #define RRI4_R RRR_R |
925 | #define RRI4_S RRR_S | |
926 | #define RRI4_T RRR_T | |
927 | #ifdef TARGET_WORDS_BIGENDIAN | |
928 | #define RRI4_IMM4 ((b2) & 0xf) | |
929 | #else | |
930 | #define RRI4_IMM4 (((b2) & 0xf0) >> 4) | |
931 | #endif | |
932 | ||
dedc5eae MF |
933 | #define RRI8_R RRR_R |
934 | #define RRI8_S RRR_S | |
935 | #define RRI8_T RRR_T | |
936 | #define RRI8_IMM8 (b2) | |
937 | #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8) | |
938 | ||
939 | #ifdef TARGET_WORDS_BIGENDIAN | |
940 | #define RI16_IMM16 (((b1) << 8) | (b2)) | |
941 | #else | |
942 | #define RI16_IMM16 (((b2) << 8) | (b1)) | |
943 | #endif | |
944 | ||
945 | #ifdef TARGET_WORDS_BIGENDIAN | |
946 | #define CALL_N (((b0) & 0xc) >> 2) | |
947 | #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2)) | |
948 | #else | |
949 | #define CALL_N (((b0) & 0x30) >> 4) | |
950 | #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10)) | |
951 | #endif | |
952 | #define CALL_OFFSET_SE \ | |
953 | (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET) | |
954 | ||
955 | #define CALLX_N CALL_N | |
956 | #ifdef TARGET_WORDS_BIGENDIAN | |
957 | #define CALLX_M ((b0) & 0x3) | |
958 | #else | |
959 | #define CALLX_M (((b0) & 0xc0) >> 6) | |
960 | #endif | |
961 | #define CALLX_S RRR_S | |
962 | ||
963 | #define BRI12_M CALLX_M | |
964 | #define BRI12_S RRR_S | |
965 | #ifdef TARGET_WORDS_BIGENDIAN | |
966 | #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2)) | |
967 | #else | |
968 | #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4)) | |
969 | #endif | |
970 | #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12) | |
971 | ||
972 | #define BRI8_M BRI12_M | |
973 | #define BRI8_R RRI8_R | |
974 | #define BRI8_S RRI8_S | |
975 | #define BRI8_IMM8 RRI8_IMM8 | |
976 | #define BRI8_IMM8_SE RRI8_IMM8_SE | |
977 | ||
978 | #define RSR_SR (b1) | |
979 | ||
0c4fabea BS |
980 | uint8_t b0 = cpu_ldub_code(env, dc->pc); |
981 | uint8_t b1 = cpu_ldub_code(env, dc->pc + 1); | |
a044ec2a | 982 | uint8_t b2 = 0; |
01673a34 | 983 | unsigned len = xtensa_op0_insn_len(OP0); |
dedc5eae | 984 | |
bd57fb91 MF |
985 | static const uint32_t B4CONST[] = { |
986 | 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 | |
987 | }; | |
988 | ||
989 | static const uint32_t B4CONSTU[] = { | |
990 | 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 | |
991 | }; | |
992 | ||
01673a34 MF |
993 | switch (len) { |
994 | case 2: | |
dedc5eae | 995 | HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); |
01673a34 MF |
996 | break; |
997 | ||
998 | case 3: | |
0c4fabea | 999 | b2 = cpu_ldub_code(env, dc->pc + 2); |
01673a34 MF |
1000 | break; |
1001 | ||
1002 | default: | |
1003 | RESERVED(); | |
dedc5eae | 1004 | } |
01673a34 | 1005 | dc->next_pc = dc->pc + len; |
dedc5eae MF |
1006 | |
1007 | switch (OP0) { | |
1008 | case 0: /*QRST*/ | |
1009 | switch (OP1) { | |
1010 | case 0: /*RST0*/ | |
1011 | switch (OP2) { | |
1012 | case 0: /*ST0*/ | |
1013 | if ((RRR_R & 0xc) == 0x8) { | |
1014 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
1015 | } | |
1016 | ||
1017 | switch (RRR_R) { | |
1018 | case 0: /*SNM0*/ | |
5da4a6a8 MF |
1019 | switch (CALLX_M) { |
1020 | case 0: /*ILL*/ | |
40643d7c | 1021 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
5da4a6a8 MF |
1022 | break; |
1023 | ||
1024 | case 1: /*reserved*/ | |
91a5bb76 | 1025 | RESERVED(); |
5da4a6a8 MF |
1026 | break; |
1027 | ||
1028 | case 2: /*JR*/ | |
1029 | switch (CALLX_N) { | |
1030 | case 0: /*RET*/ | |
1031 | case 2: /*JX*/ | |
97e89ee9 MF |
1032 | if (gen_window_check1(dc, CALLX_S)) { |
1033 | gen_jump(dc, cpu_R[CALLX_S]); | |
1034 | } | |
5da4a6a8 MF |
1035 | break; |
1036 | ||
1037 | case 1: /*RETWw*/ | |
1038 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
1039 | { |
1040 | TCGv_i32 tmp = tcg_const_i32(dc->pc); | |
b994e91b | 1041 | gen_advance_ccount(dc); |
f492b82d | 1042 | gen_helper_retw(tmp, cpu_env, tmp); |
553e44f9 MF |
1043 | gen_jump(dc, tmp); |
1044 | tcg_temp_free(tmp); | |
1045 | } | |
5da4a6a8 MF |
1046 | break; |
1047 | ||
1048 | case 3: /*reserved*/ | |
91a5bb76 | 1049 | RESERVED(); |
5da4a6a8 MF |
1050 | break; |
1051 | } | |
1052 | break; | |
1053 | ||
1054 | case 3: /*CALLX*/ | |
97e89ee9 MF |
1055 | if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) { |
1056 | break; | |
1057 | } | |
5da4a6a8 MF |
1058 | switch (CALLX_N) { |
1059 | case 0: /*CALLX0*/ | |
1060 | { | |
1061 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1062 | tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); | |
1063 | tcg_gen_movi_i32(cpu_R[0], dc->next_pc); | |
1064 | gen_jump(dc, tmp); | |
1065 | tcg_temp_free(tmp); | |
1066 | } | |
1067 | break; | |
1068 | ||
1069 | case 1: /*CALLX4w*/ | |
1070 | case 2: /*CALLX8w*/ | |
1071 | case 3: /*CALLX12w*/ | |
1072 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
1073 | { |
1074 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1075 | ||
1076 | tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); | |
1077 | gen_callw(dc, CALLX_N, tmp); | |
1078 | tcg_temp_free(tmp); | |
1079 | } | |
5da4a6a8 MF |
1080 | break; |
1081 | } | |
1082 | break; | |
1083 | } | |
dedc5eae MF |
1084 | break; |
1085 | ||
1086 | case 1: /*MOVSPw*/ | |
1087 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
97e89ee9 | 1088 | if (gen_window_check2(dc, RRR_T, RRR_S)) { |
553e44f9 | 1089 | TCGv_i32 pc = tcg_const_i32(dc->pc); |
b994e91b | 1090 | gen_advance_ccount(dc); |
f492b82d | 1091 | gen_helper_movsp(cpu_env, pc); |
553e44f9 MF |
1092 | tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]); |
1093 | tcg_temp_free(pc); | |
1094 | } | |
dedc5eae MF |
1095 | break; |
1096 | ||
1097 | case 2: /*SYNC*/ | |
28067b22 MF |
1098 | switch (RRR_T) { |
1099 | case 0: /*ISYNC*/ | |
1100 | break; | |
1101 | ||
1102 | case 1: /*RSYNC*/ | |
1103 | break; | |
1104 | ||
1105 | case 2: /*ESYNC*/ | |
1106 | break; | |
1107 | ||
1108 | case 3: /*DSYNC*/ | |
1109 | break; | |
1110 | ||
1111 | case 8: /*EXCW*/ | |
1112 | HAS_OPTION(XTENSA_OPTION_EXCEPTION); | |
1113 | break; | |
1114 | ||
1115 | case 12: /*MEMW*/ | |
1116 | break; | |
1117 | ||
1118 | case 13: /*EXTW*/ | |
1119 | break; | |
1120 | ||
1121 | case 15: /*NOP*/ | |
1122 | break; | |
1123 | ||
1124 | default: /*reserved*/ | |
1125 | RESERVED(); | |
1126 | break; | |
1127 | } | |
91a5bb76 MF |
1128 | break; |
1129 | ||
1130 | case 3: /*RFEIx*/ | |
40643d7c MF |
1131 | switch (RRR_T) { |
1132 | case 0: /*RFETx*/ | |
1133 | HAS_OPTION(XTENSA_OPTION_EXCEPTION); | |
1134 | switch (RRR_S) { | |
1135 | case 0: /*RFEx*/ | |
97e89ee9 MF |
1136 | if (gen_check_privilege(dc)) { |
1137 | tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); | |
1138 | gen_helper_check_interrupts(cpu_env); | |
1139 | gen_jump(dc, cpu_SR[EPC1]); | |
1140 | } | |
40643d7c MF |
1141 | break; |
1142 | ||
1143 | case 1: /*RFUEx*/ | |
1144 | RESERVED(); | |
1145 | break; | |
1146 | ||
1147 | case 2: /*RFDEx*/ | |
97e89ee9 MF |
1148 | if (gen_check_privilege(dc)) { |
1149 | gen_jump(dc, cpu_SR[ | |
1150 | dc->config->ndepc ? DEPC : EPC1]); | |
1151 | } | |
40643d7c MF |
1152 | break; |
1153 | ||
1154 | case 4: /*RFWOw*/ | |
1155 | case 5: /*RFWUw*/ | |
1156 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
97e89ee9 | 1157 | if (gen_check_privilege(dc)) { |
553e44f9 MF |
1158 | TCGv_i32 tmp = tcg_const_i32(1); |
1159 | ||
1160 | tcg_gen_andi_i32( | |
1161 | cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); | |
1162 | tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); | |
1163 | ||
1164 | if (RRR_S == 4) { | |
1165 | tcg_gen_andc_i32(cpu_SR[WINDOW_START], | |
1166 | cpu_SR[WINDOW_START], tmp); | |
1167 | } else { | |
1168 | tcg_gen_or_i32(cpu_SR[WINDOW_START], | |
1169 | cpu_SR[WINDOW_START], tmp); | |
1170 | } | |
1171 | ||
f492b82d | 1172 | gen_helper_restore_owb(cpu_env); |
b994e91b | 1173 | gen_helper_check_interrupts(cpu_env); |
553e44f9 MF |
1174 | gen_jump(dc, cpu_SR[EPC1]); |
1175 | ||
1176 | tcg_temp_free(tmp); | |
1177 | } | |
40643d7c MF |
1178 | break; |
1179 | ||
1180 | default: /*reserved*/ | |
1181 | RESERVED(); | |
1182 | break; | |
1183 | } | |
1184 | break; | |
1185 | ||
1186 | case 1: /*RFIx*/ | |
1187 | HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT); | |
b994e91b | 1188 | if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) { |
97e89ee9 MF |
1189 | if (gen_check_privilege(dc)) { |
1190 | tcg_gen_mov_i32(cpu_SR[PS], | |
1191 | cpu_SR[EPS2 + RRR_S - 2]); | |
1192 | gen_helper_check_interrupts(cpu_env); | |
1193 | gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]); | |
1194 | } | |
b994e91b | 1195 | } else { |
c30f0d18 | 1196 | qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S); |
b994e91b MF |
1197 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
1198 | } | |
40643d7c MF |
1199 | break; |
1200 | ||
1201 | case 2: /*RFME*/ | |
1202 | TBD(); | |
1203 | break; | |
1204 | ||
1205 | default: /*reserved*/ | |
1206 | RESERVED(); | |
1207 | break; | |
1208 | ||
1209 | } | |
91a5bb76 MF |
1210 | break; |
1211 | ||
1212 | case 4: /*BREAKx*/ | |
e61dc8f7 MF |
1213 | HAS_OPTION(XTENSA_OPTION_DEBUG); |
1214 | if (dc->debug) { | |
1215 | gen_debug_exception(dc, DEBUGCAUSE_BI); | |
1216 | } | |
91a5bb76 MF |
1217 | break; |
1218 | ||
1219 | case 5: /*SYSCALLx*/ | |
1220 | HAS_OPTION(XTENSA_OPTION_EXCEPTION); | |
40643d7c MF |
1221 | switch (RRR_S) { |
1222 | case 0: /*SYSCALLx*/ | |
1223 | gen_exception_cause(dc, SYSCALL_CAUSE); | |
1224 | break; | |
1225 | ||
1226 | case 1: /*SIMCALL*/ | |
cfe67cef | 1227 | if (semihosting_enabled()) { |
97e89ee9 MF |
1228 | if (gen_check_privilege(dc)) { |
1229 | gen_helper_simcall(cpu_env); | |
1230 | } | |
1ddeaa5d | 1231 | } else { |
c30f0d18 | 1232 | qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); |
1ddeaa5d MF |
1233 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
1234 | } | |
40643d7c MF |
1235 | break; |
1236 | ||
1237 | default: | |
1238 | RESERVED(); | |
1239 | break; | |
1240 | } | |
91a5bb76 MF |
1241 | break; |
1242 | ||
1243 | case 6: /*RSILx*/ | |
1244 | HAS_OPTION(XTENSA_OPTION_INTERRUPT); | |
97e89ee9 MF |
1245 | if (gen_check_privilege(dc) && |
1246 | gen_window_check1(dc, RRR_T)) { | |
1247 | tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]); | |
1248 | tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); | |
1249 | tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S); | |
1250 | gen_helper_check_interrupts(cpu_env); | |
1251 | gen_jumpi_check_loop_end(dc, 0); | |
1252 | } | |
91a5bb76 MF |
1253 | break; |
1254 | ||
1255 | case 7: /*WAITIx*/ | |
1256 | HAS_OPTION(XTENSA_OPTION_INTERRUPT); | |
97e89ee9 MF |
1257 | if (gen_check_privilege(dc)) { |
1258 | gen_waiti(dc, RRR_S); | |
1259 | } | |
91a5bb76 MF |
1260 | break; |
1261 | ||
1262 | case 8: /*ANY4p*/ | |
91a5bb76 | 1263 | case 9: /*ALL4p*/ |
91a5bb76 | 1264 | case 10: /*ANY8p*/ |
91a5bb76 MF |
1265 | case 11: /*ALL8p*/ |
1266 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
4dd85b6b MF |
1267 | { |
1268 | const unsigned shift = (RRR_R & 2) ? 8 : 4; | |
1269 | TCGv_i32 mask = tcg_const_i32( | |
1270 | ((1 << shift) - 1) << RRR_S); | |
1271 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1272 | ||
1273 | tcg_gen_and_i32(tmp, cpu_SR[BR], mask); | |
1274 | if (RRR_R & 1) { /*ALL*/ | |
1275 | tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S); | |
1276 | } else { /*ANY*/ | |
1277 | tcg_gen_add_i32(tmp, tmp, mask); | |
1278 | } | |
1279 | tcg_gen_shri_i32(tmp, tmp, RRR_S + shift); | |
1280 | tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], | |
1281 | tmp, RRR_T, 1); | |
1282 | tcg_temp_free(mask); | |
1283 | tcg_temp_free(tmp); | |
1284 | } | |
91a5bb76 MF |
1285 | break; |
1286 | ||
1287 | default: /*reserved*/ | |
1288 | RESERVED(); | |
dedc5eae MF |
1289 | break; |
1290 | ||
1291 | } | |
1292 | break; | |
1293 | ||
1294 | case 1: /*AND*/ | |
97e89ee9 MF |
1295 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1296 | tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1297 | } | |
dedc5eae MF |
1298 | break; |
1299 | ||
1300 | case 2: /*OR*/ | |
97e89ee9 MF |
1301 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1302 | tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1303 | } | |
dedc5eae MF |
1304 | break; |
1305 | ||
1306 | case 3: /*XOR*/ | |
97e89ee9 MF |
1307 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1308 | tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1309 | } | |
dedc5eae MF |
1310 | break; |
1311 | ||
1312 | case 4: /*ST1*/ | |
3580ecad MF |
1313 | switch (RRR_R) { |
1314 | case 0: /*SSR*/ | |
97e89ee9 MF |
1315 | if (gen_window_check1(dc, RRR_S)) { |
1316 | gen_right_shift_sar(dc, cpu_R[RRR_S]); | |
1317 | } | |
3580ecad MF |
1318 | break; |
1319 | ||
1320 | case 1: /*SSL*/ | |
97e89ee9 MF |
1321 | if (gen_window_check1(dc, RRR_S)) { |
1322 | gen_left_shift_sar(dc, cpu_R[RRR_S]); | |
1323 | } | |
3580ecad MF |
1324 | break; |
1325 | ||
1326 | case 2: /*SSA8L*/ | |
97e89ee9 | 1327 | if (gen_window_check1(dc, RRR_S)) { |
3580ecad MF |
1328 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1329 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); | |
1330 | gen_right_shift_sar(dc, tmp); | |
1331 | tcg_temp_free(tmp); | |
1332 | } | |
1333 | break; | |
1334 | ||
1335 | case 3: /*SSA8B*/ | |
97e89ee9 | 1336 | if (gen_window_check1(dc, RRR_S)) { |
3580ecad MF |
1337 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1338 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); | |
1339 | gen_left_shift_sar(dc, tmp); | |
1340 | tcg_temp_free(tmp); | |
1341 | } | |
1342 | break; | |
1343 | ||
1344 | case 4: /*SSAI*/ | |
1345 | { | |
1346 | TCGv_i32 tmp = tcg_const_i32( | |
1347 | RRR_S | ((RRR_T & 1) << 4)); | |
1348 | gen_right_shift_sar(dc, tmp); | |
1349 | tcg_temp_free(tmp); | |
1350 | } | |
1351 | break; | |
1352 | ||
1353 | case 6: /*RER*/ | |
91a5bb76 | 1354 | TBD(); |
3580ecad MF |
1355 | break; |
1356 | ||
1357 | case 7: /*WER*/ | |
91a5bb76 | 1358 | TBD(); |
3580ecad MF |
1359 | break; |
1360 | ||
1361 | case 8: /*ROTWw*/ | |
1362 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
97e89ee9 | 1363 | if (gen_check_privilege(dc)) { |
553e44f9 MF |
1364 | TCGv_i32 tmp = tcg_const_i32( |
1365 | RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0)); | |
f492b82d | 1366 | gen_helper_rotw(cpu_env, tmp); |
553e44f9 | 1367 | tcg_temp_free(tmp); |
2db59a76 MF |
1368 | /* This can change tb->flags, so exit tb */ |
1369 | gen_jumpi_check_loop_end(dc, -1); | |
553e44f9 | 1370 | } |
3580ecad MF |
1371 | break; |
1372 | ||
1373 | case 14: /*NSAu*/ | |
7f65f4b0 | 1374 | HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); |
97e89ee9 MF |
1375 | if (gen_window_check2(dc, RRR_S, RRR_T)) { |
1376 | gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]); | |
1377 | } | |
3580ecad MF |
1378 | break; |
1379 | ||
1380 | case 15: /*NSAUu*/ | |
7f65f4b0 | 1381 | HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); |
97e89ee9 MF |
1382 | if (gen_window_check2(dc, RRR_S, RRR_T)) { |
1383 | gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]); | |
1384 | } | |
3580ecad MF |
1385 | break; |
1386 | ||
1387 | default: /*reserved*/ | |
91a5bb76 | 1388 | RESERVED(); |
3580ecad MF |
1389 | break; |
1390 | } | |
dedc5eae MF |
1391 | break; |
1392 | ||
1393 | case 5: /*TLB*/ | |
b67ea0cd MF |
1394 | HAS_OPTION_BITS( |
1395 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | | |
1396 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | | |
1397 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)); | |
97e89ee9 MF |
1398 | if (gen_check_privilege(dc) && |
1399 | gen_window_check2(dc, RRR_S, RRR_T)) { | |
b67ea0cd MF |
1400 | TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0); |
1401 | ||
1402 | switch (RRR_R & 7) { | |
1403 | case 3: /*RITLB0*/ /*RDTLB0*/ | |
f492b82d MF |
1404 | gen_helper_rtlb0(cpu_R[RRR_T], |
1405 | cpu_env, cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1406 | break; |
1407 | ||
1408 | case 4: /*IITLB*/ /*IDTLB*/ | |
f492b82d | 1409 | gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb); |
b67ea0cd MF |
1410 | /* This could change memory mapping, so exit tb */ |
1411 | gen_jumpi_check_loop_end(dc, -1); | |
1412 | break; | |
1413 | ||
1414 | case 5: /*PITLB*/ /*PDTLB*/ | |
1415 | tcg_gen_movi_i32(cpu_pc, dc->pc); | |
f492b82d MF |
1416 | gen_helper_ptlb(cpu_R[RRR_T], |
1417 | cpu_env, cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1418 | break; |
1419 | ||
1420 | case 6: /*WITLB*/ /*WDTLB*/ | |
f492b82d MF |
1421 | gen_helper_wtlb( |
1422 | cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1423 | /* This could change memory mapping, so exit tb */ |
1424 | gen_jumpi_check_loop_end(dc, -1); | |
1425 | break; | |
1426 | ||
1427 | case 7: /*RITLB1*/ /*RDTLB1*/ | |
f492b82d MF |
1428 | gen_helper_rtlb1(cpu_R[RRR_T], |
1429 | cpu_env, cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1430 | break; |
1431 | ||
1432 | default: | |
1433 | tcg_temp_free(dtlb); | |
1434 | RESERVED(); | |
1435 | break; | |
1436 | } | |
1437 | tcg_temp_free(dtlb); | |
1438 | } | |
dedc5eae MF |
1439 | break; |
1440 | ||
1441 | case 6: /*RT0*/ | |
97e89ee9 MF |
1442 | if (!gen_window_check2(dc, RRR_R, RRR_T)) { |
1443 | break; | |
1444 | } | |
f331fe5e MF |
1445 | switch (RRR_S) { |
1446 | case 0: /*NEG*/ | |
1447 | tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]); | |
1448 | break; | |
1449 | ||
1450 | case 1: /*ABS*/ | |
1451 | { | |
f877d09e MF |
1452 | TCGv_i32 zero = tcg_const_i32(0); |
1453 | TCGv_i32 neg = tcg_temp_new_i32(); | |
1454 | ||
1455 | tcg_gen_neg_i32(neg, cpu_R[RRR_T]); | |
1456 | tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R], | |
1457 | cpu_R[RRR_T], zero, cpu_R[RRR_T], neg); | |
1458 | tcg_temp_free(neg); | |
1459 | tcg_temp_free(zero); | |
f331fe5e MF |
1460 | } |
1461 | break; | |
1462 | ||
1463 | default: /*reserved*/ | |
91a5bb76 | 1464 | RESERVED(); |
f331fe5e MF |
1465 | break; |
1466 | } | |
dedc5eae MF |
1467 | break; |
1468 | ||
1469 | case 7: /*reserved*/ | |
91a5bb76 | 1470 | RESERVED(); |
dedc5eae MF |
1471 | break; |
1472 | ||
1473 | case 8: /*ADD*/ | |
97e89ee9 MF |
1474 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1475 | tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1476 | } | |
dedc5eae MF |
1477 | break; |
1478 | ||
1479 | case 9: /*ADD**/ | |
1480 | case 10: | |
1481 | case 11: | |
97e89ee9 | 1482 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
dedc5eae MF |
1483 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1484 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8); | |
1485 | tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); | |
1486 | tcg_temp_free(tmp); | |
1487 | } | |
1488 | break; | |
1489 | ||
1490 | case 12: /*SUB*/ | |
97e89ee9 MF |
1491 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1492 | tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1493 | } | |
dedc5eae MF |
1494 | break; |
1495 | ||
1496 | case 13: /*SUB**/ | |
1497 | case 14: | |
1498 | case 15: | |
97e89ee9 | 1499 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
dedc5eae MF |
1500 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1501 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12); | |
1502 | tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); | |
1503 | tcg_temp_free(tmp); | |
1504 | } | |
1505 | break; | |
1506 | } | |
1507 | break; | |
1508 | ||
1509 | case 1: /*RST1*/ | |
3580ecad MF |
1510 | switch (OP2) { |
1511 | case 0: /*SLLI*/ | |
1512 | case 1: | |
97e89ee9 MF |
1513 | if (gen_window_check2(dc, RRR_R, RRR_S)) { |
1514 | tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S], | |
1515 | 32 - (RRR_T | ((OP2 & 1) << 4))); | |
1516 | } | |
3580ecad MF |
1517 | break; |
1518 | ||
1519 | case 2: /*SRAI*/ | |
1520 | case 3: | |
97e89ee9 MF |
1521 | if (gen_window_check2(dc, RRR_R, RRR_T)) { |
1522 | tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T], | |
1523 | RRR_S | ((OP2 & 1) << 4)); | |
1524 | } | |
3580ecad MF |
1525 | break; |
1526 | ||
1527 | case 4: /*SRLI*/ | |
97e89ee9 MF |
1528 | if (gen_window_check2(dc, RRR_R, RRR_T)) { |
1529 | tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S); | |
1530 | } | |
3580ecad MF |
1531 | break; |
1532 | ||
1533 | case 6: /*XSR*/ | |
97e89ee9 MF |
1534 | if (gen_check_sr(dc, RSR_SR, SR_X) && |
1535 | (RSR_SR < 64 || gen_check_privilege(dc)) && | |
1536 | gen_window_check1(dc, RRR_T)) { | |
3580ecad | 1537 | TCGv_i32 tmp = tcg_temp_new_i32(); |
0857a06e | 1538 | |
3580ecad MF |
1539 | tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); |
1540 | gen_rsr(dc, cpu_R[RRR_T], RSR_SR); | |
1541 | gen_wsr(dc, RSR_SR, tmp); | |
1542 | tcg_temp_free(tmp); | |
1543 | } | |
1544 | break; | |
1545 | ||
1546 | /* | |
1547 | * Note: 64 bit ops are used here solely because SAR values | |
1548 | * have range 0..63 | |
1549 | */ | |
1550 | #define gen_shift_reg(cmd, reg) do { \ | |
1551 | TCGv_i64 tmp = tcg_temp_new_i64(); \ | |
1552 | tcg_gen_extu_i32_i64(tmp, reg); \ | |
1553 | tcg_gen_##cmd##_i64(v, v, tmp); \ | |
ecc7b3aa | 1554 | tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \ |
3580ecad MF |
1555 | tcg_temp_free_i64(v); \ |
1556 | tcg_temp_free_i64(tmp); \ | |
1557 | } while (0) | |
1558 | ||
1559 | #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) | |
1560 | ||
1561 | case 8: /*SRC*/ | |
97e89ee9 | 1562 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
3580ecad MF |
1563 | TCGv_i64 v = tcg_temp_new_i64(); |
1564 | tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]); | |
1565 | gen_shift(shr); | |
1566 | } | |
1567 | break; | |
1568 | ||
1569 | case 9: /*SRL*/ | |
97e89ee9 MF |
1570 | if (!gen_window_check2(dc, RRR_R, RRR_T)) { |
1571 | break; | |
1572 | } | |
3580ecad MF |
1573 | if (dc->sar_5bit) { |
1574 | tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); | |
1575 | } else { | |
1576 | TCGv_i64 v = tcg_temp_new_i64(); | |
1577 | tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]); | |
1578 | gen_shift(shr); | |
1579 | } | |
1580 | break; | |
1581 | ||
1582 | case 10: /*SLL*/ | |
97e89ee9 MF |
1583 | if (!gen_window_check2(dc, RRR_R, RRR_S)) { |
1584 | break; | |
1585 | } | |
3580ecad MF |
1586 | if (dc->sar_m32_5bit) { |
1587 | tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32); | |
1588 | } else { | |
1589 | TCGv_i64 v = tcg_temp_new_i64(); | |
1590 | TCGv_i32 s = tcg_const_i32(32); | |
1591 | tcg_gen_sub_i32(s, s, cpu_SR[SAR]); | |
1592 | tcg_gen_andi_i32(s, s, 0x3f); | |
1593 | tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]); | |
1594 | gen_shift_reg(shl, s); | |
1595 | tcg_temp_free(s); | |
1596 | } | |
1597 | break; | |
1598 | ||
1599 | case 11: /*SRA*/ | |
97e89ee9 MF |
1600 | if (!gen_window_check2(dc, RRR_R, RRR_T)) { |
1601 | break; | |
1602 | } | |
3580ecad MF |
1603 | if (dc->sar_5bit) { |
1604 | tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); | |
1605 | } else { | |
1606 | TCGv_i64 v = tcg_temp_new_i64(); | |
1607 | tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]); | |
1608 | gen_shift(sar); | |
1609 | } | |
1610 | break; | |
1611 | #undef gen_shift | |
1612 | #undef gen_shift_reg | |
1613 | ||
1614 | case 12: /*MUL16U*/ | |
1615 | HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); | |
97e89ee9 | 1616 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
3580ecad MF |
1617 | TCGv_i32 v1 = tcg_temp_new_i32(); |
1618 | TCGv_i32 v2 = tcg_temp_new_i32(); | |
1619 | tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]); | |
1620 | tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]); | |
1621 | tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); | |
1622 | tcg_temp_free(v2); | |
1623 | tcg_temp_free(v1); | |
1624 | } | |
1625 | break; | |
1626 | ||
1627 | case 13: /*MUL16S*/ | |
1628 | HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); | |
97e89ee9 | 1629 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
3580ecad MF |
1630 | TCGv_i32 v1 = tcg_temp_new_i32(); |
1631 | TCGv_i32 v2 = tcg_temp_new_i32(); | |
1632 | tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]); | |
1633 | tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]); | |
1634 | tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); | |
1635 | tcg_temp_free(v2); | |
1636 | tcg_temp_free(v1); | |
1637 | } | |
1638 | break; | |
1639 | ||
1640 | default: /*reserved*/ | |
91a5bb76 | 1641 | RESERVED(); |
3580ecad MF |
1642 | break; |
1643 | } | |
dedc5eae MF |
1644 | break; |
1645 | ||
1646 | case 2: /*RST2*/ | |
97e89ee9 MF |
1647 | if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
1648 | break; | |
4dd85b6b | 1649 | } |
772177c1 | 1650 | |
f76ebf55 MF |
1651 | if (OP2 >= 12) { |
1652 | HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV); | |
42a268c2 | 1653 | TCGLabel *label = gen_new_label(); |
f76ebf55 MF |
1654 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label); |
1655 | gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); | |
1656 | gen_set_label(label); | |
1657 | } | |
1658 | ||
1659 | switch (OP2) { | |
4dd85b6b MF |
1660 | #define BOOLEAN_LOGIC(fn, r, s, t) \ |
1661 | do { \ | |
1662 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); \ | |
1663 | TCGv_i32 tmp1 = tcg_temp_new_i32(); \ | |
1664 | TCGv_i32 tmp2 = tcg_temp_new_i32(); \ | |
1665 | \ | |
1666 | tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \ | |
1667 | tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \ | |
1668 | tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \ | |
1669 | tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \ | |
1670 | tcg_temp_free(tmp1); \ | |
1671 | tcg_temp_free(tmp2); \ | |
1672 | } while (0) | |
1673 | ||
1674 | case 0: /*ANDBp*/ | |
1675 | BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T); | |
1676 | break; | |
1677 | ||
1678 | case 1: /*ANDBCp*/ | |
1679 | BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T); | |
1680 | break; | |
1681 | ||
1682 | case 2: /*ORBp*/ | |
1683 | BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T); | |
1684 | break; | |
1685 | ||
1686 | case 3: /*ORBCp*/ | |
1687 | BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T); | |
1688 | break; | |
1689 | ||
1690 | case 4: /*XORBp*/ | |
1691 | BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T); | |
1692 | break; | |
1693 | ||
1694 | #undef BOOLEAN_LOGIC | |
1695 | ||
f76ebf55 MF |
1696 | case 8: /*MULLi*/ |
1697 | HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); | |
1698 | tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1699 | break; | |
1700 | ||
1701 | case 10: /*MULUHi*/ | |
1702 | case 11: /*MULSHi*/ | |
7f65f4b0 | 1703 | HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); |
f76ebf55 | 1704 | { |
c9cda20b | 1705 | TCGv lo = tcg_temp_new(); |
f76ebf55 MF |
1706 | |
1707 | if (OP2 == 10) { | |
c9cda20b RH |
1708 | tcg_gen_mulu2_i32(lo, cpu_R[RRR_R], |
1709 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
f76ebf55 | 1710 | } else { |
c9cda20b RH |
1711 | tcg_gen_muls2_i32(lo, cpu_R[RRR_R], |
1712 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
f76ebf55 | 1713 | } |
c9cda20b | 1714 | tcg_temp_free(lo); |
f76ebf55 MF |
1715 | } |
1716 | break; | |
1717 | ||
1718 | case 12: /*QUOUi*/ | |
1719 | tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1720 | break; | |
1721 | ||
1722 | case 13: /*QUOSi*/ | |
1723 | case 15: /*REMSi*/ | |
1724 | { | |
42a268c2 RH |
1725 | TCGLabel *label1 = gen_new_label(); |
1726 | TCGLabel *label2 = gen_new_label(); | |
f76ebf55 MF |
1727 | |
1728 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000, | |
1729 | label1); | |
1730 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff, | |
1731 | label1); | |
1732 | tcg_gen_movi_i32(cpu_R[RRR_R], | |
1733 | OP2 == 13 ? 0x80000000 : 0); | |
1734 | tcg_gen_br(label2); | |
1735 | gen_set_label(label1); | |
1736 | if (OP2 == 13) { | |
1737 | tcg_gen_div_i32(cpu_R[RRR_R], | |
1738 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
1739 | } else { | |
1740 | tcg_gen_rem_i32(cpu_R[RRR_R], | |
1741 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
1742 | } | |
1743 | gen_set_label(label2); | |
1744 | } | |
1745 | break; | |
1746 | ||
1747 | case 14: /*REMUi*/ | |
1748 | tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1749 | break; | |
1750 | ||
1751 | default: /*reserved*/ | |
1752 | RESERVED(); | |
1753 | break; | |
1754 | } | |
dedc5eae MF |
1755 | break; |
1756 | ||
1757 | case 3: /*RST3*/ | |
b8132eff MF |
1758 | switch (OP2) { |
1759 | case 0: /*RSR*/ | |
97e89ee9 MF |
1760 | if (gen_check_sr(dc, RSR_SR, SR_R) && |
1761 | (RSR_SR < 64 || gen_check_privilege(dc)) && | |
1762 | gen_window_check1(dc, RRR_T)) { | |
0857a06e | 1763 | gen_rsr(dc, cpu_R[RRR_T], RSR_SR); |
40643d7c | 1764 | } |
b8132eff MF |
1765 | break; |
1766 | ||
1767 | case 1: /*WSR*/ | |
97e89ee9 MF |
1768 | if (gen_check_sr(dc, RSR_SR, SR_W) && |
1769 | (RSR_SR < 64 || gen_check_privilege(dc)) && | |
1770 | gen_window_check1(dc, RRR_T)) { | |
0857a06e | 1771 | gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); |
40643d7c | 1772 | } |
b8132eff MF |
1773 | break; |
1774 | ||
1775 | case 2: /*SEXTu*/ | |
7f65f4b0 | 1776 | HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT); |
97e89ee9 | 1777 | if (gen_window_check2(dc, RRR_R, RRR_S)) { |
b8132eff MF |
1778 | int shift = 24 - RRR_T; |
1779 | ||
1780 | if (shift == 24) { | |
1781 | tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); | |
1782 | } else if (shift == 16) { | |
1783 | tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); | |
1784 | } else { | |
1785 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1786 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift); | |
1787 | tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift); | |
1788 | tcg_temp_free(tmp); | |
1789 | } | |
1790 | } | |
1791 | break; | |
1792 | ||
1793 | case 3: /*CLAMPSu*/ | |
7f65f4b0 | 1794 | HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS); |
97e89ee9 | 1795 | if (gen_window_check2(dc, RRR_R, RRR_S)) { |
b8132eff MF |
1796 | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
1797 | TCGv_i32 tmp2 = tcg_temp_new_i32(); | |
f877d09e | 1798 | TCGv_i32 zero = tcg_const_i32(0); |
b8132eff MF |
1799 | |
1800 | tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T); | |
1801 | tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]); | |
1802 | tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7)); | |
b8132eff MF |
1803 | |
1804 | tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31); | |
f877d09e | 1805 | tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T)); |
b8132eff | 1806 | |
f877d09e MF |
1807 | tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero, |
1808 | cpu_R[RRR_S], tmp1); | |
b8132eff MF |
1809 | tcg_temp_free(tmp1); |
1810 | tcg_temp_free(tmp2); | |
f877d09e | 1811 | tcg_temp_free(zero); |
b8132eff MF |
1812 | } |
1813 | break; | |
1814 | ||
1815 | case 4: /*MINu*/ | |
1816 | case 5: /*MAXu*/ | |
1817 | case 6: /*MINUu*/ | |
1818 | case 7: /*MAXUu*/ | |
7f65f4b0 | 1819 | HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX); |
97e89ee9 | 1820 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
b8132eff MF |
1821 | static const TCGCond cond[] = { |
1822 | TCG_COND_LE, | |
1823 | TCG_COND_GE, | |
1824 | TCG_COND_LEU, | |
1825 | TCG_COND_GEU | |
1826 | }; | |
f877d09e MF |
1827 | tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R], |
1828 | cpu_R[RRR_S], cpu_R[RRR_T], | |
1829 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
b8132eff MF |
1830 | } |
1831 | break; | |
1832 | ||
1833 | case 8: /*MOVEQZ*/ | |
1834 | case 9: /*MOVNEZ*/ | |
1835 | case 10: /*MOVLTZ*/ | |
1836 | case 11: /*MOVGEZ*/ | |
97e89ee9 | 1837 | if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { |
b8132eff | 1838 | static const TCGCond cond[] = { |
b8132eff | 1839 | TCG_COND_EQ, |
f877d09e MF |
1840 | TCG_COND_NE, |
1841 | TCG_COND_LT, | |
b8132eff | 1842 | TCG_COND_GE, |
b8132eff | 1843 | }; |
f877d09e MF |
1844 | TCGv_i32 zero = tcg_const_i32(0); |
1845 | ||
1846 | tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R], | |
1847 | cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]); | |
1848 | tcg_temp_free(zero); | |
b8132eff MF |
1849 | } |
1850 | break; | |
1851 | ||
1852 | case 12: /*MOVFp*/ | |
b8132eff MF |
1853 | case 13: /*MOVTp*/ |
1854 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
97e89ee9 | 1855 | if (gen_window_check2(dc, RRR_R, RRR_S)) { |
f877d09e | 1856 | TCGv_i32 zero = tcg_const_i32(0); |
4dd85b6b MF |
1857 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1858 | ||
1859 | tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); | |
f877d09e MF |
1860 | tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, |
1861 | cpu_R[RRR_R], tmp, zero, | |
1862 | cpu_R[RRR_S], cpu_R[RRR_R]); | |
1863 | ||
4dd85b6b | 1864 | tcg_temp_free(tmp); |
f877d09e | 1865 | tcg_temp_free(zero); |
4dd85b6b | 1866 | } |
b8132eff MF |
1867 | break; |
1868 | ||
1869 | case 14: /*RUR*/ | |
97e89ee9 | 1870 | if (gen_window_check1(dc, RRR_R)) { |
b8132eff | 1871 | int st = (RRR_S << 4) + RRR_T; |
fe0bd475 | 1872 | if (uregnames[st].name) { |
b8132eff MF |
1873 | tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); |
1874 | } else { | |
c30f0d18 | 1875 | qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st); |
91a5bb76 | 1876 | TBD(); |
b8132eff MF |
1877 | } |
1878 | } | |
1879 | break; | |
1880 | ||
1881 | case 15: /*WUR*/ | |
97e89ee9 MF |
1882 | if (gen_window_check1(dc, RRR_T)) { |
1883 | if (uregnames[RSR_SR].name) { | |
1884 | gen_wur(RSR_SR, cpu_R[RRR_T]); | |
1885 | } else { | |
c30f0d18 | 1886 | qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR); |
97e89ee9 MF |
1887 | TBD(); |
1888 | } | |
b8132eff MF |
1889 | } |
1890 | break; | |
1891 | ||
1892 | } | |
dedc5eae MF |
1893 | break; |
1894 | ||
1895 | case 4: /*EXTUI*/ | |
1896 | case 5: | |
97e89ee9 | 1897 | if (gen_window_check2(dc, RRR_R, RRR_T)) { |
f9cb5045 | 1898 | int shiftimm = RRR_S | ((OP1 & 1) << 4); |
3580ecad MF |
1899 | int maskimm = (1 << (OP2 + 1)) - 1; |
1900 | ||
1901 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
f783cb22 AJ |
1902 | tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); |
1903 | tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); | |
3580ecad MF |
1904 | tcg_temp_free(tmp); |
1905 | } | |
dedc5eae MF |
1906 | break; |
1907 | ||
1908 | case 6: /*CUST0*/ | |
91a5bb76 | 1909 | RESERVED(); |
dedc5eae MF |
1910 | break; |
1911 | ||
1912 | case 7: /*CUST1*/ | |
91a5bb76 | 1913 | RESERVED(); |
dedc5eae MF |
1914 | break; |
1915 | ||
1916 | case 8: /*LSCXp*/ | |
9ed7ae12 MF |
1917 | switch (OP2) { |
1918 | case 0: /*LSXf*/ | |
1919 | case 1: /*LSXUf*/ | |
1920 | case 4: /*SSXf*/ | |
1921 | case 5: /*SSXUf*/ | |
1922 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); | |
97e89ee9 MF |
1923 | if (gen_window_check2(dc, RRR_S, RRR_T) && |
1924 | gen_check_cpenable(dc, 0)) { | |
9ed7ae12 MF |
1925 | TCGv_i32 addr = tcg_temp_new_i32(); |
1926 | tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]); | |
1927 | gen_load_store_alignment(dc, 2, addr, false); | |
1928 | if (OP2 & 0x4) { | |
1929 | tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring); | |
1930 | } else { | |
1931 | tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring); | |
1932 | } | |
1933 | if (OP2 & 0x1) { | |
1934 | tcg_gen_mov_i32(cpu_R[RRR_S], addr); | |
1935 | } | |
1936 | tcg_temp_free(addr); | |
1937 | } | |
1938 | break; | |
1939 | ||
1940 | default: /*reserved*/ | |
1941 | RESERVED(); | |
1942 | break; | |
1943 | } | |
dedc5eae MF |
1944 | break; |
1945 | ||
1946 | case 9: /*LSC4*/ | |
97e89ee9 MF |
1947 | if (!gen_window_check2(dc, RRR_S, RRR_T)) { |
1948 | break; | |
1949 | } | |
553e44f9 MF |
1950 | switch (OP2) { |
1951 | case 0: /*L32E*/ | |
1952 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
f822b7e4 MF |
1953 | if (gen_check_privilege(dc) && |
1954 | gen_window_check2(dc, RRR_S, RRR_T)) { | |
553e44f9 MF |
1955 | TCGv_i32 addr = tcg_temp_new_i32(); |
1956 | tcg_gen_addi_i32(addr, cpu_R[RRR_S], | |
1957 | (0xffffffc0 | (RRR_R << 2))); | |
1958 | tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring); | |
1959 | tcg_temp_free(addr); | |
1960 | } | |
1961 | break; | |
1962 | ||
1963 | case 4: /*S32E*/ | |
1964 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
f822b7e4 MF |
1965 | if (gen_check_privilege(dc) && |
1966 | gen_window_check2(dc, RRR_S, RRR_T)) { | |
553e44f9 MF |
1967 | TCGv_i32 addr = tcg_temp_new_i32(); |
1968 | tcg_gen_addi_i32(addr, cpu_R[RRR_S], | |
1969 | (0xffffffc0 | (RRR_R << 2))); | |
1970 | tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring); | |
1971 | tcg_temp_free(addr); | |
1972 | } | |
1973 | break; | |
1974 | ||
19b7bec4 MF |
1975 | case 5: /*S32N*/ |
1976 | if (gen_window_check2(dc, RRI4_S, RRI4_T)) { | |
1977 | TCGv_i32 addr = tcg_temp_new_i32(); | |
1978 | ||
1979 | tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2); | |
1980 | gen_load_store_alignment(dc, 2, addr, false); | |
1981 | tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring); | |
1982 | tcg_temp_free(addr); | |
1983 | } | |
1984 | break; | |
1985 | ||
553e44f9 MF |
1986 | default: |
1987 | RESERVED(); | |
1988 | break; | |
1989 | } | |
dedc5eae MF |
1990 | break; |
1991 | ||
1992 | case 10: /*FP0*/ | |
5eeb40c5 MF |
1993 | /*DEPBITS*/ |
1994 | if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { | |
1995 | if (!gen_window_check2(dc, RRR_S, RRR_T)) { | |
1996 | break; | |
1997 | } | |
1998 | tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], | |
1999 | OP2, RRR_R + 1); | |
2000 | break; | |
2001 | } | |
2002 | ||
dedc5eae | 2003 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); |
0b6df838 MF |
2004 | switch (OP2) { |
2005 | case 0: /*ADD.Sf*/ | |
97e89ee9 MF |
2006 | if (gen_check_cpenable(dc, 0)) { |
2007 | gen_helper_add_s(cpu_FR[RRR_R], cpu_env, | |
2008 | cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
2009 | } | |
0b6df838 MF |
2010 | break; |
2011 | ||
2012 | case 1: /*SUB.Sf*/ | |
97e89ee9 MF |
2013 | if (gen_check_cpenable(dc, 0)) { |
2014 | gen_helper_sub_s(cpu_FR[RRR_R], cpu_env, | |
2015 | cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
2016 | } | |
0b6df838 MF |
2017 | break; |
2018 | ||
2019 | case 2: /*MUL.Sf*/ | |
97e89ee9 MF |
2020 | if (gen_check_cpenable(dc, 0)) { |
2021 | gen_helper_mul_s(cpu_FR[RRR_R], cpu_env, | |
2022 | cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
2023 | } | |
0b6df838 MF |
2024 | break; |
2025 | ||
2026 | case 4: /*MADD.Sf*/ | |
97e89ee9 MF |
2027 | if (gen_check_cpenable(dc, 0)) { |
2028 | gen_helper_madd_s(cpu_FR[RRR_R], cpu_env, | |
2029 | cpu_FR[RRR_R], cpu_FR[RRR_S], | |
2030 | cpu_FR[RRR_T]); | |
2031 | } | |
0b6df838 MF |
2032 | break; |
2033 | ||
2034 | case 5: /*MSUB.Sf*/ | |
97e89ee9 MF |
2035 | if (gen_check_cpenable(dc, 0)) { |
2036 | gen_helper_msub_s(cpu_FR[RRR_R], cpu_env, | |
2037 | cpu_FR[RRR_R], cpu_FR[RRR_S], | |
2038 | cpu_FR[RRR_T]); | |
2039 | } | |
0b6df838 MF |
2040 | break; |
2041 | ||
b7ee8c6a MF |
2042 | case 8: /*ROUND.Sf*/ |
2043 | case 9: /*TRUNC.Sf*/ | |
2044 | case 10: /*FLOOR.Sf*/ | |
2045 | case 11: /*CEIL.Sf*/ | |
2046 | case 14: /*UTRUNC.Sf*/ | |
97e89ee9 MF |
2047 | if (gen_window_check1(dc, RRR_R) && |
2048 | gen_check_cpenable(dc, 0)) { | |
b7ee8c6a MF |
2049 | static const unsigned rounding_mode_const[] = { |
2050 | float_round_nearest_even, | |
2051 | float_round_to_zero, | |
2052 | float_round_down, | |
2053 | float_round_up, | |
2054 | [6] = float_round_to_zero, | |
2055 | }; | |
2056 | TCGv_i32 rounding_mode = tcg_const_i32( | |
2057 | rounding_mode_const[OP2 & 7]); | |
2058 | TCGv_i32 scale = tcg_const_i32(RRR_T); | |
2059 | ||
2060 | if (OP2 == 14) { | |
2061 | gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S], | |
2062 | rounding_mode, scale); | |
2063 | } else { | |
2064 | gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S], | |
2065 | rounding_mode, scale); | |
2066 | } | |
2067 | ||
2068 | tcg_temp_free(rounding_mode); | |
2069 | tcg_temp_free(scale); | |
2070 | } | |
2071 | break; | |
2072 | ||
2073 | case 12: /*FLOAT.Sf*/ | |
2074 | case 13: /*UFLOAT.Sf*/ | |
97e89ee9 MF |
2075 | if (gen_window_check1(dc, RRR_S) && |
2076 | gen_check_cpenable(dc, 0)) { | |
b7ee8c6a MF |
2077 | TCGv_i32 scale = tcg_const_i32(-RRR_T); |
2078 | ||
2079 | if (OP2 == 13) { | |
2080 | gen_helper_uitof(cpu_FR[RRR_R], cpu_env, | |
2081 | cpu_R[RRR_S], scale); | |
2082 | } else { | |
2083 | gen_helper_itof(cpu_FR[RRR_R], cpu_env, | |
2084 | cpu_R[RRR_S], scale); | |
2085 | } | |
2086 | tcg_temp_free(scale); | |
2087 | } | |
2088 | break; | |
2089 | ||
0b6df838 MF |
2090 | case 15: /*FP1OP*/ |
2091 | switch (RRR_T) { | |
2092 | case 0: /*MOV.Sf*/ | |
97e89ee9 MF |
2093 | if (gen_check_cpenable(dc, 0)) { |
2094 | tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); | |
2095 | } | |
0b6df838 MF |
2096 | break; |
2097 | ||
2098 | case 1: /*ABS.Sf*/ | |
97e89ee9 MF |
2099 | if (gen_check_cpenable(dc, 0)) { |
2100 | gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); | |
2101 | } | |
0b6df838 MF |
2102 | break; |
2103 | ||
2104 | case 4: /*RFRf*/ | |
97e89ee9 MF |
2105 | if (gen_window_check1(dc, RRR_R) && |
2106 | gen_check_cpenable(dc, 0)) { | |
2107 | tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]); | |
2108 | } | |
0b6df838 MF |
2109 | break; |
2110 | ||
2111 | case 5: /*WFRf*/ | |
97e89ee9 MF |
2112 | if (gen_window_check1(dc, RRR_S) && |
2113 | gen_check_cpenable(dc, 0)) { | |
2114 | tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]); | |
2115 | } | |
0b6df838 MF |
2116 | break; |
2117 | ||
2118 | case 6: /*NEG.Sf*/ | |
97e89ee9 MF |
2119 | if (gen_check_cpenable(dc, 0)) { |
2120 | gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); | |
2121 | } | |
0b6df838 MF |
2122 | break; |
2123 | ||
2124 | default: /*reserved*/ | |
2125 | RESERVED(); | |
2126 | break; | |
2127 | } | |
2128 | break; | |
2129 | ||
2130 | default: /*reserved*/ | |
2131 | RESERVED(); | |
2132 | break; | |
2133 | } | |
dedc5eae MF |
2134 | break; |
2135 | ||
2136 | case 11: /*FP1*/ | |
5eeb40c5 MF |
2137 | /*DEPBITS*/ |
2138 | if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { | |
2139 | if (!gen_window_check2(dc, RRR_S, RRR_T)) { | |
2140 | break; | |
2141 | } | |
2142 | tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], | |
2143 | OP2 + 16, RRR_R + 1); | |
2144 | break; | |
2145 | } | |
2146 | ||
dedc5eae | 2147 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); |
4e273869 MF |
2148 | |
2149 | #define gen_compare(rel, br, a, b) \ | |
2150 | do { \ | |
97e89ee9 MF |
2151 | if (gen_check_cpenable(dc, 0)) { \ |
2152 | TCGv_i32 bit = tcg_const_i32(1 << br); \ | |
2153 | \ | |
2154 | gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \ | |
2155 | tcg_temp_free(bit); \ | |
2156 | } \ | |
4e273869 MF |
2157 | } while (0) |
2158 | ||
2159 | switch (OP2) { | |
2160 | case 1: /*UN.Sf*/ | |
2161 | gen_compare(un_s, RRR_R, RRR_S, RRR_T); | |
2162 | break; | |
2163 | ||
2164 | case 2: /*OEQ.Sf*/ | |
2165 | gen_compare(oeq_s, RRR_R, RRR_S, RRR_T); | |
2166 | break; | |
2167 | ||
2168 | case 3: /*UEQ.Sf*/ | |
2169 | gen_compare(ueq_s, RRR_R, RRR_S, RRR_T); | |
2170 | break; | |
2171 | ||
2172 | case 4: /*OLT.Sf*/ | |
2173 | gen_compare(olt_s, RRR_R, RRR_S, RRR_T); | |
2174 | break; | |
2175 | ||
2176 | case 5: /*ULT.Sf*/ | |
2177 | gen_compare(ult_s, RRR_R, RRR_S, RRR_T); | |
2178 | break; | |
2179 | ||
2180 | case 6: /*OLE.Sf*/ | |
2181 | gen_compare(ole_s, RRR_R, RRR_S, RRR_T); | |
2182 | break; | |
2183 | ||
2184 | case 7: /*ULE.Sf*/ | |
2185 | gen_compare(ule_s, RRR_R, RRR_S, RRR_T); | |
2186 | break; | |
2187 | ||
2188 | #undef gen_compare | |
2189 | ||
2190 | case 8: /*MOVEQZ.Sf*/ | |
2191 | case 9: /*MOVNEZ.Sf*/ | |
2192 | case 10: /*MOVLTZ.Sf*/ | |
2193 | case 11: /*MOVGEZ.Sf*/ | |
97e89ee9 MF |
2194 | if (gen_window_check1(dc, RRR_T) && |
2195 | gen_check_cpenable(dc, 0)) { | |
4e273869 | 2196 | static const TCGCond cond[] = { |
4e273869 | 2197 | TCG_COND_EQ, |
f877d09e MF |
2198 | TCG_COND_NE, |
2199 | TCG_COND_LT, | |
4e273869 | 2200 | TCG_COND_GE, |
4e273869 | 2201 | }; |
f877d09e MF |
2202 | TCGv_i32 zero = tcg_const_i32(0); |
2203 | ||
2204 | tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R], | |
2205 | cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]); | |
2206 | tcg_temp_free(zero); | |
4e273869 MF |
2207 | } |
2208 | break; | |
2209 | ||
2210 | case 12: /*MOVF.Sf*/ | |
2211 | case 13: /*MOVT.Sf*/ | |
2212 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
97e89ee9 | 2213 | if (gen_check_cpenable(dc, 0)) { |
f877d09e | 2214 | TCGv_i32 zero = tcg_const_i32(0); |
4e273869 MF |
2215 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2216 | ||
2217 | tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); | |
f877d09e MF |
2218 | tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, |
2219 | cpu_FR[RRR_R], tmp, zero, | |
2220 | cpu_FR[RRR_S], cpu_FR[RRR_R]); | |
2221 | ||
4e273869 | 2222 | tcg_temp_free(tmp); |
f877d09e | 2223 | tcg_temp_free(zero); |
4e273869 MF |
2224 | } |
2225 | break; | |
2226 | ||
2227 | default: /*reserved*/ | |
2228 | RESERVED(); | |
2229 | break; | |
2230 | } | |
dedc5eae MF |
2231 | break; |
2232 | ||
2233 | default: /*reserved*/ | |
91a5bb76 | 2234 | RESERVED(); |
dedc5eae MF |
2235 | break; |
2236 | } | |
2237 | break; | |
2238 | ||
2239 | case 1: /*L32R*/ | |
97e89ee9 | 2240 | if (gen_window_check1(dc, RRR_T)) { |
dedc5eae | 2241 | TCGv_i32 tmp = tcg_const_i32( |
6ad6dbf7 MF |
2242 | ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? |
2243 | 0 : ((dc->pc + 3) & ~3)) + | |
2244 | (0xfffc0000 | (RI16_IMM16 << 2))); | |
dedc5eae | 2245 | |
6ad6dbf7 MF |
2246 | if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { |
2247 | tcg_gen_add_i32(tmp, tmp, dc->litbase); | |
2248 | } | |
f0a548b9 | 2249 | tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring); |
dedc5eae MF |
2250 | tcg_temp_free(tmp); |
2251 | } | |
2252 | break; | |
2253 | ||
2254 | case 2: /*LSAI*/ | |
809377aa | 2255 | #define gen_load_store(type, shift) do { \ |
97e89ee9 MF |
2256 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ |
2257 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
2258 | \ | |
2259 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \ | |
2260 | if (shift) { \ | |
2261 | gen_load_store_alignment(dc, shift, addr, false); \ | |
2262 | } \ | |
2263 | tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ | |
2264 | tcg_temp_free(addr); \ | |
5b4e481b | 2265 | } \ |
809377aa MF |
2266 | } while (0) |
2267 | ||
2268 | switch (RRI8_R) { | |
2269 | case 0: /*L8UI*/ | |
2270 | gen_load_store(ld8u, 0); | |
2271 | break; | |
2272 | ||
2273 | case 1: /*L16UI*/ | |
2274 | gen_load_store(ld16u, 1); | |
2275 | break; | |
2276 | ||
2277 | case 2: /*L32I*/ | |
2278 | gen_load_store(ld32u, 2); | |
2279 | break; | |
2280 | ||
2281 | case 4: /*S8I*/ | |
2282 | gen_load_store(st8, 0); | |
2283 | break; | |
2284 | ||
2285 | case 5: /*S16I*/ | |
2286 | gen_load_store(st16, 1); | |
2287 | break; | |
2288 | ||
2289 | case 6: /*S32I*/ | |
2290 | gen_load_store(st32, 2); | |
2291 | break; | |
2292 | ||
7c842590 | 2293 | #define gen_dcache_hit_test(w, shift) do { \ |
97e89ee9 MF |
2294 | if (gen_window_check1(dc, RRI##w##_S)) { \ |
2295 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
2296 | TCGv_i32 res = tcg_temp_new_i32(); \ | |
2297 | tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ | |
2298 | RRI##w##_IMM##w << shift); \ | |
2299 | tcg_gen_qemu_ld8u(res, addr, dc->cring); \ | |
2300 | tcg_temp_free(addr); \ | |
2301 | tcg_temp_free(res); \ | |
2302 | } \ | |
7c842590 MF |
2303 | } while (0) |
2304 | ||
2305 | #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4) | |
2306 | #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2) | |
2307 | ||
809377aa | 2308 | case 7: /*CACHEc*/ |
8ffc2d0d MF |
2309 | if (RRI8_T < 8) { |
2310 | HAS_OPTION(XTENSA_OPTION_DCACHE); | |
2311 | } | |
2312 | ||
2313 | switch (RRI8_T) { | |
2314 | case 0: /*DPFRc*/ | |
7c842590 | 2315 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2316 | break; |
2317 | ||
2318 | case 1: /*DPFWc*/ | |
7c842590 | 2319 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2320 | break; |
2321 | ||
2322 | case 2: /*DPFROc*/ | |
7c842590 | 2323 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2324 | break; |
2325 | ||
2326 | case 3: /*DPFWOc*/ | |
7c842590 | 2327 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2328 | break; |
2329 | ||
2330 | case 4: /*DHWBc*/ | |
7c842590 | 2331 | gen_dcache_hit_test8(); |
8ffc2d0d MF |
2332 | break; |
2333 | ||
2334 | case 5: /*DHWBIc*/ | |
7c842590 | 2335 | gen_dcache_hit_test8(); |
8ffc2d0d MF |
2336 | break; |
2337 | ||
2338 | case 6: /*DHIc*/ | |
97e89ee9 MF |
2339 | if (gen_check_privilege(dc)) { |
2340 | gen_dcache_hit_test8(); | |
2341 | } | |
8ffc2d0d MF |
2342 | break; |
2343 | ||
2344 | case 7: /*DIIc*/ | |
97e89ee9 MF |
2345 | if (gen_check_privilege(dc)) { |
2346 | gen_window_check1(dc, RRI8_S); | |
2347 | } | |
8ffc2d0d MF |
2348 | break; |
2349 | ||
2350 | case 8: /*DCEc*/ | |
2351 | switch (OP1) { | |
2352 | case 0: /*DPFLl*/ | |
2353 | HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); | |
97e89ee9 MF |
2354 | if (gen_check_privilege(dc)) { |
2355 | gen_dcache_hit_test4(); | |
2356 | } | |
8ffc2d0d MF |
2357 | break; |
2358 | ||
2359 | case 2: /*DHUl*/ | |
2360 | HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); | |
97e89ee9 MF |
2361 | if (gen_check_privilege(dc)) { |
2362 | gen_dcache_hit_test4(); | |
2363 | } | |
8ffc2d0d MF |
2364 | break; |
2365 | ||
2366 | case 3: /*DIUl*/ | |
2367 | HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); | |
97e89ee9 MF |
2368 | if (gen_check_privilege(dc)) { |
2369 | gen_window_check1(dc, RRI4_S); | |
2370 | } | |
8ffc2d0d MF |
2371 | break; |
2372 | ||
2373 | case 4: /*DIWBc*/ | |
2374 | HAS_OPTION(XTENSA_OPTION_DCACHE); | |
97e89ee9 MF |
2375 | if (gen_check_privilege(dc)) { |
2376 | gen_window_check1(dc, RRI4_S); | |
2377 | } | |
8ffc2d0d MF |
2378 | break; |
2379 | ||
2380 | case 5: /*DIWBIc*/ | |
2381 | HAS_OPTION(XTENSA_OPTION_DCACHE); | |
97e89ee9 MF |
2382 | if (gen_check_privilege(dc)) { |
2383 | gen_window_check1(dc, RRI4_S); | |
2384 | } | |
8ffc2d0d MF |
2385 | break; |
2386 | ||
2387 | default: /*reserved*/ | |
2388 | RESERVED(); | |
2389 | break; | |
2390 | ||
2391 | } | |
2392 | break; | |
2393 | ||
7c842590 MF |
2394 | #undef gen_dcache_hit_test |
2395 | #undef gen_dcache_hit_test4 | |
2396 | #undef gen_dcache_hit_test8 | |
2397 | ||
e848dd42 | 2398 | #define gen_icache_hit_test(w, shift) do { \ |
97e89ee9 MF |
2399 | if (gen_window_check1(dc, RRI##w##_S)) { \ |
2400 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
2401 | tcg_gen_movi_i32(cpu_pc, dc->pc); \ | |
2402 | tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ | |
2403 | RRI##w##_IMM##w << shift); \ | |
2404 | gen_helper_itlb_hit_test(cpu_env, addr); \ | |
2405 | tcg_temp_free(addr); \ | |
2406 | }\ | |
e848dd42 MF |
2407 | } while (0) |
2408 | ||
2409 | #define gen_icache_hit_test4() gen_icache_hit_test(4, 4) | |
2410 | #define gen_icache_hit_test8() gen_icache_hit_test(8, 2) | |
2411 | ||
8ffc2d0d MF |
2412 | case 12: /*IPFc*/ |
2413 | HAS_OPTION(XTENSA_OPTION_ICACHE); | |
e848dd42 | 2414 | gen_window_check1(dc, RRI8_S); |
8ffc2d0d MF |
2415 | break; |
2416 | ||
2417 | case 13: /*ICEc*/ | |
2418 | switch (OP1) { | |
2419 | case 0: /*IPFLl*/ | |
2420 | HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); | |
97e89ee9 MF |
2421 | if (gen_check_privilege(dc)) { |
2422 | gen_icache_hit_test4(); | |
2423 | } | |
8ffc2d0d MF |
2424 | break; |
2425 | ||
2426 | case 2: /*IHUl*/ | |
2427 | HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); | |
97e89ee9 MF |
2428 | if (gen_check_privilege(dc)) { |
2429 | gen_icache_hit_test4(); | |
2430 | } | |
8ffc2d0d MF |
2431 | break; |
2432 | ||
2433 | case 3: /*IIUl*/ | |
2434 | HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); | |
97e89ee9 MF |
2435 | if (gen_check_privilege(dc)) { |
2436 | gen_window_check1(dc, RRI4_S); | |
2437 | } | |
8ffc2d0d MF |
2438 | break; |
2439 | ||
2440 | default: /*reserved*/ | |
2441 | RESERVED(); | |
2442 | break; | |
2443 | } | |
2444 | break; | |
2445 | ||
2446 | case 14: /*IHIc*/ | |
2447 | HAS_OPTION(XTENSA_OPTION_ICACHE); | |
e848dd42 | 2448 | gen_icache_hit_test8(); |
8ffc2d0d MF |
2449 | break; |
2450 | ||
2451 | case 15: /*IIIc*/ | |
2452 | HAS_OPTION(XTENSA_OPTION_ICACHE); | |
97e89ee9 MF |
2453 | if (gen_check_privilege(dc)) { |
2454 | gen_window_check1(dc, RRI8_S); | |
2455 | } | |
8ffc2d0d MF |
2456 | break; |
2457 | ||
2458 | default: /*reserved*/ | |
2459 | RESERVED(); | |
2460 | break; | |
2461 | } | |
809377aa MF |
2462 | break; |
2463 | ||
e848dd42 MF |
2464 | #undef gen_icache_hit_test |
2465 | #undef gen_icache_hit_test4 | |
2466 | #undef gen_icache_hit_test8 | |
2467 | ||
809377aa MF |
2468 | case 9: /*L16SI*/ |
2469 | gen_load_store(ld16s, 1); | |
2470 | break; | |
5b4e481b | 2471 | #undef gen_load_store |
809377aa MF |
2472 | |
2473 | case 10: /*MOVI*/ | |
97e89ee9 MF |
2474 | if (gen_window_check1(dc, RRI8_T)) { |
2475 | tcg_gen_movi_i32(cpu_R[RRI8_T], | |
2476 | RRI8_IMM8 | (RRI8_S << 8) | | |
2477 | ((RRI8_S & 0x8) ? 0xfffff000 : 0)); | |
2478 | } | |
809377aa MF |
2479 | break; |
2480 | ||
5b4e481b | 2481 | #define gen_load_store_no_hw_align(type) do { \ |
97e89ee9 MF |
2482 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ |
2483 | TCGv_i32 addr = tcg_temp_local_new_i32(); \ | |
2484 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \ | |
2485 | gen_load_store_alignment(dc, 2, addr, true); \ | |
2486 | tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ | |
2487 | tcg_temp_free(addr); \ | |
2488 | } \ | |
5b4e481b MF |
2489 | } while (0) |
2490 | ||
809377aa MF |
2491 | case 11: /*L32AIy*/ |
2492 | HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); | |
5b4e481b | 2493 | gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/ |
809377aa MF |
2494 | break; |
2495 | ||
2496 | case 12: /*ADDI*/ | |
97e89ee9 MF |
2497 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
2498 | tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE); | |
2499 | } | |
809377aa MF |
2500 | break; |
2501 | ||
2502 | case 13: /*ADDMI*/ | |
97e89ee9 MF |
2503 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
2504 | tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], | |
2505 | RRI8_IMM8_SE << 8); | |
2506 | } | |
809377aa MF |
2507 | break; |
2508 | ||
2509 | case 14: /*S32C1Iy*/ | |
7f65f4b0 | 2510 | HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE); |
97e89ee9 | 2511 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
42a268c2 | 2512 | TCGLabel *label = gen_new_label(); |
809377aa MF |
2513 | TCGv_i32 tmp = tcg_temp_local_new_i32(); |
2514 | TCGv_i32 addr = tcg_temp_local_new_i32(); | |
fcc803d1 | 2515 | TCGv_i32 tpc; |
809377aa MF |
2516 | |
2517 | tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]); | |
2518 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); | |
5b4e481b | 2519 | gen_load_store_alignment(dc, 2, addr, true); |
fcc803d1 MF |
2520 | |
2521 | gen_advance_ccount(dc); | |
2522 | tpc = tcg_const_i32(dc->pc); | |
2523 | gen_helper_check_atomctl(cpu_env, tpc, addr); | |
f0a548b9 | 2524 | tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring); |
809377aa MF |
2525 | tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T], |
2526 | cpu_SR[SCOMPARE1], label); | |
2527 | ||
f0a548b9 | 2528 | tcg_gen_qemu_st32(tmp, addr, dc->cring); |
809377aa MF |
2529 | |
2530 | gen_set_label(label); | |
fcc803d1 | 2531 | tcg_temp_free(tpc); |
809377aa MF |
2532 | tcg_temp_free(addr); |
2533 | tcg_temp_free(tmp); | |
2534 | } | |
2535 | break; | |
2536 | ||
2537 | case 15: /*S32RIy*/ | |
2538 | HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); | |
5b4e481b | 2539 | gen_load_store_no_hw_align(st32); /*TODO release?*/ |
809377aa | 2540 | break; |
5b4e481b | 2541 | #undef gen_load_store_no_hw_align |
809377aa MF |
2542 | |
2543 | default: /*reserved*/ | |
91a5bb76 | 2544 | RESERVED(); |
809377aa MF |
2545 | break; |
2546 | } | |
dedc5eae MF |
2547 | break; |
2548 | ||
2549 | case 3: /*LSCIp*/ | |
9ed7ae12 MF |
2550 | switch (RRI8_R) { |
2551 | case 0: /*LSIf*/ | |
2552 | case 4: /*SSIf*/ | |
2553 | case 8: /*LSIUf*/ | |
2554 | case 12: /*SSIUf*/ | |
2555 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); | |
97e89ee9 MF |
2556 | if (gen_window_check1(dc, RRI8_S) && |
2557 | gen_check_cpenable(dc, 0)) { | |
9ed7ae12 MF |
2558 | TCGv_i32 addr = tcg_temp_new_i32(); |
2559 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); | |
2560 | gen_load_store_alignment(dc, 2, addr, false); | |
2561 | if (RRI8_R & 0x4) { | |
2562 | tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring); | |
2563 | } else { | |
2564 | tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring); | |
2565 | } | |
2566 | if (RRI8_R & 0x8) { | |
2567 | tcg_gen_mov_i32(cpu_R[RRI8_S], addr); | |
2568 | } | |
2569 | tcg_temp_free(addr); | |
2570 | } | |
2571 | break; | |
2572 | ||
2573 | default: /*reserved*/ | |
2574 | RESERVED(); | |
2575 | break; | |
2576 | } | |
dedc5eae MF |
2577 | break; |
2578 | ||
2579 | case 4: /*MAC16d*/ | |
2580 | HAS_OPTION(XTENSA_OPTION_MAC16); | |
6825b6c3 MF |
2581 | { |
2582 | enum { | |
2583 | MAC16_UMUL = 0x0, | |
2584 | MAC16_MUL = 0x4, | |
2585 | MAC16_MULA = 0x8, | |
2586 | MAC16_MULS = 0xc, | |
2587 | MAC16_NONE = 0xf, | |
2588 | } op = OP1 & 0xc; | |
2589 | bool is_m1_sr = (OP2 & 0x3) == 2; | |
2590 | bool is_m2_sr = (OP2 & 0xc) == 0; | |
2591 | uint32_t ld_offset = 0; | |
2592 | ||
2593 | if (OP2 > 9) { | |
2594 | RESERVED(); | |
2595 | } | |
2596 | ||
2597 | switch (OP2 & 2) { | |
2598 | case 0: /*MACI?/MACC?*/ | |
2599 | is_m1_sr = true; | |
2600 | ld_offset = (OP2 & 1) ? -4 : 4; | |
2601 | ||
2602 | if (OP2 >= 8) { /*MACI/MACC*/ | |
2603 | if (OP1 == 0) { /*LDINC/LDDEC*/ | |
2604 | op = MAC16_NONE; | |
2605 | } else { | |
2606 | RESERVED(); | |
2607 | } | |
2608 | } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/ | |
2609 | RESERVED(); | |
2610 | } | |
2611 | break; | |
2612 | ||
2613 | case 2: /*MACD?/MACA?*/ | |
2614 | if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/ | |
2615 | RESERVED(); | |
2616 | } | |
2617 | break; | |
2618 | } | |
2619 | ||
2620 | if (op != MAC16_NONE) { | |
97e89ee9 MF |
2621 | if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) { |
2622 | break; | |
6825b6c3 | 2623 | } |
97e89ee9 MF |
2624 | if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) { |
2625 | break; | |
6825b6c3 MF |
2626 | } |
2627 | } | |
2628 | ||
97e89ee9 MF |
2629 | if (ld_offset && !gen_window_check1(dc, RRR_S)) { |
2630 | break; | |
2631 | } | |
2632 | ||
6825b6c3 MF |
2633 | { |
2634 | TCGv_i32 vaddr = tcg_temp_new_i32(); | |
2635 | TCGv_i32 mem32 = tcg_temp_new_i32(); | |
2636 | ||
2637 | if (ld_offset) { | |
6825b6c3 MF |
2638 | tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset); |
2639 | gen_load_store_alignment(dc, 2, vaddr, false); | |
2640 | tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); | |
2641 | } | |
2642 | if (op != MAC16_NONE) { | |
2643 | TCGv_i32 m1 = gen_mac16_m( | |
2644 | is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S], | |
2645 | OP1 & 1, op == MAC16_UMUL); | |
2646 | TCGv_i32 m2 = gen_mac16_m( | |
2647 | is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T], | |
2648 | OP1 & 2, op == MAC16_UMUL); | |
2649 | ||
2650 | if (op == MAC16_MUL || op == MAC16_UMUL) { | |
2651 | tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); | |
2652 | if (op == MAC16_UMUL) { | |
2653 | tcg_gen_movi_i32(cpu_SR[ACCHI], 0); | |
2654 | } else { | |
2655 | tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); | |
2656 | } | |
2657 | } else { | |
d2123a07 RH |
2658 | TCGv_i32 lo = tcg_temp_new_i32(); |
2659 | TCGv_i32 hi = tcg_temp_new_i32(); | |
2660 | ||
2661 | tcg_gen_mul_i32(lo, m1, m2); | |
2662 | tcg_gen_sari_i32(hi, lo, 31); | |
6825b6c3 | 2663 | if (op == MAC16_MULA) { |
d2123a07 RH |
2664 | tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], |
2665 | cpu_SR[ACCLO], cpu_SR[ACCHI], | |
2666 | lo, hi); | |
6825b6c3 | 2667 | } else { |
d2123a07 RH |
2668 | tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], |
2669 | cpu_SR[ACCLO], cpu_SR[ACCHI], | |
2670 | lo, hi); | |
6825b6c3 | 2671 | } |
6825b6c3 MF |
2672 | tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); |
2673 | ||
d2123a07 RH |
2674 | tcg_temp_free_i32(lo); |
2675 | tcg_temp_free_i32(hi); | |
6825b6c3 MF |
2676 | } |
2677 | tcg_temp_free(m1); | |
2678 | tcg_temp_free(m2); | |
2679 | } | |
2680 | if (ld_offset) { | |
2681 | tcg_gen_mov_i32(cpu_R[RRR_S], vaddr); | |
2682 | tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32); | |
2683 | } | |
2684 | tcg_temp_free(vaddr); | |
2685 | tcg_temp_free(mem32); | |
2686 | } | |
2687 | } | |
dedc5eae MF |
2688 | break; |
2689 | ||
2690 | case 5: /*CALLN*/ | |
2691 | switch (CALL_N) { | |
2692 | case 0: /*CALL0*/ | |
2693 | tcg_gen_movi_i32(cpu_R[0], dc->next_pc); | |
2694 | gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); | |
2695 | break; | |
2696 | ||
2697 | case 1: /*CALL4w*/ | |
2698 | case 2: /*CALL8w*/ | |
2699 | case 3: /*CALL12w*/ | |
2700 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
97e89ee9 MF |
2701 | if (gen_window_check1(dc, CALL_N << 2)) { |
2702 | gen_callwi(dc, CALL_N, | |
2703 | (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); | |
2704 | } | |
dedc5eae MF |
2705 | break; |
2706 | } | |
2707 | break; | |
2708 | ||
2709 | case 6: /*SI*/ | |
2710 | switch (CALL_N) { | |
2711 | case 0: /*J*/ | |
2712 | gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0); | |
2713 | break; | |
2714 | ||
bd57fb91 | 2715 | case 1: /*BZ*/ |
97e89ee9 | 2716 | if (gen_window_check1(dc, BRI12_S)) { |
bd57fb91 MF |
2717 | static const TCGCond cond[] = { |
2718 | TCG_COND_EQ, /*BEQZ*/ | |
2719 | TCG_COND_NE, /*BNEZ*/ | |
2720 | TCG_COND_LT, /*BLTZ*/ | |
2721 | TCG_COND_GE, /*BGEZ*/ | |
2722 | }; | |
2723 | ||
2724 | gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0, | |
2725 | 4 + BRI12_IMM12_SE); | |
2726 | } | |
2727 | break; | |
2728 | ||
2729 | case 2: /*BI0*/ | |
97e89ee9 | 2730 | if (gen_window_check1(dc, BRI8_S)) { |
bd57fb91 MF |
2731 | static const TCGCond cond[] = { |
2732 | TCG_COND_EQ, /*BEQI*/ | |
2733 | TCG_COND_NE, /*BNEI*/ | |
2734 | TCG_COND_LT, /*BLTI*/ | |
2735 | TCG_COND_GE, /*BGEI*/ | |
2736 | }; | |
2737 | ||
2738 | gen_brcondi(dc, cond[BRI8_M & 3], | |
2739 | cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE); | |
2740 | } | |
2741 | break; | |
2742 | ||
2743 | case 3: /*BI1*/ | |
2744 | switch (BRI8_M) { | |
2745 | case 0: /*ENTRYw*/ | |
2746 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
2747 | { |
2748 | TCGv_i32 pc = tcg_const_i32(dc->pc); | |
2749 | TCGv_i32 s = tcg_const_i32(BRI12_S); | |
2750 | TCGv_i32 imm = tcg_const_i32(BRI12_IMM12); | |
b994e91b | 2751 | gen_advance_ccount(dc); |
f492b82d | 2752 | gen_helper_entry(cpu_env, pc, s, imm); |
553e44f9 MF |
2753 | tcg_temp_free(imm); |
2754 | tcg_temp_free(s); | |
2755 | tcg_temp_free(pc); | |
2db59a76 MF |
2756 | /* This can change tb->flags, so exit tb */ |
2757 | gen_jumpi_check_loop_end(dc, -1); | |
553e44f9 | 2758 | } |
bd57fb91 MF |
2759 | break; |
2760 | ||
2761 | case 1: /*B1*/ | |
2762 | switch (BRI8_R) { | |
2763 | case 0: /*BFp*/ | |
bd57fb91 MF |
2764 | case 1: /*BTp*/ |
2765 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
4dd85b6b MF |
2766 | { |
2767 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
2768 | tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S); | |
2769 | gen_brcondi(dc, | |
2770 | BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ, | |
2771 | tmp, 0, 4 + RRI8_IMM8_SE); | |
2772 | tcg_temp_free(tmp); | |
2773 | } | |
bd57fb91 MF |
2774 | break; |
2775 | ||
2776 | case 8: /*LOOP*/ | |
bd57fb91 | 2777 | case 9: /*LOOPNEZ*/ |
bd57fb91 | 2778 | case 10: /*LOOPGTZ*/ |
797d780b | 2779 | HAS_OPTION(XTENSA_OPTION_LOOP); |
97e89ee9 | 2780 | if (gen_window_check1(dc, RRI8_S)) { |
797d780b MF |
2781 | uint32_t lend = dc->pc + RRI8_IMM8 + 4; |
2782 | TCGv_i32 tmp = tcg_const_i32(lend); | |
2783 | ||
2784 | tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1); | |
2785 | tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); | |
f492b82d | 2786 | gen_helper_wsr_lend(cpu_env, tmp); |
797d780b MF |
2787 | tcg_temp_free(tmp); |
2788 | ||
2789 | if (BRI8_R > 8) { | |
42a268c2 | 2790 | TCGLabel *label = gen_new_label(); |
797d780b MF |
2791 | tcg_gen_brcondi_i32( |
2792 | BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT, | |
2793 | cpu_R[RRI8_S], 0, label); | |
2794 | gen_jumpi(dc, lend, 1); | |
2795 | gen_set_label(label); | |
2796 | } | |
2797 | ||
2798 | gen_jumpi(dc, dc->next_pc, 0); | |
2799 | } | |
bd57fb91 MF |
2800 | break; |
2801 | ||
2802 | default: /*reserved*/ | |
91a5bb76 | 2803 | RESERVED(); |
bd57fb91 MF |
2804 | break; |
2805 | ||
2806 | } | |
2807 | break; | |
2808 | ||
2809 | case 2: /*BLTUI*/ | |
2810 | case 3: /*BGEUI*/ | |
97e89ee9 MF |
2811 | if (gen_window_check1(dc, BRI8_S)) { |
2812 | gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU, | |
2813 | cpu_R[BRI8_S], B4CONSTU[BRI8_R], | |
2814 | 4 + BRI8_IMM8_SE); | |
2815 | } | |
bd57fb91 MF |
2816 | break; |
2817 | } | |
2818 | break; | |
2819 | ||
dedc5eae MF |
2820 | } |
2821 | break; | |
2822 | ||
2823 | case 7: /*B*/ | |
bd57fb91 MF |
2824 | { |
2825 | TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ; | |
2826 | ||
2827 | switch (RRI8_R & 7) { | |
2828 | case 0: /*BNONE*/ /*BANY*/ | |
97e89ee9 | 2829 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
bd57fb91 MF |
2830 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2831 | tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); | |
2832 | gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); | |
2833 | tcg_temp_free(tmp); | |
2834 | } | |
2835 | break; | |
2836 | ||
2837 | case 1: /*BEQ*/ /*BNE*/ | |
2838 | case 2: /*BLT*/ /*BGE*/ | |
2839 | case 3: /*BLTU*/ /*BGEU*/ | |
97e89ee9 | 2840 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
bd57fb91 MF |
2841 | static const TCGCond cond[] = { |
2842 | [1] = TCG_COND_EQ, | |
2843 | [2] = TCG_COND_LT, | |
2844 | [3] = TCG_COND_LTU, | |
2845 | [9] = TCG_COND_NE, | |
2846 | [10] = TCG_COND_GE, | |
2847 | [11] = TCG_COND_GEU, | |
2848 | }; | |
2849 | gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T], | |
2850 | 4 + RRI8_IMM8_SE); | |
2851 | } | |
2852 | break; | |
2853 | ||
2854 | case 4: /*BALL*/ /*BNALL*/ | |
97e89ee9 | 2855 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
bd57fb91 MF |
2856 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2857 | tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); | |
2858 | gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T], | |
2859 | 4 + RRI8_IMM8_SE); | |
2860 | tcg_temp_free(tmp); | |
2861 | } | |
2862 | break; | |
2863 | ||
2864 | case 5: /*BBC*/ /*BBS*/ | |
97e89ee9 | 2865 | if (gen_window_check2(dc, RRI8_S, RRI8_T)) { |
7ff7563f MF |
2866 | #ifdef TARGET_WORDS_BIGENDIAN |
2867 | TCGv_i32 bit = tcg_const_i32(0x80000000); | |
2868 | #else | |
2869 | TCGv_i32 bit = tcg_const_i32(0x00000001); | |
2870 | #endif | |
bd57fb91 MF |
2871 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2872 | tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f); | |
7ff7563f MF |
2873 | #ifdef TARGET_WORDS_BIGENDIAN |
2874 | tcg_gen_shr_i32(bit, bit, tmp); | |
2875 | #else | |
bd57fb91 | 2876 | tcg_gen_shl_i32(bit, bit, tmp); |
7ff7563f | 2877 | #endif |
bd57fb91 MF |
2878 | tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit); |
2879 | gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); | |
2880 | tcg_temp_free(tmp); | |
2881 | tcg_temp_free(bit); | |
2882 | } | |
2883 | break; | |
2884 | ||
2885 | case 6: /*BBCI*/ /*BBSI*/ | |
2886 | case 7: | |
97e89ee9 | 2887 | if (gen_window_check1(dc, RRI8_S)) { |
bd57fb91 MF |
2888 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2889 | tcg_gen_andi_i32(tmp, cpu_R[RRI8_S], | |
7ff7563f MF |
2890 | #ifdef TARGET_WORDS_BIGENDIAN |
2891 | 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T)); | |
2892 | #else | |
2893 | 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T)); | |
2894 | #endif | |
bd57fb91 MF |
2895 | gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); |
2896 | tcg_temp_free(tmp); | |
2897 | } | |
2898 | break; | |
2899 | ||
2900 | } | |
2901 | } | |
dedc5eae MF |
2902 | break; |
2903 | ||
67882fd1 | 2904 | #define gen_narrow_load_store(type) do { \ |
97e89ee9 MF |
2905 | if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \ |
2906 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
2907 | tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \ | |
2908 | gen_load_store_alignment(dc, 2, addr, false); \ | |
2909 | tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \ | |
2910 | tcg_temp_free(addr); \ | |
2911 | } \ | |
67882fd1 MF |
2912 | } while (0) |
2913 | ||
dedc5eae | 2914 | case 8: /*L32I.Nn*/ |
67882fd1 | 2915 | gen_narrow_load_store(ld32u); |
dedc5eae MF |
2916 | break; |
2917 | ||
2918 | case 9: /*S32I.Nn*/ | |
67882fd1 | 2919 | gen_narrow_load_store(st32); |
dedc5eae | 2920 | break; |
67882fd1 | 2921 | #undef gen_narrow_load_store |
dedc5eae MF |
2922 | |
2923 | case 10: /*ADD.Nn*/ | |
97e89ee9 MF |
2924 | if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) { |
2925 | tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]); | |
2926 | } | |
dedc5eae MF |
2927 | break; |
2928 | ||
2929 | case 11: /*ADDI.Nn*/ | |
97e89ee9 MF |
2930 | if (gen_window_check2(dc, RRRN_R, RRRN_S)) { |
2931 | tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], | |
2932 | RRRN_T ? RRRN_T : -1); | |
2933 | } | |
dedc5eae MF |
2934 | break; |
2935 | ||
2936 | case 12: /*ST2n*/ | |
97e89ee9 MF |
2937 | if (!gen_window_check1(dc, RRRN_S)) { |
2938 | break; | |
2939 | } | |
67882fd1 MF |
2940 | if (RRRN_T < 8) { /*MOVI.Nn*/ |
2941 | tcg_gen_movi_i32(cpu_R[RRRN_S], | |
2942 | RRRN_R | (RRRN_T << 4) | | |
2943 | ((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); | |
2944 | } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ | |
bd57fb91 MF |
2945 | TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ; |
2946 | ||
2947 | gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0, | |
2948 | 4 + (RRRN_R | ((RRRN_T & 3) << 4))); | |
67882fd1 | 2949 | } |
dedc5eae MF |
2950 | break; |
2951 | ||
2952 | case 13: /*ST3n*/ | |
67882fd1 MF |
2953 | switch (RRRN_R) { |
2954 | case 0: /*MOV.Nn*/ | |
97e89ee9 MF |
2955 | if (gen_window_check2(dc, RRRN_S, RRRN_T)) { |
2956 | tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]); | |
2957 | } | |
67882fd1 MF |
2958 | break; |
2959 | ||
2960 | case 15: /*S3*/ | |
2961 | switch (RRRN_T) { | |
2962 | case 0: /*RET.Nn*/ | |
2963 | gen_jump(dc, cpu_R[0]); | |
2964 | break; | |
2965 | ||
2966 | case 1: /*RETW.Nn*/ | |
91a5bb76 | 2967 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
553e44f9 MF |
2968 | { |
2969 | TCGv_i32 tmp = tcg_const_i32(dc->pc); | |
b994e91b | 2970 | gen_advance_ccount(dc); |
f492b82d | 2971 | gen_helper_retw(tmp, cpu_env, tmp); |
553e44f9 MF |
2972 | gen_jump(dc, tmp); |
2973 | tcg_temp_free(tmp); | |
2974 | } | |
67882fd1 MF |
2975 | break; |
2976 | ||
2977 | case 2: /*BREAK.Nn*/ | |
e61dc8f7 MF |
2978 | HAS_OPTION(XTENSA_OPTION_DEBUG); |
2979 | if (dc->debug) { | |
2980 | gen_debug_exception(dc, DEBUGCAUSE_BN); | |
2981 | } | |
67882fd1 MF |
2982 | break; |
2983 | ||
2984 | case 3: /*NOP.Nn*/ | |
2985 | break; | |
2986 | ||
2987 | case 6: /*ILL.Nn*/ | |
40643d7c | 2988 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
67882fd1 MF |
2989 | break; |
2990 | ||
2991 | default: /*reserved*/ | |
91a5bb76 | 2992 | RESERVED(); |
67882fd1 MF |
2993 | break; |
2994 | } | |
2995 | break; | |
2996 | ||
2997 | default: /*reserved*/ | |
91a5bb76 | 2998 | RESERVED(); |
67882fd1 MF |
2999 | break; |
3000 | } | |
dedc5eae MF |
3001 | break; |
3002 | ||
3003 | default: /*reserved*/ | |
91a5bb76 | 3004 | RESERVED(); |
dedc5eae MF |
3005 | break; |
3006 | } | |
3007 | ||
c26032b2 MF |
3008 | if (dc->is_jmp == DISAS_NEXT) { |
3009 | gen_check_loop_end(dc, 0); | |
3010 | } | |
dedc5eae | 3011 | dc->pc = dc->next_pc; |
797d780b | 3012 | |
dedc5eae MF |
3013 | return; |
3014 | ||
3015 | invalid_opcode: | |
c30f0d18 | 3016 | qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc); |
6b814719 | 3017 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
dedc5eae MF |
3018 | #undef HAS_OPTION |
3019 | } | |
3020 | ||
01673a34 MF |
3021 | static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) |
3022 | { | |
3023 | uint8_t b0 = cpu_ldub_code(env, dc->pc); | |
3024 | return xtensa_op0_insn_len(OP0); | |
3025 | } | |
3026 | ||
97129ac8 | 3027 | static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) |
e61dc8f7 MF |
3028 | { |
3029 | unsigned i; | |
3030 | ||
3031 | for (i = 0; i < dc->config->nibreak; ++i) { | |
3032 | if ((env->sregs[IBREAKENABLE] & (1 << i)) && | |
3033 | env->sregs[IBREAKA + i] == dc->pc) { | |
3034 | gen_debug_exception(dc, DEBUGCAUSE_IB); | |
3035 | break; | |
3036 | } | |
3037 | } | |
3038 | } | |
3039 | ||
4e5e1215 | 3040 | void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) |
dedc5eae | 3041 | { |
4e5e1215 | 3042 | XtensaCPU *cpu = xtensa_env_get_cpu(env); |
ed2803da | 3043 | CPUState *cs = CPU(cpu); |
dedc5eae MF |
3044 | DisasContext dc; |
3045 | int insn_count = 0; | |
dedc5eae MF |
3046 | int max_insns = tb->cflags & CF_COUNT_MASK; |
3047 | uint32_t pc_start = tb->pc; | |
3048 | uint32_t next_page_start = | |
3049 | (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
3050 | ||
3051 | if (max_insns == 0) { | |
3052 | max_insns = CF_COUNT_MASK; | |
3053 | } | |
190ce7fb RH |
3054 | if (max_insns > TCG_MAX_INSNS) { |
3055 | max_insns = TCG_MAX_INSNS; | |
3056 | } | |
dedc5eae MF |
3057 | |
3058 | dc.config = env->config; | |
ed2803da | 3059 | dc.singlestep_enabled = cs->singlestep_enabled; |
dedc5eae MF |
3060 | dc.tb = tb; |
3061 | dc.pc = pc_start; | |
f0a548b9 MF |
3062 | dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK; |
3063 | dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; | |
797d780b MF |
3064 | dc.lbeg = env->sregs[LBEG]; |
3065 | dc.lend = env->sregs[LEND]; | |
dedc5eae | 3066 | dc.is_jmp = DISAS_NEXT; |
b994e91b | 3067 | dc.ccount_delta = 0; |
e61dc8f7 | 3068 | dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; |
35b5c044 | 3069 | dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; |
ef04a846 MF |
3070 | dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> |
3071 | XTENSA_TBFLAG_CPENABLE_SHIFT; | |
2db59a76 MF |
3072 | dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> |
3073 | XTENSA_TBFLAG_WINDOW_SHIFT); | |
dedc5eae | 3074 | |
6ad6dbf7 | 3075 | init_litbase(&dc); |
3580ecad | 3076 | init_sar_tracker(&dc); |
35b5c044 MF |
3077 | if (dc.icount) { |
3078 | dc.next_icount = tcg_temp_local_new_i32(); | |
3079 | } | |
3580ecad | 3080 | |
cd42d5b2 | 3081 | gen_tb_start(tb); |
dedc5eae | 3082 | |
a00817cc | 3083 | if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { |
40643d7c | 3084 | tcg_gen_movi_i32(cpu_pc, dc.pc); |
b994e91b | 3085 | gen_exception(&dc, EXCP_DEBUG); |
40643d7c MF |
3086 | } |
3087 | ||
dedc5eae | 3088 | do { |
667b8e29 | 3089 | tcg_gen_insn_start(dc.pc); |
959082fc | 3090 | ++insn_count; |
dedc5eae | 3091 | |
b994e91b MF |
3092 | ++dc.ccount_delta; |
3093 | ||
b933066a RH |
3094 | if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { |
3095 | tcg_gen_movi_i32(cpu_pc, dc.pc); | |
3096 | gen_exception(&dc, EXCP_DEBUG); | |
3097 | dc.is_jmp = DISAS_UPDATE; | |
522a0d4e RH |
3098 | /* The address covered by the breakpoint must be included in |
3099 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
3100 | properly cleared -- thus we increment the PC here so that | |
3101 | the logic setting tb->size below does the right thing. */ | |
3102 | dc.pc += 2; | |
b933066a RH |
3103 | break; |
3104 | } | |
3105 | ||
959082fc | 3106 | if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) { |
b994e91b MF |
3107 | gen_io_start(); |
3108 | } | |
3109 | ||
35b5c044 | 3110 | if (dc.icount) { |
42a268c2 | 3111 | TCGLabel *label = gen_new_label(); |
35b5c044 MF |
3112 | |
3113 | tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1); | |
3114 | tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label); | |
3115 | tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); | |
3116 | if (dc.debug) { | |
3117 | gen_debug_exception(&dc, DEBUGCAUSE_IC); | |
3118 | } | |
3119 | gen_set_label(label); | |
3120 | } | |
3121 | ||
e61dc8f7 MF |
3122 | if (dc.debug) { |
3123 | gen_ibreak_check(env, &dc); | |
3124 | } | |
3125 | ||
0c4fabea | 3126 | disas_xtensa_insn(env, &dc); |
35b5c044 MF |
3127 | if (dc.icount) { |
3128 | tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); | |
3129 | } | |
ed2803da | 3130 | if (cs->singlestep_enabled) { |
dedc5eae | 3131 | tcg_gen_movi_i32(cpu_pc, dc.pc); |
b994e91b | 3132 | gen_exception(&dc, EXCP_DEBUG); |
dedc5eae MF |
3133 | break; |
3134 | } | |
3135 | } while (dc.is_jmp == DISAS_NEXT && | |
3136 | insn_count < max_insns && | |
3137 | dc.pc < next_page_start && | |
01673a34 | 3138 | dc.pc + xtensa_insn_len(env, &dc) <= next_page_start && |
fe700adb | 3139 | !tcg_op_buf_full()); |
dedc5eae | 3140 | |
6ad6dbf7 | 3141 | reset_litbase(&dc); |
3580ecad | 3142 | reset_sar_tracker(&dc); |
35b5c044 MF |
3143 | if (dc.icount) { |
3144 | tcg_temp_free(dc.next_icount); | |
3145 | } | |
3580ecad | 3146 | |
b994e91b MF |
3147 | if (tb->cflags & CF_LAST_IO) { |
3148 | gen_io_end(); | |
3149 | } | |
3150 | ||
dedc5eae MF |
3151 | if (dc.is_jmp == DISAS_NEXT) { |
3152 | gen_jumpi(&dc, dc.pc, 0); | |
3153 | } | |
806f352d | 3154 | gen_tb_end(tb, insn_count); |
dedc5eae | 3155 | |
ca529f8e | 3156 | #ifdef DEBUG_DISAS |
4910e6e4 RH |
3157 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
3158 | && qemu_log_in_addr_range(pc_start)) { | |
ca529f8e MF |
3159 | qemu_log("----------------\n"); |
3160 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 3161 | log_target_disas(cs, pc_start, dc.pc - pc_start, 0); |
ca529f8e MF |
3162 | qemu_log("\n"); |
3163 | } | |
3164 | #endif | |
4e5e1215 RH |
3165 | tb->size = dc.pc - pc_start; |
3166 | tb->icount = insn_count; | |
2328826b MF |
3167 | } |
3168 | ||
878096ee AF |
3169 | void xtensa_cpu_dump_state(CPUState *cs, FILE *f, |
3170 | fprintf_function cpu_fprintf, int flags) | |
2328826b | 3171 | { |
878096ee AF |
3172 | XtensaCPU *cpu = XTENSA_CPU(cs); |
3173 | CPUXtensaState *env = &cpu->env; | |
2af3da91 MF |
3174 | int i, j; |
3175 | ||
3176 | cpu_fprintf(f, "PC=%08x\n\n", env->pc); | |
3177 | ||
3178 | for (i = j = 0; i < 256; ++i) { | |
fe0bd475 MF |
3179 | if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) { |
3180 | cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i], | |
2af3da91 MF |
3181 | (j++ % 4) == 3 ? '\n' : ' '); |
3182 | } | |
3183 | } | |
3184 | ||
3185 | cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); | |
3186 | ||
3187 | for (i = j = 0; i < 256; ++i) { | |
fe0bd475 MF |
3188 | if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) { |
3189 | cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i], | |
2af3da91 MF |
3190 | (j++ % 4) == 3 ? '\n' : ' '); |
3191 | } | |
3192 | } | |
2328826b | 3193 | |
2af3da91 | 3194 | cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); |
2328826b MF |
3195 | |
3196 | for (i = 0; i < 16; ++i) { | |
fe0bd475 | 3197 | cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i], |
2328826b MF |
3198 | (i % 4) == 3 ? '\n' : ' '); |
3199 | } | |
553e44f9 MF |
3200 | |
3201 | cpu_fprintf(f, "\n"); | |
3202 | ||
3203 | for (i = 0; i < env->config->nareg; ++i) { | |
3204 | cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i], | |
3205 | (i % 4) == 3 ? '\n' : ' '); | |
3206 | } | |
dd519cbe MF |
3207 | |
3208 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { | |
3209 | cpu_fprintf(f, "\n"); | |
3210 | ||
3211 | for (i = 0; i < 16; ++i) { | |
3212 | cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, | |
ddd44279 MF |
3213 | float32_val(env->fregs[i].f32[FP_F32_LOW]), |
3214 | *(float *)(env->fregs[i].f32 + FP_F32_LOW), | |
3215 | (i % 2) == 1 ? '\n' : ' '); | |
dd519cbe MF |
3216 | } |
3217 | } | |
2328826b MF |
3218 | } |
3219 | ||
bad729e2 RH |
3220 | void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, |
3221 | target_ulong *data) | |
2328826b | 3222 | { |
bad729e2 | 3223 | env->pc = data[0]; |
2328826b | 3224 | } |