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tcg: Invert the inclusion of helper.h
[mirror_qemu.git] / target-xtensa / translate.c
CommitLineData
2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
022c62cb 34#include "exec/exec-all.h"
76cad711 35#include "disas/disas.h"
2328826b 36#include "tcg-op.h"
1de7afc9 37#include "qemu/log.h"
9c17d615 38#include "sysemu/sysemu.h"
2328826b 39
2ef6175a
RH		 40#include "exec/helper-proto.h"
41#include "exec/helper-gen.h"
dedc5eae
MF		 42
43typedef struct DisasContext {
44 const XtensaConfig *config;
45 TranslationBlock *tb;
46 uint32_t pc;
47 uint32_t next_pc;
f0a548b9
MF		 48 int cring;
49 int ring;
797d780b
MF		 50 uint32_t lbeg;
51 uint32_t lend;
6ad6dbf7 52 TCGv_i32 litbase;
dedc5eae
MF		 53 int is_jmp;
54 int singlestep_enabled;
3580ecad
MF		 55
56 bool sar_5bit;
57 bool sar_m32_5bit;
58 bool sar_m32_allocated;
59 TCGv_i32 sar_m32;
b994e91b
MF		 60
61 uint32_t ccount_delta;
772177c1 62 unsigned used_window;
e61dc8f7
MF		 63
64 bool debug;
35b5c044
MF		 65 bool icount;
66 TCGv_i32 next_icount;
ef04a846
MF		 67
68 unsigned cpenable;
dedc5eae
MF		 69} DisasContext;
70
71static TCGv_ptr cpu_env;
72static TCGv_i32 cpu_pc;
73static TCGv_i32 cpu_R[16];
dd519cbe 74static TCGv_i32 cpu_FR[16];
2af3da91
MF		 75static TCGv_i32 cpu_SR[256];
76static TCGv_i32 cpu_UR[256];
dedc5eae 77
022c62cb 78#include "exec/gen-icount.h"
2328826b 79
fe0bd475
MF		 80typedef struct XtensaReg {
81 const char *name;
82 uint64_t opt_bits;
53593e90
MF		 83 enum {
84 SR_R = 1,
85 SR_W = 2,
86 SR_X = 4,
87 SR_RW = 3,
88 SR_RWX = 7,
89 } access;
fe0bd475
MF		 90} XtensaReg;
91
53593e90 92#define XTENSA_REG_ACCESS(regname, opt, acc) { \
fe0bd475
MF		 93 .name = (regname), \
94 .opt_bits = XTENSA_OPTION_BIT(opt), \
53593e90 95 .access = (acc), \
fe0bd475
MF		 96 }
97
53593e90
MF		 98#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
99
604e1f9c 100#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
fe0bd475
MF		 101 .name = (regname), \
102 .opt_bits = (opt), \
604e1f9c 103 .access = (acc), \
fe0bd475
MF		 104 }
105
604e1f9c
MF		 106#define XTENSA_REG_BITS(regname, opt) \
107 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
108
fe0bd475
MF		 109static const XtensaReg sregnames[256] = {
110 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
111 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
112 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
113 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
114 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
115 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
116 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
117 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
118 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
119 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
120 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
121 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
122 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
123 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
124 [WINDOW_START] = XTENSA_REG("WINDOW_START",
125 XTENSA_OPTION_WINDOWED_REGISTER),
126 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
127 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
128 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
129 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
130 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
131 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
132 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
133 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
134 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
135 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
136 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
137 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
138 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
604e1f9c 139 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
fe0bd475
MF		 140 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
141 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
142 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
143 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
144 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
145 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
146 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
147 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
148 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
152 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
153 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
604e1f9c 154 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
fe0bd475
MF		 155 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
156 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
157 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
159 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
160 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
161 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
162 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
163 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
164 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
165 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
166 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
167 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
168 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
53593e90
MF		 169 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
170 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
fe0bd475
MF		 171 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
172 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
173 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
174 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
53593e90 175 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
fe0bd475 176 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
53593e90 177 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
fe0bd475
MF		 178 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
179 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
180 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
181 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
182 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
183 XTENSA_OPTION_TIMER_INTERRUPT),
184 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
185 XTENSA_OPTION_TIMER_INTERRUPT),
b7909d81
MF		 186 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
187 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
188 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
189 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
2af3da91
MF		 190};
191
fe0bd475
MF		 192static const XtensaReg uregnames[256] = {
193 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
194 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
195 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
2af3da91
MF		 196};
197
2328826b
MF		 198void xtensa_translate_init(void)
199{
dedc5eae
MF		 200 static const char * const regnames[] = {
201 "ar0", "ar1", "ar2", "ar3",
202 "ar4", "ar5", "ar6", "ar7",
203 "ar8", "ar9", "ar10", "ar11",
204 "ar12", "ar13", "ar14", "ar15",
205 };
dd519cbe
MF		 206 static const char * const fregnames[] = {
207 "f0", "f1", "f2", "f3",
208 "f4", "f5", "f6", "f7",
209 "f8", "f9", "f10", "f11",
210 "f12", "f13", "f14", "f15",
211 };
dedc5eae
MF		 212 int i;
213
214 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
215 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 216 offsetof(CPUXtensaState, pc), "pc");
dedc5eae
MF		 217
218 for (i = 0; i < 16; i++) {
219 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 220 offsetof(CPUXtensaState, regs[i]),
dedc5eae
MF		 221 regnames[i]);
222 }
2af3da91 223
dd519cbe
MF		 224 for (i = 0; i < 16; i++) {
225 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
226 offsetof(CPUXtensaState, fregs[i]),
227 fregnames[i]);
228 }
229
2af3da91 230 for (i = 0; i < 256; ++i) {
fe0bd475 231 if (sregnames[i].name) {
2af3da91 232 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 233 offsetof(CPUXtensaState, sregs[i]),
fe0bd475 234 sregnames[i].name);
2af3da91
MF		 235 }
236 }
237
238 for (i = 0; i < 256; ++i) {
fe0bd475 239 if (uregnames[i].name) {
2af3da91 240 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 241 offsetof(CPUXtensaState, uregs[i]),
fe0bd475 242 uregnames[i].name);
2af3da91
MF		 243 }
244 }
dedc5eae
MF		 245}
246
b67ea0cd
MF		 247static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
248{
249 return xtensa_option_bits_enabled(dc->config, opt);
250}
251
dedc5eae
MF		 252static inline bool option_enabled(DisasContext *dc, int opt)
253{
254 return xtensa_option_enabled(dc->config, opt);
255}
256
6ad6dbf7
MF		 257static void init_litbase(DisasContext *dc)
258{
259 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
260 dc->litbase = tcg_temp_local_new_i32();
261 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
262 }
263}
264
265static void reset_litbase(DisasContext *dc)
266{
267 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
268 tcg_temp_free(dc->litbase);
269 }
270}
271
3580ecad
MF		 272static void init_sar_tracker(DisasContext *dc)
273{
274 dc->sar_5bit = false;
275 dc->sar_m32_5bit = false;
276 dc->sar_m32_allocated = false;
277}
278
279static void reset_sar_tracker(DisasContext *dc)
280{
281 if (dc->sar_m32_allocated) {
282 tcg_temp_free(dc->sar_m32);
283 }
284}
285
286static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
287{
288 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
289 if (dc->sar_m32_5bit) {
290 tcg_gen_discard_i32(dc->sar_m32);
291 }
292 dc->sar_5bit = true;
293 dc->sar_m32_5bit = false;
294}
295
296static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
297{
298 TCGv_i32 tmp = tcg_const_i32(32);
299 if (!dc->sar_m32_allocated) {
300 dc->sar_m32 = tcg_temp_local_new_i32();
301 dc->sar_m32_allocated = true;
302 }
303 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
304 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
305 dc->sar_5bit = false;
306 dc->sar_m32_5bit = true;
307 tcg_temp_free(tmp);
308}
309
908c67fc 310static void gen_advance_ccount_cond(DisasContext *dc)
b994e91b
MF		 311{
312 if (dc->ccount_delta > 0) {
313 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
f492b82d 314 gen_helper_advance_ccount(cpu_env, tmp);
b994e91b
MF		 315 tcg_temp_free(tmp);
316 }
317}
318
908c67fc
MF		 319static void gen_advance_ccount(DisasContext *dc)
320{
321 gen_advance_ccount_cond(dc);
322 dc->ccount_delta = 0;
323}
324
772177c1
MF		 325static void reset_used_window(DisasContext *dc)
326{
327 dc->used_window = 0;
328}
329
b994e91b 330static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 331{
332 TCGv_i32 tmp = tcg_const_i32(excp);
b994e91b 333 gen_advance_ccount(dc);
f492b82d 334 gen_helper_exception(cpu_env, tmp);
dedc5eae
MF		 335 tcg_temp_free(tmp);
336}
337
40643d7c
MF		 338static void gen_exception_cause(DisasContext *dc, uint32_t cause)
339{
340 TCGv_i32 tpc = tcg_const_i32(dc->pc);
341 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 342 gen_advance_ccount(dc);
f492b82d 343 gen_helper_exception_cause(cpu_env, tpc, tcause);
40643d7c
MF		 344 tcg_temp_free(tpc);
345 tcg_temp_free(tcause);
6b814719
MF		 346 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
347 cause == SYSCALL_CAUSE) {
348 dc->is_jmp = DISAS_UPDATE;
349 }
40643d7c
MF		 350}
351
5b4e481b
MF		 352static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
353 TCGv_i32 vaddr)
354{
355 TCGv_i32 tpc = tcg_const_i32(dc->pc);
356 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 357 gen_advance_ccount(dc);
f492b82d 358 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
5b4e481b
MF		 359 tcg_temp_free(tpc);
360 tcg_temp_free(tcause);
361}
362
e61dc8f7
MF		 363static void gen_debug_exception(DisasContext *dc, uint32_t cause)
364{
365 TCGv_i32 tpc = tcg_const_i32(dc->pc);
366 TCGv_i32 tcause = tcg_const_i32(cause);
367 gen_advance_ccount(dc);
f492b82d 368 gen_helper_debug_exception(cpu_env, tpc, tcause);
e61dc8f7
MF		 369 tcg_temp_free(tpc);
370 tcg_temp_free(tcause);
371 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
372 dc->is_jmp = DISAS_UPDATE;
373 }
374}
375
40643d7c
MF		 376static void gen_check_privilege(DisasContext *dc)
377{
378 if (dc->cring) {
379 gen_exception_cause(dc, PRIVILEGED_CAUSE);
6b814719 380 dc->is_jmp = DISAS_UPDATE;
40643d7c
MF		 381 }
382}
383
ef04a846
MF		 384static void gen_check_cpenable(DisasContext *dc, unsigned cp)
385{
386 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
387 !(dc->cpenable & (1 << cp))) {
388 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
389 dc->is_jmp = DISAS_UPDATE;
390 }
391}
392
dedc5eae
MF		 393static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
394{
395 tcg_gen_mov_i32(cpu_pc, dest);
35b5c044
MF		 396 gen_advance_ccount(dc);
397 if (dc->icount) {
398 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
399 }
dedc5eae 400 if (dc->singlestep_enabled) {
b994e91b 401 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 402 } else {
403 if (slot >= 0) {
404 tcg_gen_goto_tb(slot);
8cfd0495 405 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
dedc5eae
MF		 406 } else {
407 tcg_gen_exit_tb(0);
408 }
409 }
410 dc->is_jmp = DISAS_UPDATE;
411}
412
67882fd1
MF		 413static void gen_jump(DisasContext *dc, TCGv dest)
414{
415 gen_jump_slot(dc, dest, -1);
416}
417
dedc5eae
MF		 418static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
419{
420 TCGv_i32 tmp = tcg_const_i32(dest);
433d33c5 421 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
dedc5eae
MF		 422 slot = -1;
423 }
424 gen_jump_slot(dc, tmp, slot);
425 tcg_temp_free(tmp);
426}
427
553e44f9
MF		 428static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
429 int slot)
430{
431 TCGv_i32 tcallinc = tcg_const_i32(callinc);
432
433 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
434 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
435 tcg_temp_free(tcallinc);
436 tcg_gen_movi_i32(cpu_R[callinc << 2],
437 (callinc << 30) | (dc->next_pc & 0x3fffffff));
438 gen_jump_slot(dc, dest, slot);
439}
440
441static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
442{
443 gen_callw_slot(dc, callinc, dest, -1);
444}
445
446static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
447{
448 TCGv_i32 tmp = tcg_const_i32(dest);
433d33c5 449 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
553e44f9
MF		 450 slot = -1;
451 }
452 gen_callw_slot(dc, callinc, tmp, slot);
453 tcg_temp_free(tmp);
454}
455
797d780b
MF		 456static bool gen_check_loop_end(DisasContext *dc, int slot)
457{
458 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
459 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
460 dc->next_pc == dc->lend) {
461 int label = gen_new_label();
462
d865f307 463 gen_advance_ccount(dc);
797d780b
MF		 464 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
465 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
466 gen_jumpi(dc, dc->lbeg, slot);
467 gen_set_label(label);
468 gen_jumpi(dc, dc->next_pc, -1);
469 return true;
470 }
471 return false;
472}
473
474static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
475{
476 if (!gen_check_loop_end(dc, slot)) {
477 gen_jumpi(dc, dc->next_pc, slot);
478 }
479}
480
bd57fb91
MF		 481static void gen_brcond(DisasContext *dc, TCGCond cond,
482 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
483{
484 int label = gen_new_label();
485
d865f307 486 gen_advance_ccount(dc);
bd57fb91 487 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 488 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 489 gen_set_label(label);
490 gen_jumpi(dc, dc->pc + offset, 1);
491}
492
493static void gen_brcondi(DisasContext *dc, TCGCond cond,
494 TCGv_i32 t0, uint32_t t1, uint32_t offset)
495{
496 TCGv_i32 tmp = tcg_const_i32(t1);
497 gen_brcond(dc, cond, t0, tmp, offset);
498 tcg_temp_free(tmp);
499}
500
0857a06e 501static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
fe0bd475
MF		 502{
503 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
504 if (sregnames[sr].name) {
505 qemu_log("SR %s is not configured\n", sregnames[sr].name);
506 } else {
507 qemu_log("SR %d is not implemented\n", sr);
508 }
509 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
0857a06e 510 return false;
53593e90
MF		 511 } else if (!(sregnames[sr].access & access)) {
512 static const char * const access_text[] = {
513 [SR_R] = "rsr",
514 [SR_W] = "wsr",
515 [SR_X] = "xsr",
516 };
517 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
518 qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
519 access_text[access]);
520 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
0857a06e 521 return false;
fe0bd475 522 }
0857a06e 523 return true;
fe0bd475
MF		 524}
525
b994e91b
MF		 526static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
527{
528 gen_advance_ccount(dc);
529 tcg_gen_mov_i32(d, cpu_SR[sr]);
530}
531
b67ea0cd
MF		 532static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
533{
534 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
535 tcg_gen_or_i32(d, d, cpu_SR[sr]);
536 tcg_gen_andi_i32(d, d, 0xfffffffc);
537}
538
b8132eff
MF		 539static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
540{
541 static void (* const rsr_handler[256])(DisasContext *dc,
542 TCGv_i32 d, uint32_t sr) = {
b994e91b 543 [CCOUNT] = gen_rsr_ccount,
b67ea0cd 544 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 545 };
546
fe0bd475
MF		 547 if (rsr_handler[sr]) {
548 rsr_handler[sr](dc, d, sr);
b8132eff 549 } else {
fe0bd475 550 tcg_gen_mov_i32(d, cpu_SR[sr]);
b8132eff
MF		 551 }
552}
553
797d780b
MF		 554static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
555{
f492b82d 556 gen_helper_wsr_lbeg(cpu_env, s);
3d0be8a5 557 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 558}
559
560static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
561{
f492b82d 562 gen_helper_wsr_lend(cpu_env, s);
3d0be8a5 563 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 564}
565
3580ecad
MF		 566static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
567{
568 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
569 if (dc->sar_m32_5bit) {
570 tcg_gen_discard_i32(dc->sar_m32);
571 }
572 dc->sar_5bit = false;
573 dc->sar_m32_5bit = false;
574}
575
4dd85b6b
MF		 576static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
577{
578 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
579}
580
6ad6dbf7
MF		 581static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
582{
583 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
584 /* This can change tb->flags, so exit tb */
585 gen_jumpi_check_loop_end(dc, -1);
586}
587
6825b6c3
MF		 588static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
589{
590 tcg_gen_ext8s_i32(cpu_SR[sr], s);
591}
592
553e44f9
MF		 593static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
594{
f492b82d 595 gen_helper_wsr_windowbase(cpu_env, v);
772177c1
MF		 596 reset_used_window(dc);
597}
598
599static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
600{
53a72dfd 601 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
772177c1 602 reset_used_window(dc);
553e44f9
MF		 603}
604
b67ea0cd
MF		 605static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
606{
607 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
608}
609
610static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
611{
f492b82d 612 gen_helper_wsr_rasid(cpu_env, v);
b67ea0cd
MF		 613 /* This can change tb->flags, so exit tb */
614 gen_jumpi_check_loop_end(dc, -1);
615}
616
617static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
618{
619 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
620}
621
e61dc8f7
MF		 622static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
623{
f492b82d 624 gen_helper_wsr_ibreakenable(cpu_env, v);
e61dc8f7
MF		 625 gen_jumpi_check_loop_end(dc, 0);
626}
627
fcc803d1
MF		 628static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
629{
630 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
631}
632
e61dc8f7
MF		 633static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
634{
635 unsigned id = sr - IBREAKA;
636
637 if (id < dc->config->nibreak) {
638 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 639 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
e61dc8f7
MF		 640 tcg_temp_free(tmp);
641 gen_jumpi_check_loop_end(dc, 0);
642 }
643}
644
f14c4b5f
MF		 645static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
646{
647 unsigned id = sr - DBREAKA;
648
649 if (id < dc->config->ndbreak) {
650 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 651 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
f14c4b5f
MF		 652 tcg_temp_free(tmp);
653 }
654}
655
656static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
657{
658 unsigned id = sr - DBREAKC;
659
660 if (id < dc->config->ndbreak) {
661 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 662 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
f14c4b5f
MF		 663 tcg_temp_free(tmp);
664 }
665}
666
ef04a846
MF		 667static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
668{
669 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
670 /* This can change tb->flags, so exit tb */
671 gen_jumpi_check_loop_end(dc, -1);
672}
673
b994e91b
MF		 674static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
675{
676 tcg_gen_andi_i32(cpu_SR[sr], v,
677 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
678 gen_helper_check_interrupts(cpu_env);
679 gen_jumpi_check_loop_end(dc, 0);
680}
681
682static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
683{
684 TCGv_i32 tmp = tcg_temp_new_i32();
685
686 tcg_gen_andi_i32(tmp, v,
687 dc->config->inttype_mask[INTTYPE_EDGE] |
688 dc->config->inttype_mask[INTTYPE_NMI] |
689 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
690 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
691 tcg_temp_free(tmp);
692 gen_helper_check_interrupts(cpu_env);
693}
694
695static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
696{
697 tcg_gen_mov_i32(cpu_SR[sr], v);
698 gen_helper_check_interrupts(cpu_env);
699 gen_jumpi_check_loop_end(dc, 0);
700}
701
f0a548b9
MF		 702static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
703{
704 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
705 PS_UM | PS_EXCM | PS_INTLEVEL;
706
707 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
708 mask |= PS_RING;
709 }
710 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
772177c1 711 reset_used_window(dc);
b994e91b
MF		 712 gen_helper_check_interrupts(cpu_env);
713 /* This can change mmu index and tb->flags, so exit tb */
797d780b 714 gen_jumpi_check_loop_end(dc, -1);
f0a548b9
MF		 715}
716
35b5c044
MF		 717static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
718{
719 if (dc->icount) {
720 tcg_gen_mov_i32(dc->next_icount, v);
721 } else {
722 tcg_gen_mov_i32(cpu_SR[sr], v);
723 }
724}
725
726static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
727{
728 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
729 /* This can change tb->flags, so exit tb */
730 gen_jumpi_check_loop_end(dc, -1);
731}
732
b994e91b
MF		 733static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
734{
735 uint32_t id = sr - CCOMPARE;
736 if (id < dc->config->nccompare) {
737 uint32_t int_bit = 1 << dc->config->timerint[id];
738 gen_advance_ccount(dc);
739 tcg_gen_mov_i32(cpu_SR[sr], v);
740 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
741 gen_helper_check_interrupts(cpu_env);
742 }
743}
744
b8132eff
MF		 745static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
746{
747 static void (* const wsr_handler[256])(DisasContext *dc,
748 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 749 [LBEG] = gen_wsr_lbeg,
750 [LEND] = gen_wsr_lend,
3580ecad 751 [SAR] = gen_wsr_sar,
4dd85b6b 752 [BR] = gen_wsr_br,
6ad6dbf7 753 [LITBASE] = gen_wsr_litbase,
6825b6c3 754 [ACCHI] = gen_wsr_acchi,
553e44f9 755 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 756 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 757 [PTEVADDR] = gen_wsr_ptevaddr,
758 [RASID] = gen_wsr_rasid,
759 [ITLBCFG] = gen_wsr_tlbcfg,
760 [DTLBCFG] = gen_wsr_tlbcfg,
e61dc8f7 761 [IBREAKENABLE] = gen_wsr_ibreakenable,
fcc803d1 762 [ATOMCTL] = gen_wsr_atomctl,
e61dc8f7
MF		 763 [IBREAKA] = gen_wsr_ibreaka,
764 [IBREAKA + 1] = gen_wsr_ibreaka,
f14c4b5f
MF		 765 [DBREAKA] = gen_wsr_dbreaka,
766 [DBREAKA + 1] = gen_wsr_dbreaka,
767 [DBREAKC] = gen_wsr_dbreakc,
768 [DBREAKC + 1] = gen_wsr_dbreakc,
ef04a846 769 [CPENABLE] = gen_wsr_cpenable,
b994e91b
MF		 770 [INTSET] = gen_wsr_intset,
771 [INTCLEAR] = gen_wsr_intclear,
772 [INTENABLE] = gen_wsr_intenable,
f0a548b9 773 [PS] = gen_wsr_ps,
35b5c044
MF		 774 [ICOUNT] = gen_wsr_icount,
775 [ICOUNTLEVEL] = gen_wsr_icountlevel,
b994e91b
MF		 776 [CCOMPARE] = gen_wsr_ccompare,
777 [CCOMPARE + 1] = gen_wsr_ccompare,
778 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 779 };
780
fe0bd475
MF		 781 if (wsr_handler[sr]) {
782 wsr_handler[sr](dc, sr, s);
b8132eff 783 } else {
fe0bd475 784 tcg_gen_mov_i32(cpu_SR[sr], s);
b8132eff
MF		 785 }
786}
787
dd519cbe
MF		 788static void gen_wur(uint32_t ur, TCGv_i32 s)
789{
790 switch (ur) {
791 case FCR:
792 gen_helper_wur_fcr(cpu_env, s);
793 break;
794
795 case FSR:
796 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
797 break;
798
799 default:
800 tcg_gen_mov_i32(cpu_UR[ur], s);
801 break;
802 }
803}
804
5b4e481b
MF		 805static void gen_load_store_alignment(DisasContext *dc, int shift,
806 TCGv_i32 addr, bool no_hw_alignment)
807{
808 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
809 tcg_gen_andi_i32(addr, addr, ~0 << shift);
810 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
811 no_hw_alignment) {
812 int label = gen_new_label();
813 TCGv_i32 tmp = tcg_temp_new_i32();
814 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
815 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
816 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
817 gen_set_label(label);
818 tcg_temp_free(tmp);
819 }
820}
821
b994e91b
MF		 822static void gen_waiti(DisasContext *dc, uint32_t imm4)
823{
824 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
825 TCGv_i32 intlevel = tcg_const_i32(imm4);
826 gen_advance_ccount(dc);
f492b82d 827 gen_helper_waiti(cpu_env, pc, intlevel);
b994e91b
MF		 828 tcg_temp_free(pc);
829 tcg_temp_free(intlevel);
830}
831
772177c1
MF		 832static void gen_window_check1(DisasContext *dc, unsigned r1)
833{
834 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
835 return;
836 }
837 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
838 r1 / 4 > dc->used_window) {
908c67fc
MF		 839 int label = gen_new_label();
840 TCGv_i32 ws = tcg_temp_new_i32();
772177c1
MF		 841
842 dc->used_window = r1 / 4;
908c67fc
MF		 843 tcg_gen_deposit_i32(ws, cpu_SR[WINDOW_START], cpu_SR[WINDOW_START],
844 dc->config->nareg / 4, dc->config->nareg / 4);
845 tcg_gen_shr_i32(ws, ws, cpu_SR[WINDOW_BASE]);
846 tcg_gen_andi_i32(ws, ws, (2 << (r1 / 4)) - 2);
847 tcg_gen_brcondi_i32(TCG_COND_EQ, ws, 0, label);
848 {
849 TCGv_i32 pc = tcg_const_i32(dc->pc);
850 TCGv_i32 w = tcg_const_i32(r1 / 4);
851
852 gen_advance_ccount_cond(dc);
853 gen_helper_window_check(cpu_env, pc, w);
854
855 tcg_temp_free(w);
856 tcg_temp_free(pc);
857 }
858 gen_set_label(label);
859 tcg_temp_free(ws);
772177c1
MF		 860 }
861}
862
863static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
864{
865 gen_window_check1(dc, r1 > r2 ? r1 : r2);
866}
867
868static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
869 unsigned r3)
870{
871 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
872}
873
6825b6c3
MF		 874static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
875{
876 TCGv_i32 m = tcg_temp_new_i32();
877
878 if (hi) {
879 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
880 } else {
881 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
882 }
883 return m;
884}
885
0c4fabea 886static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
dedc5eae 887{
b67ea0cd
MF		 888#define HAS_OPTION_BITS(opt) do { \
889 if (!option_bits_enabled(dc, opt)) { \
890 qemu_log("Option is not enabled %s:%d\n", \
891 __FILE__, __LINE__); \
dedc5eae
MF		 892 goto invalid_opcode; \
893 } \
894 } while (0)
895
b67ea0cd
MF		 896#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
897
91a5bb76
MF		 898#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
899#define RESERVED() do { \
900 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
901 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
902 goto invalid_opcode; \
903 } while (0)
904
905
dedc5eae
MF		 906#ifdef TARGET_WORDS_BIGENDIAN
907#define OP0 (((b0) & 0xf0) >> 4)
908#define OP1 (((b2) & 0xf0) >> 4)
909#define OP2 ((b2) & 0xf)
910#define RRR_R ((b1) & 0xf)
911#define RRR_S (((b1) & 0xf0) >> 4)
912#define RRR_T ((b0) & 0xf)
913#else
914#define OP0 (((b0) & 0xf))
915#define OP1 (((b2) & 0xf))
916#define OP2 (((b2) & 0xf0) >> 4)
917#define RRR_R (((b1) & 0xf0) >> 4)
918#define RRR_S (((b1) & 0xf))
919#define RRR_T (((b0) & 0xf0) >> 4)
920#endif
6825b6c3
MF		 921#define RRR_X ((RRR_R & 0x4) >> 2)
922#define RRR_Y ((RRR_T & 0x4) >> 2)
923#define RRR_W (RRR_R & 0x3)
dedc5eae
MF		 924
925#define RRRN_R RRR_R
926#define RRRN_S RRR_S
927#define RRRN_T RRR_T
928
65026682
MF		 929#define RRI4_R RRR_R
930#define RRI4_S RRR_S
931#define RRI4_T RRR_T
932#ifdef TARGET_WORDS_BIGENDIAN
933#define RRI4_IMM4 ((b2) & 0xf)
934#else
935#define RRI4_IMM4 (((b2) & 0xf0) >> 4)
936#endif
937
dedc5eae
MF		 938#define RRI8_R RRR_R
939#define RRI8_S RRR_S
940#define RRI8_T RRR_T
941#define RRI8_IMM8 (b2)
942#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
943
944#ifdef TARGET_WORDS_BIGENDIAN
945#define RI16_IMM16 (((b1) << 8) | (b2))
946#else
947#define RI16_IMM16 (((b2) << 8) | (b1))
948#endif
949
950#ifdef TARGET_WORDS_BIGENDIAN
951#define CALL_N (((b0) & 0xc) >> 2)
952#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
953#else
954#define CALL_N (((b0) & 0x30) >> 4)
955#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
956#endif
957#define CALL_OFFSET_SE \
958 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
959
960#define CALLX_N CALL_N
961#ifdef TARGET_WORDS_BIGENDIAN
962#define CALLX_M ((b0) & 0x3)
963#else
964#define CALLX_M (((b0) & 0xc0) >> 6)
965#endif
966#define CALLX_S RRR_S
967
968#define BRI12_M CALLX_M
969#define BRI12_S RRR_S
970#ifdef TARGET_WORDS_BIGENDIAN
971#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
972#else
973#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
974#endif
975#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
976
977#define BRI8_M BRI12_M
978#define BRI8_R RRI8_R
979#define BRI8_S RRI8_S
980#define BRI8_IMM8 RRI8_IMM8
981#define BRI8_IMM8_SE RRI8_IMM8_SE
982
983#define RSR_SR (b1)
984
0c4fabea
BS		 985 uint8_t b0 = cpu_ldub_code(env, dc->pc);
986 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
a044ec2a 987 uint8_t b2 = 0;
dedc5eae 988
bd57fb91
MF		 989 static const uint32_t B4CONST[] = {
990 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
991 };
992
993 static const uint32_t B4CONSTU[] = {
994 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
995 };
996
dedc5eae
MF		 997 if (OP0 >= 8) {
998 dc->next_pc = dc->pc + 2;
999 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
1000 } else {
1001 dc->next_pc = dc->pc + 3;
0c4fabea 1002 b2 = cpu_ldub_code(env, dc->pc + 2);
dedc5eae
MF		 1003 }
1004
1005 switch (OP0) {
1006 case 0: /*QRST*/
1007 switch (OP1) {
1008 case 0: /*RST0*/
1009 switch (OP2) {
1010 case 0: /*ST0*/
1011 if ((RRR_R & 0xc) == 0x8) {
1012 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1013 }
1014
1015 switch (RRR_R) {
1016 case 0: /*SNM0*/
5da4a6a8
MF		 1017 switch (CALLX_M) {
1018 case 0: /*ILL*/
40643d7c 1019 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 1020 break;
1021
1022 case 1: /*reserved*/
91a5bb76 1023 RESERVED();
5da4a6a8
MF		 1024 break;
1025
1026 case 2: /*JR*/
1027 switch (CALLX_N) {
1028 case 0: /*RET*/
1029 case 2: /*JX*/
772177c1 1030 gen_window_check1(dc, CALLX_S);
5da4a6a8
MF		 1031 gen_jump(dc, cpu_R[CALLX_S]);
1032 break;
1033
1034 case 1: /*RETWw*/
1035 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1036 {
1037 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 1038 gen_advance_ccount(dc);
f492b82d 1039 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 1040 gen_jump(dc, tmp);
1041 tcg_temp_free(tmp);
1042 }
5da4a6a8
MF		 1043 break;
1044
1045 case 3: /*reserved*/
91a5bb76 1046 RESERVED();
5da4a6a8
MF		 1047 break;
1048 }
1049 break;
1050
1051 case 3: /*CALLX*/
772177c1 1052 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
5da4a6a8
MF		 1053 switch (CALLX_N) {
1054 case 0: /*CALLX0*/
1055 {
1056 TCGv_i32 tmp = tcg_temp_new_i32();
1057 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1058 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1059 gen_jump(dc, tmp);
1060 tcg_temp_free(tmp);
1061 }
1062 break;
1063
1064 case 1: /*CALLX4w*/
1065 case 2: /*CALLX8w*/
1066 case 3: /*CALLX12w*/
1067 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1068 {
1069 TCGv_i32 tmp = tcg_temp_new_i32();
1070
1071 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1072 gen_callw(dc, CALLX_N, tmp);
1073 tcg_temp_free(tmp);
1074 }
5da4a6a8
MF		 1075 break;
1076 }
1077 break;
1078 }
dedc5eae
MF		 1079 break;
1080
1081 case 1: /*MOVSPw*/
1082 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 1083 gen_window_check2(dc, RRR_T, RRR_S);
553e44f9
MF		 1084 {
1085 TCGv_i32 pc = tcg_const_i32(dc->pc);
b994e91b 1086 gen_advance_ccount(dc);
f492b82d 1087 gen_helper_movsp(cpu_env, pc);
553e44f9
MF		 1088 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1089 tcg_temp_free(pc);
1090 }
dedc5eae
MF		 1091 break;
1092
1093 case 2: /*SYNC*/
28067b22
MF		 1094 switch (RRR_T) {
1095 case 0: /*ISYNC*/
1096 break;
1097
1098 case 1: /*RSYNC*/
1099 break;
1100
1101 case 2: /*ESYNC*/
1102 break;
1103
1104 case 3: /*DSYNC*/
1105 break;
1106
1107 case 8: /*EXCW*/
1108 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1109 break;
1110
1111 case 12: /*MEMW*/
1112 break;
1113
1114 case 13: /*EXTW*/
1115 break;
1116
1117 case 15: /*NOP*/
1118 break;
1119
1120 default: /*reserved*/
1121 RESERVED();
1122 break;
1123 }
91a5bb76
MF		 1124 break;
1125
1126 case 3: /*RFEIx*/
40643d7c
MF		 1127 switch (RRR_T) {
1128 case 0: /*RFETx*/
1129 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1130 switch (RRR_S) {
1131 case 0: /*RFEx*/
1132 gen_check_privilege(dc);
1133 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
b994e91b 1134 gen_helper_check_interrupts(cpu_env);
40643d7c
MF		 1135 gen_jump(dc, cpu_SR[EPC1]);
1136 break;
1137
1138 case 1: /*RFUEx*/
1139 RESERVED();
1140 break;
1141
1142 case 2: /*RFDEx*/
1143 gen_check_privilege(dc);
1144 gen_jump(dc, cpu_SR[
1145 dc->config->ndepc ? DEPC : EPC1]);
1146 break;
1147
1148 case 4: /*RFWOw*/
1149 case 5: /*RFWUw*/
1150 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1151 gen_check_privilege(dc);
1152 {
1153 TCGv_i32 tmp = tcg_const_i32(1);
1154
1155 tcg_gen_andi_i32(
1156 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1157 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1158
1159 if (RRR_S == 4) {
1160 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1161 cpu_SR[WINDOW_START], tmp);
1162 } else {
1163 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1164 cpu_SR[WINDOW_START], tmp);
1165 }
1166
f492b82d 1167 gen_helper_restore_owb(cpu_env);
b994e91b 1168 gen_helper_check_interrupts(cpu_env);
553e44f9
MF		 1169 gen_jump(dc, cpu_SR[EPC1]);
1170
1171 tcg_temp_free(tmp);
1172 }
40643d7c
MF		 1173 break;
1174
1175 default: /*reserved*/
1176 RESERVED();
1177 break;
1178 }
1179 break;
1180
1181 case 1: /*RFIx*/
1182 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b
MF		 1183 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1184 gen_check_privilege(dc);
1185 tcg_gen_mov_i32(cpu_SR[PS],
1186 cpu_SR[EPS2 + RRR_S - 2]);
1187 gen_helper_check_interrupts(cpu_env);
1188 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1189 } else {
1190 qemu_log("RFI %d is illegal\n", RRR_S);
1191 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1192 }
40643d7c
MF		 1193 break;
1194
1195 case 2: /*RFME*/
1196 TBD();
1197 break;
1198
1199 default: /*reserved*/
1200 RESERVED();
1201 break;
1202
1203 }
91a5bb76
MF		 1204 break;
1205
1206 case 4: /*BREAKx*/
e61dc8f7
MF		 1207 HAS_OPTION(XTENSA_OPTION_DEBUG);
1208 if (dc->debug) {
1209 gen_debug_exception(dc, DEBUGCAUSE_BI);
1210 }
91a5bb76
MF		 1211 break;
1212
1213 case 5: /*SYSCALLx*/
1214 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 1215 switch (RRR_S) {
1216 case 0: /*SYSCALLx*/
1217 gen_exception_cause(dc, SYSCALL_CAUSE);
1218 break;
1219
1220 case 1: /*SIMCALL*/
1ddeaa5d
MF		 1221 if (semihosting_enabled) {
1222 gen_check_privilege(dc);
1223 gen_helper_simcall(cpu_env);
1224 } else {
1225 qemu_log("SIMCALL but semihosting is disabled\n");
1226 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1227 }
40643d7c
MF		 1228 break;
1229
1230 default:
1231 RESERVED();
1232 break;
1233 }
91a5bb76
MF		 1234 break;
1235
1236 case 6: /*RSILx*/
1237 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
40643d7c 1238 gen_check_privilege(dc);
772177c1 1239 gen_window_check1(dc, RRR_T);
40643d7c 1240 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
b994e91b 1241 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
40643d7c 1242 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
b994e91b
MF		 1243 gen_helper_check_interrupts(cpu_env);
1244 gen_jumpi_check_loop_end(dc, 0);
91a5bb76
MF		 1245 break;
1246
1247 case 7: /*WAITIx*/
1248 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
b994e91b
MF		 1249 gen_check_privilege(dc);
1250 gen_waiti(dc, RRR_S);
91a5bb76
MF		 1251 break;
1252
1253 case 8: /*ANY4p*/
91a5bb76 1254 case 9: /*ALL4p*/
91a5bb76 1255 case 10: /*ANY8p*/
91a5bb76
MF		 1256 case 11: /*ALL8p*/
1257 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1258 {
1259 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1260 TCGv_i32 mask = tcg_const_i32(
1261 ((1 << shift) - 1) << RRR_S);
1262 TCGv_i32 tmp = tcg_temp_new_i32();
1263
1264 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1265 if (RRR_R & 1) { /*ALL*/
1266 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1267 } else { /*ANY*/
1268 tcg_gen_add_i32(tmp, tmp, mask);
1269 }
1270 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1271 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1272 tmp, RRR_T, 1);
1273 tcg_temp_free(mask);
1274 tcg_temp_free(tmp);
1275 }
91a5bb76
MF		 1276 break;
1277
1278 default: /*reserved*/
1279 RESERVED();
dedc5eae
MF		 1280 break;
1281
1282 }
1283 break;
1284
1285 case 1: /*AND*/
772177c1 1286 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1287 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1288 break;
1289
1290 case 2: /*OR*/
772177c1 1291 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1292 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1293 break;
1294
1295 case 3: /*XOR*/
772177c1 1296 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1297 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1298 break;
1299
1300 case 4: /*ST1*/
3580ecad
MF		 1301 switch (RRR_R) {
1302 case 0: /*SSR*/
772177c1 1303 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1304 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1305 break;
1306
1307 case 1: /*SSL*/
772177c1 1308 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1309 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1310 break;
1311
1312 case 2: /*SSA8L*/
772177c1 1313 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1314 {
1315 TCGv_i32 tmp = tcg_temp_new_i32();
1316 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1317 gen_right_shift_sar(dc, tmp);
1318 tcg_temp_free(tmp);
1319 }
1320 break;
1321
1322 case 3: /*SSA8B*/
772177c1 1323 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1324 {
1325 TCGv_i32 tmp = tcg_temp_new_i32();
1326 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1327 gen_left_shift_sar(dc, tmp);
1328 tcg_temp_free(tmp);
1329 }
1330 break;
1331
1332 case 4: /*SSAI*/
1333 {
1334 TCGv_i32 tmp = tcg_const_i32(
1335 RRR_S | ((RRR_T & 1) << 4));
1336 gen_right_shift_sar(dc, tmp);
1337 tcg_temp_free(tmp);
1338 }
1339 break;
1340
1341 case 6: /*RER*/
91a5bb76 1342 TBD();
3580ecad
MF		 1343 break;
1344
1345 case 7: /*WER*/
91a5bb76 1346 TBD();
3580ecad
MF		 1347 break;
1348
1349 case 8: /*ROTWw*/
1350 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1351 gen_check_privilege(dc);
1352 {
1353 TCGv_i32 tmp = tcg_const_i32(
1354 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
f492b82d 1355 gen_helper_rotw(cpu_env, tmp);
553e44f9 1356 tcg_temp_free(tmp);
772177c1 1357 reset_used_window(dc);
553e44f9 1358 }
3580ecad
MF		 1359 break;
1360
1361 case 14: /*NSAu*/
7f65f4b0 1362 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1363 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1364 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1365 break;
1366
1367 case 15: /*NSAUu*/
7f65f4b0 1368 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1369 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1370 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1371 break;
1372
1373 default: /*reserved*/
91a5bb76 1374 RESERVED();
3580ecad
MF		 1375 break;
1376 }
dedc5eae
MF		 1377 break;
1378
1379 case 5: /*TLB*/
b67ea0cd
MF		 1380 HAS_OPTION_BITS(
1381 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1382 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1383 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1384 gen_check_privilege(dc);
1385 gen_window_check2(dc, RRR_S, RRR_T);
1386 {
1387 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1388
1389 switch (RRR_R & 7) {
1390 case 3: /*RITLB0*/ /*RDTLB0*/
f492b82d
MF		 1391 gen_helper_rtlb0(cpu_R[RRR_T],
1392 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1393 break;
1394
1395 case 4: /*IITLB*/ /*IDTLB*/
f492b82d 1396 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1397 /* This could change memory mapping, so exit tb */
1398 gen_jumpi_check_loop_end(dc, -1);
1399 break;
1400
1401 case 5: /*PITLB*/ /*PDTLB*/
1402 tcg_gen_movi_i32(cpu_pc, dc->pc);
f492b82d
MF		 1403 gen_helper_ptlb(cpu_R[RRR_T],
1404 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1405 break;
1406
1407 case 6: /*WITLB*/ /*WDTLB*/
f492b82d
MF		 1408 gen_helper_wtlb(
1409 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1410 /* This could change memory mapping, so exit tb */
1411 gen_jumpi_check_loop_end(dc, -1);
1412 break;
1413
1414 case 7: /*RITLB1*/ /*RDTLB1*/
f492b82d
MF		 1415 gen_helper_rtlb1(cpu_R[RRR_T],
1416 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1417 break;
1418
1419 default:
1420 tcg_temp_free(dtlb);
1421 RESERVED();
1422 break;
1423 }
1424 tcg_temp_free(dtlb);
1425 }
dedc5eae
MF		 1426 break;
1427
1428 case 6: /*RT0*/
772177c1 1429 gen_window_check2(dc, RRR_R, RRR_T);
f331fe5e
MF		 1430 switch (RRR_S) {
1431 case 0: /*NEG*/
1432 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1433 break;
1434
1435 case 1: /*ABS*/
1436 {
f877d09e
MF		 1437 TCGv_i32 zero = tcg_const_i32(0);
1438 TCGv_i32 neg = tcg_temp_new_i32();
1439
1440 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1441 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1442 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1443 tcg_temp_free(neg);
1444 tcg_temp_free(zero);
f331fe5e
MF		 1445 }
1446 break;
1447
1448 default: /*reserved*/
91a5bb76 1449 RESERVED();
f331fe5e
MF		 1450 break;
1451 }
dedc5eae
MF		 1452 break;
1453
1454 case 7: /*reserved*/
91a5bb76 1455 RESERVED();
dedc5eae
MF		 1456 break;
1457
1458 case 8: /*ADD*/
772177c1 1459 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1460 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1461 break;
1462
1463 case 9: /*ADD**/
1464 case 10:
1465 case 11:
772177c1 1466 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1467 {
1468 TCGv_i32 tmp = tcg_temp_new_i32();
1469 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1470 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1471 tcg_temp_free(tmp);
1472 }
1473 break;
1474
1475 case 12: /*SUB*/
772177c1 1476 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1477 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1478 break;
1479
1480 case 13: /*SUB**/
1481 case 14:
1482 case 15:
772177c1 1483 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1484 {
1485 TCGv_i32 tmp = tcg_temp_new_i32();
1486 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1487 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1488 tcg_temp_free(tmp);
1489 }
1490 break;
1491 }
1492 break;
1493
1494 case 1: /*RST1*/
3580ecad
MF		 1495 switch (OP2) {
1496 case 0: /*SLLI*/
1497 case 1:
772177c1 1498 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1499 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1500 32 - (RRR_T | ((OP2 & 1) << 4)));
1501 break;
1502
1503 case 2: /*SRAI*/
1504 case 3:
772177c1 1505 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1506 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1507 RRR_S | ((OP2 & 1) << 4));
1508 break;
1509
1510 case 4: /*SRLI*/
772177c1 1511 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1512 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1513 break;
1514
1515 case 6: /*XSR*/
0857a06e 1516 if (gen_check_sr(dc, RSR_SR, SR_X)) {
3580ecad 1517 TCGv_i32 tmp = tcg_temp_new_i32();
0857a06e 1518
40643d7c
MF		 1519 if (RSR_SR >= 64) {
1520 gen_check_privilege(dc);
1521 }
772177c1 1522 gen_window_check1(dc, RRR_T);
3580ecad
MF		 1523 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1524 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1525 gen_wsr(dc, RSR_SR, tmp);
1526 tcg_temp_free(tmp);
1527 }
1528 break;
1529
1530 /*
1531 * Note: 64 bit ops are used here solely because SAR values
1532 * have range 0..63
1533 */
1534#define gen_shift_reg(cmd, reg) do { \
1535 TCGv_i64 tmp = tcg_temp_new_i64(); \
1536 tcg_gen_extu_i32_i64(tmp, reg); \
1537 tcg_gen_##cmd##_i64(v, v, tmp); \
1538 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1539 tcg_temp_free_i64(v); \
1540 tcg_temp_free_i64(tmp); \
1541 } while (0)
1542
1543#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1544
1545 case 8: /*SRC*/
772177c1 1546 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1547 {
1548 TCGv_i64 v = tcg_temp_new_i64();
1549 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1550 gen_shift(shr);
1551 }
1552 break;
1553
1554 case 9: /*SRL*/
772177c1 1555 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1556 if (dc->sar_5bit) {
1557 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1558 } else {
1559 TCGv_i64 v = tcg_temp_new_i64();
1560 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1561 gen_shift(shr);
1562 }
1563 break;
1564
1565 case 10: /*SLL*/
772177c1 1566 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1567 if (dc->sar_m32_5bit) {
1568 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1569 } else {
1570 TCGv_i64 v = tcg_temp_new_i64();
1571 TCGv_i32 s = tcg_const_i32(32);
1572 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1573 tcg_gen_andi_i32(s, s, 0x3f);
1574 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1575 gen_shift_reg(shl, s);
1576 tcg_temp_free(s);
1577 }
1578 break;
1579
1580 case 11: /*SRA*/
772177c1 1581 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1582 if (dc->sar_5bit) {
1583 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1584 } else {
1585 TCGv_i64 v = tcg_temp_new_i64();
1586 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1587 gen_shift(sar);
1588 }
1589 break;
1590#undef gen_shift
1591#undef gen_shift_reg
1592
1593 case 12: /*MUL16U*/
1594 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1595 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1596 {
1597 TCGv_i32 v1 = tcg_temp_new_i32();
1598 TCGv_i32 v2 = tcg_temp_new_i32();
1599 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1600 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1601 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1602 tcg_temp_free(v2);
1603 tcg_temp_free(v1);
1604 }
1605 break;
1606
1607 case 13: /*MUL16S*/
1608 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1609 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1610 {
1611 TCGv_i32 v1 = tcg_temp_new_i32();
1612 TCGv_i32 v2 = tcg_temp_new_i32();
1613 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1614 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1615 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1616 tcg_temp_free(v2);
1617 tcg_temp_free(v1);
1618 }
1619 break;
1620
1621 default: /*reserved*/
91a5bb76 1622 RESERVED();
3580ecad
MF		 1623 break;
1624 }
dedc5eae
MF		 1625 break;
1626
1627 case 2: /*RST2*/
4dd85b6b
MF		 1628 if (OP2 >= 8) {
1629 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1630 }
772177c1 1631
f76ebf55
MF		 1632 if (OP2 >= 12) {
1633 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1634 int label = gen_new_label();
1635 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1636 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1637 gen_set_label(label);
1638 }
1639
1640 switch (OP2) {
4dd85b6b
MF		 1641#define BOOLEAN_LOGIC(fn, r, s, t) \
1642 do { \
1643 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1644 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1645 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1646 \
1647 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1648 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1649 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1650 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1651 tcg_temp_free(tmp1); \
1652 tcg_temp_free(tmp2); \
1653 } while (0)
1654
1655 case 0: /*ANDBp*/
1656 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1657 break;
1658
1659 case 1: /*ANDBCp*/
1660 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1661 break;
1662
1663 case 2: /*ORBp*/
1664 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1665 break;
1666
1667 case 3: /*ORBCp*/
1668 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1669 break;
1670
1671 case 4: /*XORBp*/
1672 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1673 break;
1674
1675#undef BOOLEAN_LOGIC
1676
f76ebf55
MF		 1677 case 8: /*MULLi*/
1678 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1679 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1680 break;
1681
1682 case 10: /*MULUHi*/
1683 case 11: /*MULSHi*/
7f65f4b0 1684 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
f76ebf55 1685 {
c9cda20b 1686 TCGv lo = tcg_temp_new();
f76ebf55
MF		 1687
1688 if (OP2 == 10) {
c9cda20b
RH		 1689 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1690 cpu_R[RRR_S], cpu_R[RRR_T]);
f76ebf55 1691 } else {
c9cda20b
RH		 1692 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1693 cpu_R[RRR_S], cpu_R[RRR_T]);
f76ebf55 1694 }
c9cda20b 1695 tcg_temp_free(lo);
f76ebf55
MF		 1696 }
1697 break;
1698
1699 case 12: /*QUOUi*/
1700 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1701 break;
1702
1703 case 13: /*QUOSi*/
1704 case 15: /*REMSi*/
1705 {
1706 int label1 = gen_new_label();
1707 int label2 = gen_new_label();
1708
1709 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1710 label1);
1711 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1712 label1);
1713 tcg_gen_movi_i32(cpu_R[RRR_R],
1714 OP2 == 13 ? 0x80000000 : 0);
1715 tcg_gen_br(label2);
1716 gen_set_label(label1);
1717 if (OP2 == 13) {
1718 tcg_gen_div_i32(cpu_R[RRR_R],
1719 cpu_R[RRR_S], cpu_R[RRR_T]);
1720 } else {
1721 tcg_gen_rem_i32(cpu_R[RRR_R],
1722 cpu_R[RRR_S], cpu_R[RRR_T]);
1723 }
1724 gen_set_label(label2);
1725 }
1726 break;
1727
1728 case 14: /*REMUi*/
1729 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1730 break;
1731
1732 default: /*reserved*/
1733 RESERVED();
1734 break;
1735 }
dedc5eae
MF		 1736 break;
1737
1738 case 3: /*RST3*/
b8132eff
MF		 1739 switch (OP2) {
1740 case 0: /*RSR*/
0857a06e
MF		 1741 if (gen_check_sr(dc, RSR_SR, SR_R)) {
1742 if (RSR_SR >= 64) {
1743 gen_check_privilege(dc);
1744 }
1745 gen_window_check1(dc, RRR_T);
1746 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
40643d7c 1747 }
b8132eff
MF		 1748 break;
1749
1750 case 1: /*WSR*/
0857a06e
MF		 1751 if (gen_check_sr(dc, RSR_SR, SR_W)) {
1752 if (RSR_SR >= 64) {
1753 gen_check_privilege(dc);
1754 }
1755 gen_window_check1(dc, RRR_T);
1756 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
40643d7c 1757 }
b8132eff
MF		 1758 break;
1759
1760 case 2: /*SEXTu*/
7f65f4b0 1761 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
772177c1 1762 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1763 {
1764 int shift = 24 - RRR_T;
1765
1766 if (shift == 24) {
1767 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1768 } else if (shift == 16) {
1769 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1770 } else {
1771 TCGv_i32 tmp = tcg_temp_new_i32();
1772 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1773 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1774 tcg_temp_free(tmp);
1775 }
1776 }
1777 break;
1778
1779 case 3: /*CLAMPSu*/
7f65f4b0 1780 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
772177c1 1781 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1782 {
1783 TCGv_i32 tmp1 = tcg_temp_new_i32();
1784 TCGv_i32 tmp2 = tcg_temp_new_i32();
f877d09e 1785 TCGv_i32 zero = tcg_const_i32(0);
b8132eff
MF		 1786
1787 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1788 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1789 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
b8132eff
MF		 1790
1791 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
f877d09e 1792 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
b8132eff 1793
f877d09e
MF		 1794 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1795 cpu_R[RRR_S], tmp1);
b8132eff
MF		 1796 tcg_temp_free(tmp1);
1797 tcg_temp_free(tmp2);
f877d09e 1798 tcg_temp_free(zero);
b8132eff
MF		 1799 }
1800 break;
1801
1802 case 4: /*MINu*/
1803 case 5: /*MAXu*/
1804 case 6: /*MINUu*/
1805 case 7: /*MAXUu*/
7f65f4b0 1806 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
772177c1 1807 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1808 {
1809 static const TCGCond cond[] = {
1810 TCG_COND_LE,
1811 TCG_COND_GE,
1812 TCG_COND_LEU,
1813 TCG_COND_GEU
1814 };
f877d09e
MF		 1815 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1816 cpu_R[RRR_S], cpu_R[RRR_T],
1817 cpu_R[RRR_S], cpu_R[RRR_T]);
b8132eff
MF		 1818 }
1819 break;
1820
1821 case 8: /*MOVEQZ*/
1822 case 9: /*MOVNEZ*/
1823 case 10: /*MOVLTZ*/
1824 case 11: /*MOVGEZ*/
772177c1 1825 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1826 {
1827 static const TCGCond cond[] = {
b8132eff 1828 TCG_COND_EQ,
f877d09e
MF		 1829 TCG_COND_NE,
1830 TCG_COND_LT,
b8132eff 1831 TCG_COND_GE,
b8132eff 1832 };
f877d09e
MF		 1833 TCGv_i32 zero = tcg_const_i32(0);
1834
1835 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1836 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1837 tcg_temp_free(zero);
b8132eff
MF		 1838 }
1839 break;
1840
1841 case 12: /*MOVFp*/
b8132eff
MF		 1842 case 13: /*MOVTp*/
1843 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1844 gen_window_check2(dc, RRR_R, RRR_S);
1845 {
f877d09e 1846 TCGv_i32 zero = tcg_const_i32(0);
4dd85b6b
MF		 1847 TCGv_i32 tmp = tcg_temp_new_i32();
1848
1849 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
f877d09e
MF		 1850 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1851 cpu_R[RRR_R], tmp, zero,
1852 cpu_R[RRR_S], cpu_R[RRR_R]);
1853
4dd85b6b 1854 tcg_temp_free(tmp);
f877d09e 1855 tcg_temp_free(zero);
4dd85b6b 1856 }
b8132eff
MF		 1857 break;
1858
1859 case 14: /*RUR*/
772177c1 1860 gen_window_check1(dc, RRR_R);
b8132eff
MF		 1861 {
1862 int st = (RRR_S << 4) + RRR_T;
fe0bd475 1863 if (uregnames[st].name) {
b8132eff
MF		 1864 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1865 } else {
1866 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1867 TBD();
b8132eff
MF		 1868 }
1869 }
1870 break;
1871
1872 case 15: /*WUR*/
772177c1 1873 gen_window_check1(dc, RRR_T);
fe0bd475 1874 if (uregnames[RSR_SR].name) {
dd519cbe
MF		 1875 gen_wur(RSR_SR, cpu_R[RRR_T]);
1876 } else {
1877 qemu_log("WUR %d not implemented, ", RSR_SR);
1878 TBD();
b8132eff
MF		 1879 }
1880 break;
1881
1882 }
dedc5eae
MF		 1883 break;
1884
1885 case 4: /*EXTUI*/
1886 case 5:
772177c1 1887 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad 1888 {
f9cb5045 1889 int shiftimm = RRR_S | ((OP1 & 1) << 4);
3580ecad
MF		 1890 int maskimm = (1 << (OP2 + 1)) - 1;
1891
1892 TCGv_i32 tmp = tcg_temp_new_i32();
f783cb22
AJ		 1893 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1894 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
3580ecad
MF		 1895 tcg_temp_free(tmp);
1896 }
dedc5eae
MF		 1897 break;
1898
1899 case 6: /*CUST0*/
91a5bb76 1900 RESERVED();
dedc5eae
MF		 1901 break;
1902
1903 case 7: /*CUST1*/
91a5bb76 1904 RESERVED();
dedc5eae
MF		 1905 break;
1906
1907 case 8: /*LSCXp*/
9ed7ae12
MF		 1908 switch (OP2) {
1909 case 0: /*LSXf*/
1910 case 1: /*LSXUf*/
1911 case 4: /*SSXf*/
1912 case 5: /*SSXUf*/
1913 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1914 gen_window_check2(dc, RRR_S, RRR_T);
ef04a846 1915 gen_check_cpenable(dc, 0);
9ed7ae12
MF		 1916 {
1917 TCGv_i32 addr = tcg_temp_new_i32();
1918 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1919 gen_load_store_alignment(dc, 2, addr, false);
1920 if (OP2 & 0x4) {
1921 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1922 } else {
1923 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1924 }
1925 if (OP2 & 0x1) {
1926 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1927 }
1928 tcg_temp_free(addr);
1929 }
1930 break;
1931
1932 default: /*reserved*/
1933 RESERVED();
1934 break;
1935 }
dedc5eae
MF		 1936 break;
1937
1938 case 9: /*LSC4*/
772177c1 1939 gen_window_check2(dc, RRR_S, RRR_T);
553e44f9
MF		 1940 switch (OP2) {
1941 case 0: /*L32E*/
1942 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1943 gen_check_privilege(dc);
1944 {
1945 TCGv_i32 addr = tcg_temp_new_i32();
1946 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1947 (0xffffffc0 | (RRR_R << 2)));
1948 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1949 tcg_temp_free(addr);
1950 }
1951 break;
1952
1953 case 4: /*S32E*/
1954 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1955 gen_check_privilege(dc);
1956 {
1957 TCGv_i32 addr = tcg_temp_new_i32();
1958 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1959 (0xffffffc0 | (RRR_R << 2)));
1960 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1961 tcg_temp_free(addr);
1962 }
1963 break;
1964
1965 default:
1966 RESERVED();
1967 break;
1968 }
dedc5eae
MF		 1969 break;
1970
1971 case 10: /*FP0*/
1972 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
0b6df838
MF		 1973 switch (OP2) {
1974 case 0: /*ADD.Sf*/
ef04a846 1975 gen_check_cpenable(dc, 0);
0b6df838
MF		 1976 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
1977 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1978 break;
1979
1980 case 1: /*SUB.Sf*/
ef04a846 1981 gen_check_cpenable(dc, 0);
0b6df838
MF		 1982 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
1983 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1984 break;
1985
1986 case 2: /*MUL.Sf*/
ef04a846 1987 gen_check_cpenable(dc, 0);
0b6df838
MF		 1988 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
1989 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1990 break;
1991
1992 case 4: /*MADD.Sf*/
ef04a846 1993 gen_check_cpenable(dc, 0);
0b6df838
MF		 1994 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
1995 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1996 break;
1997
1998 case 5: /*MSUB.Sf*/
ef04a846 1999 gen_check_cpenable(dc, 0);
0b6df838
MF		 2000 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2001 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
2002 break;
2003
b7ee8c6a
MF		 2004 case 8: /*ROUND.Sf*/
2005 case 9: /*TRUNC.Sf*/
2006 case 10: /*FLOOR.Sf*/
2007 case 11: /*CEIL.Sf*/
2008 case 14: /*UTRUNC.Sf*/
2009 gen_window_check1(dc, RRR_R);
ef04a846 2010 gen_check_cpenable(dc, 0);
b7ee8c6a
MF		 2011 {
2012 static const unsigned rounding_mode_const[] = {
2013 float_round_nearest_even,
2014 float_round_to_zero,
2015 float_round_down,
2016 float_round_up,
2017 [6] = float_round_to_zero,
2018 };
2019 TCGv_i32 rounding_mode = tcg_const_i32(
2020 rounding_mode_const[OP2 & 7]);
2021 TCGv_i32 scale = tcg_const_i32(RRR_T);
2022
2023 if (OP2 == 14) {
2024 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2025 rounding_mode, scale);
2026 } else {
2027 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2028 rounding_mode, scale);
2029 }
2030
2031 tcg_temp_free(rounding_mode);
2032 tcg_temp_free(scale);
2033 }
2034 break;
2035
2036 case 12: /*FLOAT.Sf*/
2037 case 13: /*UFLOAT.Sf*/
2038 gen_window_check1(dc, RRR_S);
ef04a846 2039 gen_check_cpenable(dc, 0);
b7ee8c6a
MF		 2040 {
2041 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2042
2043 if (OP2 == 13) {
2044 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2045 cpu_R[RRR_S], scale);
2046 } else {
2047 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2048 cpu_R[RRR_S], scale);
2049 }
2050 tcg_temp_free(scale);
2051 }
2052 break;
2053
0b6df838
MF		 2054 case 15: /*FP1OP*/
2055 switch (RRR_T) {
2056 case 0: /*MOV.Sf*/
ef04a846 2057 gen_check_cpenable(dc, 0);
0b6df838
MF		 2058 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2059 break;
2060
2061 case 1: /*ABS.Sf*/
ef04a846 2062 gen_check_cpenable(dc, 0);
0b6df838
MF		 2063 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2064 break;
2065
2066 case 4: /*RFRf*/
2067 gen_window_check1(dc, RRR_R);
ef04a846 2068 gen_check_cpenable(dc, 0);
0b6df838
MF		 2069 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2070 break;
2071
2072 case 5: /*WFRf*/
2073 gen_window_check1(dc, RRR_S);
ef04a846 2074 gen_check_cpenable(dc, 0);
0b6df838
MF		 2075 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2076 break;
2077
2078 case 6: /*NEG.Sf*/
ef04a846 2079 gen_check_cpenable(dc, 0);
0b6df838
MF		 2080 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2081 break;
2082
2083 default: /*reserved*/
2084 RESERVED();
2085 break;
2086 }
2087 break;
2088
2089 default: /*reserved*/
2090 RESERVED();
2091 break;
2092 }
dedc5eae
MF		 2093 break;
2094
2095 case 11: /*FP1*/
2096 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
4e273869
MF		 2097
2098#define gen_compare(rel, br, a, b) \
2099 do { \
2100 TCGv_i32 bit = tcg_const_i32(1 << br); \
2101 \
ef04a846 2102 gen_check_cpenable(dc, 0); \
4e273869
MF		 2103 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2104 tcg_temp_free(bit); \
2105 } while (0)
2106
2107 switch (OP2) {
2108 case 1: /*UN.Sf*/
2109 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2110 break;
2111
2112 case 2: /*OEQ.Sf*/
2113 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2114 break;
2115
2116 case 3: /*UEQ.Sf*/
2117 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2118 break;
2119
2120 case 4: /*OLT.Sf*/
2121 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2122 break;
2123
2124 case 5: /*ULT.Sf*/
2125 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2126 break;
2127
2128 case 6: /*OLE.Sf*/
2129 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2130 break;
2131
2132 case 7: /*ULE.Sf*/
2133 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2134 break;
2135
2136#undef gen_compare
2137
2138 case 8: /*MOVEQZ.Sf*/
2139 case 9: /*MOVNEZ.Sf*/
2140 case 10: /*MOVLTZ.Sf*/
2141 case 11: /*MOVGEZ.Sf*/
2142 gen_window_check1(dc, RRR_T);
ef04a846 2143 gen_check_cpenable(dc, 0);
4e273869
MF		 2144 {
2145 static const TCGCond cond[] = {
4e273869 2146 TCG_COND_EQ,
f877d09e
MF		 2147 TCG_COND_NE,
2148 TCG_COND_LT,
4e273869 2149 TCG_COND_GE,
4e273869 2150 };
f877d09e
MF		 2151 TCGv_i32 zero = tcg_const_i32(0);
2152
2153 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2154 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2155 tcg_temp_free(zero);
4e273869
MF		 2156 }
2157 break;
2158
2159 case 12: /*MOVF.Sf*/
2160 case 13: /*MOVT.Sf*/
2161 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
ef04a846 2162 gen_check_cpenable(dc, 0);
4e273869 2163 {
f877d09e 2164 TCGv_i32 zero = tcg_const_i32(0);
4e273869
MF		 2165 TCGv_i32 tmp = tcg_temp_new_i32();
2166
2167 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
f877d09e
MF		 2168 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2169 cpu_FR[RRR_R], tmp, zero,
2170 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2171
4e273869 2172 tcg_temp_free(tmp);
f877d09e 2173 tcg_temp_free(zero);
4e273869
MF		 2174 }
2175 break;
2176
2177 default: /*reserved*/
2178 RESERVED();
2179 break;
2180 }
dedc5eae
MF		 2181 break;
2182
2183 default: /*reserved*/
91a5bb76 2184 RESERVED();
dedc5eae
MF		 2185 break;
2186 }
2187 break;
2188
2189 case 1: /*L32R*/
772177c1 2190 gen_window_check1(dc, RRR_T);
dedc5eae
MF		 2191 {
2192 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 2193 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2194 0 : ((dc->pc + 3) & ~3)) +
2195 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 2196
6ad6dbf7
MF		 2197 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2198 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2199 }
f0a548b9 2200 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 2201 tcg_temp_free(tmp);
2202 }
2203 break;
2204
2205 case 2: /*LSAI*/
809377aa
MF		 2206#define gen_load_store(type, shift) do { \
2207 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2208 gen_window_check2(dc, RRI8_S, RRI8_T); \
809377aa 2209 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
5b4e481b
MF		 2210 if (shift) { \
2211 gen_load_store_alignment(dc, shift, addr, false); \
2212 } \
f0a548b9 2213 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
809377aa
MF		 2214 tcg_temp_free(addr); \
2215 } while (0)
2216
2217 switch (RRI8_R) {
2218 case 0: /*L8UI*/
2219 gen_load_store(ld8u, 0);
2220 break;
2221
2222 case 1: /*L16UI*/
2223 gen_load_store(ld16u, 1);
2224 break;
2225
2226 case 2: /*L32I*/
2227 gen_load_store(ld32u, 2);
2228 break;
2229
2230 case 4: /*S8I*/
2231 gen_load_store(st8, 0);
2232 break;
2233
2234 case 5: /*S16I*/
2235 gen_load_store(st16, 1);
2236 break;
2237
2238 case 6: /*S32I*/
2239 gen_load_store(st32, 2);
2240 break;
2241
7c842590
MF		 2242#define gen_dcache_hit_test(w, shift) do { \
2243 TCGv_i32 addr = tcg_temp_new_i32(); \
2244 TCGv_i32 res = tcg_temp_new_i32(); \
2245 gen_window_check1(dc, RRI##w##_S); \
2246 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2247 RRI##w##_IMM##w << shift); \
2248 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2249 tcg_temp_free(addr); \
2250 tcg_temp_free(res); \
2251 } while (0)
2252
2253#define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2254#define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2255
809377aa 2256 case 7: /*CACHEc*/
8ffc2d0d
MF		 2257 if (RRI8_T < 8) {
2258 HAS_OPTION(XTENSA_OPTION_DCACHE);
2259 }
2260
2261 switch (RRI8_T) {
2262 case 0: /*DPFRc*/
7c842590 2263 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2264 break;
2265
2266 case 1: /*DPFWc*/
7c842590 2267 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2268 break;
2269
2270 case 2: /*DPFROc*/
7c842590 2271 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2272 break;
2273
2274 case 3: /*DPFWOc*/
7c842590 2275 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2276 break;
2277
2278 case 4: /*DHWBc*/
7c842590 2279 gen_dcache_hit_test8();
8ffc2d0d
MF		 2280 break;
2281
2282 case 5: /*DHWBIc*/
7c842590 2283 gen_dcache_hit_test8();
8ffc2d0d
MF		 2284 break;
2285
2286 case 6: /*DHIc*/
7c842590
MF		 2287 gen_check_privilege(dc);
2288 gen_dcache_hit_test8();
8ffc2d0d
MF		 2289 break;
2290
2291 case 7: /*DIIc*/
7c842590
MF		 2292 gen_check_privilege(dc);
2293 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2294 break;
2295
2296 case 8: /*DCEc*/
2297 switch (OP1) {
2298 case 0: /*DPFLl*/
2299 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
7c842590
MF		 2300 gen_check_privilege(dc);
2301 gen_dcache_hit_test4();
8ffc2d0d
MF		 2302 break;
2303
2304 case 2: /*DHUl*/
2305 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
7c842590
MF		 2306 gen_check_privilege(dc);
2307 gen_dcache_hit_test4();
8ffc2d0d
MF		 2308 break;
2309
2310 case 3: /*DIUl*/
2311 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
7c842590
MF		 2312 gen_check_privilege(dc);
2313 gen_window_check1(dc, RRI4_S);
8ffc2d0d
MF		 2314 break;
2315
2316 case 4: /*DIWBc*/
2317 HAS_OPTION(XTENSA_OPTION_DCACHE);
7c842590
MF		 2318 gen_check_privilege(dc);
2319 gen_window_check1(dc, RRI4_S);
8ffc2d0d
MF		 2320 break;
2321
2322 case 5: /*DIWBIc*/
2323 HAS_OPTION(XTENSA_OPTION_DCACHE);
7c842590
MF		 2324 gen_check_privilege(dc);
2325 gen_window_check1(dc, RRI4_S);
8ffc2d0d
MF		 2326 break;
2327
2328 default: /*reserved*/
2329 RESERVED();
2330 break;
2331
2332 }
2333 break;
2334
7c842590
MF		 2335#undef gen_dcache_hit_test
2336#undef gen_dcache_hit_test4
2337#undef gen_dcache_hit_test8
2338
e848dd42
MF		 2339#define gen_icache_hit_test(w, shift) do { \
2340 TCGv_i32 addr = tcg_temp_new_i32(); \
2341 gen_window_check1(dc, RRI##w##_S); \
2342 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2343 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2344 RRI##w##_IMM##w << shift); \
2345 gen_helper_itlb_hit_test(cpu_env, addr); \
2346 tcg_temp_free(addr); \
2347 } while (0)
2348
2349#define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2350#define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2351
8ffc2d0d
MF		 2352 case 12: /*IPFc*/
2353 HAS_OPTION(XTENSA_OPTION_ICACHE);
e848dd42 2354 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2355 break;
2356
2357 case 13: /*ICEc*/
2358 switch (OP1) {
2359 case 0: /*IPFLl*/
2360 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
e848dd42
MF		 2361 gen_check_privilege(dc);
2362 gen_icache_hit_test4();
8ffc2d0d
MF		 2363 break;
2364
2365 case 2: /*IHUl*/
2366 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
e848dd42
MF		 2367 gen_check_privilege(dc);
2368 gen_icache_hit_test4();
8ffc2d0d
MF		 2369 break;
2370
2371 case 3: /*IIUl*/
2372 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
e848dd42
MF		 2373 gen_check_privilege(dc);
2374 gen_window_check1(dc, RRI4_S);
8ffc2d0d
MF		 2375 break;
2376
2377 default: /*reserved*/
2378 RESERVED();
2379 break;
2380 }
2381 break;
2382
2383 case 14: /*IHIc*/
2384 HAS_OPTION(XTENSA_OPTION_ICACHE);
e848dd42 2385 gen_icache_hit_test8();
8ffc2d0d
MF		 2386 break;
2387
2388 case 15: /*IIIc*/
2389 HAS_OPTION(XTENSA_OPTION_ICACHE);
e848dd42
MF		 2390 gen_check_privilege(dc);
2391 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2392 break;
2393
2394 default: /*reserved*/
2395 RESERVED();
2396 break;
2397 }
809377aa
MF		 2398 break;
2399
e848dd42
MF		 2400#undef gen_icache_hit_test
2401#undef gen_icache_hit_test4
2402#undef gen_icache_hit_test8
2403
809377aa
MF		 2404 case 9: /*L16SI*/
2405 gen_load_store(ld16s, 1);
2406 break;
5b4e481b 2407#undef gen_load_store
809377aa
MF		 2408
2409 case 10: /*MOVI*/
772177c1 2410 gen_window_check1(dc, RRI8_T);
809377aa
MF		 2411 tcg_gen_movi_i32(cpu_R[RRI8_T],
2412 RRI8_IMM8 | (RRI8_S << 8) |
2413 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2414 break;
2415
5b4e481b
MF		 2416#define gen_load_store_no_hw_align(type) do { \
2417 TCGv_i32 addr = tcg_temp_local_new_i32(); \
772177c1 2418 gen_window_check2(dc, RRI8_S, RRI8_T); \
5b4e481b
MF		 2419 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2420 gen_load_store_alignment(dc, 2, addr, true); \
2421 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2422 tcg_temp_free(addr); \
2423 } while (0)
2424
809377aa
MF		 2425 case 11: /*L32AIy*/
2426 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2427 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 2428 break;
2429
2430 case 12: /*ADDI*/
772177c1 2431 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2432 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2433 break;
2434
2435 case 13: /*ADDMI*/
772177c1 2436 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2437 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
2438 break;
2439
2440 case 14: /*S32C1Iy*/
7f65f4b0 2441 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
772177c1 2442 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2443 {
2444 int label = gen_new_label();
2445 TCGv_i32 tmp = tcg_temp_local_new_i32();
2446 TCGv_i32 addr = tcg_temp_local_new_i32();
fcc803d1 2447 TCGv_i32 tpc;
809377aa
MF		 2448
2449 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2450 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 2451 gen_load_store_alignment(dc, 2, addr, true);
fcc803d1
MF		 2452
2453 gen_advance_ccount(dc);
2454 tpc = tcg_const_i32(dc->pc);
2455 gen_helper_check_atomctl(cpu_env, tpc, addr);
f0a548b9 2456 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 2457 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2458 cpu_SR[SCOMPARE1], label);
2459
f0a548b9 2460 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 2461
2462 gen_set_label(label);
fcc803d1 2463 tcg_temp_free(tpc);
809377aa
MF		 2464 tcg_temp_free(addr);
2465 tcg_temp_free(tmp);
2466 }
2467 break;
2468
2469 case 15: /*S32RIy*/
2470 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2471 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 2472 break;
5b4e481b 2473#undef gen_load_store_no_hw_align
809377aa
MF		 2474
2475 default: /*reserved*/
91a5bb76 2476 RESERVED();
809377aa
MF		 2477 break;
2478 }
dedc5eae
MF		 2479 break;
2480
2481 case 3: /*LSCIp*/
9ed7ae12
MF		 2482 switch (RRI8_R) {
2483 case 0: /*LSIf*/
2484 case 4: /*SSIf*/
2485 case 8: /*LSIUf*/
2486 case 12: /*SSIUf*/
2487 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2488 gen_window_check1(dc, RRI8_S);
ef04a846 2489 gen_check_cpenable(dc, 0);
9ed7ae12
MF		 2490 {
2491 TCGv_i32 addr = tcg_temp_new_i32();
2492 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2493 gen_load_store_alignment(dc, 2, addr, false);
2494 if (RRI8_R & 0x4) {
2495 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2496 } else {
2497 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2498 }
2499 if (RRI8_R & 0x8) {
2500 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2501 }
2502 tcg_temp_free(addr);
2503 }
2504 break;
2505
2506 default: /*reserved*/
2507 RESERVED();
2508 break;
2509 }
dedc5eae
MF		 2510 break;
2511
2512 case 4: /*MAC16d*/
2513 HAS_OPTION(XTENSA_OPTION_MAC16);
6825b6c3
MF		 2514 {
2515 enum {
2516 MAC16_UMUL = 0x0,
2517 MAC16_MUL = 0x4,
2518 MAC16_MULA = 0x8,
2519 MAC16_MULS = 0xc,
2520 MAC16_NONE = 0xf,
2521 } op = OP1 & 0xc;
2522 bool is_m1_sr = (OP2 & 0x3) == 2;
2523 bool is_m2_sr = (OP2 & 0xc) == 0;
2524 uint32_t ld_offset = 0;
2525
2526 if (OP2 > 9) {
2527 RESERVED();
2528 }
2529
2530 switch (OP2 & 2) {
2531 case 0: /*MACI?/MACC?*/
2532 is_m1_sr = true;
2533 ld_offset = (OP2 & 1) ? -4 : 4;
2534
2535 if (OP2 >= 8) { /*MACI/MACC*/
2536 if (OP1 == 0) { /*LDINC/LDDEC*/
2537 op = MAC16_NONE;
2538 } else {
2539 RESERVED();
2540 }
2541 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2542 RESERVED();
2543 }
2544 break;
2545
2546 case 2: /*MACD?/MACA?*/
2547 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2548 RESERVED();
2549 }
2550 break;
2551 }
2552
2553 if (op != MAC16_NONE) {
2554 if (!is_m1_sr) {
2555 gen_window_check1(dc, RRR_S);
2556 }
2557 if (!is_m2_sr) {
2558 gen_window_check1(dc, RRR_T);
2559 }
2560 }
2561
2562 {
2563 TCGv_i32 vaddr = tcg_temp_new_i32();
2564 TCGv_i32 mem32 = tcg_temp_new_i32();
2565
2566 if (ld_offset) {
2567 gen_window_check1(dc, RRR_S);
2568 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2569 gen_load_store_alignment(dc, 2, vaddr, false);
2570 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2571 }
2572 if (op != MAC16_NONE) {
2573 TCGv_i32 m1 = gen_mac16_m(
2574 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2575 OP1 & 1, op == MAC16_UMUL);
2576 TCGv_i32 m2 = gen_mac16_m(
2577 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2578 OP1 & 2, op == MAC16_UMUL);
2579
2580 if (op == MAC16_MUL || op == MAC16_UMUL) {
2581 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2582 if (op == MAC16_UMUL) {
2583 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2584 } else {
2585 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2586 }
2587 } else {
d2123a07
RH		 2588 TCGv_i32 lo = tcg_temp_new_i32();
2589 TCGv_i32 hi = tcg_temp_new_i32();
2590
2591 tcg_gen_mul_i32(lo, m1, m2);
2592 tcg_gen_sari_i32(hi, lo, 31);
6825b6c3 2593 if (op == MAC16_MULA) {
d2123a07
RH		 2594 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2595 cpu_SR[ACCLO], cpu_SR[ACCHI],
2596 lo, hi);
6825b6c3 2597 } else {
d2123a07
RH		 2598 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2599 cpu_SR[ACCLO], cpu_SR[ACCHI],
2600 lo, hi);
6825b6c3 2601 }
6825b6c3
MF		 2602 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2603
d2123a07
RH		 2604 tcg_temp_free_i32(lo);
2605 tcg_temp_free_i32(hi);
6825b6c3
MF		 2606 }
2607 tcg_temp_free(m1);
2608 tcg_temp_free(m2);
2609 }
2610 if (ld_offset) {
2611 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2612 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2613 }
2614 tcg_temp_free(vaddr);
2615 tcg_temp_free(mem32);
2616 }
2617 }
dedc5eae
MF		 2618 break;
2619
2620 case 5: /*CALLN*/
2621 switch (CALL_N) {
2622 case 0: /*CALL0*/
2623 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2624 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2625 break;
2626
2627 case 1: /*CALL4w*/
2628 case 2: /*CALL8w*/
2629 case 3: /*CALL12w*/
2630 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 2631 gen_window_check1(dc, CALL_N << 2);
553e44f9
MF		 2632 gen_callwi(dc, CALL_N,
2633 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
dedc5eae
MF		 2634 break;
2635 }
2636 break;
2637
2638 case 6: /*SI*/
2639 switch (CALL_N) {
2640 case 0: /*J*/
2641 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2642 break;
2643
bd57fb91 2644 case 1: /*BZ*/
772177c1 2645 gen_window_check1(dc, BRI12_S);
bd57fb91
MF		 2646 {
2647 static const TCGCond cond[] = {
2648 TCG_COND_EQ, /*BEQZ*/
2649 TCG_COND_NE, /*BNEZ*/
2650 TCG_COND_LT, /*BLTZ*/
2651 TCG_COND_GE, /*BGEZ*/
2652 };
2653
2654 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2655 4 + BRI12_IMM12_SE);
2656 }
2657 break;
2658
2659 case 2: /*BI0*/
772177c1 2660 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2661 {
2662 static const TCGCond cond[] = {
2663 TCG_COND_EQ, /*BEQI*/
2664 TCG_COND_NE, /*BNEI*/
2665 TCG_COND_LT, /*BLTI*/
2666 TCG_COND_GE, /*BGEI*/
2667 };
2668
2669 gen_brcondi(dc, cond[BRI8_M & 3],
2670 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2671 }
2672 break;
2673
2674 case 3: /*BI1*/
2675 switch (BRI8_M) {
2676 case 0: /*ENTRYw*/
2677 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2678 {
2679 TCGv_i32 pc = tcg_const_i32(dc->pc);
2680 TCGv_i32 s = tcg_const_i32(BRI12_S);
2681 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
b994e91b 2682 gen_advance_ccount(dc);
f492b82d 2683 gen_helper_entry(cpu_env, pc, s, imm);
553e44f9
MF		 2684 tcg_temp_free(imm);
2685 tcg_temp_free(s);
2686 tcg_temp_free(pc);
772177c1 2687 reset_used_window(dc);
553e44f9 2688 }
bd57fb91
MF		 2689 break;
2690
2691 case 1: /*B1*/
2692 switch (BRI8_R) {
2693 case 0: /*BFp*/
bd57fb91
MF		 2694 case 1: /*BTp*/
2695 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 2696 {
2697 TCGv_i32 tmp = tcg_temp_new_i32();
2698 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2699 gen_brcondi(dc,
2700 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2701 tmp, 0, 4 + RRI8_IMM8_SE);
2702 tcg_temp_free(tmp);
2703 }
bd57fb91
MF		 2704 break;
2705
2706 case 8: /*LOOP*/
bd57fb91 2707 case 9: /*LOOPNEZ*/
bd57fb91 2708 case 10: /*LOOPGTZ*/
797d780b 2709 HAS_OPTION(XTENSA_OPTION_LOOP);
772177c1 2710 gen_window_check1(dc, RRI8_S);
797d780b
MF		 2711 {
2712 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2713 TCGv_i32 tmp = tcg_const_i32(lend);
2714
2715 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2716 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
f492b82d 2717 gen_helper_wsr_lend(cpu_env, tmp);
797d780b
MF		 2718 tcg_temp_free(tmp);
2719
2720 if (BRI8_R > 8) {
2721 int label = gen_new_label();
2722 tcg_gen_brcondi_i32(
2723 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2724 cpu_R[RRI8_S], 0, label);
2725 gen_jumpi(dc, lend, 1);
2726 gen_set_label(label);
2727 }
2728
2729 gen_jumpi(dc, dc->next_pc, 0);
2730 }
bd57fb91
MF		 2731 break;
2732
2733 default: /*reserved*/
91a5bb76 2734 RESERVED();
bd57fb91
MF		 2735 break;
2736
2737 }
2738 break;
2739
2740 case 2: /*BLTUI*/
2741 case 3: /*BGEUI*/
772177c1 2742 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2743 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2744 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2745 break;
2746 }
2747 break;
2748
dedc5eae
MF		 2749 }
2750 break;
2751
2752 case 7: /*B*/
bd57fb91
MF		 2753 {
2754 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2755
2756 switch (RRI8_R & 7) {
2757 case 0: /*BNONE*/ /*BANY*/
772177c1 2758 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2759 {
2760 TCGv_i32 tmp = tcg_temp_new_i32();
2761 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2762 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2763 tcg_temp_free(tmp);
2764 }
2765 break;
2766
2767 case 1: /*BEQ*/ /*BNE*/
2768 case 2: /*BLT*/ /*BGE*/
2769 case 3: /*BLTU*/ /*BGEU*/
772177c1 2770 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2771 {
2772 static const TCGCond cond[] = {
2773 [1] = TCG_COND_EQ,
2774 [2] = TCG_COND_LT,
2775 [3] = TCG_COND_LTU,
2776 [9] = TCG_COND_NE,
2777 [10] = TCG_COND_GE,
2778 [11] = TCG_COND_GEU,
2779 };
2780 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2781 4 + RRI8_IMM8_SE);
2782 }
2783 break;
2784
2785 case 4: /*BALL*/ /*BNALL*/
772177c1 2786 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2787 {
2788 TCGv_i32 tmp = tcg_temp_new_i32();
2789 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2790 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2791 4 + RRI8_IMM8_SE);
2792 tcg_temp_free(tmp);
2793 }
2794 break;
2795
2796 case 5: /*BBC*/ /*BBS*/
772177c1 2797 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91 2798 {
7ff7563f
MF		 2799#ifdef TARGET_WORDS_BIGENDIAN
2800 TCGv_i32 bit = tcg_const_i32(0x80000000);
2801#else
2802 TCGv_i32 bit = tcg_const_i32(0x00000001);
2803#endif
bd57fb91
MF		 2804 TCGv_i32 tmp = tcg_temp_new_i32();
2805 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
7ff7563f
MF		 2806#ifdef TARGET_WORDS_BIGENDIAN
2807 tcg_gen_shr_i32(bit, bit, tmp);
2808#else
bd57fb91 2809 tcg_gen_shl_i32(bit, bit, tmp);
7ff7563f 2810#endif
bd57fb91
MF		 2811 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2812 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2813 tcg_temp_free(tmp);
2814 tcg_temp_free(bit);
2815 }
2816 break;
2817
2818 case 6: /*BBCI*/ /*BBSI*/
2819 case 7:
772177c1 2820 gen_window_check1(dc, RRI8_S);
bd57fb91
MF		 2821 {
2822 TCGv_i32 tmp = tcg_temp_new_i32();
2823 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
7ff7563f
MF		 2824#ifdef TARGET_WORDS_BIGENDIAN
2825 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2826#else
2827 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2828#endif
bd57fb91
MF		 2829 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2830 tcg_temp_free(tmp);
2831 }
2832 break;
2833
2834 }
2835 }
dedc5eae
MF		 2836 break;
2837
67882fd1
MF		 2838#define gen_narrow_load_store(type) do { \
2839 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2840 gen_window_check2(dc, RRRN_S, RRRN_T); \
67882fd1 2841 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
5b4e481b 2842 gen_load_store_alignment(dc, 2, addr, false); \
f0a548b9 2843 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
67882fd1
MF		 2844 tcg_temp_free(addr); \
2845 } while (0)
2846
dedc5eae 2847 case 8: /*L32I.Nn*/
67882fd1 2848 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2849 break;
2850
2851 case 9: /*S32I.Nn*/
67882fd1 2852 gen_narrow_load_store(st32);
dedc5eae 2853 break;
67882fd1 2854#undef gen_narrow_load_store
dedc5eae
MF		 2855
2856 case 10: /*ADD.Nn*/
772177c1 2857 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
67882fd1 2858 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae
MF		 2859 break;
2860
2861 case 11: /*ADDI.Nn*/
772177c1 2862 gen_window_check2(dc, RRRN_R, RRRN_S);
67882fd1 2863 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae
MF		 2864 break;
2865
2866 case 12: /*ST2n*/
772177c1 2867 gen_window_check1(dc, RRRN_S);
67882fd1
MF		 2868 if (RRRN_T < 8) { /*MOVI.Nn*/
2869 tcg_gen_movi_i32(cpu_R[RRRN_S],
2870 RRRN_R | (RRRN_T << 4) |
2871 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2872 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 2873 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2874
2875 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2876 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 2877 }
dedc5eae
MF		 2878 break;
2879
2880 case 13: /*ST3n*/
67882fd1
MF		 2881 switch (RRRN_R) {
2882 case 0: /*MOV.Nn*/
772177c1 2883 gen_window_check2(dc, RRRN_S, RRRN_T);
67882fd1
MF		 2884 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2885 break;
2886
2887 case 15: /*S3*/
2888 switch (RRRN_T) {
2889 case 0: /*RET.Nn*/
2890 gen_jump(dc, cpu_R[0]);
2891 break;
2892
2893 case 1: /*RETW.Nn*/
91a5bb76 2894 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2895 {
2896 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 2897 gen_advance_ccount(dc);
f492b82d 2898 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 2899 gen_jump(dc, tmp);
2900 tcg_temp_free(tmp);
2901 }
67882fd1
MF		 2902 break;
2903
2904 case 2: /*BREAK.Nn*/
e61dc8f7
MF		 2905 HAS_OPTION(XTENSA_OPTION_DEBUG);
2906 if (dc->debug) {
2907 gen_debug_exception(dc, DEBUGCAUSE_BN);
2908 }
67882fd1
MF		 2909 break;
2910
2911 case 3: /*NOP.Nn*/
2912 break;
2913
2914 case 6: /*ILL.Nn*/
40643d7c 2915 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 2916 break;
2917
2918 default: /*reserved*/
91a5bb76 2919 RESERVED();
67882fd1
MF		 2920 break;
2921 }
2922 break;
2923
2924 default: /*reserved*/
91a5bb76 2925 RESERVED();
67882fd1
MF		 2926 break;
2927 }
dedc5eae
MF		 2928 break;
2929
2930 default: /*reserved*/
91a5bb76 2931 RESERVED();
dedc5eae
MF		 2932 break;
2933 }
2934
c26032b2
MF		 2935 if (dc->is_jmp == DISAS_NEXT) {
2936 gen_check_loop_end(dc, 0);
2937 }
dedc5eae 2938 dc->pc = dc->next_pc;
797d780b 2939
dedc5eae
MF		 2940 return;
2941
2942invalid_opcode:
2943 qemu_log("INVALID(pc = %08x)\n", dc->pc);
6b814719 2944 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dedc5eae
MF		 2945#undef HAS_OPTION
2946}
2947
97129ac8 2948static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
dedc5eae 2949{
f0c3c505 2950 CPUState *cs = CPU(xtensa_env_get_cpu(env));
dedc5eae
MF		 2951 CPUBreakpoint *bp;
2952
f0c3c505
AF		 2953 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
2954 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
dedc5eae
MF		 2955 if (bp->pc == dc->pc) {
2956 tcg_gen_movi_i32(cpu_pc, dc->pc);
b994e91b 2957 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 2958 dc->is_jmp = DISAS_UPDATE;
2959 }
2960 }
2961 }
2962}
2963
97129ac8 2964static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
e61dc8f7
MF		 2965{
2966 unsigned i;
2967
2968 for (i = 0; i < dc->config->nibreak; ++i) {
2969 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2970 env->sregs[IBREAKA + i] == dc->pc) {
2971 gen_debug_exception(dc, DEBUGCAUSE_IB);
2972 break;
2973 }
2974 }
2975}
2976
ae06d498 2977static inline
90b85b77
AF		 2978void gen_intermediate_code_internal(XtensaCPU *cpu,
2979 TranslationBlock *tb, bool search_pc)
dedc5eae 2980{
ed2803da 2981 CPUState *cs = CPU(cpu);
90b85b77 2982 CPUXtensaState *env = &cpu->env;
dedc5eae
MF		 2983 DisasContext dc;
2984 int insn_count = 0;
2985 int j, lj = -1;
92414b31 2986 uint16_t *gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
dedc5eae
MF		 2987 int max_insns = tb->cflags & CF_COUNT_MASK;
2988 uint32_t pc_start = tb->pc;
2989 uint32_t next_page_start =
2990 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2991
2992 if (max_insns == 0) {
2993 max_insns = CF_COUNT_MASK;
2994 }
2995
2996 dc.config = env->config;
ed2803da 2997 dc.singlestep_enabled = cs->singlestep_enabled;
dedc5eae
MF		 2998 dc.tb = tb;
2999 dc.pc = pc_start;
f0a548b9
MF		 3000 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3001 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 3002 dc.lbeg = env->sregs[LBEG];
3003 dc.lend = env->sregs[LEND];
dedc5eae 3004 dc.is_jmp = DISAS_NEXT;
b994e91b 3005 dc.ccount_delta = 0;
e61dc8f7 3006 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
35b5c044 3007 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
ef04a846
MF		 3008 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3009 XTENSA_TBFLAG_CPENABLE_SHIFT;
dedc5eae 3010
6ad6dbf7 3011 init_litbase(&dc);
3580ecad 3012 init_sar_tracker(&dc);
772177c1 3013 reset_used_window(&dc);
35b5c044
MF		 3014 if (dc.icount) {
3015 dc.next_icount = tcg_temp_local_new_i32();
3016 }
3580ecad 3017
806f352d 3018 gen_tb_start();
dedc5eae 3019
a00817cc 3020 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
40643d7c 3021 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 3022 gen_exception(&dc, EXCP_DEBUG);
40643d7c
MF		 3023 }
3024
dedc5eae
MF		 3025 do {
3026 check_breakpoint(env, &dc);
3027
3028 if (search_pc) {
92414b31 3029 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
dedc5eae
MF		 3030 if (lj < j) {
3031 lj++;
3032 while (lj < j) {
ab1103de 3033 tcg_ctx.gen_opc_instr_start[lj++] = 0;
dedc5eae
MF		 3034 }
3035 }
25983cad 3036 tcg_ctx.gen_opc_pc[lj] = dc.pc;
ab1103de 3037 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 3038 tcg_ctx.gen_opc_icount[lj] = insn_count;
dedc5eae
MF		 3039 }
3040
fdefe51c 3041 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
dedc5eae
MF		 3042 tcg_gen_debug_insn_start(dc.pc);
3043 }
3044
b994e91b
MF		 3045 ++dc.ccount_delta;
3046
3047 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
3048 gen_io_start();
3049 }
3050
35b5c044
MF		 3051 if (dc.icount) {
3052 int label = gen_new_label();
3053
3054 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3055 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3056 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3057 if (dc.debug) {
3058 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3059 }
3060 gen_set_label(label);
3061 }
3062
e61dc8f7
MF		 3063 if (dc.debug) {
3064 gen_ibreak_check(env, &dc);
3065 }
3066
0c4fabea 3067 disas_xtensa_insn(env, &dc);
dedc5eae 3068 ++insn_count;
35b5c044
MF		 3069 if (dc.icount) {
3070 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3071 }
ed2803da 3072 if (cs->singlestep_enabled) {
dedc5eae 3073 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 3074 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 3075 break;
3076 }
3077 } while (dc.is_jmp == DISAS_NEXT &&
3078 insn_count < max_insns &&
3079 dc.pc < next_page_start &&
efd7f486 3080 tcg_ctx.gen_opc_ptr < gen_opc_end);
dedc5eae 3081
6ad6dbf7 3082 reset_litbase(&dc);
3580ecad 3083 reset_sar_tracker(&dc);
35b5c044
MF		 3084 if (dc.icount) {
3085 tcg_temp_free(dc.next_icount);
3086 }
3580ecad 3087
b994e91b
MF		 3088 if (tb->cflags & CF_LAST_IO) {
3089 gen_io_end();
3090 }
3091
dedc5eae
MF		 3092 if (dc.is_jmp == DISAS_NEXT) {
3093 gen_jumpi(&dc, dc.pc, 0);
3094 }
806f352d 3095 gen_tb_end(tb, insn_count);
efd7f486 3096 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
dedc5eae 3097
ca529f8e
MF		 3098#ifdef DEBUG_DISAS
3099 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3100 qemu_log("----------------\n");
3101 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3102 log_target_disas(env, pc_start, dc.pc - pc_start, 0);
3103 qemu_log("\n");
3104 }
3105#endif
36f25d25
MF		 3106 if (search_pc) {
3107 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3108 memset(tcg_ctx.gen_opc_instr_start + lj + 1, 0,
3109 (j - lj) * sizeof(tcg_ctx.gen_opc_instr_start[0]));
3110 } else {
dedc5eae
MF		 3111 tb->size = dc.pc - pc_start;
3112 tb->icount = insn_count;
3113 }
2328826b
MF		 3114}
3115
97129ac8 3116void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
2328826b 3117{
90b85b77 3118 gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, false);
2328826b
MF		 3119}
3120
97129ac8 3121void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
2328826b 3122{
90b85b77 3123 gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, true);
2328826b
MF		 3124}
3125
878096ee
AF		 3126void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3127 fprintf_function cpu_fprintf, int flags)
2328826b 3128{
878096ee
AF		 3129 XtensaCPU *cpu = XTENSA_CPU(cs);
3130 CPUXtensaState *env = &cpu->env;
2af3da91
MF		 3131 int i, j;
3132
3133 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3134
3135 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3136 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3137 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
2af3da91
MF		 3138 (j++ % 4) == 3 ? '\n' : ' ');
3139 }
3140 }
3141
3142 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3143
3144 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3145 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3146 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
2af3da91
MF		 3147 (j++ % 4) == 3 ? '\n' : ' ');
3148 }
3149 }
2328826b 3150
2af3da91 3151 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 3152
3153 for (i = 0; i < 16; ++i) {
fe0bd475 3154 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
2328826b
MF		 3155 (i % 4) == 3 ? '\n' : ' ');
3156 }
553e44f9
MF		 3157
3158 cpu_fprintf(f, "\n");
3159
3160 for (i = 0; i < env->config->nareg; ++i) {
3161 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3162 (i % 4) == 3 ? '\n' : ' ');
3163 }
dd519cbe
MF		 3164
3165 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3166 cpu_fprintf(f, "\n");
3167
3168 for (i = 0; i < 16; ++i) {
3169 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3170 float32_val(env->fregs[i]),
3171 *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
3172 }
3173 }
2328826b
MF		 3174}
3175
97129ac8 3176void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
2328826b 3177{
25983cad 3178 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
2328826b 3179}
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