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Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging
[mirror_qemu.git] / target-xtensa / translate.c
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2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
022c62cb 34#include "exec/exec-all.h"
76cad711 35#include "disas/disas.h"
2328826b 36#include "tcg-op.h"
1de7afc9 37#include "qemu/log.h"
9c17d615 38#include "sysemu/sysemu.h"
f08b6170 39#include "exec/cpu_ldst.h"
cfe67cef 40#include "exec/semihost.h"
2328826b 41
2ef6175a
RH		 42#include "exec/helper-proto.h"
43#include "exec/helper-gen.h"
dedc5eae 44
a7e30d84
LV		 45#include "trace-tcg.h"
46
47
dedc5eae
MF		 48typedef struct DisasContext {
49 const XtensaConfig *config;
50 TranslationBlock *tb;
51 uint32_t pc;
52 uint32_t next_pc;
f0a548b9
MF		 53 int cring;
54 int ring;
797d780b
MF		 55 uint32_t lbeg;
56 uint32_t lend;
6ad6dbf7 57 TCGv_i32 litbase;
dedc5eae
MF		 58 int is_jmp;
59 int singlestep_enabled;
3580ecad
MF		 60
61 bool sar_5bit;
62 bool sar_m32_5bit;
63 bool sar_m32_allocated;
64 TCGv_i32 sar_m32;
b994e91b
MF		 65
66 uint32_t ccount_delta;
2db59a76 67 unsigned window;
e61dc8f7
MF		 68
69 bool debug;
35b5c044
MF		 70 bool icount;
71 TCGv_i32 next_icount;
ef04a846
MF		 72
73 unsigned cpenable;
dedc5eae
MF		 74} DisasContext;
75
76static TCGv_ptr cpu_env;
77static TCGv_i32 cpu_pc;
78static TCGv_i32 cpu_R[16];
dd519cbe 79static TCGv_i32 cpu_FR[16];
2af3da91
MF		 80static TCGv_i32 cpu_SR[256];
81static TCGv_i32 cpu_UR[256];
dedc5eae 82
022c62cb 83#include "exec/gen-icount.h"
2328826b 84
fe0bd475
MF		 85typedef struct XtensaReg {
86 const char *name;
87 uint64_t opt_bits;
53593e90
MF		 88 enum {
89 SR_R = 1,
90 SR_W = 2,
91 SR_X = 4,
92 SR_RW = 3,
93 SR_RWX = 7,
94 } access;
fe0bd475
MF		 95} XtensaReg;
96
53593e90 97#define XTENSA_REG_ACCESS(regname, opt, acc) { \
fe0bd475
MF		 98 .name = (regname), \
99 .opt_bits = XTENSA_OPTION_BIT(opt), \
53593e90 100 .access = (acc), \
fe0bd475
MF		 101 }
102
53593e90
MF		 103#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
104
604e1f9c 105#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
fe0bd475
MF		 106 .name = (regname), \
107 .opt_bits = (opt), \
604e1f9c 108 .access = (acc), \
fe0bd475
MF		 109 }
110
604e1f9c
MF		 111#define XTENSA_REG_BITS(regname, opt) \
112 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
113
fe0bd475
MF		 114static const XtensaReg sregnames[256] = {
115 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
116 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
117 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
118 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
119 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
120 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
121 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
122 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
123 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
124 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
125 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
126 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
127 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
128 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
129 [WINDOW_START] = XTENSA_REG("WINDOW_START",
130 XTENSA_OPTION_WINDOWED_REGISTER),
131 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
132 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
133 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
134 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
135 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
136 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
137 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
138 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
139 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
140 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
141 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
142 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
143 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
604e1f9c 144 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
fe0bd475
MF		 145 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
146 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
147 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
148 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
152 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
153 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
154 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
155 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
157 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
604e1f9c 159 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
fe0bd475
MF		 160 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
161 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
162 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
163 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
164 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
165 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
166 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
167 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
168 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
169 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
170 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
171 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
172 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
173 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
53593e90
MF		 174 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
175 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
fe0bd475
MF		 176 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
177 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
178 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
179 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
53593e90 180 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
fe0bd475 181 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
53593e90 182 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
fe0bd475
MF		 183 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
184 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
185 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
186 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
187 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
188 XTENSA_OPTION_TIMER_INTERRUPT),
189 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
190 XTENSA_OPTION_TIMER_INTERRUPT),
b7909d81
MF		 191 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
192 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
193 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
194 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
2af3da91
MF		 195};
196
fe0bd475
MF		 197static const XtensaReg uregnames[256] = {
198 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
199 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
200 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
2af3da91
MF		 201};
202
2328826b
MF		 203void xtensa_translate_init(void)
204{
dedc5eae
MF		 205 static const char * const regnames[] = {
206 "ar0", "ar1", "ar2", "ar3",
207 "ar4", "ar5", "ar6", "ar7",
208 "ar8", "ar9", "ar10", "ar11",
209 "ar12", "ar13", "ar14", "ar15",
210 };
dd519cbe
MF		 211 static const char * const fregnames[] = {
212 "f0", "f1", "f2", "f3",
213 "f4", "f5", "f6", "f7",
214 "f8", "f9", "f10", "f11",
215 "f12", "f13", "f14", "f15",
216 };
dedc5eae
MF		 217 int i;
218
219 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
220 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 221 offsetof(CPUXtensaState, pc), "pc");
dedc5eae
MF		 222
223 for (i = 0; i < 16; i++) {
224 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 225 offsetof(CPUXtensaState, regs[i]),
dedc5eae
MF		 226 regnames[i]);
227 }
2af3da91 228
dd519cbe
MF		 229 for (i = 0; i < 16; i++) {
230 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
ddd44279 231 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
dd519cbe
MF		 232 fregnames[i]);
233 }
234
2af3da91 235 for (i = 0; i < 256; ++i) {
fe0bd475 236 if (sregnames[i].name) {
2af3da91 237 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 238 offsetof(CPUXtensaState, sregs[i]),
fe0bd475 239 sregnames[i].name);
2af3da91
MF		 240 }
241 }
242
243 for (i = 0; i < 256; ++i) {
fe0bd475 244 if (uregnames[i].name) {
2af3da91 245 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 246 offsetof(CPUXtensaState, uregs[i]),
fe0bd475 247 uregnames[i].name);
2af3da91
MF		 248 }
249 }
dedc5eae
MF		 250}
251
b67ea0cd
MF		 252static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
253{
254 return xtensa_option_bits_enabled(dc->config, opt);
255}
256
dedc5eae
MF		 257static inline bool option_enabled(DisasContext *dc, int opt)
258{
259 return xtensa_option_enabled(dc->config, opt);
260}
261
6ad6dbf7
MF		 262static void init_litbase(DisasContext *dc)
263{
264 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
265 dc->litbase = tcg_temp_local_new_i32();
266 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
267 }
268}
269
270static void reset_litbase(DisasContext *dc)
271{
272 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
273 tcg_temp_free(dc->litbase);
274 }
275}
276
3580ecad
MF		 277static void init_sar_tracker(DisasContext *dc)
278{
279 dc->sar_5bit = false;
280 dc->sar_m32_5bit = false;
281 dc->sar_m32_allocated = false;
282}
283
284static void reset_sar_tracker(DisasContext *dc)
285{
286 if (dc->sar_m32_allocated) {
287 tcg_temp_free(dc->sar_m32);
288 }
289}
290
291static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
292{
293 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
294 if (dc->sar_m32_5bit) {
295 tcg_gen_discard_i32(dc->sar_m32);
296 }
297 dc->sar_5bit = true;
298 dc->sar_m32_5bit = false;
299}
300
301static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
302{
303 TCGv_i32 tmp = tcg_const_i32(32);
304 if (!dc->sar_m32_allocated) {
305 dc->sar_m32 = tcg_temp_local_new_i32();
306 dc->sar_m32_allocated = true;
307 }
308 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
309 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
310 dc->sar_5bit = false;
311 dc->sar_m32_5bit = true;
312 tcg_temp_free(tmp);
313}
314
2db59a76 315static void gen_advance_ccount(DisasContext *dc)
b994e91b
MF		 316{
317 if (dc->ccount_delta > 0) {
318 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
f492b82d 319 gen_helper_advance_ccount(cpu_env, tmp);
b994e91b
MF		 320 tcg_temp_free(tmp);
321 }
908c67fc
MF		 322 dc->ccount_delta = 0;
323}
324
b994e91b 325static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 326{
327 TCGv_i32 tmp = tcg_const_i32(excp);
b994e91b 328 gen_advance_ccount(dc);
f492b82d 329 gen_helper_exception(cpu_env, tmp);
dedc5eae
MF		 330 tcg_temp_free(tmp);
331}
332
40643d7c
MF		 333static void gen_exception_cause(DisasContext *dc, uint32_t cause)
334{
335 TCGv_i32 tpc = tcg_const_i32(dc->pc);
336 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 337 gen_advance_ccount(dc);
f492b82d 338 gen_helper_exception_cause(cpu_env, tpc, tcause);
40643d7c
MF		 339 tcg_temp_free(tpc);
340 tcg_temp_free(tcause);
6b814719
MF		 341 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
342 cause == SYSCALL_CAUSE) {
343 dc->is_jmp = DISAS_UPDATE;
344 }
40643d7c
MF		 345}
346
5b4e481b
MF		 347static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
348 TCGv_i32 vaddr)
349{
350 TCGv_i32 tpc = tcg_const_i32(dc->pc);
351 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 352 gen_advance_ccount(dc);
f492b82d 353 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
5b4e481b
MF		 354 tcg_temp_free(tpc);
355 tcg_temp_free(tcause);
356}
357
e61dc8f7
MF		 358static void gen_debug_exception(DisasContext *dc, uint32_t cause)
359{
360 TCGv_i32 tpc = tcg_const_i32(dc->pc);
361 TCGv_i32 tcause = tcg_const_i32(cause);
362 gen_advance_ccount(dc);
f492b82d 363 gen_helper_debug_exception(cpu_env, tpc, tcause);
e61dc8f7
MF		 364 tcg_temp_free(tpc);
365 tcg_temp_free(tcause);
366 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
367 dc->is_jmp = DISAS_UPDATE;
368 }
369}
370
97e89ee9 371static bool gen_check_privilege(DisasContext *dc)
40643d7c
MF		 372{
373 if (dc->cring) {
374 gen_exception_cause(dc, PRIVILEGED_CAUSE);
6b814719 375 dc->is_jmp = DISAS_UPDATE;
97e89ee9 376 return false;
40643d7c 377 }
97e89ee9 378 return true;
40643d7c
MF		 379}
380
97e89ee9 381static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
ef04a846
MF		 382{
383 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
384 !(dc->cpenable & (1 << cp))) {
385 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
386 dc->is_jmp = DISAS_UPDATE;
97e89ee9 387 return false;
ef04a846 388 }
97e89ee9 389 return true;
ef04a846
MF		 390}
391
dedc5eae
MF		 392static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
393{
394 tcg_gen_mov_i32(cpu_pc, dest);
35b5c044
MF		 395 gen_advance_ccount(dc);
396 if (dc->icount) {
397 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
398 }
dedc5eae 399 if (dc->singlestep_enabled) {
b994e91b 400 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 401 } else {
402 if (slot >= 0) {
403 tcg_gen_goto_tb(slot);
8cfd0495 404 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
dedc5eae
MF		 405 } else {
406 tcg_gen_exit_tb(0);
407 }
408 }
409 dc->is_jmp = DISAS_UPDATE;
410}
411
67882fd1
MF		 412static void gen_jump(DisasContext *dc, TCGv dest)
413{
414 gen_jump_slot(dc, dest, -1);
415}
416
dedc5eae
MF		 417static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
418{
419 TCGv_i32 tmp = tcg_const_i32(dest);
433d33c5 420 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
dedc5eae
MF		 421 slot = -1;
422 }
423 gen_jump_slot(dc, tmp, slot);
424 tcg_temp_free(tmp);
425}
426
553e44f9
MF		 427static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
428 int slot)
429{
430 TCGv_i32 tcallinc = tcg_const_i32(callinc);
431
432 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
433 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
434 tcg_temp_free(tcallinc);
435 tcg_gen_movi_i32(cpu_R[callinc << 2],
436 (callinc << 30) | (dc->next_pc & 0x3fffffff));
437 gen_jump_slot(dc, dest, slot);
438}
439
440static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
441{
442 gen_callw_slot(dc, callinc, dest, -1);
443}
444
445static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
446{
447 TCGv_i32 tmp = tcg_const_i32(dest);
433d33c5 448 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
553e44f9
MF		 449 slot = -1;
450 }
451 gen_callw_slot(dc, callinc, tmp, slot);
452 tcg_temp_free(tmp);
453}
454
797d780b
MF		 455static bool gen_check_loop_end(DisasContext *dc, int slot)
456{
457 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
458 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
459 dc->next_pc == dc->lend) {
42a268c2 460 TCGLabel *label = gen_new_label();
797d780b 461
d865f307 462 gen_advance_ccount(dc);
797d780b
MF		 463 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
464 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
465 gen_jumpi(dc, dc->lbeg, slot);
466 gen_set_label(label);
467 gen_jumpi(dc, dc->next_pc, -1);
468 return true;
469 }
470 return false;
471}
472
473static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
474{
475 if (!gen_check_loop_end(dc, slot)) {
476 gen_jumpi(dc, dc->next_pc, slot);
477 }
478}
479
bd57fb91
MF		 480static void gen_brcond(DisasContext *dc, TCGCond cond,
481 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
482{
42a268c2 483 TCGLabel *label = gen_new_label();
bd57fb91 484
d865f307 485 gen_advance_ccount(dc);
bd57fb91 486 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 487 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 488 gen_set_label(label);
489 gen_jumpi(dc, dc->pc + offset, 1);
490}
491
492static void gen_brcondi(DisasContext *dc, TCGCond cond,
493 TCGv_i32 t0, uint32_t t1, uint32_t offset)
494{
495 TCGv_i32 tmp = tcg_const_i32(t1);
496 gen_brcond(dc, cond, t0, tmp, offset);
497 tcg_temp_free(tmp);
498}
499
0857a06e 500static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
fe0bd475
MF		 501{
502 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
503 if (sregnames[sr].name) {
504 qemu_log("SR %s is not configured\n", sregnames[sr].name);
505 } else {
506 qemu_log("SR %d is not implemented\n", sr);
507 }
508 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
0857a06e 509 return false;
53593e90
MF		 510 } else if (!(sregnames[sr].access & access)) {
511 static const char * const access_text[] = {
512 [SR_R] = "rsr",
513 [SR_W] = "wsr",
514 [SR_X] = "xsr",
515 };
516 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
517 qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
518 access_text[access]);
519 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
0857a06e 520 return false;
fe0bd475 521 }
0857a06e 522 return true;
fe0bd475
MF		 523}
524
b994e91b
MF		 525static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
526{
527 gen_advance_ccount(dc);
528 tcg_gen_mov_i32(d, cpu_SR[sr]);
529}
530
b67ea0cd
MF		 531static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
532{
533 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
534 tcg_gen_or_i32(d, d, cpu_SR[sr]);
535 tcg_gen_andi_i32(d, d, 0xfffffffc);
536}
537
b8132eff
MF		 538static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
539{
540 static void (* const rsr_handler[256])(DisasContext *dc,
541 TCGv_i32 d, uint32_t sr) = {
b994e91b 542 [CCOUNT] = gen_rsr_ccount,
b67ea0cd 543 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 544 };
545
fe0bd475
MF		 546 if (rsr_handler[sr]) {
547 rsr_handler[sr](dc, d, sr);
b8132eff 548 } else {
fe0bd475 549 tcg_gen_mov_i32(d, cpu_SR[sr]);
b8132eff
MF		 550 }
551}
552
797d780b
MF		 553static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
554{
f492b82d 555 gen_helper_wsr_lbeg(cpu_env, s);
3d0be8a5 556 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 557}
558
559static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
560{
f492b82d 561 gen_helper_wsr_lend(cpu_env, s);
3d0be8a5 562 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 563}
564
3580ecad
MF		 565static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
566{
567 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
568 if (dc->sar_m32_5bit) {
569 tcg_gen_discard_i32(dc->sar_m32);
570 }
571 dc->sar_5bit = false;
572 dc->sar_m32_5bit = false;
573}
574
4dd85b6b
MF		 575static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
576{
577 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
578}
579
6ad6dbf7
MF		 580static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
581{
582 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
583 /* This can change tb->flags, so exit tb */
584 gen_jumpi_check_loop_end(dc, -1);
585}
586
6825b6c3
MF		 587static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
588{
589 tcg_gen_ext8s_i32(cpu_SR[sr], s);
590}
591
553e44f9
MF		 592static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
593{
f492b82d 594 gen_helper_wsr_windowbase(cpu_env, v);
2db59a76
MF		 595 /* This can change tb->flags, so exit tb */
596 gen_jumpi_check_loop_end(dc, -1);
772177c1
MF		 597}
598
599static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
600{
53a72dfd 601 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
2db59a76
MF		 602 /* This can change tb->flags, so exit tb */
603 gen_jumpi_check_loop_end(dc, -1);
553e44f9
MF		 604}
605
b67ea0cd
MF		 606static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
607{
608 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
609}
610
611static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
612{
f492b82d 613 gen_helper_wsr_rasid(cpu_env, v);
b67ea0cd
MF		 614 /* This can change tb->flags, so exit tb */
615 gen_jumpi_check_loop_end(dc, -1);
616}
617
618static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
619{
620 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
621}
622
e61dc8f7
MF		 623static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
624{
f492b82d 625 gen_helper_wsr_ibreakenable(cpu_env, v);
e61dc8f7
MF		 626 gen_jumpi_check_loop_end(dc, 0);
627}
628
fcc803d1
MF		 629static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
630{
631 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
632}
633
e61dc8f7
MF		 634static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
635{
636 unsigned id = sr - IBREAKA;
637
638 if (id < dc->config->nibreak) {
639 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 640 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
e61dc8f7
MF		 641 tcg_temp_free(tmp);
642 gen_jumpi_check_loop_end(dc, 0);
643 }
644}
645
f14c4b5f
MF		 646static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
647{
648 unsigned id = sr - DBREAKA;
649
650 if (id < dc->config->ndbreak) {
651 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 652 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
f14c4b5f
MF		 653 tcg_temp_free(tmp);
654 }
655}
656
657static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
658{
659 unsigned id = sr - DBREAKC;
660
661 if (id < dc->config->ndbreak) {
662 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 663 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
f14c4b5f
MF		 664 tcg_temp_free(tmp);
665 }
666}
667
ef04a846
MF		 668static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
669{
670 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
671 /* This can change tb->flags, so exit tb */
672 gen_jumpi_check_loop_end(dc, -1);
673}
674
b994e91b
MF		 675static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
676{
677 tcg_gen_andi_i32(cpu_SR[sr], v,
678 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
679 gen_helper_check_interrupts(cpu_env);
680 gen_jumpi_check_loop_end(dc, 0);
681}
682
683static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
684{
685 TCGv_i32 tmp = tcg_temp_new_i32();
686
687 tcg_gen_andi_i32(tmp, v,
688 dc->config->inttype_mask[INTTYPE_EDGE] |
689 dc->config->inttype_mask[INTTYPE_NMI] |
690 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
691 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
692 tcg_temp_free(tmp);
693 gen_helper_check_interrupts(cpu_env);
694}
695
696static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
697{
698 tcg_gen_mov_i32(cpu_SR[sr], v);
699 gen_helper_check_interrupts(cpu_env);
700 gen_jumpi_check_loop_end(dc, 0);
701}
702
f0a548b9
MF		 703static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
704{
705 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
706 PS_UM | PS_EXCM | PS_INTLEVEL;
707
708 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
709 mask |= PS_RING;
710 }
711 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
b994e91b
MF		 712 gen_helper_check_interrupts(cpu_env);
713 /* This can change mmu index and tb->flags, so exit tb */
797d780b 714 gen_jumpi_check_loop_end(dc, -1);
f0a548b9
MF		 715}
716
35b5c044
MF		 717static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
718{
719 if (dc->icount) {
720 tcg_gen_mov_i32(dc->next_icount, v);
721 } else {
722 tcg_gen_mov_i32(cpu_SR[sr], v);
723 }
724}
725
726static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
727{
728 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
729 /* This can change tb->flags, so exit tb */
730 gen_jumpi_check_loop_end(dc, -1);
731}
732
b994e91b
MF		 733static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
734{
735 uint32_t id = sr - CCOMPARE;
736 if (id < dc->config->nccompare) {
737 uint32_t int_bit = 1 << dc->config->timerint[id];
738 gen_advance_ccount(dc);
739 tcg_gen_mov_i32(cpu_SR[sr], v);
740 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
741 gen_helper_check_interrupts(cpu_env);
742 }
743}
744
b8132eff
MF		 745static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
746{
747 static void (* const wsr_handler[256])(DisasContext *dc,
748 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 749 [LBEG] = gen_wsr_lbeg,
750 [LEND] = gen_wsr_lend,
3580ecad 751 [SAR] = gen_wsr_sar,
4dd85b6b 752 [BR] = gen_wsr_br,
6ad6dbf7 753 [LITBASE] = gen_wsr_litbase,
6825b6c3 754 [ACCHI] = gen_wsr_acchi,
553e44f9 755 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 756 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 757 [PTEVADDR] = gen_wsr_ptevaddr,
758 [RASID] = gen_wsr_rasid,
759 [ITLBCFG] = gen_wsr_tlbcfg,
760 [DTLBCFG] = gen_wsr_tlbcfg,
e61dc8f7 761 [IBREAKENABLE] = gen_wsr_ibreakenable,
fcc803d1 762 [ATOMCTL] = gen_wsr_atomctl,
e61dc8f7
MF		 763 [IBREAKA] = gen_wsr_ibreaka,
764 [IBREAKA + 1] = gen_wsr_ibreaka,
f14c4b5f
MF		 765 [DBREAKA] = gen_wsr_dbreaka,
766 [DBREAKA + 1] = gen_wsr_dbreaka,
767 [DBREAKC] = gen_wsr_dbreakc,
768 [DBREAKC + 1] = gen_wsr_dbreakc,
ef04a846 769 [CPENABLE] = gen_wsr_cpenable,
b994e91b
MF		 770 [INTSET] = gen_wsr_intset,
771 [INTCLEAR] = gen_wsr_intclear,
772 [INTENABLE] = gen_wsr_intenable,
f0a548b9 773 [PS] = gen_wsr_ps,
35b5c044
MF		 774 [ICOUNT] = gen_wsr_icount,
775 [ICOUNTLEVEL] = gen_wsr_icountlevel,
b994e91b
MF		 776 [CCOMPARE] = gen_wsr_ccompare,
777 [CCOMPARE + 1] = gen_wsr_ccompare,
778 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 779 };
780
fe0bd475
MF		 781 if (wsr_handler[sr]) {
782 wsr_handler[sr](dc, sr, s);
b8132eff 783 } else {
fe0bd475 784 tcg_gen_mov_i32(cpu_SR[sr], s);
b8132eff
MF		 785 }
786}
787
dd519cbe
MF		 788static void gen_wur(uint32_t ur, TCGv_i32 s)
789{
790 switch (ur) {
791 case FCR:
792 gen_helper_wur_fcr(cpu_env, s);
793 break;
794
795 case FSR:
796 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
797 break;
798
799 default:
800 tcg_gen_mov_i32(cpu_UR[ur], s);
801 break;
802 }
803}
804
5b4e481b
MF		 805static void gen_load_store_alignment(DisasContext *dc, int shift,
806 TCGv_i32 addr, bool no_hw_alignment)
807{
808 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
809 tcg_gen_andi_i32(addr, addr, ~0 << shift);
810 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
811 no_hw_alignment) {
42a268c2 812 TCGLabel *label = gen_new_label();
5b4e481b
MF		 813 TCGv_i32 tmp = tcg_temp_new_i32();
814 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
815 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
816 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
817 gen_set_label(label);
818 tcg_temp_free(tmp);
819 }
820}
821
b994e91b
MF		 822static void gen_waiti(DisasContext *dc, uint32_t imm4)
823{
824 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
825 TCGv_i32 intlevel = tcg_const_i32(imm4);
826 gen_advance_ccount(dc);
f492b82d 827 gen_helper_waiti(cpu_env, pc, intlevel);
b994e91b
MF		 828 tcg_temp_free(pc);
829 tcg_temp_free(intlevel);
830}
831
97e89ee9 832static bool gen_window_check1(DisasContext *dc, unsigned r1)
772177c1 833{
2db59a76
MF		 834 if (r1 / 4 > dc->window) {
835 TCGv_i32 pc = tcg_const_i32(dc->pc);
836 TCGv_i32 w = tcg_const_i32(r1 / 4);
908c67fc 837
2db59a76
MF		 838 gen_advance_ccount(dc);
839 gen_helper_window_check(cpu_env, pc, w);
840 dc->is_jmp = DISAS_UPDATE;
97e89ee9 841 return false;
772177c1 842 }
97e89ee9 843 return true;
772177c1
MF		 844}
845
97e89ee9 846static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
772177c1 847{
97e89ee9 848 return gen_window_check1(dc, r1 > r2 ? r1 : r2);
772177c1
MF		 849}
850
97e89ee9 851static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
772177c1
MF		 852 unsigned r3)
853{
97e89ee9 854 return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
772177c1
MF		 855}
856
6825b6c3
MF		 857static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
858{
859 TCGv_i32 m = tcg_temp_new_i32();
860
861 if (hi) {
862 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
863 } else {
864 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
865 }
866 return m;
867}
868
01673a34
MF		 869static inline unsigned xtensa_op0_insn_len(unsigned op0)
870{
871 return op0 >= 8 ? 2 : 3;
872}
873
0c4fabea 874static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
dedc5eae 875{
b67ea0cd
MF		 876#define HAS_OPTION_BITS(opt) do { \
877 if (!option_bits_enabled(dc, opt)) { \
878 qemu_log("Option is not enabled %s:%d\n", \
879 __FILE__, __LINE__); \
dedc5eae
MF		 880 goto invalid_opcode; \
881 } \
882 } while (0)
883
b67ea0cd
MF		 884#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
885
91a5bb76
MF		 886#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
887#define RESERVED() do { \
888 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
889 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
890 goto invalid_opcode; \
891 } while (0)
892
893
dedc5eae
MF		 894#ifdef TARGET_WORDS_BIGENDIAN
895#define OP0 (((b0) & 0xf0) >> 4)
896#define OP1 (((b2) & 0xf0) >> 4)
897#define OP2 ((b2) & 0xf)
898#define RRR_R ((b1) & 0xf)
899#define RRR_S (((b1) & 0xf0) >> 4)
900#define RRR_T ((b0) & 0xf)
901#else
902#define OP0 (((b0) & 0xf))
903#define OP1 (((b2) & 0xf))
904#define OP2 (((b2) & 0xf0) >> 4)
905#define RRR_R (((b1) & 0xf0) >> 4)
906#define RRR_S (((b1) & 0xf))
907#define RRR_T (((b0) & 0xf0) >> 4)
908#endif
6825b6c3
MF		 909#define RRR_X ((RRR_R & 0x4) >> 2)
910#define RRR_Y ((RRR_T & 0x4) >> 2)
911#define RRR_W (RRR_R & 0x3)
dedc5eae
MF		 912
913#define RRRN_R RRR_R
914#define RRRN_S RRR_S
915#define RRRN_T RRR_T
916
65026682
MF		 917#define RRI4_R RRR_R
918#define RRI4_S RRR_S
919#define RRI4_T RRR_T
920#ifdef TARGET_WORDS_BIGENDIAN
921#define RRI4_IMM4 ((b2) & 0xf)
922#else
923#define RRI4_IMM4 (((b2) & 0xf0) >> 4)
924#endif
925
dedc5eae
MF		 926#define RRI8_R RRR_R
927#define RRI8_S RRR_S
928#define RRI8_T RRR_T
929#define RRI8_IMM8 (b2)
930#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
931
932#ifdef TARGET_WORDS_BIGENDIAN
933#define RI16_IMM16 (((b1) << 8) | (b2))
934#else
935#define RI16_IMM16 (((b2) << 8) | (b1))
936#endif
937
938#ifdef TARGET_WORDS_BIGENDIAN
939#define CALL_N (((b0) & 0xc) >> 2)
940#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
941#else
942#define CALL_N (((b0) & 0x30) >> 4)
943#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
944#endif
945#define CALL_OFFSET_SE \
946 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
947
948#define CALLX_N CALL_N
949#ifdef TARGET_WORDS_BIGENDIAN
950#define CALLX_M ((b0) & 0x3)
951#else
952#define CALLX_M (((b0) & 0xc0) >> 6)
953#endif
954#define CALLX_S RRR_S
955
956#define BRI12_M CALLX_M
957#define BRI12_S RRR_S
958#ifdef TARGET_WORDS_BIGENDIAN
959#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
960#else
961#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
962#endif
963#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
964
965#define BRI8_M BRI12_M
966#define BRI8_R RRI8_R
967#define BRI8_S RRI8_S
968#define BRI8_IMM8 RRI8_IMM8
969#define BRI8_IMM8_SE RRI8_IMM8_SE
970
971#define RSR_SR (b1)
972
0c4fabea
BS		 973 uint8_t b0 = cpu_ldub_code(env, dc->pc);
974 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
a044ec2a 975 uint8_t b2 = 0;
01673a34 976 unsigned len = xtensa_op0_insn_len(OP0);
dedc5eae 977
bd57fb91
MF		 978 static const uint32_t B4CONST[] = {
979 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
980 };
981
982 static const uint32_t B4CONSTU[] = {
983 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
984 };
985
01673a34
MF		 986 switch (len) {
987 case 2:
dedc5eae 988 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
01673a34
MF		 989 break;
990
991 case 3:
0c4fabea 992 b2 = cpu_ldub_code(env, dc->pc + 2);
01673a34
MF		 993 break;
994
995 default:
996 RESERVED();
dedc5eae 997 }
01673a34 998 dc->next_pc = dc->pc + len;
dedc5eae
MF		 999
1000 switch (OP0) {
1001 case 0: /*QRST*/
1002 switch (OP1) {
1003 case 0: /*RST0*/
1004 switch (OP2) {
1005 case 0: /*ST0*/
1006 if ((RRR_R & 0xc) == 0x8) {
1007 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1008 }
1009
1010 switch (RRR_R) {
1011 case 0: /*SNM0*/
5da4a6a8
MF		 1012 switch (CALLX_M) {
1013 case 0: /*ILL*/
40643d7c 1014 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 1015 break;
1016
1017 case 1: /*reserved*/
91a5bb76 1018 RESERVED();
5da4a6a8
MF		 1019 break;
1020
1021 case 2: /*JR*/
1022 switch (CALLX_N) {
1023 case 0: /*RET*/
1024 case 2: /*JX*/
97e89ee9
MF		 1025 if (gen_window_check1(dc, CALLX_S)) {
1026 gen_jump(dc, cpu_R[CALLX_S]);
1027 }
5da4a6a8
MF		 1028 break;
1029
1030 case 1: /*RETWw*/
1031 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1032 {
1033 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 1034 gen_advance_ccount(dc);
f492b82d 1035 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 1036 gen_jump(dc, tmp);
1037 tcg_temp_free(tmp);
1038 }
5da4a6a8
MF		 1039 break;
1040
1041 case 3: /*reserved*/
91a5bb76 1042 RESERVED();
5da4a6a8
MF		 1043 break;
1044 }
1045 break;
1046
1047 case 3: /*CALLX*/
97e89ee9
MF		 1048 if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) {
1049 break;
1050 }
5da4a6a8
MF		 1051 switch (CALLX_N) {
1052 case 0: /*CALLX0*/
1053 {
1054 TCGv_i32 tmp = tcg_temp_new_i32();
1055 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1056 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1057 gen_jump(dc, tmp);
1058 tcg_temp_free(tmp);
1059 }
1060 break;
1061
1062 case 1: /*CALLX4w*/
1063 case 2: /*CALLX8w*/
1064 case 3: /*CALLX12w*/
1065 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1066 {
1067 TCGv_i32 tmp = tcg_temp_new_i32();
1068
1069 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1070 gen_callw(dc, CALLX_N, tmp);
1071 tcg_temp_free(tmp);
1072 }
5da4a6a8
MF		 1073 break;
1074 }
1075 break;
1076 }
dedc5eae
MF		 1077 break;
1078
1079 case 1: /*MOVSPw*/
1080 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9 1081 if (gen_window_check2(dc, RRR_T, RRR_S)) {
553e44f9 1082 TCGv_i32 pc = tcg_const_i32(dc->pc);
b994e91b 1083 gen_advance_ccount(dc);
f492b82d 1084 gen_helper_movsp(cpu_env, pc);
553e44f9
MF		 1085 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1086 tcg_temp_free(pc);
1087 }
dedc5eae
MF		 1088 break;
1089
1090 case 2: /*SYNC*/
28067b22
MF		 1091 switch (RRR_T) {
1092 case 0: /*ISYNC*/
1093 break;
1094
1095 case 1: /*RSYNC*/
1096 break;
1097
1098 case 2: /*ESYNC*/
1099 break;
1100
1101 case 3: /*DSYNC*/
1102 break;
1103
1104 case 8: /*EXCW*/
1105 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1106 break;
1107
1108 case 12: /*MEMW*/
1109 break;
1110
1111 case 13: /*EXTW*/
1112 break;
1113
1114 case 15: /*NOP*/
1115 break;
1116
1117 default: /*reserved*/
1118 RESERVED();
1119 break;
1120 }
91a5bb76
MF		 1121 break;
1122
1123 case 3: /*RFEIx*/
40643d7c
MF		 1124 switch (RRR_T) {
1125 case 0: /*RFETx*/
1126 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1127 switch (RRR_S) {
1128 case 0: /*RFEx*/
97e89ee9
MF		 1129 if (gen_check_privilege(dc)) {
1130 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1131 gen_helper_check_interrupts(cpu_env);
1132 gen_jump(dc, cpu_SR[EPC1]);
1133 }
40643d7c
MF		 1134 break;
1135
1136 case 1: /*RFUEx*/
1137 RESERVED();
1138 break;
1139
1140 case 2: /*RFDEx*/
97e89ee9
MF		 1141 if (gen_check_privilege(dc)) {
1142 gen_jump(dc, cpu_SR[
1143 dc->config->ndepc ? DEPC : EPC1]);
1144 }
40643d7c
MF		 1145 break;
1146
1147 case 4: /*RFWOw*/
1148 case 5: /*RFWUw*/
1149 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9 1150 if (gen_check_privilege(dc)) {
553e44f9
MF		 1151 TCGv_i32 tmp = tcg_const_i32(1);
1152
1153 tcg_gen_andi_i32(
1154 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1155 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1156
1157 if (RRR_S == 4) {
1158 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1159 cpu_SR[WINDOW_START], tmp);
1160 } else {
1161 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1162 cpu_SR[WINDOW_START], tmp);
1163 }
1164
f492b82d 1165 gen_helper_restore_owb(cpu_env);
b994e91b 1166 gen_helper_check_interrupts(cpu_env);
553e44f9
MF		 1167 gen_jump(dc, cpu_SR[EPC1]);
1168
1169 tcg_temp_free(tmp);
1170 }
40643d7c
MF		 1171 break;
1172
1173 default: /*reserved*/
1174 RESERVED();
1175 break;
1176 }
1177 break;
1178
1179 case 1: /*RFIx*/
1180 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b 1181 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
97e89ee9
MF		 1182 if (gen_check_privilege(dc)) {
1183 tcg_gen_mov_i32(cpu_SR[PS],
1184 cpu_SR[EPS2 + RRR_S - 2]);
1185 gen_helper_check_interrupts(cpu_env);
1186 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1187 }
b994e91b
MF		 1188 } else {
1189 qemu_log("RFI %d is illegal\n", RRR_S);
1190 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1191 }
40643d7c
MF		 1192 break;
1193
1194 case 2: /*RFME*/
1195 TBD();
1196 break;
1197
1198 default: /*reserved*/
1199 RESERVED();
1200 break;
1201
1202 }
91a5bb76
MF		 1203 break;
1204
1205 case 4: /*BREAKx*/
e61dc8f7
MF		 1206 HAS_OPTION(XTENSA_OPTION_DEBUG);
1207 if (dc->debug) {
1208 gen_debug_exception(dc, DEBUGCAUSE_BI);
1209 }
91a5bb76
MF		 1210 break;
1211
1212 case 5: /*SYSCALLx*/
1213 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 1214 switch (RRR_S) {
1215 case 0: /*SYSCALLx*/
1216 gen_exception_cause(dc, SYSCALL_CAUSE);
1217 break;
1218
1219 case 1: /*SIMCALL*/
cfe67cef 1220 if (semihosting_enabled()) {
97e89ee9
MF		 1221 if (gen_check_privilege(dc)) {
1222 gen_helper_simcall(cpu_env);
1223 }
1ddeaa5d
MF		 1224 } else {
1225 qemu_log("SIMCALL but semihosting is disabled\n");
1226 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1227 }
40643d7c
MF		 1228 break;
1229
1230 default:
1231 RESERVED();
1232 break;
1233 }
91a5bb76
MF		 1234 break;
1235
1236 case 6: /*RSILx*/
1237 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
97e89ee9
MF		 1238 if (gen_check_privilege(dc) &&
1239 gen_window_check1(dc, RRR_T)) {
1240 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1241 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1242 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1243 gen_helper_check_interrupts(cpu_env);
1244 gen_jumpi_check_loop_end(dc, 0);
1245 }
91a5bb76
MF		 1246 break;
1247
1248 case 7: /*WAITIx*/
1249 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
97e89ee9
MF		 1250 if (gen_check_privilege(dc)) {
1251 gen_waiti(dc, RRR_S);
1252 }
91a5bb76
MF		 1253 break;
1254
1255 case 8: /*ANY4p*/
91a5bb76 1256 case 9: /*ALL4p*/
91a5bb76 1257 case 10: /*ANY8p*/
91a5bb76
MF		 1258 case 11: /*ALL8p*/
1259 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1260 {
1261 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1262 TCGv_i32 mask = tcg_const_i32(
1263 ((1 << shift) - 1) << RRR_S);
1264 TCGv_i32 tmp = tcg_temp_new_i32();
1265
1266 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1267 if (RRR_R & 1) { /*ALL*/
1268 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1269 } else { /*ANY*/
1270 tcg_gen_add_i32(tmp, tmp, mask);
1271 }
1272 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1273 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1274 tmp, RRR_T, 1);
1275 tcg_temp_free(mask);
1276 tcg_temp_free(tmp);
1277 }
91a5bb76
MF		 1278 break;
1279
1280 default: /*reserved*/
1281 RESERVED();
dedc5eae
MF		 1282 break;
1283
1284 }
1285 break;
1286
1287 case 1: /*AND*/
97e89ee9
MF		 1288 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1289 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1290 }
dedc5eae
MF		 1291 break;
1292
1293 case 2: /*OR*/
97e89ee9
MF		 1294 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1295 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1296 }
dedc5eae
MF		 1297 break;
1298
1299 case 3: /*XOR*/
97e89ee9
MF		 1300 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1301 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1302 }
dedc5eae
MF		 1303 break;
1304
1305 case 4: /*ST1*/
3580ecad
MF		 1306 switch (RRR_R) {
1307 case 0: /*SSR*/
97e89ee9
MF		 1308 if (gen_window_check1(dc, RRR_S)) {
1309 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1310 }
3580ecad
MF		 1311 break;
1312
1313 case 1: /*SSL*/
97e89ee9
MF		 1314 if (gen_window_check1(dc, RRR_S)) {
1315 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1316 }
3580ecad
MF		 1317 break;
1318
1319 case 2: /*SSA8L*/
97e89ee9 1320 if (gen_window_check1(dc, RRR_S)) {
3580ecad
MF		 1321 TCGv_i32 tmp = tcg_temp_new_i32();
1322 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1323 gen_right_shift_sar(dc, tmp);
1324 tcg_temp_free(tmp);
1325 }
1326 break;
1327
1328 case 3: /*SSA8B*/
97e89ee9 1329 if (gen_window_check1(dc, RRR_S)) {
3580ecad
MF		 1330 TCGv_i32 tmp = tcg_temp_new_i32();
1331 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1332 gen_left_shift_sar(dc, tmp);
1333 tcg_temp_free(tmp);
1334 }
1335 break;
1336
1337 case 4: /*SSAI*/
1338 {
1339 TCGv_i32 tmp = tcg_const_i32(
1340 RRR_S | ((RRR_T & 1) << 4));
1341 gen_right_shift_sar(dc, tmp);
1342 tcg_temp_free(tmp);
1343 }
1344 break;
1345
1346 case 6: /*RER*/
91a5bb76 1347 TBD();
3580ecad
MF		 1348 break;
1349
1350 case 7: /*WER*/
91a5bb76 1351 TBD();
3580ecad
MF		 1352 break;
1353
1354 case 8: /*ROTWw*/
1355 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9 1356 if (gen_check_privilege(dc)) {
553e44f9
MF		 1357 TCGv_i32 tmp = tcg_const_i32(
1358 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
f492b82d 1359 gen_helper_rotw(cpu_env, tmp);
553e44f9 1360 tcg_temp_free(tmp);
2db59a76
MF		 1361 /* This can change tb->flags, so exit tb */
1362 gen_jumpi_check_loop_end(dc, -1);
553e44f9 1363 }
3580ecad
MF		 1364 break;
1365
1366 case 14: /*NSAu*/
7f65f4b0 1367 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
97e89ee9
MF		 1368 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1369 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1370 }
3580ecad
MF		 1371 break;
1372
1373 case 15: /*NSAUu*/
7f65f4b0 1374 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
97e89ee9
MF		 1375 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1376 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1377 }
3580ecad
MF		 1378 break;
1379
1380 default: /*reserved*/
91a5bb76 1381 RESERVED();
3580ecad
MF		 1382 break;
1383 }
dedc5eae
MF		 1384 break;
1385
1386 case 5: /*TLB*/
b67ea0cd
MF		 1387 HAS_OPTION_BITS(
1388 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1389 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1390 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
97e89ee9
MF		 1391 if (gen_check_privilege(dc) &&
1392 gen_window_check2(dc, RRR_S, RRR_T)) {
b67ea0cd
MF		 1393 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1394
1395 switch (RRR_R & 7) {
1396 case 3: /*RITLB0*/ /*RDTLB0*/
f492b82d
MF		 1397 gen_helper_rtlb0(cpu_R[RRR_T],
1398 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1399 break;
1400
1401 case 4: /*IITLB*/ /*IDTLB*/
f492b82d 1402 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1403 /* This could change memory mapping, so exit tb */
1404 gen_jumpi_check_loop_end(dc, -1);
1405 break;
1406
1407 case 5: /*PITLB*/ /*PDTLB*/
1408 tcg_gen_movi_i32(cpu_pc, dc->pc);
f492b82d
MF		 1409 gen_helper_ptlb(cpu_R[RRR_T],
1410 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1411 break;
1412
1413 case 6: /*WITLB*/ /*WDTLB*/
f492b82d
MF		 1414 gen_helper_wtlb(
1415 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1416 /* This could change memory mapping, so exit tb */
1417 gen_jumpi_check_loop_end(dc, -1);
1418 break;
1419
1420 case 7: /*RITLB1*/ /*RDTLB1*/
f492b82d
MF		 1421 gen_helper_rtlb1(cpu_R[RRR_T],
1422 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1423 break;
1424
1425 default:
1426 tcg_temp_free(dtlb);
1427 RESERVED();
1428 break;
1429 }
1430 tcg_temp_free(dtlb);
1431 }
dedc5eae
MF		 1432 break;
1433
1434 case 6: /*RT0*/
97e89ee9
MF		 1435 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1436 break;
1437 }
f331fe5e
MF		 1438 switch (RRR_S) {
1439 case 0: /*NEG*/
1440 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1441 break;
1442
1443 case 1: /*ABS*/
1444 {
f877d09e
MF		 1445 TCGv_i32 zero = tcg_const_i32(0);
1446 TCGv_i32 neg = tcg_temp_new_i32();
1447
1448 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1449 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1450 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1451 tcg_temp_free(neg);
1452 tcg_temp_free(zero);
f331fe5e
MF		 1453 }
1454 break;
1455
1456 default: /*reserved*/
91a5bb76 1457 RESERVED();
f331fe5e
MF		 1458 break;
1459 }
dedc5eae
MF		 1460 break;
1461
1462 case 7: /*reserved*/
91a5bb76 1463 RESERVED();
dedc5eae
MF		 1464 break;
1465
1466 case 8: /*ADD*/
97e89ee9
MF		 1467 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1468 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1469 }
dedc5eae
MF		 1470 break;
1471
1472 case 9: /*ADD**/
1473 case 10:
1474 case 11:
97e89ee9 1475 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
dedc5eae
MF		 1476 TCGv_i32 tmp = tcg_temp_new_i32();
1477 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1478 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1479 tcg_temp_free(tmp);
1480 }
1481 break;
1482
1483 case 12: /*SUB*/
97e89ee9
MF		 1484 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1485 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1486 }
dedc5eae
MF		 1487 break;
1488
1489 case 13: /*SUB**/
1490 case 14:
1491 case 15:
97e89ee9 1492 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
dedc5eae
MF		 1493 TCGv_i32 tmp = tcg_temp_new_i32();
1494 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1495 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1496 tcg_temp_free(tmp);
1497 }
1498 break;
1499 }
1500 break;
1501
1502 case 1: /*RST1*/
3580ecad
MF		 1503 switch (OP2) {
1504 case 0: /*SLLI*/
1505 case 1:
97e89ee9
MF		 1506 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1507 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1508 32 - (RRR_T | ((OP2 & 1) << 4)));
1509 }
3580ecad
MF		 1510 break;
1511
1512 case 2: /*SRAI*/
1513 case 3:
97e89ee9
MF		 1514 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1515 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1516 RRR_S | ((OP2 & 1) << 4));
1517 }
3580ecad
MF		 1518 break;
1519
1520 case 4: /*SRLI*/
97e89ee9
MF		 1521 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1522 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1523 }
3580ecad
MF		 1524 break;
1525
1526 case 6: /*XSR*/
97e89ee9
MF		 1527 if (gen_check_sr(dc, RSR_SR, SR_X) &&
1528 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1529 gen_window_check1(dc, RRR_T)) {
3580ecad 1530 TCGv_i32 tmp = tcg_temp_new_i32();
0857a06e 1531
3580ecad
MF		 1532 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1533 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1534 gen_wsr(dc, RSR_SR, tmp);
1535 tcg_temp_free(tmp);
1536 }
1537 break;
1538
1539 /*
1540 * Note: 64 bit ops are used here solely because SAR values
1541 * have range 0..63
1542 */
1543#define gen_shift_reg(cmd, reg) do { \
1544 TCGv_i64 tmp = tcg_temp_new_i64(); \
1545 tcg_gen_extu_i32_i64(tmp, reg); \
1546 tcg_gen_##cmd##_i64(v, v, tmp); \
ecc7b3aa 1547 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \
3580ecad
MF		 1548 tcg_temp_free_i64(v); \
1549 tcg_temp_free_i64(tmp); \
1550 } while (0)
1551
1552#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1553
1554 case 8: /*SRC*/
97e89ee9 1555 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
3580ecad
MF		 1556 TCGv_i64 v = tcg_temp_new_i64();
1557 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1558 gen_shift(shr);
1559 }
1560 break;
1561
1562 case 9: /*SRL*/
97e89ee9
MF		 1563 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1564 break;
1565 }
3580ecad
MF		 1566 if (dc->sar_5bit) {
1567 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1568 } else {
1569 TCGv_i64 v = tcg_temp_new_i64();
1570 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1571 gen_shift(shr);
1572 }
1573 break;
1574
1575 case 10: /*SLL*/
97e89ee9
MF		 1576 if (!gen_window_check2(dc, RRR_R, RRR_S)) {
1577 break;
1578 }
3580ecad
MF		 1579 if (dc->sar_m32_5bit) {
1580 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1581 } else {
1582 TCGv_i64 v = tcg_temp_new_i64();
1583 TCGv_i32 s = tcg_const_i32(32);
1584 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1585 tcg_gen_andi_i32(s, s, 0x3f);
1586 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1587 gen_shift_reg(shl, s);
1588 tcg_temp_free(s);
1589 }
1590 break;
1591
1592 case 11: /*SRA*/
97e89ee9
MF		 1593 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1594 break;
1595 }
3580ecad
MF		 1596 if (dc->sar_5bit) {
1597 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1598 } else {
1599 TCGv_i64 v = tcg_temp_new_i64();
1600 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1601 gen_shift(sar);
1602 }
1603 break;
1604#undef gen_shift
1605#undef gen_shift_reg
1606
1607 case 12: /*MUL16U*/
1608 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
97e89ee9 1609 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
3580ecad
MF		 1610 TCGv_i32 v1 = tcg_temp_new_i32();
1611 TCGv_i32 v2 = tcg_temp_new_i32();
1612 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1613 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1614 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1615 tcg_temp_free(v2);
1616 tcg_temp_free(v1);
1617 }
1618 break;
1619
1620 case 13: /*MUL16S*/
1621 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
97e89ee9 1622 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
3580ecad
MF		 1623 TCGv_i32 v1 = tcg_temp_new_i32();
1624 TCGv_i32 v2 = tcg_temp_new_i32();
1625 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1626 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1627 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1628 tcg_temp_free(v2);
1629 tcg_temp_free(v1);
1630 }
1631 break;
1632
1633 default: /*reserved*/
91a5bb76 1634 RESERVED();
3580ecad
MF		 1635 break;
1636 }
dedc5eae
MF		 1637 break;
1638
1639 case 2: /*RST2*/
97e89ee9
MF		 1640 if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1641 break;
4dd85b6b 1642 }
772177c1 1643
f76ebf55
MF		 1644 if (OP2 >= 12) {
1645 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
42a268c2 1646 TCGLabel *label = gen_new_label();
f76ebf55
MF		 1647 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1648 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1649 gen_set_label(label);
1650 }
1651
1652 switch (OP2) {
4dd85b6b
MF		 1653#define BOOLEAN_LOGIC(fn, r, s, t) \
1654 do { \
1655 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1656 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1657 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1658 \
1659 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1660 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1661 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1662 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1663 tcg_temp_free(tmp1); \
1664 tcg_temp_free(tmp2); \
1665 } while (0)
1666
1667 case 0: /*ANDBp*/
1668 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1669 break;
1670
1671 case 1: /*ANDBCp*/
1672 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1673 break;
1674
1675 case 2: /*ORBp*/
1676 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1677 break;
1678
1679 case 3: /*ORBCp*/
1680 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1681 break;
1682
1683 case 4: /*XORBp*/
1684 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1685 break;
1686
1687#undef BOOLEAN_LOGIC
1688
f76ebf55
MF		 1689 case 8: /*MULLi*/
1690 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1691 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1692 break;
1693
1694 case 10: /*MULUHi*/
1695 case 11: /*MULSHi*/
7f65f4b0 1696 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
f76ebf55 1697 {
c9cda20b 1698 TCGv lo = tcg_temp_new();
f76ebf55
MF		 1699
1700 if (OP2 == 10) {
c9cda20b
RH		 1701 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1702 cpu_R[RRR_S], cpu_R[RRR_T]);
f76ebf55 1703 } else {
c9cda20b
RH		 1704 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1705 cpu_R[RRR_S], cpu_R[RRR_T]);
f76ebf55 1706 }
c9cda20b 1707 tcg_temp_free(lo);
f76ebf55
MF		 1708 }
1709 break;
1710
1711 case 12: /*QUOUi*/
1712 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1713 break;
1714
1715 case 13: /*QUOSi*/
1716 case 15: /*REMSi*/
1717 {
42a268c2
RH		 1718 TCGLabel *label1 = gen_new_label();
1719 TCGLabel *label2 = gen_new_label();
f76ebf55
MF		 1720
1721 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1722 label1);
1723 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1724 label1);
1725 tcg_gen_movi_i32(cpu_R[RRR_R],
1726 OP2 == 13 ? 0x80000000 : 0);
1727 tcg_gen_br(label2);
1728 gen_set_label(label1);
1729 if (OP2 == 13) {
1730 tcg_gen_div_i32(cpu_R[RRR_R],
1731 cpu_R[RRR_S], cpu_R[RRR_T]);
1732 } else {
1733 tcg_gen_rem_i32(cpu_R[RRR_R],
1734 cpu_R[RRR_S], cpu_R[RRR_T]);
1735 }
1736 gen_set_label(label2);
1737 }
1738 break;
1739
1740 case 14: /*REMUi*/
1741 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1742 break;
1743
1744 default: /*reserved*/
1745 RESERVED();
1746 break;
1747 }
dedc5eae
MF		 1748 break;
1749
1750 case 3: /*RST3*/
b8132eff
MF		 1751 switch (OP2) {
1752 case 0: /*RSR*/
97e89ee9
MF		 1753 if (gen_check_sr(dc, RSR_SR, SR_R) &&
1754 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1755 gen_window_check1(dc, RRR_T)) {
0857a06e 1756 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
40643d7c 1757 }
b8132eff
MF		 1758 break;
1759
1760 case 1: /*WSR*/
97e89ee9
MF		 1761 if (gen_check_sr(dc, RSR_SR, SR_W) &&
1762 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1763 gen_window_check1(dc, RRR_T)) {
0857a06e 1764 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
40643d7c 1765 }
b8132eff
MF		 1766 break;
1767
1768 case 2: /*SEXTu*/
7f65f4b0 1769 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
97e89ee9 1770 if (gen_window_check2(dc, RRR_R, RRR_S)) {
b8132eff
MF		 1771 int shift = 24 - RRR_T;
1772
1773 if (shift == 24) {
1774 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1775 } else if (shift == 16) {
1776 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1777 } else {
1778 TCGv_i32 tmp = tcg_temp_new_i32();
1779 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1780 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1781 tcg_temp_free(tmp);
1782 }
1783 }
1784 break;
1785
1786 case 3: /*CLAMPSu*/
7f65f4b0 1787 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
97e89ee9 1788 if (gen_window_check2(dc, RRR_R, RRR_S)) {
b8132eff
MF		 1789 TCGv_i32 tmp1 = tcg_temp_new_i32();
1790 TCGv_i32 tmp2 = tcg_temp_new_i32();
f877d09e 1791 TCGv_i32 zero = tcg_const_i32(0);
b8132eff
MF		 1792
1793 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1794 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1795 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
b8132eff
MF		 1796
1797 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
f877d09e 1798 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
b8132eff 1799
f877d09e
MF		 1800 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1801 cpu_R[RRR_S], tmp1);
b8132eff
MF		 1802 tcg_temp_free(tmp1);
1803 tcg_temp_free(tmp2);
f877d09e 1804 tcg_temp_free(zero);
b8132eff
MF		 1805 }
1806 break;
1807
1808 case 4: /*MINu*/
1809 case 5: /*MAXu*/
1810 case 6: /*MINUu*/
1811 case 7: /*MAXUu*/
7f65f4b0 1812 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
97e89ee9 1813 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
b8132eff
MF		 1814 static const TCGCond cond[] = {
1815 TCG_COND_LE,
1816 TCG_COND_GE,
1817 TCG_COND_LEU,
1818 TCG_COND_GEU
1819 };
f877d09e
MF		 1820 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1821 cpu_R[RRR_S], cpu_R[RRR_T],
1822 cpu_R[RRR_S], cpu_R[RRR_T]);
b8132eff
MF		 1823 }
1824 break;
1825
1826 case 8: /*MOVEQZ*/
1827 case 9: /*MOVNEZ*/
1828 case 10: /*MOVLTZ*/
1829 case 11: /*MOVGEZ*/
97e89ee9 1830 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
b8132eff 1831 static const TCGCond cond[] = {
b8132eff 1832 TCG_COND_EQ,
f877d09e
MF		 1833 TCG_COND_NE,
1834 TCG_COND_LT,
b8132eff 1835 TCG_COND_GE,
b8132eff 1836 };
f877d09e
MF		 1837 TCGv_i32 zero = tcg_const_i32(0);
1838
1839 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1840 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1841 tcg_temp_free(zero);
b8132eff
MF		 1842 }
1843 break;
1844
1845 case 12: /*MOVFp*/
b8132eff
MF		 1846 case 13: /*MOVTp*/
1847 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
97e89ee9 1848 if (gen_window_check2(dc, RRR_R, RRR_S)) {
f877d09e 1849 TCGv_i32 zero = tcg_const_i32(0);
4dd85b6b
MF		 1850 TCGv_i32 tmp = tcg_temp_new_i32();
1851
1852 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
f877d09e
MF		 1853 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1854 cpu_R[RRR_R], tmp, zero,
1855 cpu_R[RRR_S], cpu_R[RRR_R]);
1856
4dd85b6b 1857 tcg_temp_free(tmp);
f877d09e 1858 tcg_temp_free(zero);
4dd85b6b 1859 }
b8132eff
MF		 1860 break;
1861
1862 case 14: /*RUR*/
97e89ee9 1863 if (gen_window_check1(dc, RRR_R)) {
b8132eff 1864 int st = (RRR_S << 4) + RRR_T;
fe0bd475 1865 if (uregnames[st].name) {
b8132eff
MF		 1866 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1867 } else {
1868 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1869 TBD();
b8132eff
MF		 1870 }
1871 }
1872 break;
1873
1874 case 15: /*WUR*/
97e89ee9
MF		 1875 if (gen_window_check1(dc, RRR_T)) {
1876 if (uregnames[RSR_SR].name) {
1877 gen_wur(RSR_SR, cpu_R[RRR_T]);
1878 } else {
1879 qemu_log("WUR %d not implemented, ", RSR_SR);
1880 TBD();
1881 }
b8132eff
MF		 1882 }
1883 break;
1884
1885 }
dedc5eae
MF		 1886 break;
1887
1888 case 4: /*EXTUI*/
1889 case 5:
97e89ee9 1890 if (gen_window_check2(dc, RRR_R, RRR_T)) {
f9cb5045 1891 int shiftimm = RRR_S | ((OP1 & 1) << 4);
3580ecad
MF		 1892 int maskimm = (1 << (OP2 + 1)) - 1;
1893
1894 TCGv_i32 tmp = tcg_temp_new_i32();
f783cb22
AJ		 1895 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1896 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
3580ecad
MF		 1897 tcg_temp_free(tmp);
1898 }
dedc5eae
MF		 1899 break;
1900
1901 case 6: /*CUST0*/
91a5bb76 1902 RESERVED();
dedc5eae
MF		 1903 break;
1904
1905 case 7: /*CUST1*/
91a5bb76 1906 RESERVED();
dedc5eae
MF		 1907 break;
1908
1909 case 8: /*LSCXp*/
9ed7ae12
MF		 1910 switch (OP2) {
1911 case 0: /*LSXf*/
1912 case 1: /*LSXUf*/
1913 case 4: /*SSXf*/
1914 case 5: /*SSXUf*/
1915 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
97e89ee9
MF		 1916 if (gen_window_check2(dc, RRR_S, RRR_T) &&
1917 gen_check_cpenable(dc, 0)) {
9ed7ae12
MF		 1918 TCGv_i32 addr = tcg_temp_new_i32();
1919 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1920 gen_load_store_alignment(dc, 2, addr, false);
1921 if (OP2 & 0x4) {
1922 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1923 } else {
1924 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1925 }
1926 if (OP2 & 0x1) {
1927 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1928 }
1929 tcg_temp_free(addr);
1930 }
1931 break;
1932
1933 default: /*reserved*/
1934 RESERVED();
1935 break;
1936 }
dedc5eae
MF		 1937 break;
1938
1939 case 9: /*LSC4*/
97e89ee9
MF		 1940 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1941 break;
1942 }
553e44f9
MF		 1943 switch (OP2) {
1944 case 0: /*L32E*/
1945 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
f822b7e4
MF		 1946 if (gen_check_privilege(dc) &&
1947 gen_window_check2(dc, RRR_S, RRR_T)) {
553e44f9
MF		 1948 TCGv_i32 addr = tcg_temp_new_i32();
1949 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1950 (0xffffffc0 | (RRR_R << 2)));
1951 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1952 tcg_temp_free(addr);
1953 }
1954 break;
1955
1956 case 4: /*S32E*/
1957 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
f822b7e4
MF		 1958 if (gen_check_privilege(dc) &&
1959 gen_window_check2(dc, RRR_S, RRR_T)) {
553e44f9
MF		 1960 TCGv_i32 addr = tcg_temp_new_i32();
1961 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1962 (0xffffffc0 | (RRR_R << 2)));
1963 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1964 tcg_temp_free(addr);
1965 }
1966 break;
1967
19b7bec4
MF		 1968 case 5: /*S32N*/
1969 if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
1970 TCGv_i32 addr = tcg_temp_new_i32();
1971
1972 tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
1973 gen_load_store_alignment(dc, 2, addr, false);
1974 tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
1975 tcg_temp_free(addr);
1976 }
1977 break;
1978
553e44f9
MF		 1979 default:
1980 RESERVED();
1981 break;
1982 }
dedc5eae
MF		 1983 break;
1984
1985 case 10: /*FP0*/
5eeb40c5
MF		 1986 /*DEPBITS*/
1987 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
1988 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1989 break;
1990 }
1991 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
1992 OP2, RRR_R + 1);
1993 break;
1994 }
1995
dedc5eae 1996 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
0b6df838
MF		 1997 switch (OP2) {
1998 case 0: /*ADD.Sf*/
97e89ee9
MF		 1999 if (gen_check_cpenable(dc, 0)) {
2000 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
2001 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2002 }
0b6df838
MF		 2003 break;
2004
2005 case 1: /*SUB.Sf*/
97e89ee9
MF		 2006 if (gen_check_cpenable(dc, 0)) {
2007 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
2008 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2009 }
0b6df838
MF		 2010 break;
2011
2012 case 2: /*MUL.Sf*/
97e89ee9
MF		 2013 if (gen_check_cpenable(dc, 0)) {
2014 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
2015 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2016 }
0b6df838
MF		 2017 break;
2018
2019 case 4: /*MADD.Sf*/
97e89ee9
MF		 2020 if (gen_check_cpenable(dc, 0)) {
2021 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
2022 cpu_FR[RRR_R], cpu_FR[RRR_S],
2023 cpu_FR[RRR_T]);
2024 }
0b6df838
MF		 2025 break;
2026
2027 case 5: /*MSUB.Sf*/
97e89ee9
MF		 2028 if (gen_check_cpenable(dc, 0)) {
2029 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2030 cpu_FR[RRR_R], cpu_FR[RRR_S],
2031 cpu_FR[RRR_T]);
2032 }
0b6df838
MF		 2033 break;
2034
b7ee8c6a
MF		 2035 case 8: /*ROUND.Sf*/
2036 case 9: /*TRUNC.Sf*/
2037 case 10: /*FLOOR.Sf*/
2038 case 11: /*CEIL.Sf*/
2039 case 14: /*UTRUNC.Sf*/
97e89ee9
MF		 2040 if (gen_window_check1(dc, RRR_R) &&
2041 gen_check_cpenable(dc, 0)) {
b7ee8c6a
MF		 2042 static const unsigned rounding_mode_const[] = {
2043 float_round_nearest_even,
2044 float_round_to_zero,
2045 float_round_down,
2046 float_round_up,
2047 [6] = float_round_to_zero,
2048 };
2049 TCGv_i32 rounding_mode = tcg_const_i32(
2050 rounding_mode_const[OP2 & 7]);
2051 TCGv_i32 scale = tcg_const_i32(RRR_T);
2052
2053 if (OP2 == 14) {
2054 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2055 rounding_mode, scale);
2056 } else {
2057 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2058 rounding_mode, scale);
2059 }
2060
2061 tcg_temp_free(rounding_mode);
2062 tcg_temp_free(scale);
2063 }
2064 break;
2065
2066 case 12: /*FLOAT.Sf*/
2067 case 13: /*UFLOAT.Sf*/
97e89ee9
MF		 2068 if (gen_window_check1(dc, RRR_S) &&
2069 gen_check_cpenable(dc, 0)) {
b7ee8c6a
MF		 2070 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2071
2072 if (OP2 == 13) {
2073 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2074 cpu_R[RRR_S], scale);
2075 } else {
2076 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2077 cpu_R[RRR_S], scale);
2078 }
2079 tcg_temp_free(scale);
2080 }
2081 break;
2082
0b6df838
MF		 2083 case 15: /*FP1OP*/
2084 switch (RRR_T) {
2085 case 0: /*MOV.Sf*/
97e89ee9
MF		 2086 if (gen_check_cpenable(dc, 0)) {
2087 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2088 }
0b6df838
MF		 2089 break;
2090
2091 case 1: /*ABS.Sf*/
97e89ee9
MF		 2092 if (gen_check_cpenable(dc, 0)) {
2093 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2094 }
0b6df838
MF		 2095 break;
2096
2097 case 4: /*RFRf*/
97e89ee9
MF		 2098 if (gen_window_check1(dc, RRR_R) &&
2099 gen_check_cpenable(dc, 0)) {
2100 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2101 }
0b6df838
MF		 2102 break;
2103
2104 case 5: /*WFRf*/
97e89ee9
MF		 2105 if (gen_window_check1(dc, RRR_S) &&
2106 gen_check_cpenable(dc, 0)) {
2107 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2108 }
0b6df838
MF		 2109 break;
2110
2111 case 6: /*NEG.Sf*/
97e89ee9
MF		 2112 if (gen_check_cpenable(dc, 0)) {
2113 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2114 }
0b6df838
MF		 2115 break;
2116
2117 default: /*reserved*/
2118 RESERVED();
2119 break;
2120 }
2121 break;
2122
2123 default: /*reserved*/
2124 RESERVED();
2125 break;
2126 }
dedc5eae
MF		 2127 break;
2128
2129 case 11: /*FP1*/
5eeb40c5
MF		 2130 /*DEPBITS*/
2131 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
2132 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2133 break;
2134 }
2135 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
2136 OP2 + 16, RRR_R + 1);
2137 break;
2138 }
2139
dedc5eae 2140 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
4e273869
MF		 2141
2142#define gen_compare(rel, br, a, b) \
2143 do { \
97e89ee9
MF		 2144 if (gen_check_cpenable(dc, 0)) { \
2145 TCGv_i32 bit = tcg_const_i32(1 << br); \
2146 \
2147 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2148 tcg_temp_free(bit); \
2149 } \
4e273869
MF		 2150 } while (0)
2151
2152 switch (OP2) {
2153 case 1: /*UN.Sf*/
2154 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2155 break;
2156
2157 case 2: /*OEQ.Sf*/
2158 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2159 break;
2160
2161 case 3: /*UEQ.Sf*/
2162 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2163 break;
2164
2165 case 4: /*OLT.Sf*/
2166 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2167 break;
2168
2169 case 5: /*ULT.Sf*/
2170 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2171 break;
2172
2173 case 6: /*OLE.Sf*/
2174 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2175 break;
2176
2177 case 7: /*ULE.Sf*/
2178 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2179 break;
2180
2181#undef gen_compare
2182
2183 case 8: /*MOVEQZ.Sf*/
2184 case 9: /*MOVNEZ.Sf*/
2185 case 10: /*MOVLTZ.Sf*/
2186 case 11: /*MOVGEZ.Sf*/
97e89ee9
MF		 2187 if (gen_window_check1(dc, RRR_T) &&
2188 gen_check_cpenable(dc, 0)) {
4e273869 2189 static const TCGCond cond[] = {
4e273869 2190 TCG_COND_EQ,
f877d09e
MF		 2191 TCG_COND_NE,
2192 TCG_COND_LT,
4e273869 2193 TCG_COND_GE,
4e273869 2194 };
f877d09e
MF		 2195 TCGv_i32 zero = tcg_const_i32(0);
2196
2197 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2198 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2199 tcg_temp_free(zero);
4e273869
MF		 2200 }
2201 break;
2202
2203 case 12: /*MOVF.Sf*/
2204 case 13: /*MOVT.Sf*/
2205 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
97e89ee9 2206 if (gen_check_cpenable(dc, 0)) {
f877d09e 2207 TCGv_i32 zero = tcg_const_i32(0);
4e273869
MF		 2208 TCGv_i32 tmp = tcg_temp_new_i32();
2209
2210 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
f877d09e
MF		 2211 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2212 cpu_FR[RRR_R], tmp, zero,
2213 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2214
4e273869 2215 tcg_temp_free(tmp);
f877d09e 2216 tcg_temp_free(zero);
4e273869
MF		 2217 }
2218 break;
2219
2220 default: /*reserved*/
2221 RESERVED();
2222 break;
2223 }
dedc5eae
MF		 2224 break;
2225
2226 default: /*reserved*/
91a5bb76 2227 RESERVED();
dedc5eae
MF		 2228 break;
2229 }
2230 break;
2231
2232 case 1: /*L32R*/
97e89ee9 2233 if (gen_window_check1(dc, RRR_T)) {
dedc5eae 2234 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 2235 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2236 0 : ((dc->pc + 3) & ~3)) +
2237 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 2238
6ad6dbf7
MF		 2239 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2240 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2241 }
f0a548b9 2242 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 2243 tcg_temp_free(tmp);
2244 }
2245 break;
2246
2247 case 2: /*LSAI*/
809377aa 2248#define gen_load_store(type, shift) do { \
97e89ee9
MF		 2249 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2250 TCGv_i32 addr = tcg_temp_new_i32(); \
2251 \
2252 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2253 if (shift) { \
2254 gen_load_store_alignment(dc, shift, addr, false); \
2255 } \
2256 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2257 tcg_temp_free(addr); \
5b4e481b 2258 } \
809377aa
MF		 2259 } while (0)
2260
2261 switch (RRI8_R) {
2262 case 0: /*L8UI*/
2263 gen_load_store(ld8u, 0);
2264 break;
2265
2266 case 1: /*L16UI*/
2267 gen_load_store(ld16u, 1);
2268 break;
2269
2270 case 2: /*L32I*/
2271 gen_load_store(ld32u, 2);
2272 break;
2273
2274 case 4: /*S8I*/
2275 gen_load_store(st8, 0);
2276 break;
2277
2278 case 5: /*S16I*/
2279 gen_load_store(st16, 1);
2280 break;
2281
2282 case 6: /*S32I*/
2283 gen_load_store(st32, 2);
2284 break;
2285
7c842590 2286#define gen_dcache_hit_test(w, shift) do { \
97e89ee9
MF		 2287 if (gen_window_check1(dc, RRI##w##_S)) { \
2288 TCGv_i32 addr = tcg_temp_new_i32(); \
2289 TCGv_i32 res = tcg_temp_new_i32(); \
2290 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2291 RRI##w##_IMM##w << shift); \
2292 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2293 tcg_temp_free(addr); \
2294 tcg_temp_free(res); \
2295 } \
7c842590
MF		 2296 } while (0)
2297
2298#define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2299#define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2300
809377aa 2301 case 7: /*CACHEc*/
8ffc2d0d
MF		 2302 if (RRI8_T < 8) {
2303 HAS_OPTION(XTENSA_OPTION_DCACHE);
2304 }
2305
2306 switch (RRI8_T) {
2307 case 0: /*DPFRc*/
7c842590 2308 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2309 break;
2310
2311 case 1: /*DPFWc*/
7c842590 2312 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2313 break;
2314
2315 case 2: /*DPFROc*/
7c842590 2316 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2317 break;
2318
2319 case 3: /*DPFWOc*/
7c842590 2320 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2321 break;
2322
2323 case 4: /*DHWBc*/
7c842590 2324 gen_dcache_hit_test8();
8ffc2d0d
MF		 2325 break;
2326
2327 case 5: /*DHWBIc*/
7c842590 2328 gen_dcache_hit_test8();
8ffc2d0d
MF		 2329 break;
2330
2331 case 6: /*DHIc*/
97e89ee9
MF		 2332 if (gen_check_privilege(dc)) {
2333 gen_dcache_hit_test8();
2334 }
8ffc2d0d
MF		 2335 break;
2336
2337 case 7: /*DIIc*/
97e89ee9
MF		 2338 if (gen_check_privilege(dc)) {
2339 gen_window_check1(dc, RRI8_S);
2340 }
8ffc2d0d
MF		 2341 break;
2342
2343 case 8: /*DCEc*/
2344 switch (OP1) {
2345 case 0: /*DPFLl*/
2346 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
97e89ee9
MF		 2347 if (gen_check_privilege(dc)) {
2348 gen_dcache_hit_test4();
2349 }
8ffc2d0d
MF		 2350 break;
2351
2352 case 2: /*DHUl*/
2353 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
97e89ee9
MF		 2354 if (gen_check_privilege(dc)) {
2355 gen_dcache_hit_test4();
2356 }
8ffc2d0d
MF		 2357 break;
2358
2359 case 3: /*DIUl*/
2360 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
97e89ee9
MF		 2361 if (gen_check_privilege(dc)) {
2362 gen_window_check1(dc, RRI4_S);
2363 }
8ffc2d0d
MF		 2364 break;
2365
2366 case 4: /*DIWBc*/
2367 HAS_OPTION(XTENSA_OPTION_DCACHE);
97e89ee9
MF		 2368 if (gen_check_privilege(dc)) {
2369 gen_window_check1(dc, RRI4_S);
2370 }
8ffc2d0d
MF		 2371 break;
2372
2373 case 5: /*DIWBIc*/
2374 HAS_OPTION(XTENSA_OPTION_DCACHE);
97e89ee9
MF		 2375 if (gen_check_privilege(dc)) {
2376 gen_window_check1(dc, RRI4_S);
2377 }
8ffc2d0d
MF		 2378 break;
2379
2380 default: /*reserved*/
2381 RESERVED();
2382 break;
2383
2384 }
2385 break;
2386
7c842590
MF		 2387#undef gen_dcache_hit_test
2388#undef gen_dcache_hit_test4
2389#undef gen_dcache_hit_test8
2390
e848dd42 2391#define gen_icache_hit_test(w, shift) do { \
97e89ee9
MF		 2392 if (gen_window_check1(dc, RRI##w##_S)) { \
2393 TCGv_i32 addr = tcg_temp_new_i32(); \
2394 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2395 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2396 RRI##w##_IMM##w << shift); \
2397 gen_helper_itlb_hit_test(cpu_env, addr); \
2398 tcg_temp_free(addr); \
2399 }\
e848dd42
MF		 2400 } while (0)
2401
2402#define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2403#define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2404
8ffc2d0d
MF		 2405 case 12: /*IPFc*/
2406 HAS_OPTION(XTENSA_OPTION_ICACHE);
e848dd42 2407 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2408 break;
2409
2410 case 13: /*ICEc*/
2411 switch (OP1) {
2412 case 0: /*IPFLl*/
2413 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
97e89ee9
MF		 2414 if (gen_check_privilege(dc)) {
2415 gen_icache_hit_test4();
2416 }
8ffc2d0d
MF		 2417 break;
2418
2419 case 2: /*IHUl*/
2420 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
97e89ee9
MF		 2421 if (gen_check_privilege(dc)) {
2422 gen_icache_hit_test4();
2423 }
8ffc2d0d
MF		 2424 break;
2425
2426 case 3: /*IIUl*/
2427 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
97e89ee9
MF		 2428 if (gen_check_privilege(dc)) {
2429 gen_window_check1(dc, RRI4_S);
2430 }
8ffc2d0d
MF		 2431 break;
2432
2433 default: /*reserved*/
2434 RESERVED();
2435 break;
2436 }
2437 break;
2438
2439 case 14: /*IHIc*/
2440 HAS_OPTION(XTENSA_OPTION_ICACHE);
e848dd42 2441 gen_icache_hit_test8();
8ffc2d0d
MF		 2442 break;
2443
2444 case 15: /*IIIc*/
2445 HAS_OPTION(XTENSA_OPTION_ICACHE);
97e89ee9
MF		 2446 if (gen_check_privilege(dc)) {
2447 gen_window_check1(dc, RRI8_S);
2448 }
8ffc2d0d
MF		 2449 break;
2450
2451 default: /*reserved*/
2452 RESERVED();
2453 break;
2454 }
809377aa
MF		 2455 break;
2456
e848dd42
MF		 2457#undef gen_icache_hit_test
2458#undef gen_icache_hit_test4
2459#undef gen_icache_hit_test8
2460
809377aa
MF		 2461 case 9: /*L16SI*/
2462 gen_load_store(ld16s, 1);
2463 break;
5b4e481b 2464#undef gen_load_store
809377aa
MF		 2465
2466 case 10: /*MOVI*/
97e89ee9
MF		 2467 if (gen_window_check1(dc, RRI8_T)) {
2468 tcg_gen_movi_i32(cpu_R[RRI8_T],
2469 RRI8_IMM8 | (RRI8_S << 8) |
2470 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2471 }
809377aa
MF		 2472 break;
2473
5b4e481b 2474#define gen_load_store_no_hw_align(type) do { \
97e89ee9
MF		 2475 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2476 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2477 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2478 gen_load_store_alignment(dc, 2, addr, true); \
2479 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2480 tcg_temp_free(addr); \
2481 } \
5b4e481b
MF		 2482 } while (0)
2483
809377aa
MF		 2484 case 11: /*L32AIy*/
2485 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2486 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 2487 break;
2488
2489 case 12: /*ADDI*/
97e89ee9
MF		 2490 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2491 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2492 }
809377aa
MF		 2493 break;
2494
2495 case 13: /*ADDMI*/
97e89ee9
MF		 2496 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2497 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S],
2498 RRI8_IMM8_SE << 8);
2499 }
809377aa
MF		 2500 break;
2501
2502 case 14: /*S32C1Iy*/
7f65f4b0 2503 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
97e89ee9 2504 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
42a268c2 2505 TCGLabel *label = gen_new_label();
809377aa
MF		 2506 TCGv_i32 tmp = tcg_temp_local_new_i32();
2507 TCGv_i32 addr = tcg_temp_local_new_i32();
fcc803d1 2508 TCGv_i32 tpc;
809377aa
MF		 2509
2510 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2511 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 2512 gen_load_store_alignment(dc, 2, addr, true);
fcc803d1
MF		 2513
2514 gen_advance_ccount(dc);
2515 tpc = tcg_const_i32(dc->pc);
2516 gen_helper_check_atomctl(cpu_env, tpc, addr);
f0a548b9 2517 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 2518 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2519 cpu_SR[SCOMPARE1], label);
2520
f0a548b9 2521 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 2522
2523 gen_set_label(label);
fcc803d1 2524 tcg_temp_free(tpc);
809377aa
MF		 2525 tcg_temp_free(addr);
2526 tcg_temp_free(tmp);
2527 }
2528 break;
2529
2530 case 15: /*S32RIy*/
2531 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2532 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 2533 break;
5b4e481b 2534#undef gen_load_store_no_hw_align
809377aa
MF		 2535
2536 default: /*reserved*/
91a5bb76 2537 RESERVED();
809377aa
MF		 2538 break;
2539 }
dedc5eae
MF		 2540 break;
2541
2542 case 3: /*LSCIp*/
9ed7ae12
MF		 2543 switch (RRI8_R) {
2544 case 0: /*LSIf*/
2545 case 4: /*SSIf*/
2546 case 8: /*LSIUf*/
2547 case 12: /*SSIUf*/
2548 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
97e89ee9
MF		 2549 if (gen_window_check1(dc, RRI8_S) &&
2550 gen_check_cpenable(dc, 0)) {
9ed7ae12
MF		 2551 TCGv_i32 addr = tcg_temp_new_i32();
2552 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2553 gen_load_store_alignment(dc, 2, addr, false);
2554 if (RRI8_R & 0x4) {
2555 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2556 } else {
2557 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2558 }
2559 if (RRI8_R & 0x8) {
2560 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2561 }
2562 tcg_temp_free(addr);
2563 }
2564 break;
2565
2566 default: /*reserved*/
2567 RESERVED();
2568 break;
2569 }
dedc5eae
MF		 2570 break;
2571
2572 case 4: /*MAC16d*/
2573 HAS_OPTION(XTENSA_OPTION_MAC16);
6825b6c3
MF		 2574 {
2575 enum {
2576 MAC16_UMUL = 0x0,
2577 MAC16_MUL = 0x4,
2578 MAC16_MULA = 0x8,
2579 MAC16_MULS = 0xc,
2580 MAC16_NONE = 0xf,
2581 } op = OP1 & 0xc;
2582 bool is_m1_sr = (OP2 & 0x3) == 2;
2583 bool is_m2_sr = (OP2 & 0xc) == 0;
2584 uint32_t ld_offset = 0;
2585
2586 if (OP2 > 9) {
2587 RESERVED();
2588 }
2589
2590 switch (OP2 & 2) {
2591 case 0: /*MACI?/MACC?*/
2592 is_m1_sr = true;
2593 ld_offset = (OP2 & 1) ? -4 : 4;
2594
2595 if (OP2 >= 8) { /*MACI/MACC*/
2596 if (OP1 == 0) { /*LDINC/LDDEC*/
2597 op = MAC16_NONE;
2598 } else {
2599 RESERVED();
2600 }
2601 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2602 RESERVED();
2603 }
2604 break;
2605
2606 case 2: /*MACD?/MACA?*/
2607 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2608 RESERVED();
2609 }
2610 break;
2611 }
2612
2613 if (op != MAC16_NONE) {
97e89ee9
MF		 2614 if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) {
2615 break;
6825b6c3 2616 }
97e89ee9
MF		 2617 if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) {
2618 break;
6825b6c3
MF		 2619 }
2620 }
2621
97e89ee9
MF		 2622 if (ld_offset && !gen_window_check1(dc, RRR_S)) {
2623 break;
2624 }
2625
6825b6c3
MF		 2626 {
2627 TCGv_i32 vaddr = tcg_temp_new_i32();
2628 TCGv_i32 mem32 = tcg_temp_new_i32();
2629
2630 if (ld_offset) {
6825b6c3
MF		 2631 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2632 gen_load_store_alignment(dc, 2, vaddr, false);
2633 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2634 }
2635 if (op != MAC16_NONE) {
2636 TCGv_i32 m1 = gen_mac16_m(
2637 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2638 OP1 & 1, op == MAC16_UMUL);
2639 TCGv_i32 m2 = gen_mac16_m(
2640 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2641 OP1 & 2, op == MAC16_UMUL);
2642
2643 if (op == MAC16_MUL || op == MAC16_UMUL) {
2644 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2645 if (op == MAC16_UMUL) {
2646 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2647 } else {
2648 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2649 }
2650 } else {
d2123a07
RH		 2651 TCGv_i32 lo = tcg_temp_new_i32();
2652 TCGv_i32 hi = tcg_temp_new_i32();
2653
2654 tcg_gen_mul_i32(lo, m1, m2);
2655 tcg_gen_sari_i32(hi, lo, 31);
6825b6c3 2656 if (op == MAC16_MULA) {
d2123a07
RH		 2657 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2658 cpu_SR[ACCLO], cpu_SR[ACCHI],
2659 lo, hi);
6825b6c3 2660 } else {
d2123a07
RH		 2661 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2662 cpu_SR[ACCLO], cpu_SR[ACCHI],
2663 lo, hi);
6825b6c3 2664 }
6825b6c3
MF		 2665 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2666
d2123a07
RH		 2667 tcg_temp_free_i32(lo);
2668 tcg_temp_free_i32(hi);
6825b6c3
MF		 2669 }
2670 tcg_temp_free(m1);
2671 tcg_temp_free(m2);
2672 }
2673 if (ld_offset) {
2674 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2675 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2676 }
2677 tcg_temp_free(vaddr);
2678 tcg_temp_free(mem32);
2679 }
2680 }
dedc5eae
MF		 2681 break;
2682
2683 case 5: /*CALLN*/
2684 switch (CALL_N) {
2685 case 0: /*CALL0*/
2686 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2687 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2688 break;
2689
2690 case 1: /*CALL4w*/
2691 case 2: /*CALL8w*/
2692 case 3: /*CALL12w*/
2693 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9
MF		 2694 if (gen_window_check1(dc, CALL_N << 2)) {
2695 gen_callwi(dc, CALL_N,
2696 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2697 }
dedc5eae
MF		 2698 break;
2699 }
2700 break;
2701
2702 case 6: /*SI*/
2703 switch (CALL_N) {
2704 case 0: /*J*/
2705 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2706 break;
2707
bd57fb91 2708 case 1: /*BZ*/
97e89ee9 2709 if (gen_window_check1(dc, BRI12_S)) {
bd57fb91
MF		 2710 static const TCGCond cond[] = {
2711 TCG_COND_EQ, /*BEQZ*/
2712 TCG_COND_NE, /*BNEZ*/
2713 TCG_COND_LT, /*BLTZ*/
2714 TCG_COND_GE, /*BGEZ*/
2715 };
2716
2717 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2718 4 + BRI12_IMM12_SE);
2719 }
2720 break;
2721
2722 case 2: /*BI0*/
97e89ee9 2723 if (gen_window_check1(dc, BRI8_S)) {
bd57fb91
MF		 2724 static const TCGCond cond[] = {
2725 TCG_COND_EQ, /*BEQI*/
2726 TCG_COND_NE, /*BNEI*/
2727 TCG_COND_LT, /*BLTI*/
2728 TCG_COND_GE, /*BGEI*/
2729 };
2730
2731 gen_brcondi(dc, cond[BRI8_M & 3],
2732 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2733 }
2734 break;
2735
2736 case 3: /*BI1*/
2737 switch (BRI8_M) {
2738 case 0: /*ENTRYw*/
2739 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2740 {
2741 TCGv_i32 pc = tcg_const_i32(dc->pc);
2742 TCGv_i32 s = tcg_const_i32(BRI12_S);
2743 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
b994e91b 2744 gen_advance_ccount(dc);
f492b82d 2745 gen_helper_entry(cpu_env, pc, s, imm);
553e44f9
MF		 2746 tcg_temp_free(imm);
2747 tcg_temp_free(s);
2748 tcg_temp_free(pc);
2db59a76
MF		 2749 /* This can change tb->flags, so exit tb */
2750 gen_jumpi_check_loop_end(dc, -1);
553e44f9 2751 }
bd57fb91
MF		 2752 break;
2753
2754 case 1: /*B1*/
2755 switch (BRI8_R) {
2756 case 0: /*BFp*/
bd57fb91
MF		 2757 case 1: /*BTp*/
2758 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 2759 {
2760 TCGv_i32 tmp = tcg_temp_new_i32();
2761 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2762 gen_brcondi(dc,
2763 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2764 tmp, 0, 4 + RRI8_IMM8_SE);
2765 tcg_temp_free(tmp);
2766 }
bd57fb91
MF		 2767 break;
2768
2769 case 8: /*LOOP*/
bd57fb91 2770 case 9: /*LOOPNEZ*/
bd57fb91 2771 case 10: /*LOOPGTZ*/
797d780b 2772 HAS_OPTION(XTENSA_OPTION_LOOP);
97e89ee9 2773 if (gen_window_check1(dc, RRI8_S)) {
797d780b
MF		 2774 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2775 TCGv_i32 tmp = tcg_const_i32(lend);
2776
2777 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2778 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
f492b82d 2779 gen_helper_wsr_lend(cpu_env, tmp);
797d780b
MF		 2780 tcg_temp_free(tmp);
2781
2782 if (BRI8_R > 8) {
42a268c2 2783 TCGLabel *label = gen_new_label();
797d780b
MF		 2784 tcg_gen_brcondi_i32(
2785 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2786 cpu_R[RRI8_S], 0, label);
2787 gen_jumpi(dc, lend, 1);
2788 gen_set_label(label);
2789 }
2790
2791 gen_jumpi(dc, dc->next_pc, 0);
2792 }
bd57fb91
MF		 2793 break;
2794
2795 default: /*reserved*/
91a5bb76 2796 RESERVED();
bd57fb91
MF		 2797 break;
2798
2799 }
2800 break;
2801
2802 case 2: /*BLTUI*/
2803 case 3: /*BGEUI*/
97e89ee9
MF		 2804 if (gen_window_check1(dc, BRI8_S)) {
2805 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2806 cpu_R[BRI8_S], B4CONSTU[BRI8_R],
2807 4 + BRI8_IMM8_SE);
2808 }
bd57fb91
MF		 2809 break;
2810 }
2811 break;
2812
dedc5eae
MF		 2813 }
2814 break;
2815
2816 case 7: /*B*/
bd57fb91
MF		 2817 {
2818 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2819
2820 switch (RRI8_R & 7) {
2821 case 0: /*BNONE*/ /*BANY*/
97e89ee9 2822 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
bd57fb91
MF		 2823 TCGv_i32 tmp = tcg_temp_new_i32();
2824 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2825 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2826 tcg_temp_free(tmp);
2827 }
2828 break;
2829
2830 case 1: /*BEQ*/ /*BNE*/
2831 case 2: /*BLT*/ /*BGE*/
2832 case 3: /*BLTU*/ /*BGEU*/
97e89ee9 2833 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
bd57fb91
MF		 2834 static const TCGCond cond[] = {
2835 [1] = TCG_COND_EQ,
2836 [2] = TCG_COND_LT,
2837 [3] = TCG_COND_LTU,
2838 [9] = TCG_COND_NE,
2839 [10] = TCG_COND_GE,
2840 [11] = TCG_COND_GEU,
2841 };
2842 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2843 4 + RRI8_IMM8_SE);
2844 }
2845 break;
2846
2847 case 4: /*BALL*/ /*BNALL*/
97e89ee9 2848 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
bd57fb91
MF		 2849 TCGv_i32 tmp = tcg_temp_new_i32();
2850 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2851 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2852 4 + RRI8_IMM8_SE);
2853 tcg_temp_free(tmp);
2854 }
2855 break;
2856
2857 case 5: /*BBC*/ /*BBS*/
97e89ee9 2858 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
7ff7563f
MF		 2859#ifdef TARGET_WORDS_BIGENDIAN
2860 TCGv_i32 bit = tcg_const_i32(0x80000000);
2861#else
2862 TCGv_i32 bit = tcg_const_i32(0x00000001);
2863#endif
bd57fb91
MF		 2864 TCGv_i32 tmp = tcg_temp_new_i32();
2865 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
7ff7563f
MF		 2866#ifdef TARGET_WORDS_BIGENDIAN
2867 tcg_gen_shr_i32(bit, bit, tmp);
2868#else
bd57fb91 2869 tcg_gen_shl_i32(bit, bit, tmp);
7ff7563f 2870#endif
bd57fb91
MF		 2871 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2872 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2873 tcg_temp_free(tmp);
2874 tcg_temp_free(bit);
2875 }
2876 break;
2877
2878 case 6: /*BBCI*/ /*BBSI*/
2879 case 7:
97e89ee9 2880 if (gen_window_check1(dc, RRI8_S)) {
bd57fb91
MF		 2881 TCGv_i32 tmp = tcg_temp_new_i32();
2882 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
7ff7563f
MF		 2883#ifdef TARGET_WORDS_BIGENDIAN
2884 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2885#else
2886 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2887#endif
bd57fb91
MF		 2888 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2889 tcg_temp_free(tmp);
2890 }
2891 break;
2892
2893 }
2894 }
dedc5eae
MF		 2895 break;
2896
67882fd1 2897#define gen_narrow_load_store(type) do { \
97e89ee9
MF		 2898 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2899 TCGv_i32 addr = tcg_temp_new_i32(); \
2900 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2901 gen_load_store_alignment(dc, 2, addr, false); \
2902 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2903 tcg_temp_free(addr); \
2904 } \
67882fd1
MF		 2905 } while (0)
2906
dedc5eae 2907 case 8: /*L32I.Nn*/
67882fd1 2908 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2909 break;
2910
2911 case 9: /*S32I.Nn*/
67882fd1 2912 gen_narrow_load_store(st32);
dedc5eae 2913 break;
67882fd1 2914#undef gen_narrow_load_store
dedc5eae
MF		 2915
2916 case 10: /*ADD.Nn*/
97e89ee9
MF		 2917 if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) {
2918 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2919 }
dedc5eae
MF		 2920 break;
2921
2922 case 11: /*ADDI.Nn*/
97e89ee9
MF		 2923 if (gen_window_check2(dc, RRRN_R, RRRN_S)) {
2924 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S],
2925 RRRN_T ? RRRN_T : -1);
2926 }
dedc5eae
MF		 2927 break;
2928
2929 case 12: /*ST2n*/
97e89ee9
MF		 2930 if (!gen_window_check1(dc, RRRN_S)) {
2931 break;
2932 }
67882fd1
MF		 2933 if (RRRN_T < 8) { /*MOVI.Nn*/
2934 tcg_gen_movi_i32(cpu_R[RRRN_S],
2935 RRRN_R | (RRRN_T << 4) |
2936 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2937 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 2938 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2939
2940 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2941 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 2942 }
dedc5eae
MF		 2943 break;
2944
2945 case 13: /*ST3n*/
67882fd1
MF		 2946 switch (RRRN_R) {
2947 case 0: /*MOV.Nn*/
97e89ee9
MF		 2948 if (gen_window_check2(dc, RRRN_S, RRRN_T)) {
2949 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2950 }
67882fd1
MF		 2951 break;
2952
2953 case 15: /*S3*/
2954 switch (RRRN_T) {
2955 case 0: /*RET.Nn*/
2956 gen_jump(dc, cpu_R[0]);
2957 break;
2958
2959 case 1: /*RETW.Nn*/
91a5bb76 2960 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2961 {
2962 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 2963 gen_advance_ccount(dc);
f492b82d 2964 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 2965 gen_jump(dc, tmp);
2966 tcg_temp_free(tmp);
2967 }
67882fd1
MF		 2968 break;
2969
2970 case 2: /*BREAK.Nn*/
e61dc8f7
MF		 2971 HAS_OPTION(XTENSA_OPTION_DEBUG);
2972 if (dc->debug) {
2973 gen_debug_exception(dc, DEBUGCAUSE_BN);
2974 }
67882fd1
MF		 2975 break;
2976
2977 case 3: /*NOP.Nn*/
2978 break;
2979
2980 case 6: /*ILL.Nn*/
40643d7c 2981 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 2982 break;
2983
2984 default: /*reserved*/
91a5bb76 2985 RESERVED();
67882fd1
MF		 2986 break;
2987 }
2988 break;
2989
2990 default: /*reserved*/
91a5bb76 2991 RESERVED();
67882fd1
MF		 2992 break;
2993 }
dedc5eae
MF		 2994 break;
2995
2996 default: /*reserved*/
91a5bb76 2997 RESERVED();
dedc5eae
MF		 2998 break;
2999 }
3000
c26032b2
MF		 3001 if (dc->is_jmp == DISAS_NEXT) {
3002 gen_check_loop_end(dc, 0);
3003 }
dedc5eae 3004 dc->pc = dc->next_pc;
797d780b 3005
dedc5eae
MF		 3006 return;
3007
3008invalid_opcode:
3009 qemu_log("INVALID(pc = %08x)\n", dc->pc);
6b814719 3010 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dedc5eae
MF		 3011#undef HAS_OPTION
3012}
3013
01673a34
MF		 3014static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
3015{
3016 uint8_t b0 = cpu_ldub_code(env, dc->pc);
3017 return xtensa_op0_insn_len(OP0);
3018}
3019
97129ac8 3020static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
e61dc8f7
MF		 3021{
3022 unsigned i;
3023
3024 for (i = 0; i < dc->config->nibreak; ++i) {
3025 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
3026 env->sregs[IBREAKA + i] == dc->pc) {
3027 gen_debug_exception(dc, DEBUGCAUSE_IB);
3028 break;
3029 }
3030 }
3031}
3032
4e5e1215 3033void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
dedc5eae 3034{
4e5e1215 3035 XtensaCPU *cpu = xtensa_env_get_cpu(env);
ed2803da 3036 CPUState *cs = CPU(cpu);
dedc5eae
MF		 3037 DisasContext dc;
3038 int insn_count = 0;
dedc5eae
MF		 3039 int max_insns = tb->cflags & CF_COUNT_MASK;
3040 uint32_t pc_start = tb->pc;
3041 uint32_t next_page_start =
3042 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3043
3044 if (max_insns == 0) {
3045 max_insns = CF_COUNT_MASK;
3046 }
190ce7fb
RH		 3047 if (max_insns > TCG_MAX_INSNS) {
3048 max_insns = TCG_MAX_INSNS;
3049 }
dedc5eae
MF		 3050
3051 dc.config = env->config;
ed2803da 3052 dc.singlestep_enabled = cs->singlestep_enabled;
dedc5eae
MF		 3053 dc.tb = tb;
3054 dc.pc = pc_start;
f0a548b9
MF		 3055 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3056 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 3057 dc.lbeg = env->sregs[LBEG];
3058 dc.lend = env->sregs[LEND];
dedc5eae 3059 dc.is_jmp = DISAS_NEXT;
b994e91b 3060 dc.ccount_delta = 0;
e61dc8f7 3061 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
35b5c044 3062 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
ef04a846
MF		 3063 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3064 XTENSA_TBFLAG_CPENABLE_SHIFT;
2db59a76
MF		 3065 dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
3066 XTENSA_TBFLAG_WINDOW_SHIFT);
dedc5eae 3067
6ad6dbf7 3068 init_litbase(&dc);
3580ecad 3069 init_sar_tracker(&dc);
35b5c044
MF		 3070 if (dc.icount) {
3071 dc.next_icount = tcg_temp_local_new_i32();
3072 }
3580ecad 3073
cd42d5b2 3074 gen_tb_start(tb);
dedc5eae 3075
a00817cc 3076 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
40643d7c 3077 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 3078 gen_exception(&dc, EXCP_DEBUG);
40643d7c
MF		 3079 }
3080
dedc5eae 3081 do {
667b8e29 3082 tcg_gen_insn_start(dc.pc);
959082fc 3083 ++insn_count;
dedc5eae 3084
b994e91b
MF		 3085 ++dc.ccount_delta;
3086
b933066a
RH		 3087 if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
3088 tcg_gen_movi_i32(cpu_pc, dc.pc);
3089 gen_exception(&dc, EXCP_DEBUG);
3090 dc.is_jmp = DISAS_UPDATE;
3091 break;
3092 }
3093
959082fc 3094 if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
b994e91b
MF		 3095 gen_io_start();
3096 }
3097
35b5c044 3098 if (dc.icount) {
42a268c2 3099 TCGLabel *label = gen_new_label();
35b5c044
MF		 3100
3101 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3102 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3103 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3104 if (dc.debug) {
3105 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3106 }
3107 gen_set_label(label);
3108 }
3109
e61dc8f7
MF		 3110 if (dc.debug) {
3111 gen_ibreak_check(env, &dc);
3112 }
3113
0c4fabea 3114 disas_xtensa_insn(env, &dc);
35b5c044
MF		 3115 if (dc.icount) {
3116 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3117 }
ed2803da 3118 if (cs->singlestep_enabled) {
dedc5eae 3119 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 3120 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 3121 break;
3122 }
3123 } while (dc.is_jmp == DISAS_NEXT &&
3124 insn_count < max_insns &&
3125 dc.pc < next_page_start &&
01673a34 3126 dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
fe700adb 3127 !tcg_op_buf_full());
dedc5eae 3128
6ad6dbf7 3129 reset_litbase(&dc);
3580ecad 3130 reset_sar_tracker(&dc);
35b5c044
MF		 3131 if (dc.icount) {
3132 tcg_temp_free(dc.next_icount);
3133 }
3580ecad 3134
b994e91b
MF		 3135 if (tb->cflags & CF_LAST_IO) {
3136 gen_io_end();
3137 }
3138
dedc5eae
MF		 3139 if (dc.is_jmp == DISAS_NEXT) {
3140 gen_jumpi(&dc, dc.pc, 0);
3141 }
806f352d 3142 gen_tb_end(tb, insn_count);
dedc5eae 3143
ca529f8e
MF		 3144#ifdef DEBUG_DISAS
3145 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3146 qemu_log("----------------\n");
3147 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 3148 log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
ca529f8e
MF		 3149 qemu_log("\n");
3150 }
3151#endif
4e5e1215
RH		 3152 tb->size = dc.pc - pc_start;
3153 tb->icount = insn_count;
2328826b
MF		 3154}
3155
878096ee
AF		 3156void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3157 fprintf_function cpu_fprintf, int flags)
2328826b 3158{
878096ee
AF		 3159 XtensaCPU *cpu = XTENSA_CPU(cs);
3160 CPUXtensaState *env = &cpu->env;
2af3da91
MF		 3161 int i, j;
3162
3163 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3164
3165 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3166 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3167 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
2af3da91
MF		 3168 (j++ % 4) == 3 ? '\n' : ' ');
3169 }
3170 }
3171
3172 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3173
3174 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3175 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3176 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
2af3da91
MF		 3177 (j++ % 4) == 3 ? '\n' : ' ');
3178 }
3179 }
2328826b 3180
2af3da91 3181 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 3182
3183 for (i = 0; i < 16; ++i) {
fe0bd475 3184 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
2328826b
MF		 3185 (i % 4) == 3 ? '\n' : ' ');
3186 }
553e44f9
MF		 3187
3188 cpu_fprintf(f, "\n");
3189
3190 for (i = 0; i < env->config->nareg; ++i) {
3191 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3192 (i % 4) == 3 ? '\n' : ' ');
3193 }
dd519cbe
MF		 3194
3195 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3196 cpu_fprintf(f, "\n");
3197
3198 for (i = 0; i < 16; ++i) {
3199 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
ddd44279
MF		 3200 float32_val(env->fregs[i].f32[FP_F32_LOW]),
3201 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
3202 (i % 2) == 1 ? '\n' : ' ');
dd519cbe
MF		 3203 }
3204 }
2328826b
MF		 3205}
3206
bad729e2
RH		 3207void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
3208 target_ulong *data)
2328826b 3209{
bad729e2 3210 env->pc = data[0];
2328826b 3211}
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