[mirror_qemu.git] / tcg / arm / tcg-target-con-str.h

/* SPDX-License-Identifier: MIT */
/*
 * Define Arm target-specific operand constraints.
 * Copyright (c) 2021 Linaro
 */

/*
 * Define constraint letters for register sets:
 * REGS(letter, register_mask)
 */
REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */
REGS('r', ALL_GENERAL_REGS)
REGS('l', ALL_QLOAD_REGS)
REGS('s', ALL_QSTORE_REGS)
REGS('S', ALL_QSTORE_REGS & 0x5555)  /* even qstore */
REGS('w', ALL_VECTOR_REGS)

/*
 * Define constraint letters for constants:
 * CONST(letter, TCG_CT_CONST_* bit set)
 */
CONST('I', TCG_CT_CONST_ARM)
CONST('K', TCG_CT_CONST_INV)
CONST('N', TCG_CT_CONST_NEG)
CONST('O', TCG_CT_CONST_ORRI)
CONST('V', TCG_CT_CONST_ANDI)
CONST('Z', TCG_CT_CONST_ZERO)
Commit	Line	Data
3440d583 RH	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Define Arm target-specific operand constraints.
	4	* Copyright (c) 2021 Linaro
	5	*/
	6
	7	/*
	8	* Define constraint letters for register sets:
	9	* REGS(letter, register_mask)
	10	*/
1b18d1fa	11	REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */
3440d583 RH	12	REGS('r', ALL_GENERAL_REGS)
	13	REGS('l', ALL_QLOAD_REGS)
	14	REGS('s', ALL_QSTORE_REGS)
1b18d1fa	15	REGS('S', ALL_QSTORE_REGS & 0x5555) /* even qstore */
000cf477	16	REGS('w', ALL_VECTOR_REGS)
3440d583 RH	17
	18	/*
	19	* Define constraint letters for constants:
	20	* CONST(letter, TCG_CT_CONST_* bit set)
	21	*/
	22	CONST('I', TCG_CT_CONST_ARM)
	23	CONST('K', TCG_CT_CONST_INV)
	24	CONST('N', TCG_CT_CONST_NEG)
d74b86ed RH	25	CONST('O', TCG_CT_CONST_ORRI)
d74b86ed RH	26	CONST('V', TCG_CT_CONST_ANDI)
3440d583	27	CONST('Z', TCG_CT_CONST_ZERO)