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tcg/arm: remove SAVE_LR code
[mirror_qemu.git] / tcg / arm / tcg-target.c
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811d4cf4
AZ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
d4a9eb1f
BS		 24
25#ifndef NDEBUG
26static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
811d4cf4
AZ		 27 "%r0",
28 "%r1",
29 "%r2",
30 "%r3",
31 "%r4",
32 "%r5",
33 "%r6",
34 "%r7",
35 "%r8",
36 "%r9",
37 "%r10",
38 "%r11",
39 "%r12",
40 "%r13",
41 "%r14",
42};
d4a9eb1f 43#endif
811d4cf4 44
d4a9eb1f 45static const int tcg_target_reg_alloc_order[] = {
811d4cf4
AZ		 46 TCG_REG_R0,
47 TCG_REG_R1,
48 TCG_REG_R2,
49 TCG_REG_R3,
50 TCG_REG_R4,
51 TCG_REG_R5,
52 TCG_REG_R6,
53 TCG_REG_R7,
54 TCG_REG_R8,
55 TCG_REG_R9,
56 TCG_REG_R10,
57 TCG_REG_R11,
58 TCG_REG_R12,
59 TCG_REG_R13,
60 TCG_REG_R14,
61};
62
d4a9eb1f 63static const int tcg_target_call_iarg_regs[4] = {
811d4cf4
AZ		 64 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
65};
d4a9eb1f 66static const int tcg_target_call_oarg_regs[2] = {
811d4cf4
AZ		 67 TCG_REG_R0, TCG_REG_R1
68};
69
650bbb36 70static void patch_reloc(uint8_t *code_ptr, int type,
811d4cf4
AZ		 71 tcg_target_long value, tcg_target_long addend)
72{
73 switch (type) {
74 case R_ARM_ABS32:
75 *(uint32_t *) code_ptr = value;
76 break;
77
78 case R_ARM_CALL:
79 case R_ARM_JUMP24:
80 default:
81 tcg_abort();
82
83 case R_ARM_PC24:
eae6ce52 84 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & 0xff000000) |
e936243a 85 (((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff);
811d4cf4
AZ		 86 break;
87 }
88}
89
90/* maximum number of register used for input function arguments */
91static inline int tcg_target_get_call_iarg_regs_count(int flags)
92{
93 return 4;
94}
95
811d4cf4 96/* parse target specific constraints */
d4a9eb1f 97static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
811d4cf4
AZ		 98{
99 const char *ct_str;
100
101 ct_str = *pct_str;
102 switch (ct_str[0]) {
cb4e581f
LD		 103 case 'I':
104 ct->ct |= TCG_CT_CONST_ARM;
105 break;
106
811d4cf4
AZ		 107 case 'r':
108#ifndef CONFIG_SOFTMMU
109 case 'd':
110 case 'D':
111 case 'x':
112 case 'X':
113#endif
114 ct->ct |= TCG_CT_REG;
115 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
116 break;
117
118#ifdef CONFIG_SOFTMMU
d0660ed4 119 /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
811d4cf4
AZ		 120 case 'x':
121 ct->ct |= TCG_CT_REG;
122 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
811d4cf4
AZ		 123 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
124 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4
AZ		 125 break;
126
d0660ed4
AZ		 127 /* qemu_ld64 data_reg */
128 case 'd':
129 ct->ct |= TCG_CT_REG;
130 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
131 /* r1 is still needed to load data_reg2, so don't use it. */
132 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
133 break;
134
811d4cf4
AZ		 135 /* qemu_ld/st64 data_reg2 */
136 case 'D':
137 ct->ct |= TCG_CT_REG;
138 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
139 /* r0, r1 and optionally r2 will be overwritten by the address
140 * and the low word of data, so don't use these. */
141 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
142 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
143# if TARGET_LONG_BITS == 64
144 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
145# endif
146 break;
147
148# if TARGET_LONG_BITS == 64
149 /* qemu_ld/st addr_reg2 */
150 case 'X':
151 ct->ct |= TCG_CT_REG;
152 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
153 /* r0 will be overwritten by the low word of base, so don't use it. */
154 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
811d4cf4 155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4
AZ		 156 break;
157# endif
158#endif
159
811d4cf4
AZ		 160 default:
161 return -1;
162 }
163 ct_str++;
164 *pct_str = ct_str;
165
166 return 0;
167}
168
94953e6d
LD		 169static inline uint32_t rotl(uint32_t val, int n)
170{
171 return (val << n) | (val >> (32 - n));
172}
173
174/* ARM immediates for ALU instructions are made of an unsigned 8-bit
175 right-rotated by an even amount between 0 and 30. */
176static inline int encode_imm(uint32_t imm)
177{
4e6f6d4c
LD		 178 int shift;
179
94953e6d
LD		 180 /* simple case, only lower bits */
181 if ((imm & ~0xff) == 0)
182 return 0;
183 /* then try a simple even shift */
184 shift = ctz32(imm) & ~1;
185 if (((imm >> shift) & ~0xff) == 0)
186 return 32 - shift;
187 /* now try harder with rotations */
188 if ((rotl(imm, 2) & ~0xff) == 0)
189 return 2;
190 if ((rotl(imm, 4) & ~0xff) == 0)
191 return 4;
192 if ((rotl(imm, 6) & ~0xff) == 0)
193 return 6;
194 /* imm can't be encoded */
195 return -1;
196}
cb4e581f
LD		 197
198static inline int check_fit_imm(uint32_t imm)
199{
94953e6d 200 return encode_imm(imm) >= 0;
cb4e581f
LD		 201}
202
811d4cf4
AZ		 203/* Test if a constant matches the constraint.
204 * TODO: define constraints for:
205 *
206 * ldr/str offset: between -0xfff and 0xfff
207 * ldrh/strh offset: between -0xff and 0xff
208 * mov operand2: values represented with x << (2 * y), x < 0x100
209 * add, sub, eor...: ditto
210 */
211static inline int tcg_target_const_match(tcg_target_long val,
212 const TCGArgConstraint *arg_ct)
213{
214 int ct;
215 ct = arg_ct->ct;
216 if (ct & TCG_CT_CONST)
217 return 1;
cb4e581f
LD		 218 else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
219 return 1;
811d4cf4
AZ		 220 else
221 return 0;
222}
223
224enum arm_data_opc_e {
225 ARITH_AND = 0x0,
226 ARITH_EOR = 0x1,
227 ARITH_SUB = 0x2,
228 ARITH_RSB = 0x3,
229 ARITH_ADD = 0x4,
230 ARITH_ADC = 0x5,
231 ARITH_SBC = 0x6,
232 ARITH_RSC = 0x7,
3979144c 233 ARITH_TST = 0x8,
811d4cf4
AZ		 234 ARITH_CMP = 0xa,
235 ARITH_CMN = 0xb,
236 ARITH_ORR = 0xc,
237 ARITH_MOV = 0xd,
238 ARITH_BIC = 0xe,
239 ARITH_MVN = 0xf,
240};
241
3979144c
PB		 242#define TO_CPSR(opc) \
243 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
811d4cf4
AZ		 244
245#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
246#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
247#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
248#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
249#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
250#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
251#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
252#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
253
254enum arm_cond_code_e {
255 COND_EQ = 0x0,
256 COND_NE = 0x1,
257 COND_CS = 0x2, /* Unsigned greater or equal */
258 COND_CC = 0x3, /* Unsigned less than */
259 COND_MI = 0x4, /* Negative */
260 COND_PL = 0x5, /* Zero or greater */
261 COND_VS = 0x6, /* Overflow */
262 COND_VC = 0x7, /* No overflow */
263 COND_HI = 0x8, /* Unsigned greater than */
264 COND_LS = 0x9, /* Unsigned less or equal */
265 COND_GE = 0xa,
266 COND_LT = 0xb,
267 COND_GT = 0xc,
268 COND_LE = 0xd,
269 COND_AL = 0xe,
270};
271
272static const uint8_t tcg_cond_to_arm_cond[10] = {
273 [TCG_COND_EQ] = COND_EQ,
274 [TCG_COND_NE] = COND_NE,
275 [TCG_COND_LT] = COND_LT,
276 [TCG_COND_GE] = COND_GE,
277 [TCG_COND_LE] = COND_LE,
278 [TCG_COND_GT] = COND_GT,
279 /* unsigned */
280 [TCG_COND_LTU] = COND_CC,
281 [TCG_COND_GEU] = COND_CS,
282 [TCG_COND_LEU] = COND_LS,
283 [TCG_COND_GTU] = COND_HI,
284};
285
286static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
287{
288 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
289}
290
291static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
292{
293 tcg_out32(s, (cond << 28) | 0x0a000000 |
294 (((offset - 8) >> 2) & 0x00ffffff));
295}
296
e936243a
AZ		 297static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
298{
e2542fe2 299#ifdef HOST_WORDS_BIGENDIAN
e936243a
AZ		 300 tcg_out8(s, (cond << 4) | 0x0a);
301 s->code_ptr += 3;
302#else
303 s->code_ptr += 3;
304 tcg_out8(s, (cond << 4) | 0x0a);
305#endif
306}
307
811d4cf4
AZ		 308static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
309{
310 tcg_out32(s, (cond << 28) | 0x0b000000 |
311 (((offset - 8) >> 2) & 0x00ffffff));
312}
313
314static inline void tcg_out_dat_reg(TCGContext *s,
315 int cond, int opc, int rd, int rn, int rm, int shift)
316{
317 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
318 (rn << 16) | (rd << 12) | shift | rm);
319}
320
321static inline void tcg_out_dat_reg2(TCGContext *s,
322 int cond, int opc0, int opc1, int rd0, int rd1,
323 int rn0, int rn1, int rm0, int rm1, int shift)
324{
0c9c3a9e
AZ		 325 if (rd0 == rn1 || rd0 == rm1) {
326 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
327 (rn0 << 16) | (8 << 12) | shift | rm0);
328 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
329 (rn1 << 16) | (rd1 << 12) | shift | rm1);
330 tcg_out_dat_reg(s, cond, ARITH_MOV,
331 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
332 } else {
333 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
334 (rn0 << 16) | (rd0 << 12) | shift | rm0);
335 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
336 (rn1 << 16) | (rd1 << 12) | shift | rm1);
337 }
811d4cf4
AZ		 338}
339
340static inline void tcg_out_dat_imm(TCGContext *s,
341 int cond, int opc, int rd, int rn, int im)
342{
3979144c 343 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
811d4cf4
AZ		 344 (rn << 16) | (rd << 12) | im);
345}
346
347static inline void tcg_out_movi32(TCGContext *s,
348 int cond, int rd, int32_t arg)
349{
350 int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);
351
352 /* TODO: This is very suboptimal, we can easily have a constant
353 * pool somewhere after all the instructions. */
354
355 if (arg < 0 && arg > -0x100)
356 return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
357
358 if (offset < 0x100 && offset > -0x100)
359 return offset >= 0 ?
360 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
361 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
362
cb4e581f
LD		 363#ifdef __ARM_ARCH_7A__
364 /* use movw/movt */
365 /* movw */
366 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
367 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
368 if (arg & 0xffff0000)
369 /* movt */
370 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
371 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
372#else
811d4cf4
AZ		 373 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
374 if (arg & 0x0000ff00)
375 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
376 ((arg >> 8) & 0xff) | 0xc00);
377 if (arg & 0x00ff0000)
378 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
379 ((arg >> 16) & 0xff) | 0x800);
380 if (arg & 0xff000000)
381 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
382 ((arg >> 24) & 0xff) | 0x400);
cb4e581f 383#endif
811d4cf4
AZ		 384}
385
386static inline void tcg_out_mul32(TCGContext *s,
387 int cond, int rd, int rs, int rm)
388{
389 if (rd != rm)
390 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
391 (rs << 8) | 0x90 | rm);
392 else if (rd != rs)
393 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
394 (rm << 8) | 0x90 | rs);
395 else {
396 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
397 (rs << 8) | 0x90 | rm);
398 tcg_out_dat_reg(s, cond, ARITH_MOV,
399 rd, 0, 8, SHIFT_IMM_LSL(0));
400 }
401}
402
403static inline void tcg_out_umull32(TCGContext *s,
404 int cond, int rd0, int rd1, int rs, int rm)
405{
406 if (rd0 != rm && rd1 != rm)
407 tcg_out32(s, (cond << 28) | 0x800090 |
408 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
409 else if (rd0 != rs && rd1 != rs)
410 tcg_out32(s, (cond << 28) | 0x800090 |
411 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
412 else {
413 tcg_out_dat_reg(s, cond, ARITH_MOV,
414 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
415 tcg_out32(s, (cond << 28) | 0x800098 |
416 (rd1 << 16) | (rd0 << 12) | (rs << 8));
417 }
418}
419
420static inline void tcg_out_smull32(TCGContext *s,
421 int cond, int rd0, int rd1, int rs, int rm)
422{
423 if (rd0 != rm && rd1 != rm)
424 tcg_out32(s, (cond << 28) | 0xc00090 |
425 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
426 else if (rd0 != rs && rd1 != rs)
427 tcg_out32(s, (cond << 28) | 0xc00090 |
428 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
429 else {
430 tcg_out_dat_reg(s, cond, ARITH_MOV,
431 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
432 tcg_out32(s, (cond << 28) | 0xc00098 |
433 (rd1 << 16) | (rd0 << 12) | (rs << 8));
434 }
435}
436
437static inline void tcg_out_ld32_12(TCGContext *s, int cond,
438 int rd, int rn, tcg_target_long im)
439{
440 if (im >= 0)
441 tcg_out32(s, (cond << 28) | 0x05900000 |
442 (rn << 16) | (rd << 12) | (im & 0xfff));
443 else
444 tcg_out32(s, (cond << 28) | 0x05100000 |
445 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
446}
447
448static inline void tcg_out_st32_12(TCGContext *s, int cond,
449 int rd, int rn, tcg_target_long im)
450{
451 if (im >= 0)
452 tcg_out32(s, (cond << 28) | 0x05800000 |
453 (rn << 16) | (rd << 12) | (im & 0xfff));
454 else
455 tcg_out32(s, (cond << 28) | 0x05000000 |
456 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
457}
458
459static inline void tcg_out_ld32_r(TCGContext *s, int cond,
460 int rd, int rn, int rm)
461{
462 tcg_out32(s, (cond << 28) | 0x07900000 |
463 (rn << 16) | (rd << 12) | rm);
464}
465
466static inline void tcg_out_st32_r(TCGContext *s, int cond,
467 int rd, int rn, int rm)
468{
469 tcg_out32(s, (cond << 28) | 0x07800000 |
470 (rn << 16) | (rd << 12) | rm);
471}
472
3979144c
PB		 473/* Register pre-increment with base writeback. */
474static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
475 int rd, int rn, int rm)
476{
477 tcg_out32(s, (cond << 28) | 0x07b00000 |
478 (rn << 16) | (rd << 12) | rm);
479}
480
481static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
482 int rd, int rn, int rm)
483{
484 tcg_out32(s, (cond << 28) | 0x07a00000 |
485 (rn << 16) | (rd << 12) | rm);
486}
487
811d4cf4
AZ		 488static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
489 int rd, int rn, tcg_target_long im)
490{
491 if (im >= 0)
492 tcg_out32(s, (cond << 28) | 0x01d000b0 |
493 (rn << 16) | (rd << 12) |
494 ((im & 0xf0) << 4) | (im & 0xf));
495 else
496 tcg_out32(s, (cond << 28) | 0x015000b0 |
497 (rn << 16) | (rd << 12) |
498 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
499}
500
501static inline void tcg_out_st16u_8(TCGContext *s, int cond,
502 int rd, int rn, tcg_target_long im)
503{
504 if (im >= 0)
505 tcg_out32(s, (cond << 28) | 0x01c000b0 |
506 (rn << 16) | (rd << 12) |
507 ((im & 0xf0) << 4) | (im & 0xf));
508 else
509 tcg_out32(s, (cond << 28) | 0x014000b0 |
510 (rn << 16) | (rd << 12) |
511 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
512}
513
514static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
515 int rd, int rn, int rm)
516{
517 tcg_out32(s, (cond << 28) | 0x019000b0 |
518 (rn << 16) | (rd << 12) | rm);
519}
520
521static inline void tcg_out_st16u_r(TCGContext *s, int cond,
522 int rd, int rn, int rm)
523{
524 tcg_out32(s, (cond << 28) | 0x018000b0 |
525 (rn << 16) | (rd << 12) | rm);
526}
527
528static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
529 int rd, int rn, tcg_target_long im)
530{
531 if (im >= 0)
532 tcg_out32(s, (cond << 28) | 0x01d000f0 |
533 (rn << 16) | (rd << 12) |
534 ((im & 0xf0) << 4) | (im & 0xf));
535 else
536 tcg_out32(s, (cond << 28) | 0x015000f0 |
537 (rn << 16) | (rd << 12) |
538 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
539}
540
541static inline void tcg_out_st16s_8(TCGContext *s, int cond,
542 int rd, int rn, tcg_target_long im)
543{
544 if (im >= 0)
545 tcg_out32(s, (cond << 28) | 0x01c000f0 |
546 (rn << 16) | (rd << 12) |
547 ((im & 0xf0) << 4) | (im & 0xf));
548 else
549 tcg_out32(s, (cond << 28) | 0x014000f0 |
550 (rn << 16) | (rd << 12) |
551 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
552}
553
554static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
555 int rd, int rn, int rm)
556{
557 tcg_out32(s, (cond << 28) | 0x019000f0 |
558 (rn << 16) | (rd << 12) | rm);
559}
560
561static inline void tcg_out_st16s_r(TCGContext *s, int cond,
562 int rd, int rn, int rm)
563{
564 tcg_out32(s, (cond << 28) | 0x018000f0 |
565 (rn << 16) | (rd << 12) | rm);
566}
567
568static inline void tcg_out_ld8_12(TCGContext *s, int cond,
569 int rd, int rn, tcg_target_long im)
570{
571 if (im >= 0)
572 tcg_out32(s, (cond << 28) | 0x05d00000 |
573 (rn << 16) | (rd << 12) | (im & 0xfff));
574 else
575 tcg_out32(s, (cond << 28) | 0x05500000 |
576 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
577}
578
579static inline void tcg_out_st8_12(TCGContext *s, int cond,
580 int rd, int rn, tcg_target_long im)
581{
582 if (im >= 0)
583 tcg_out32(s, (cond << 28) | 0x05c00000 |
584 (rn << 16) | (rd << 12) | (im & 0xfff));
585 else
586 tcg_out32(s, (cond << 28) | 0x05400000 |
587 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
588}
589
590static inline void tcg_out_ld8_r(TCGContext *s, int cond,
591 int rd, int rn, int rm)
592{
593 tcg_out32(s, (cond << 28) | 0x07d00000 |
594 (rn << 16) | (rd << 12) | rm);
595}
596
597static inline void tcg_out_st8_r(TCGContext *s, int cond,
598 int rd, int rn, int rm)
599{
600 tcg_out32(s, (cond << 28) | 0x07c00000 |
601 (rn << 16) | (rd << 12) | rm);
602}
603
604static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
605 int rd, int rn, tcg_target_long im)
606{
607 if (im >= 0)
608 tcg_out32(s, (cond << 28) | 0x01d000d0 |
609 (rn << 16) | (rd << 12) |
610 ((im & 0xf0) << 4) | (im & 0xf));
611 else
612 tcg_out32(s, (cond << 28) | 0x015000d0 |
613 (rn << 16) | (rd << 12) |
614 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
615}
616
617static inline void tcg_out_st8s_8(TCGContext *s, int cond,
618 int rd, int rn, tcg_target_long im)
619{
620 if (im >= 0)
621 tcg_out32(s, (cond << 28) | 0x01c000d0 |
622 (rn << 16) | (rd << 12) |
623 ((im & 0xf0) << 4) | (im & 0xf));
624 else
625 tcg_out32(s, (cond << 28) | 0x014000d0 |
626 (rn << 16) | (rd << 12) |
627 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
628}
629
630static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
631 int rd, int rn, int rm)
632{
204c1674 633 tcg_out32(s, (cond << 28) | 0x019000d0 |
811d4cf4
AZ		 634 (rn << 16) | (rd << 12) | rm);
635}
636
637static inline void tcg_out_st8s_r(TCGContext *s, int cond,
638 int rd, int rn, int rm)
639{
204c1674 640 tcg_out32(s, (cond << 28) | 0x018000d0 |
811d4cf4
AZ		 641 (rn << 16) | (rd << 12) | rm);
642}
643
644static inline void tcg_out_ld32u(TCGContext *s, int cond,
645 int rd, int rn, int32_t offset)
646{
647 if (offset > 0xfff || offset < -0xfff) {
648 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
649 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
650 } else
651 tcg_out_ld32_12(s, cond, rd, rn, offset);
652}
653
654static inline void tcg_out_st32(TCGContext *s, int cond,
655 int rd, int rn, int32_t offset)
656{
657 if (offset > 0xfff || offset < -0xfff) {
658 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
659 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
660 } else
661 tcg_out_st32_12(s, cond, rd, rn, offset);
662}
663
664static inline void tcg_out_ld16u(TCGContext *s, int cond,
665 int rd, int rn, int32_t offset)
666{
667 if (offset > 0xff || offset < -0xff) {
668 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
669 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
670 } else
671 tcg_out_ld16u_8(s, cond, rd, rn, offset);
672}
673
674static inline void tcg_out_ld16s(TCGContext *s, int cond,
675 int rd, int rn, int32_t offset)
676{
677 if (offset > 0xff || offset < -0xff) {
678 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
679 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
680 } else
681 tcg_out_ld16s_8(s, cond, rd, rn, offset);
682}
683
684static inline void tcg_out_st16u(TCGContext *s, int cond,
685 int rd, int rn, int32_t offset)
686{
687 if (offset > 0xff || offset < -0xff) {
688 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
689 tcg_out_st16u_r(s, cond, rd, rn, TCG_REG_R8);
690 } else
691 tcg_out_st16u_8(s, cond, rd, rn, offset);
692}
693
694static inline void tcg_out_ld8u(TCGContext *s, int cond,
695 int rd, int rn, int32_t offset)
696{
697 if (offset > 0xfff || offset < -0xfff) {
698 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
699 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
700 } else
701 tcg_out_ld8_12(s, cond, rd, rn, offset);
702}
703
704static inline void tcg_out_ld8s(TCGContext *s, int cond,
705 int rd, int rn, int32_t offset)
706{
707 if (offset > 0xff || offset < -0xff) {
708 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
709 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
710 } else
711 tcg_out_ld8s_8(s, cond, rd, rn, offset);
712}
713
714static inline void tcg_out_st8u(TCGContext *s, int cond,
715 int rd, int rn, int32_t offset)
716{
717 if (offset > 0xfff || offset < -0xfff) {
718 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
719 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
720 } else
721 tcg_out_st8_12(s, cond, rd, rn, offset);
722}
723
724static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
725{
726 int32_t val;
727
728 val = addr - (tcg_target_long) s->code_ptr;
729 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
730 tcg_out_b(s, cond, val);
731 else {
732#if 1
733 tcg_abort();
734#else
735 if (cond == COND_AL) {
736 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
737 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
738 } else {
739 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
740 tcg_out_dat_reg(s, cond, ARITH_ADD,
741 15, 15, TCG_REG_R8, SHIFT_IMM_LSL(0));
742 }
743#endif
744 }
745}
746
747static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
748{
749 int32_t val;
750
811d4cf4
AZ		 751 val = addr - (tcg_target_long) s->code_ptr;
752 if (val < 0x01fffffd && val > -0x01fffffd)
753 tcg_out_bl(s, cond, val);
754 else {
755#if 1
756 tcg_abort();
757#else
758 if (cond == COND_AL) {
759 tcg_out_dat_imm(s, cond, ARITH_ADD, 14, 15, 4);
760 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
761 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
762 } else {
763 tcg_out_movi32(s, cond, TCG_REG_R9, addr);
764 tcg_out_dat_imm(s, cond, ARITH_MOV, 14, 0, 15);
765 tcg_out_bx(s, cond, TCG_REG_R9);
766 }
767#endif
768 }
811d4cf4
AZ		 769}
770
771static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
772{
811d4cf4
AZ		 773 /* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg); */
774 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 15, SHIFT_IMM_LSL(0));
775 tcg_out_bx(s, cond, arg);
811d4cf4
AZ		 776}
777
778static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
779{
780 TCGLabel *l = &s->labels[label_index];
781
782 if (l->has_value)
783 tcg_out_goto(s, cond, l->u.value);
784 else if (cond == COND_AL) {
785 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
786 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
787 s->code_ptr += 4;
788 } else {
789 /* Probably this should be preferred even for COND_AL... */
790 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
e936243a 791 tcg_out_b_noaddr(s, cond);
811d4cf4
AZ		 792 }
793}
794
811d4cf4 795#ifdef CONFIG_SOFTMMU
79383c9c
BS		 796
797#include "../../softmmu_defs.h"
811d4cf4
AZ		 798
799static void *qemu_ld_helpers[4] = {
800 __ldb_mmu,
801 __ldw_mmu,
802 __ldl_mmu,
803 __ldq_mmu,
804};
805
806static void *qemu_st_helpers[4] = {
807 __stb_mmu,
808 __stw_mmu,
809 __stl_mmu,
810 __stq_mmu,
811};
812#endif
813
3979144c
PB		 814#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
815
811d4cf4
AZ		 816static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
817 const TCGArg *args, int opc)
818{
819 int addr_reg, data_reg, data_reg2;
820#ifdef CONFIG_SOFTMMU
821 int mem_index, s_bits;
822# if TARGET_LONG_BITS == 64
823 int addr_reg2;
824# endif
811d4cf4 825 uint32_t *label_ptr;
811d4cf4
AZ		 826#endif
827
828 data_reg = *args++;
829 if (opc == 3)
830 data_reg2 = *args++;
831 else
d89c682f 832 data_reg2 = 0; /* suppress warning */
811d4cf4 833 addr_reg = *args++;
811d4cf4 834#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 835# if TARGET_LONG_BITS == 64
836 addr_reg2 = *args++;
837# endif
811d4cf4
AZ		 838 mem_index = *args;
839 s_bits = opc & 3;
840
91a3c1b0 841 /* Should generate something like the following:
3979144c 842 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 843 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 844 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0
AZ		 845 */
846# if CPU_TLB_BITS > 8
847# error
848# endif
811d4cf4 849 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
3979144c 850 8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4
AZ		 851 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
852 0, 8, CPU_TLB_SIZE - 1);
853 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
854 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 855 /* In the
856 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
857 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
858 * not exceed otherwise, so use an
859 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
860 * before.
861 */
225b4376
AZ		 862 if (mem_index)
863 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
864 (mem_index << (TLB_SHIFT & 1)) |
865 ((16 - (TLB_SHIFT >> 1)) << 8));
811d4cf4 866 tcg_out_ld32_12(s, COND_AL, 1, 0,
225b4376 867 offsetof(CPUState, tlb_table[0][0].addr_read));
811d4cf4
AZ		 868 tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
869 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 870 /* Check alignment. */
871 if (s_bits)
872 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
873 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 874# if TARGET_LONG_BITS == 64
875 /* XXX: possibly we could use a block data load or writeback in
876 * the first access. */
877 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 878 offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
811d4cf4
AZ		 879 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
880 0, 1, addr_reg2, SHIFT_IMM_LSL(0));
881# endif
882 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 883 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 884
885 switch (opc) {
886 case 0:
887 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, 1);
888 break;
889 case 0 | 4:
890 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, 1);
891 break;
892 case 1:
893 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, 1);
894 break;
895 case 1 | 4:
896 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, 1);
897 break;
898 case 2:
899 default:
900 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, 1);
901 break;
902 case 3:
3979144c 903 tcg_out_ld32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
811d4cf4
AZ		 904 tcg_out_ld32_12(s, COND_EQ, data_reg2, 1, 4);
905 break;
906 }
907
908 label_ptr = (void *) s->code_ptr;
909 tcg_out_b(s, COND_EQ, 8);
811d4cf4 910
811d4cf4
AZ		 911 /* TODO: move this code to where the constants pool will be */
912 if (addr_reg)
913 tcg_out_dat_reg(s, cond, ARITH_MOV,
914 0, 0, addr_reg, SHIFT_IMM_LSL(0));
915# if TARGET_LONG_BITS == 32
916 tcg_out_dat_imm(s, cond, ARITH_MOV, 1, 0, mem_index);
917# else
918 if (addr_reg2 != 1)
919 tcg_out_dat_reg(s, cond, ARITH_MOV,
920 1, 0, addr_reg2, SHIFT_IMM_LSL(0));
921 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
922# endif
650bbb36 923 tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] -
811d4cf4
AZ		 924 (tcg_target_long) s->code_ptr);
925
926 switch (opc) {
927 case 0 | 4:
928 tcg_out_dat_reg(s, cond, ARITH_MOV,
929 0, 0, 0, SHIFT_IMM_LSL(24));
930 tcg_out_dat_reg(s, cond, ARITH_MOV,
931 data_reg, 0, 0, SHIFT_IMM_ASR(24));
932 break;
933 case 1 | 4:
934 tcg_out_dat_reg(s, cond, ARITH_MOV,
935 0, 0, 0, SHIFT_IMM_LSL(16));
936 tcg_out_dat_reg(s, cond, ARITH_MOV,
937 data_reg, 0, 0, SHIFT_IMM_ASR(16));
938 break;
939 case 0:
940 case 1:
941 case 2:
942 default:
943 if (data_reg)
944 tcg_out_dat_reg(s, cond, ARITH_MOV,
945 data_reg, 0, 0, SHIFT_IMM_LSL(0));
946 break;
947 case 3:
d0660ed4
AZ		 948 if (data_reg != 0)
949 tcg_out_dat_reg(s, cond, ARITH_MOV,
950 data_reg, 0, 0, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 951 if (data_reg2 != 1)
952 tcg_out_dat_reg(s, cond, ARITH_MOV,
953 data_reg2, 0, 1, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 954 break;
955 }
956
811d4cf4 957 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
379f6698
PB		 958#else /* !CONFIG_SOFTMMU */
959 if (GUEST_BASE) {
960 uint32_t offset = GUEST_BASE;
961 int i;
962 int rot;
963
964 while (offset) {
965 i = ctz32(offset) & ~1;
966 rot = ((32 - i) << 7) & 0xf00;
967
968 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 8, addr_reg,
969 ((offset >> i) & 0xff) | rot);
970 addr_reg = 8;
971 offset &= ~(0xff << i);
972 }
973 }
811d4cf4
AZ		 974 switch (opc) {
975 case 0:
976 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
977 break;
978 case 0 | 4:
979 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
980 break;
981 case 1:
982 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
983 break;
984 case 1 | 4:
985 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
986 break;
987 case 2:
988 default:
989 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
990 break;
991 case 3:
eae6ce52
AZ		 992 /* TODO: use block load -
993 * check that data_reg2 > data_reg or the other way */
419bafa5
AJ		 994 if (data_reg == addr_reg) {
995 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
996 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
997 } else {
998 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
999 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1000 }
811d4cf4
AZ		 1001 break;
1002 }
1003#endif
1004}
1005
1006static inline void tcg_out_qemu_st(TCGContext *s, int cond,
1007 const TCGArg *args, int opc)
1008{
1009 int addr_reg, data_reg, data_reg2;
1010#ifdef CONFIG_SOFTMMU
1011 int mem_index, s_bits;
1012# if TARGET_LONG_BITS == 64
1013 int addr_reg2;
1014# endif
811d4cf4 1015 uint32_t *label_ptr;
811d4cf4
AZ		 1016#endif
1017
1018 data_reg = *args++;
1019 if (opc == 3)
1020 data_reg2 = *args++;
1021 else
d89c682f 1022 data_reg2 = 0; /* suppress warning */
811d4cf4 1023 addr_reg = *args++;
811d4cf4 1024#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 1025# if TARGET_LONG_BITS == 64
1026 addr_reg2 = *args++;
1027# endif
811d4cf4
AZ		 1028 mem_index = *args;
1029 s_bits = opc & 3;
1030
91a3c1b0 1031 /* Should generate something like the following:
3979144c 1032 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1033 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1034 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0 1035 */
811d4cf4 1036 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
3979144c 1037 8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4
AZ		 1038 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1039 0, 8, CPU_TLB_SIZE - 1);
1040 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
1041 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 1042 /* In the
1043 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1044 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1045 * not exceed otherwise, so use an
1046 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1047 * before.
1048 */
225b4376
AZ		 1049 if (mem_index)
1050 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
1051 (mem_index << (TLB_SHIFT & 1)) |
1052 ((16 - (TLB_SHIFT >> 1)) << 8));
811d4cf4 1053 tcg_out_ld32_12(s, COND_AL, 1, 0,
225b4376 1054 offsetof(CPUState, tlb_table[0][0].addr_write));
811d4cf4
AZ		 1055 tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
1056 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 1057 /* Check alignment. */
1058 if (s_bits)
1059 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1060 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 1061# if TARGET_LONG_BITS == 64
1062 /* XXX: possibly we could use a block data load or writeback in
1063 * the first access. */
1064 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 1065 offsetof(CPUState, tlb_table[0][0].addr_write)
811d4cf4
AZ		 1066 + 4);
1067 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
1068 0, 1, addr_reg2, SHIFT_IMM_LSL(0));
1069# endif
1070 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 1071 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 1072
1073 switch (opc) {
1074 case 0:
1075 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, 1);
1076 break;
1077 case 0 | 4:
1078 tcg_out_st8s_r(s, COND_EQ, data_reg, addr_reg, 1);
1079 break;
1080 case 1:
1081 tcg_out_st16u_r(s, COND_EQ, data_reg, addr_reg, 1);
1082 break;
1083 case 1 | 4:
1084 tcg_out_st16s_r(s, COND_EQ, data_reg, addr_reg, 1);
1085 break;
1086 case 2:
1087 default:
1088 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, 1);
1089 break;
1090 case 3:
3979144c 1091 tcg_out_st32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
811d4cf4
AZ		 1092 tcg_out_st32_12(s, COND_EQ, data_reg2, 1, 4);
1093 break;
1094 }
1095
1096 label_ptr = (void *) s->code_ptr;
1097 tcg_out_b(s, COND_EQ, 8);
811d4cf4 1098
811d4cf4
AZ		 1099 /* TODO: move this code to where the constants pool will be */
1100 if (addr_reg)
1101 tcg_out_dat_reg(s, cond, ARITH_MOV,
1102 0, 0, addr_reg, SHIFT_IMM_LSL(0));
1103# if TARGET_LONG_BITS == 32
1104 switch (opc) {
1105 case 0:
1106 tcg_out_dat_imm(s, cond, ARITH_AND, 1, data_reg, 0xff);
1107 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1108 break;
1109 case 1:
1110 tcg_out_dat_reg(s, cond, ARITH_MOV,
1111 1, 0, data_reg, SHIFT_IMM_LSL(16));
1112 tcg_out_dat_reg(s, cond, ARITH_MOV,
1113 1, 0, 1, SHIFT_IMM_LSR(16));
1114 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1115 break;
1116 case 2:
1117 if (data_reg != 1)
1118 tcg_out_dat_reg(s, cond, ARITH_MOV,
1119 1, 0, data_reg, SHIFT_IMM_LSL(0));
1120 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1121 break;
1122 case 3:
1123 if (data_reg != 1)
1124 tcg_out_dat_reg(s, cond, ARITH_MOV,
1125 1, 0, data_reg, SHIFT_IMM_LSL(0));
1126 if (data_reg2 != 2)
1127 tcg_out_dat_reg(s, cond, ARITH_MOV,
1128 2, 0, data_reg2, SHIFT_IMM_LSL(0));
1129 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1130 break;
1131 }
1132# else
1133 if (addr_reg2 != 1)
1134 tcg_out_dat_reg(s, cond, ARITH_MOV,
1135 1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1136 switch (opc) {
1137 case 0:
1138 tcg_out_dat_imm(s, cond, ARITH_AND, 2, data_reg, 0xff);
1139 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1140 break;
1141 case 1:
1142 tcg_out_dat_reg(s, cond, ARITH_MOV,
1143 2, 0, data_reg, SHIFT_IMM_LSL(16));
1144 tcg_out_dat_reg(s, cond, ARITH_MOV,
1145 2, 0, 2, SHIFT_IMM_LSR(16));
1146 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1147 break;
1148 case 2:
1149 if (data_reg != 2)
1150 tcg_out_dat_reg(s, cond, ARITH_MOV,
1151 2, 0, data_reg, SHIFT_IMM_LSL(0));
1152 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1153 break;
1154 case 3:
91a3c1b0
AZ		 1155 tcg_out_dat_imm(s, cond, ARITH_MOV, 8, 0, mem_index);
1156 tcg_out32(s, (cond << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
811d4cf4
AZ		 1157 if (data_reg != 2)
1158 tcg_out_dat_reg(s, cond, ARITH_MOV,
1159 2, 0, data_reg, SHIFT_IMM_LSL(0));
1160 if (data_reg2 != 3)
1161 tcg_out_dat_reg(s, cond, ARITH_MOV,
1162 3, 0, data_reg2, SHIFT_IMM_LSL(0));
1163 break;
1164 }
1165# endif
1166
204c1674 1167 tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] -
811d4cf4 1168 (tcg_target_long) s->code_ptr);
811d4cf4
AZ		 1169# if TARGET_LONG_BITS == 64
1170 if (opc == 3)
1171 tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 0x10);
1172# endif
1173
811d4cf4 1174 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
379f6698
PB		 1175#else /* !CONFIG_SOFTMMU */
1176 if (GUEST_BASE) {
1177 uint32_t offset = GUEST_BASE;
1178 int i;
1179 int rot;
1180
1181 while (offset) {
1182 i = ctz32(offset) & ~1;
1183 rot = ((32 - i) << 7) & 0xf00;
1184
1185 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 8, addr_reg,
1186 ((offset >> i) & 0xff) | rot);
1187 addr_reg = 8;
1188 offset &= ~(0xff << i);
1189 }
1190 }
811d4cf4
AZ		 1191 switch (opc) {
1192 case 0:
1193 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1194 break;
1195 case 0 | 4:
204c1674 1196 tcg_out_st8s_8(s, COND_AL, data_reg, addr_reg, 0);
811d4cf4
AZ		 1197 break;
1198 case 1:
1199 tcg_out_st16u_8(s, COND_AL, data_reg, addr_reg, 0);
1200 break;
1201 case 1 | 4:
1202 tcg_out_st16s_8(s, COND_AL, data_reg, addr_reg, 0);
1203 break;
1204 case 2:
1205 default:
1206 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1207 break;
1208 case 3:
eae6ce52
AZ		 1209 /* TODO: use block store -
1210 * check that data_reg2 > data_reg or the other way */
811d4cf4
AZ		 1211 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1212 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1213 break;
1214 }
1215#endif
1216}
1217
811d4cf4
AZ		 1218static uint8_t *tb_ret_addr;
1219
a9751609 1220static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
811d4cf4
AZ		 1221 const TCGArg *args, const int *const_args)
1222{
1223 int c;
1224
1225 switch (opc) {
1226 case INDEX_op_exit_tb:
fe33867b
AZ		 1227 {
1228 uint8_t *ld_ptr = s->code_ptr;
1229 if (args[0] >> 8)
1230 tcg_out_ld32_12(s, COND_AL, 0, 15, 0);
1231 else
1232 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, 0, 0, args[0]);
1233 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1234 if (args[0] >> 8) {
1235 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1236 tcg_out32(s, args[0]);
1237 }
1238 }
811d4cf4
AZ		 1239 break;
1240 case INDEX_op_goto_tb:
1241 if (s->tb_jmp_offset) {
1242 /* Direct jump method */
fe33867b 1243#if defined(USE_DIRECT_JUMP)
811d4cf4
AZ		 1244 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1245 tcg_out_b(s, COND_AL, 8);
1246#else
1247 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
1248 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1249 tcg_out32(s, 0);
1250#endif
1251 } else {
1252 /* Indirect jump method */
1253#if 1
1254 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1255 if (c > 0xfff || c < -0xfff) {
1256 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1257 (tcg_target_long) (s->tb_next + args[0]));
1258 tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1259 } else
1260 tcg_out_ld32_12(s, COND_AL, 15, 15, c);
1261#else
1262 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1263 tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1264 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1265#endif
1266 }
1267 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1268 break;
1269 case INDEX_op_call:
1270 if (const_args[0])
1271 tcg_out_call(s, COND_AL, args[0]);
1272 else
1273 tcg_out_callr(s, COND_AL, args[0]);
1274 break;
1275 case INDEX_op_jmp:
1276 if (const_args[0])
1277 tcg_out_goto(s, COND_AL, args[0]);
1278 else
1279 tcg_out_bx(s, COND_AL, args[0]);
1280 break;
1281 case INDEX_op_br:
1282 tcg_out_goto_label(s, COND_AL, args[0]);
1283 break;
1284
1285 case INDEX_op_ld8u_i32:
1286 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1287 break;
1288 case INDEX_op_ld8s_i32:
1289 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1290 break;
1291 case INDEX_op_ld16u_i32:
1292 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1293 break;
1294 case INDEX_op_ld16s_i32:
1295 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1296 break;
1297 case INDEX_op_ld_i32:
1298 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1299 break;
1300 case INDEX_op_st8_i32:
1301 tcg_out_st8u(s, COND_AL, args[0], args[1], args[2]);
1302 break;
1303 case INDEX_op_st16_i32:
1304 tcg_out_st16u(s, COND_AL, args[0], args[1], args[2]);
1305 break;
1306 case INDEX_op_st_i32:
1307 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1308 break;
1309
1310 case INDEX_op_mov_i32:
1311 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1312 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1313 break;
1314 case INDEX_op_movi_i32:
1315 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1316 break;
1317 case INDEX_op_add_i32:
1318 c = ARITH_ADD;
1319 goto gen_arith;
1320 case INDEX_op_sub_i32:
1321 c = ARITH_SUB;
1322 goto gen_arith;
1323 case INDEX_op_and_i32:
1324 c = ARITH_AND;
1325 goto gen_arith;
932234f6
AJ		 1326 case INDEX_op_andc_i32:
1327 c = ARITH_BIC;
1328 goto gen_arith;
811d4cf4
AZ		 1329 case INDEX_op_or_i32:
1330 c = ARITH_ORR;
1331 goto gen_arith;
1332 case INDEX_op_xor_i32:
1333 c = ARITH_EOR;
1334 /* Fall through. */
1335 gen_arith:
94953e6d
LD		 1336 if (const_args[2]) {
1337 int rot;
1338 rot = encode_imm(args[2]);
cb4e581f 1339 tcg_out_dat_imm(s, COND_AL, c,
94953e6d
LD		 1340 args[0], args[1], rotl(args[2], rot) | (rot << 7));
1341 } else
cb4e581f
LD		 1342 tcg_out_dat_reg(s, COND_AL, c,
1343 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1344 break;
1345 case INDEX_op_add2_i32:
1346 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1347 args[0], args[1], args[2], args[3],
1348 args[4], args[5], SHIFT_IMM_LSL(0));
1349 break;
1350 case INDEX_op_sub2_i32:
1351 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1352 args[0], args[1], args[2], args[3],
1353 args[4], args[5], SHIFT_IMM_LSL(0));
1354 break;
650bbb36
AZ		 1355 case INDEX_op_neg_i32:
1356 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1357 break;
f878d2d2
LD		 1358 case INDEX_op_not_i32:
1359 tcg_out_dat_reg(s, COND_AL,
1360 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1361 break;
811d4cf4
AZ		 1362 case INDEX_op_mul_i32:
1363 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1364 break;
1365 case INDEX_op_mulu2_i32:
1366 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1367 break;
811d4cf4
AZ		 1368 /* XXX: Perhaps args[2] & 0x1f is wrong */
1369 case INDEX_op_shl_i32:
1370 c = const_args[2] ?
1371 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1372 goto gen_shift32;
1373 case INDEX_op_shr_i32:
1374 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1375 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1376 goto gen_shift32;
1377 case INDEX_op_sar_i32:
1378 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1379 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1380 /* Fall through. */
1381 gen_shift32:
1382 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1383 break;
1384
1385 case INDEX_op_brcond_i32:
023e77f8
AJ		 1386 if (const_args[1]) {
1387 int rot;
1388 rot = encode_imm(args[1]);
1389 tcg_out_dat_imm(s, COND_AL, ARITH_CMP,
1390 0, args[0], rotl(args[1], rot) | (rot << 7));
1391 } else {
1392 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1393 args[0], args[1], SHIFT_IMM_LSL(0));
1394 }
811d4cf4
AZ		 1395 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1396 break;
1397 case INDEX_op_brcond2_i32:
1398 /* The resulting conditions are:
1399 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1400 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1401 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1402 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1403 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1404 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1405 */
1406 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1407 args[1], args[3], SHIFT_IMM_LSL(0));
1408 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1409 args[0], args[2], SHIFT_IMM_LSL(0));
1410 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1411 break;
f72a6cd7 1412 case INDEX_op_setcond_i32:
023e77f8
AJ		 1413 if (const_args[2]) {
1414 int rot;
1415 rot = encode_imm(args[2]);
1416 tcg_out_dat_imm(s, COND_AL, ARITH_CMP,
1417 0, args[1], rotl(args[2], rot) | (rot << 7));
1418 } else {
1419 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1420 args[1], args[2], SHIFT_IMM_LSL(0));
1421 }
f72a6cd7
AJ		 1422 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1423 ARITH_MOV, args[0], 0, 1);
1424 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1425 ARITH_MOV, args[0], 0, 0);
1426 break;
e0404769
AJ		 1427 case INDEX_op_setcond2_i32:
1428 /* See brcond2_i32 comment */
1429 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1430 args[2], args[4], SHIFT_IMM_LSL(0));
1431 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1432 args[1], args[3], SHIFT_IMM_LSL(0));
1433 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1434 ARITH_MOV, args[0], 0, 1);
1435 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1436 ARITH_MOV, args[0], 0, 0);
b525f0a9 1437 break;
811d4cf4
AZ		 1438
1439 case INDEX_op_qemu_ld8u:
1440 tcg_out_qemu_ld(s, COND_AL, args, 0);
1441 break;
1442 case INDEX_op_qemu_ld8s:
1443 tcg_out_qemu_ld(s, COND_AL, args, 0 | 4);
1444 break;
1445 case INDEX_op_qemu_ld16u:
1446 tcg_out_qemu_ld(s, COND_AL, args, 1);
1447 break;
1448 case INDEX_op_qemu_ld16s:
1449 tcg_out_qemu_ld(s, COND_AL, args, 1 | 4);
1450 break;
86feb1c8 1451 case INDEX_op_qemu_ld32:
811d4cf4
AZ		 1452 tcg_out_qemu_ld(s, COND_AL, args, 2);
1453 break;
1454 case INDEX_op_qemu_ld64:
1455 tcg_out_qemu_ld(s, COND_AL, args, 3);
1456 break;
650bbb36 1457
811d4cf4
AZ		 1458 case INDEX_op_qemu_st8:
1459 tcg_out_qemu_st(s, COND_AL, args, 0);
1460 break;
1461 case INDEX_op_qemu_st16:
1462 tcg_out_qemu_st(s, COND_AL, args, 1);
1463 break;
1464 case INDEX_op_qemu_st32:
1465 tcg_out_qemu_st(s, COND_AL, args, 2);
1466 break;
1467 case INDEX_op_qemu_st64:
1468 tcg_out_qemu_st(s, COND_AL, args, 3);
1469 break;
1470
1471 case INDEX_op_ext8s_i32:
7990496d
LD		 1472#ifdef __ARM_ARCH_7A__
1473 /* sxtb */
1474 tcg_out32(s, 0xe6af0070 | (args[0] << 12) | args[1]);
1475#else
811d4cf4
AZ		 1476 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1477 args[0], 0, args[1], SHIFT_IMM_LSL(24));
1478 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1479 args[0], 0, args[0], SHIFT_IMM_ASR(24));
7990496d 1480#endif
811d4cf4
AZ		 1481 break;
1482 case INDEX_op_ext16s_i32:
7990496d
LD		 1483#ifdef __ARM_ARCH_7A__
1484 /* sxth */
1485 tcg_out32(s, 0xe6bf0070 | (args[0] << 12) | args[1]);
1486#else
811d4cf4
AZ		 1487 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1488 args[0], 0, args[1], SHIFT_IMM_LSL(16));
1489 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1490 args[0], 0, args[0], SHIFT_IMM_ASR(16));
7990496d 1491#endif
811d4cf4
AZ		 1492 break;
1493
1494 default:
1495 tcg_abort();
1496 }
1497}
1498
1499static const TCGTargetOpDef arm_op_defs[] = {
1500 { INDEX_op_exit_tb, { } },
1501 { INDEX_op_goto_tb, { } },
1502 { INDEX_op_call, { "ri" } },
1503 { INDEX_op_jmp, { "ri" } },
1504 { INDEX_op_br, { } },
1505
1506 { INDEX_op_mov_i32, { "r", "r" } },
1507 { INDEX_op_movi_i32, { "r" } },
1508
1509 { INDEX_op_ld8u_i32, { "r", "r" } },
1510 { INDEX_op_ld8s_i32, { "r", "r" } },
1511 { INDEX_op_ld16u_i32, { "r", "r" } },
1512 { INDEX_op_ld16s_i32, { "r", "r" } },
1513 { INDEX_op_ld_i32, { "r", "r" } },
1514 { INDEX_op_st8_i32, { "r", "r" } },
1515 { INDEX_op_st16_i32, { "r", "r" } },
1516 { INDEX_op_st_i32, { "r", "r" } },
1517
1518 /* TODO: "r", "r", "ri" */
cb4e581f
LD		 1519 { INDEX_op_add_i32, { "r", "r", "rI" } },
1520 { INDEX_op_sub_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1521 { INDEX_op_mul_i32, { "r", "r", "r" } },
1522 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
cb4e581f 1523 { INDEX_op_and_i32, { "r", "r", "rI" } },
932234f6 1524 { INDEX_op_andc_i32, { "r", "r", "rI" } },
cb4e581f
LD		 1525 { INDEX_op_or_i32, { "r", "r", "rI" } },
1526 { INDEX_op_xor_i32, { "r", "r", "rI" } },
650bbb36 1527 { INDEX_op_neg_i32, { "r", "r" } },
f878d2d2 1528 { INDEX_op_not_i32, { "r", "r" } },
811d4cf4
AZ		 1529
1530 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1531 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1532 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1533
023e77f8
AJ		 1534 { INDEX_op_brcond_i32, { "r", "rI" } },
1535 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1536
1537 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1538 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1539 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1540 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
e0404769 1541 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
811d4cf4 1542
26c5d372
AJ		 1543#if TARGET_LONG_BITS == 32
1544 { INDEX_op_qemu_ld8u, { "r", "x" } },
1545 { INDEX_op_qemu_ld8s, { "r", "x" } },
1546 { INDEX_op_qemu_ld16u, { "r", "x" } },
1547 { INDEX_op_qemu_ld16s, { "r", "x" } },
1584c845 1548 { INDEX_op_qemu_ld32, { "r", "x" } },
26c5d372
AJ		 1549 { INDEX_op_qemu_ld64, { "d", "r", "x" } },
1550
1551 { INDEX_op_qemu_st8, { "x", "x" } },
1552 { INDEX_op_qemu_st16, { "x", "x" } },
1553 { INDEX_op_qemu_st32, { "x", "x" } },
1554 { INDEX_op_qemu_st64, { "x", "D", "x" } },
1555#else
811d4cf4
AZ		 1556 { INDEX_op_qemu_ld8u, { "r", "x", "X" } },
1557 { INDEX_op_qemu_ld8s, { "r", "x", "X" } },
1558 { INDEX_op_qemu_ld16u, { "r", "x", "X" } },
1559 { INDEX_op_qemu_ld16s, { "r", "x", "X" } },
86feb1c8 1560 { INDEX_op_qemu_ld32, { "r", "x", "X" } },
d0660ed4 1561 { INDEX_op_qemu_ld64, { "d", "r", "x", "X" } },
811d4cf4 1562
3979144c
PB		 1563 { INDEX_op_qemu_st8, { "x", "x", "X" } },
1564 { INDEX_op_qemu_st16, { "x", "x", "X" } },
1565 { INDEX_op_qemu_st32, { "x", "x", "X" } },
1566 { INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
26c5d372 1567#endif
811d4cf4
AZ		 1568
1569 { INDEX_op_ext8s_i32, { "r", "r" } },
1570 { INDEX_op_ext16s_i32, { "r", "r" } },
1571
1572 { -1 },
1573};
1574
1575void tcg_target_init(TCGContext *s)
1576{
20cb400d 1577#if !defined(CONFIG_USER_ONLY)
811d4cf4
AZ		 1578 /* fail safe */
1579 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1580 tcg_abort();
20cb400d 1581#endif
811d4cf4
AZ		 1582
1583 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
1584 ((2 << TCG_REG_R14) - 1) & ~(1 << TCG_REG_R8));
1585 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1586 ((2 << TCG_REG_R3) - 1) |
1587 (1 << TCG_REG_R12) | (1 << TCG_REG_R14));
1588
1589 tcg_regset_clear(s->reserved_regs);
811d4cf4
AZ		 1590 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1591 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
1592
1593 tcg_add_target_add_op_defs(arm_op_defs);
1594}
1595
1596static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1597 int arg1, tcg_target_long arg2)
1598{
1599 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1600}
1601
1602static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1603 int arg1, tcg_target_long arg2)
1604{
1605 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1606}
1607
2d69f359 1608static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
811d4cf4
AZ		 1609{
1610 if (val > 0)
1611 if (val < 0x100)
1612 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1613 else
1614 tcg_abort();
1615 else if (val < 0) {
1616 if (val > -0x100)
1617 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1618 else
1619 tcg_abort();
1620 }
1621}
1622
1623static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
1624{
1625 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1626}
1627
1628static inline void tcg_out_movi(TCGContext *s, TCGType type,
1629 int ret, tcg_target_long arg)
1630{
1631 tcg_out_movi32(s, COND_AL, ret, arg);
1632}
1633
1634void tcg_target_qemu_prologue(TCGContext *s)
1635{
9e97d8e9
AJ		 1636 /* There is no need to save r7, it is used to store the address
1637 of the env structure and is not modified by GCC. */
4e17eae9 1638
9e97d8e9
AJ		 1639 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1640 tcg_out32(s, (COND_AL << 28) | 0x092d4f70);
811d4cf4
AZ		 1641
1642 tcg_out_bx(s, COND_AL, TCG_REG_R0);
1643 tb_ret_addr = s->code_ptr;
1644
9e97d8e9
AJ		 1645 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1646 tcg_out32(s, (COND_AL << 28) | 0x08bd8f70);
811d4cf4 1647}
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