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Remove unused CONFIG_TCG_PASS_AREG0 and dead code
[mirror_qemu.git] / tcg / arm / tcg-target.c
CommitLineData
811d4cf4
AZ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
d4a9eb1f 24
ac34fb5c
AJ		 25#if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30#define USE_ARMV7_INSTRUCTIONS
31#endif
32
33#if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39#define USE_ARMV6_INSTRUCTIONS
40#endif
41
42#if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46#define USE_ARMV5_INSTRUCTIONS
47#endif
48
49#ifdef USE_ARMV5_INSTRUCTIONS
50static const int use_armv5_instructions = 1;
51#else
52static const int use_armv5_instructions = 0;
53#endif
54#undef USE_ARMV5_INSTRUCTIONS
55
56#ifdef USE_ARMV6_INSTRUCTIONS
57static const int use_armv6_instructions = 1;
58#else
59static const int use_armv6_instructions = 0;
60#endif
61#undef USE_ARMV6_INSTRUCTIONS
62
63#ifdef USE_ARMV7_INSTRUCTIONS
64static const int use_armv7_instructions = 1;
65#else
66static const int use_armv7_instructions = 0;
67#endif
68#undef USE_ARMV7_INSTRUCTIONS
69
d4a9eb1f
BS		 70#ifndef NDEBUG
71static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
811d4cf4
AZ		 72 "%r0",
73 "%r1",
74 "%r2",
75 "%r3",
76 "%r4",
77 "%r5",
78 "%r6",
79 "%r7",
80 "%r8",
81 "%r9",
82 "%r10",
83 "%r11",
84 "%r12",
85 "%r13",
86 "%r14",
e4a7d5e8 87 "%pc",
811d4cf4 88};
d4a9eb1f 89#endif
811d4cf4 90
d4a9eb1f 91static const int tcg_target_reg_alloc_order[] = {
811d4cf4
AZ		 92 TCG_REG_R4,
93 TCG_REG_R5,
94 TCG_REG_R6,
95 TCG_REG_R7,
96 TCG_REG_R8,
97 TCG_REG_R9,
98 TCG_REG_R10,
99 TCG_REG_R11,
811d4cf4 100 TCG_REG_R13,
914ccf51
AJ		 101 TCG_REG_R0,
102 TCG_REG_R1,
103 TCG_REG_R2,
104 TCG_REG_R3,
105 TCG_REG_R12,
811d4cf4
AZ		 106 TCG_REG_R14,
107};
108
d4a9eb1f 109static const int tcg_target_call_iarg_regs[4] = {
811d4cf4
AZ		 110 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
111};
d4a9eb1f 112static const int tcg_target_call_oarg_regs[2] = {
811d4cf4
AZ		 113 TCG_REG_R0, TCG_REG_R1
114};
115
c69806ab
AJ		 116static inline void reloc_abs32(void *code_ptr, tcg_target_long target)
117{
118 *(uint32_t *) code_ptr = target;
119}
120
121static inline void reloc_pc24(void *code_ptr, tcg_target_long target)
122{
123 uint32_t offset = ((target - ((tcg_target_long) code_ptr + 8)) >> 2);
124
125 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & ~0xffffff)
126 | (offset & 0xffffff);
127}
128
650bbb36 129static void patch_reloc(uint8_t *code_ptr, int type,
811d4cf4
AZ		 130 tcg_target_long value, tcg_target_long addend)
131{
132 switch (type) {
133 case R_ARM_ABS32:
c69806ab 134 reloc_abs32(code_ptr, value);
811d4cf4
AZ		 135 break;
136
137 case R_ARM_CALL:
138 case R_ARM_JUMP24:
139 default:
140 tcg_abort();
141
142 case R_ARM_PC24:
c69806ab 143 reloc_pc24(code_ptr, value);
811d4cf4
AZ		 144 break;
145 }
146}
147
148/* maximum number of register used for input function arguments */
149static inline int tcg_target_get_call_iarg_regs_count(int flags)
150{
151 return 4;
152}
153
811d4cf4 154/* parse target specific constraints */
d4a9eb1f 155static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
811d4cf4
AZ		 156{
157 const char *ct_str;
158
159 ct_str = *pct_str;
160 switch (ct_str[0]) {
cb4e581f
LD		 161 case 'I':
162 ct->ct |= TCG_CT_CONST_ARM;
163 break;
164
811d4cf4 165 case 'r':
811d4cf4
AZ		 166 ct->ct |= TCG_CT_REG;
167 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
168 break;
169
67dcab73
AJ		 170 /* qemu_ld address */
171 case 'l':
811d4cf4
AZ		 172 ct->ct |= TCG_CT_REG;
173 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 174#ifdef CONFIG_SOFTMMU
175 /* r0 and r1 will be overwritten when reading the tlb entry,
176 so don't use these. */
811d4cf4
AZ		 177 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
178 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
89c33337 179#if TARGET_LONG_BITS == 64
9716ef3b
PM		 180 /* If we're passing env to the helper as r0 and need a regpair
181 * for the address then r2 will be overwritten as we're setting
182 * up the args to the helper.
183 */
184 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
185#endif
67dcab73 186#endif
811d4cf4 187 break;
67dcab73 188 case 'L':
d0660ed4
AZ		 189 ct->ct |= TCG_CT_REG;
190 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 191#ifdef CONFIG_SOFTMMU
192 /* r1 is still needed to load data_reg or data_reg2,
193 so don't use it. */
d0660ed4 194 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73 195#endif
d0660ed4
AZ		 196 break;
197
67dcab73
AJ		 198 /* qemu_st address & data_reg */
199 case 's':
811d4cf4
AZ		 200 ct->ct |= TCG_CT_REG;
201 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 202 /* r0 and r1 will be overwritten when reading the tlb entry
203 (softmmu only) and doing the byte swapping, so don't
204 use these. */
811d4cf4
AZ		 205 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
206 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
89c33337 207#if defined(CONFIG_SOFTMMU) && (TARGET_LONG_BITS == 64)
9716ef3b
PM		 208 /* Avoid clashes with registers being used for helper args */
209 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
210 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
211#endif
811d4cf4 212 break;
67dcab73
AJ		 213 /* qemu_st64 data_reg2 */
214 case 'S':
811d4cf4
AZ		 215 ct->ct |= TCG_CT_REG;
216 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 217 /* r0 and r1 will be overwritten when reading the tlb entry
218 (softmmu only) and doing the byte swapping, so don't
219 use these. */
811d4cf4 220 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
811d4cf4 221 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73
AJ		 222#ifdef CONFIG_SOFTMMU
223 /* r2 is still needed to load data_reg, so don't use it. */
224 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
89c33337 225#if TARGET_LONG_BITS == 64
9716ef3b
PM		 226 /* Avoid clashes with registers being used for helper args */
227 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
228#endif
811d4cf4 229#endif
67dcab73 230 break;
811d4cf4 231
811d4cf4
AZ		 232 default:
233 return -1;
234 }
235 ct_str++;
236 *pct_str = ct_str;
237
238 return 0;
239}
240
94953e6d
LD		 241static inline uint32_t rotl(uint32_t val, int n)
242{
243 return (val << n) | (val >> (32 - n));
244}
245
246/* ARM immediates for ALU instructions are made of an unsigned 8-bit
247 right-rotated by an even amount between 0 and 30. */
248static inline int encode_imm(uint32_t imm)
249{
4e6f6d4c
LD		 250 int shift;
251
94953e6d
LD		 252 /* simple case, only lower bits */
253 if ((imm & ~0xff) == 0)
254 return 0;
255 /* then try a simple even shift */
256 shift = ctz32(imm) & ~1;
257 if (((imm >> shift) & ~0xff) == 0)
258 return 32 - shift;
259 /* now try harder with rotations */
260 if ((rotl(imm, 2) & ~0xff) == 0)
261 return 2;
262 if ((rotl(imm, 4) & ~0xff) == 0)
263 return 4;
264 if ((rotl(imm, 6) & ~0xff) == 0)
265 return 6;
266 /* imm can't be encoded */
267 return -1;
268}
cb4e581f
LD		 269
270static inline int check_fit_imm(uint32_t imm)
271{
94953e6d 272 return encode_imm(imm) >= 0;
cb4e581f
LD		 273}
274
811d4cf4
AZ		 275/* Test if a constant matches the constraint.
276 * TODO: define constraints for:
277 *
278 * ldr/str offset: between -0xfff and 0xfff
279 * ldrh/strh offset: between -0xff and 0xff
280 * mov operand2: values represented with x << (2 * y), x < 0x100
281 * add, sub, eor...: ditto
282 */
283static inline int tcg_target_const_match(tcg_target_long val,
284 const TCGArgConstraint *arg_ct)
285{
286 int ct;
287 ct = arg_ct->ct;
288 if (ct & TCG_CT_CONST)
289 return 1;
cb4e581f
LD		 290 else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
291 return 1;
811d4cf4
AZ		 292 else
293 return 0;
294}
295
296enum arm_data_opc_e {
297 ARITH_AND = 0x0,
298 ARITH_EOR = 0x1,
299 ARITH_SUB = 0x2,
300 ARITH_RSB = 0x3,
301 ARITH_ADD = 0x4,
302 ARITH_ADC = 0x5,
303 ARITH_SBC = 0x6,
304 ARITH_RSC = 0x7,
3979144c 305 ARITH_TST = 0x8,
811d4cf4
AZ		 306 ARITH_CMP = 0xa,
307 ARITH_CMN = 0xb,
308 ARITH_ORR = 0xc,
309 ARITH_MOV = 0xd,
310 ARITH_BIC = 0xe,
311 ARITH_MVN = 0xf,
312};
313
3979144c
PB		 314#define TO_CPSR(opc) \
315 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
811d4cf4
AZ		 316
317#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
318#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
319#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
320#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
321#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
322#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
323#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
324#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
325
326enum arm_cond_code_e {
327 COND_EQ = 0x0,
328 COND_NE = 0x1,
329 COND_CS = 0x2, /* Unsigned greater or equal */
330 COND_CC = 0x3, /* Unsigned less than */
331 COND_MI = 0x4, /* Negative */
332 COND_PL = 0x5, /* Zero or greater */
333 COND_VS = 0x6, /* Overflow */
334 COND_VC = 0x7, /* No overflow */
335 COND_HI = 0x8, /* Unsigned greater than */
336 COND_LS = 0x9, /* Unsigned less or equal */
337 COND_GE = 0xa,
338 COND_LT = 0xb,
339 COND_GT = 0xc,
340 COND_LE = 0xd,
341 COND_AL = 0xe,
342};
343
344static const uint8_t tcg_cond_to_arm_cond[10] = {
345 [TCG_COND_EQ] = COND_EQ,
346 [TCG_COND_NE] = COND_NE,
347 [TCG_COND_LT] = COND_LT,
348 [TCG_COND_GE] = COND_GE,
349 [TCG_COND_LE] = COND_LE,
350 [TCG_COND_GT] = COND_GT,
351 /* unsigned */
352 [TCG_COND_LTU] = COND_CC,
353 [TCG_COND_GEU] = COND_CS,
354 [TCG_COND_LEU] = COND_LS,
355 [TCG_COND_GTU] = COND_HI,
356};
357
358static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
359{
360 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
361}
362
363static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
364{
365 tcg_out32(s, (cond << 28) | 0x0a000000 |
366 (((offset - 8) >> 2) & 0x00ffffff));
367}
368
e936243a
AZ		 369static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
370{
56779034
AJ		 371 /* We pay attention here to not modify the branch target by skipping
372 the corresponding bytes. This ensure that caches and memory are
373 kept coherent during retranslation. */
e2542fe2 374#ifdef HOST_WORDS_BIGENDIAN
e936243a
AZ		 375 tcg_out8(s, (cond << 4) | 0x0a);
376 s->code_ptr += 3;
377#else
378 s->code_ptr += 3;
379 tcg_out8(s, (cond << 4) | 0x0a);
380#endif
381}
382
811d4cf4
AZ		 383static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
384{
385 tcg_out32(s, (cond << 28) | 0x0b000000 |
386 (((offset - 8) >> 2) & 0x00ffffff));
387}
388
23401b58
AJ		 389static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
390{
391 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
392}
393
24e838b7
PM		 394static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset)
395{
396 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |
397 (((offset - 8) >> 2) & 0x00ffffff));
398}
399
811d4cf4
AZ		 400static inline void tcg_out_dat_reg(TCGContext *s,
401 int cond, int opc, int rd, int rn, int rm, int shift)
402{
403 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
404 (rn << 16) | (rd << 12) | shift | rm);
405}
406
9716ef3b
PM		 407static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
408{
409 /* Simple reg-reg move, optimising out the 'do nothing' case */
410 if (rd != rm) {
411 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0));
412 }
413}
414
811d4cf4
AZ		 415static inline void tcg_out_dat_reg2(TCGContext *s,
416 int cond, int opc0, int opc1, int rd0, int rd1,
417 int rn0, int rn1, int rm0, int rm1, int shift)
418{
0c9c3a9e
AZ		 419 if (rd0 == rn1 || rd0 == rm1) {
420 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
421 (rn0 << 16) | (8 << 12) | shift | rm0);
422 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
423 (rn1 << 16) | (rd1 << 12) | shift | rm1);
424 tcg_out_dat_reg(s, cond, ARITH_MOV,
425 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
426 } else {
427 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
428 (rn0 << 16) | (rd0 << 12) | shift | rm0);
429 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
430 (rn1 << 16) | (rd1 << 12) | shift | rm1);
431 }
811d4cf4
AZ		 432}
433
434static inline void tcg_out_dat_imm(TCGContext *s,
435 int cond, int opc, int rd, int rn, int im)
436{
3979144c 437 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
811d4cf4
AZ		 438 (rn << 16) | (rd << 12) | im);
439}
440
441static inline void tcg_out_movi32(TCGContext *s,
0f11f25a 442 int cond, int rd, uint32_t arg)
811d4cf4 443{
811d4cf4
AZ		 444 /* TODO: This is very suboptimal, we can easily have a constant
445 * pool somewhere after all the instructions. */
0f11f25a
AJ		 446 if ((int)arg < 0 && (int)arg >= -0x100) {
447 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
448 } else if (use_armv7_instructions) {
ac34fb5c
AJ		 449 /* use movw/movt */
450 /* movw */
451 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
452 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
0f11f25a 453 if (arg & 0xffff0000) {
ac34fb5c
AJ		 454 /* movt */
455 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
456 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
ac34fb5c 457 }
0f11f25a
AJ		 458 } else {
459 int opc = ARITH_MOV;
460 int rn = 0;
461
462 do {
463 int i, rot;
464
465 i = ctz32(arg) & ~1;
466 rot = ((32 - i) << 7) & 0xf00;
467 tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot);
468 arg &= ~(0xff << i);
469
470 opc = ARITH_ORR;
471 rn = rd;
472 } while (arg);
473 }
811d4cf4
AZ		 474}
475
476static inline void tcg_out_mul32(TCGContext *s,
477 int cond, int rd, int rs, int rm)
478{
479 if (rd != rm)
480 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
481 (rs << 8) | 0x90 | rm);
482 else if (rd != rs)
483 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
484 (rm << 8) | 0x90 | rs);
485 else {
486 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
487 (rs << 8) | 0x90 | rm);
488 tcg_out_dat_reg(s, cond, ARITH_MOV,
c8d80cef 489 rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 490 }
491}
492
493static inline void tcg_out_umull32(TCGContext *s,
494 int cond, int rd0, int rd1, int rs, int rm)
495{
496 if (rd0 != rm && rd1 != rm)
497 tcg_out32(s, (cond << 28) | 0x800090 |
498 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
499 else if (rd0 != rs && rd1 != rs)
500 tcg_out32(s, (cond << 28) | 0x800090 |
501 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
502 else {
503 tcg_out_dat_reg(s, cond, ARITH_MOV,
504 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
505 tcg_out32(s, (cond << 28) | 0x800098 |
506 (rd1 << 16) | (rd0 << 12) | (rs << 8));
507 }
508}
509
510static inline void tcg_out_smull32(TCGContext *s,
511 int cond, int rd0, int rd1, int rs, int rm)
512{
513 if (rd0 != rm && rd1 != rm)
514 tcg_out32(s, (cond << 28) | 0xc00090 |
515 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
516 else if (rd0 != rs && rd1 != rs)
517 tcg_out32(s, (cond << 28) | 0xc00090 |
518 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
519 else {
520 tcg_out_dat_reg(s, cond, ARITH_MOV,
521 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
522 tcg_out32(s, (cond << 28) | 0xc00098 |
523 (rd1 << 16) | (rd0 << 12) | (rs << 8));
524 }
525}
526
9517094f
AJ		 527static inline void tcg_out_ext8s(TCGContext *s, int cond,
528 int rd, int rn)
529{
530 if (use_armv6_instructions) {
531 /* sxtb */
532 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
533 } else {
e23886a9 534 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 535 rd, 0, rn, SHIFT_IMM_LSL(24));
e23886a9 536 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 537 rd, 0, rd, SHIFT_IMM_ASR(24));
538 }
539}
540
e854b6d3
AJ		 541static inline void tcg_out_ext8u(TCGContext *s, int cond,
542 int rd, int rn)
543{
544 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
545}
546
9517094f
AJ		 547static inline void tcg_out_ext16s(TCGContext *s, int cond,
548 int rd, int rn)
549{
550 if (use_armv6_instructions) {
551 /* sxth */
552 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
553 } else {
e23886a9 554 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 555 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 556 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 557 rd, 0, rd, SHIFT_IMM_ASR(16));
558 }
559}
560
561static inline void tcg_out_ext16u(TCGContext *s, int cond,
562 int rd, int rn)
563{
564 if (use_armv6_instructions) {
565 /* uxth */
566 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
567 } else {
e23886a9 568 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 569 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 570 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 571 rd, 0, rd, SHIFT_IMM_LSR(16));
572 }
573}
574
67dcab73
AJ		 575static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
576{
577 if (use_armv6_instructions) {
578 /* revsh */
579 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
580 } else {
581 tcg_out_dat_reg(s, cond, ARITH_MOV,
582 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
583 tcg_out_dat_reg(s, cond, ARITH_MOV,
584 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_ASR(16));
585 tcg_out_dat_reg(s, cond, ARITH_ORR,
586 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
587 }
588}
589
244b1e81
AJ		 590static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
591{
592 if (use_armv6_instructions) {
593 /* rev16 */
594 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
595 } else {
596 tcg_out_dat_reg(s, cond, ARITH_MOV,
597 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
598 tcg_out_dat_reg(s, cond, ARITH_MOV,
599 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
600 tcg_out_dat_reg(s, cond, ARITH_ORR,
601 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
602 }
603}
604
605static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
606{
607 if (use_armv6_instructions) {
608 /* rev */
609 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
610 } else {
611 tcg_out_dat_reg(s, cond, ARITH_EOR,
612 TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
613 tcg_out_dat_imm(s, cond, ARITH_BIC,
614 TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
615 tcg_out_dat_reg(s, cond, ARITH_MOV,
616 rd, 0, rn, SHIFT_IMM_ROR(8));
617 tcg_out_dat_reg(s, cond, ARITH_EOR,
618 rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
619 }
620}
621
811d4cf4
AZ		 622static inline void tcg_out_ld32_12(TCGContext *s, int cond,
623 int rd, int rn, tcg_target_long im)
624{
625 if (im >= 0)
626 tcg_out32(s, (cond << 28) | 0x05900000 |
627 (rn << 16) | (rd << 12) | (im & 0xfff));
628 else
629 tcg_out32(s, (cond << 28) | 0x05100000 |
630 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
631}
632
633static inline void tcg_out_st32_12(TCGContext *s, int cond,
634 int rd, int rn, tcg_target_long im)
635{
636 if (im >= 0)
637 tcg_out32(s, (cond << 28) | 0x05800000 |
638 (rn << 16) | (rd << 12) | (im & 0xfff));
639 else
640 tcg_out32(s, (cond << 28) | 0x05000000 |
641 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
642}
643
644static inline void tcg_out_ld32_r(TCGContext *s, int cond,
645 int rd, int rn, int rm)
646{
647 tcg_out32(s, (cond << 28) | 0x07900000 |
648 (rn << 16) | (rd << 12) | rm);
649}
650
651static inline void tcg_out_st32_r(TCGContext *s, int cond,
652 int rd, int rn, int rm)
653{
654 tcg_out32(s, (cond << 28) | 0x07800000 |
655 (rn << 16) | (rd << 12) | rm);
656}
657
3979144c
PB		 658/* Register pre-increment with base writeback. */
659static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
660 int rd, int rn, int rm)
661{
662 tcg_out32(s, (cond << 28) | 0x07b00000 |
663 (rn << 16) | (rd << 12) | rm);
664}
665
666static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
667 int rd, int rn, int rm)
668{
669 tcg_out32(s, (cond << 28) | 0x07a00000 |
670 (rn << 16) | (rd << 12) | rm);
671}
672
811d4cf4
AZ		 673static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
674 int rd, int rn, tcg_target_long im)
675{
676 if (im >= 0)
677 tcg_out32(s, (cond << 28) | 0x01d000b0 |
678 (rn << 16) | (rd << 12) |
679 ((im & 0xf0) << 4) | (im & 0xf));
680 else
681 tcg_out32(s, (cond << 28) | 0x015000b0 |
682 (rn << 16) | (rd << 12) |
683 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
684}
685
f694a27e 686static inline void tcg_out_st16_8(TCGContext *s, int cond,
811d4cf4
AZ		 687 int rd, int rn, tcg_target_long im)
688{
689 if (im >= 0)
690 tcg_out32(s, (cond << 28) | 0x01c000b0 |
691 (rn << 16) | (rd << 12) |
692 ((im & 0xf0) << 4) | (im & 0xf));
693 else
694 tcg_out32(s, (cond << 28) | 0x014000b0 |
695 (rn << 16) | (rd << 12) |
696 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
697}
698
699static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
700 int rd, int rn, int rm)
701{
702 tcg_out32(s, (cond << 28) | 0x019000b0 |
703 (rn << 16) | (rd << 12) | rm);
704}
705
f694a27e 706static inline void tcg_out_st16_r(TCGContext *s, int cond,
811d4cf4
AZ		 707 int rd, int rn, int rm)
708{
709 tcg_out32(s, (cond << 28) | 0x018000b0 |
710 (rn << 16) | (rd << 12) | rm);
711}
712
713static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
714 int rd, int rn, tcg_target_long im)
715{
716 if (im >= 0)
717 tcg_out32(s, (cond << 28) | 0x01d000f0 |
718 (rn << 16) | (rd << 12) |
719 ((im & 0xf0) << 4) | (im & 0xf));
720 else
721 tcg_out32(s, (cond << 28) | 0x015000f0 |
722 (rn << 16) | (rd << 12) |
723 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
724}
725
811d4cf4
AZ		 726static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
727 int rd, int rn, int rm)
728{
729 tcg_out32(s, (cond << 28) | 0x019000f0 |
730 (rn << 16) | (rd << 12) | rm);
731}
732
811d4cf4
AZ		 733static inline void tcg_out_ld8_12(TCGContext *s, int cond,
734 int rd, int rn, tcg_target_long im)
735{
736 if (im >= 0)
737 tcg_out32(s, (cond << 28) | 0x05d00000 |
738 (rn << 16) | (rd << 12) | (im & 0xfff));
739 else
740 tcg_out32(s, (cond << 28) | 0x05500000 |
741 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
742}
743
744static inline void tcg_out_st8_12(TCGContext *s, int cond,
745 int rd, int rn, tcg_target_long im)
746{
747 if (im >= 0)
748 tcg_out32(s, (cond << 28) | 0x05c00000 |
749 (rn << 16) | (rd << 12) | (im & 0xfff));
750 else
751 tcg_out32(s, (cond << 28) | 0x05400000 |
752 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
753}
754
755static inline void tcg_out_ld8_r(TCGContext *s, int cond,
756 int rd, int rn, int rm)
757{
758 tcg_out32(s, (cond << 28) | 0x07d00000 |
759 (rn << 16) | (rd << 12) | rm);
760}
761
762static inline void tcg_out_st8_r(TCGContext *s, int cond,
763 int rd, int rn, int rm)
764{
765 tcg_out32(s, (cond << 28) | 0x07c00000 |
766 (rn << 16) | (rd << 12) | rm);
767}
768
769static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
770 int rd, int rn, tcg_target_long im)
771{
772 if (im >= 0)
773 tcg_out32(s, (cond << 28) | 0x01d000d0 |
774 (rn << 16) | (rd << 12) |
775 ((im & 0xf0) << 4) | (im & 0xf));
776 else
777 tcg_out32(s, (cond << 28) | 0x015000d0 |
778 (rn << 16) | (rd << 12) |
779 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
780}
781
811d4cf4
AZ		 782static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
783 int rd, int rn, int rm)
784{
204c1674 785 tcg_out32(s, (cond << 28) | 0x019000d0 |
811d4cf4
AZ		 786 (rn << 16) | (rd << 12) | rm);
787}
788
811d4cf4
AZ		 789static inline void tcg_out_ld32u(TCGContext *s, int cond,
790 int rd, int rn, int32_t offset)
791{
792 if (offset > 0xfff || offset < -0xfff) {
793 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
794 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
795 } else
796 tcg_out_ld32_12(s, cond, rd, rn, offset);
797}
798
799static inline void tcg_out_st32(TCGContext *s, int cond,
800 int rd, int rn, int32_t offset)
801{
802 if (offset > 0xfff || offset < -0xfff) {
803 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
804 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
805 } else
806 tcg_out_st32_12(s, cond, rd, rn, offset);
807}
808
809static inline void tcg_out_ld16u(TCGContext *s, int cond,
810 int rd, int rn, int32_t offset)
811{
812 if (offset > 0xff || offset < -0xff) {
813 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
814 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
815 } else
816 tcg_out_ld16u_8(s, cond, rd, rn, offset);
817}
818
819static inline void tcg_out_ld16s(TCGContext *s, int cond,
820 int rd, int rn, int32_t offset)
821{
822 if (offset > 0xff || offset < -0xff) {
823 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
824 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
825 } else
826 tcg_out_ld16s_8(s, cond, rd, rn, offset);
827}
828
f694a27e 829static inline void tcg_out_st16(TCGContext *s, int cond,
811d4cf4
AZ		 830 int rd, int rn, int32_t offset)
831{
832 if (offset > 0xff || offset < -0xff) {
833 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
f694a27e 834 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
811d4cf4 835 } else
f694a27e 836 tcg_out_st16_8(s, cond, rd, rn, offset);
811d4cf4
AZ		 837}
838
839static inline void tcg_out_ld8u(TCGContext *s, int cond,
840 int rd, int rn, int32_t offset)
841{
842 if (offset > 0xfff || offset < -0xfff) {
843 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
844 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
845 } else
846 tcg_out_ld8_12(s, cond, rd, rn, offset);
847}
848
849static inline void tcg_out_ld8s(TCGContext *s, int cond,
850 int rd, int rn, int32_t offset)
851{
852 if (offset > 0xff || offset < -0xff) {
853 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
854 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
855 } else
856 tcg_out_ld8s_8(s, cond, rd, rn, offset);
857}
858
f694a27e 859static inline void tcg_out_st8(TCGContext *s, int cond,
811d4cf4
AZ		 860 int rd, int rn, int32_t offset)
861{
862 if (offset > 0xfff || offset < -0xfff) {
863 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
864 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
865 } else
866 tcg_out_st8_12(s, cond, rd, rn, offset);
867}
868
222f23f5 869/* The _goto case is normally between TBs within the same code buffer,
5c84bd90 870 * and with the code buffer limited to 16MB we shouldn't need the long
222f23f5
DDAG		 871 * case.
872 *
873 * .... except to the prologue that is in its own buffer.
874 */
811d4cf4
AZ		 875static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
876{
877 int32_t val;
878
24e838b7
PM		 879 if (addr & 1) {
880 /* goto to a Thumb destination isn't supported */
881 tcg_abort();
882 }
883
811d4cf4
AZ		 884 val = addr - (tcg_target_long) s->code_ptr;
885 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
886 tcg_out_b(s, cond, val);
887 else {
811d4cf4 888 if (cond == COND_AL) {
c8d80cef 889 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
222f23f5 890 tcg_out32(s, addr);
811d4cf4
AZ		 891 } else {
892 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
893 tcg_out_dat_reg(s, cond, ARITH_ADD,
c8d80cef
AJ		 894 TCG_REG_PC, TCG_REG_PC,
895 TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4 896 }
811d4cf4
AZ		 897 }
898}
899
222f23f5
DDAG		 900/* The call case is mostly used for helpers - so it's not unreasonable
901 * for them to be beyond branch range */
24e838b7 902static inline void tcg_out_call(TCGContext *s, uint32_t addr)
811d4cf4
AZ		 903{
904 int32_t val;
905
811d4cf4 906 val = addr - (tcg_target_long) s->code_ptr;
24e838b7
PM		 907 if (val - 8 < 0x02000000 && val - 8 >= -0x02000000) {
908 if (addr & 1) {
909 /* Use BLX if the target is in Thumb mode */
910 if (!use_armv5_instructions) {
911 tcg_abort();
912 }
913 tcg_out_blx_imm(s, val);
914 } else {
915 tcg_out_bl(s, COND_AL, val);
916 }
917 } else {
222f23f5
DDAG		 918 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
919 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
920 tcg_out32(s, addr);
811d4cf4 921 }
811d4cf4
AZ		 922}
923
924static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
925{
23401b58
AJ		 926 if (use_armv5_instructions) {
927 tcg_out_blx(s, cond, arg);
928 } else {
929 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
930 TCG_REG_PC, SHIFT_IMM_LSL(0));
931 tcg_out_bx(s, cond, arg);
932 }
811d4cf4
AZ		 933}
934
935static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
936{
937 TCGLabel *l = &s->labels[label_index];
938
939 if (l->has_value)
940 tcg_out_goto(s, cond, l->u.value);
941 else if (cond == COND_AL) {
c8d80cef 942 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 943 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
944 s->code_ptr += 4;
945 } else {
946 /* Probably this should be preferred even for COND_AL... */
947 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
e936243a 948 tcg_out_b_noaddr(s, cond);
811d4cf4
AZ		 949 }
950}
951
811d4cf4 952#ifdef CONFIG_SOFTMMU
79383c9c
BS		 953
954#include "../../softmmu_defs.h"
811d4cf4 955
e141ab52
BS		 956/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
957 int mmu_idx) */
958static const void * const qemu_ld_helpers[4] = {
959 helper_ldb_mmu,
960 helper_ldw_mmu,
961 helper_ldl_mmu,
962 helper_ldq_mmu,
963};
964
965/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
966 uintxx_t val, int mmu_idx) */
967static const void * const qemu_st_helpers[4] = {
968 helper_stb_mmu,
969 helper_stw_mmu,
970 helper_stl_mmu,
971 helper_stq_mmu,
972};
9716ef3b
PM		 973
974/* Helper routines for marshalling helper function arguments into
975 * the correct registers and stack.
976 * argreg is where we want to put this argument, arg is the argument itself.
977 * Return value is the updated argreg ready for the next call.
978 * Note that argreg 0..3 is real registers, 4+ on stack.
979 * When we reach the first stacked argument, we allocate space for it
980 * and the following stacked arguments using "str r8, [sp, #-0x10]!".
981 * Following arguments are filled in with "str r8, [sp, #0xNN]".
982 * For more than 4 stacked arguments we'd need to know how much
983 * space to allocate when we pushed the first stacked argument.
984 * We don't need this, so don't implement it (and will assert if you try it.)
985 *
986 * We provide routines for arguments which are: immediate, 32 bit
987 * value in register, 16 and 8 bit values in register (which must be zero
988 * extended before use) and 64 bit value in a lo:hi register pair.
989 */
990#define DEFINE_TCG_OUT_ARG(NAME, ARGPARAM) \
991 static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGPARAM) \
992 { \
993 if (argreg < 4) { \
994 TCG_OUT_ARG_GET_ARG(argreg); \
995 } else if (argreg == 4) { \
996 TCG_OUT_ARG_GET_ARG(TCG_REG_R8); \
997 tcg_out32(s, (COND_AL << 28) | 0x052d8010); \
998 } else { \
999 assert(argreg < 8); \
1000 TCG_OUT_ARG_GET_ARG(TCG_REG_R8); \
1001 tcg_out32(s, (COND_AL << 28) | 0x058d8000 | (argreg - 4) * 4); \
1002 } \
1003 return argreg + 1; \
1004 }
1005
1006#define TCG_OUT_ARG_GET_ARG(A) tcg_out_dat_imm(s, COND_AL, ARITH_MOV, A, 0, arg)
1007DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t arg)
1008#undef TCG_OUT_ARG_GET_ARG
1009#define TCG_OUT_ARG_GET_ARG(A) tcg_out_ext8u(s, COND_AL, A, arg)
1010DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg arg)
1011#undef TCG_OUT_ARG_GET_ARG
1012#define TCG_OUT_ARG_GET_ARG(A) tcg_out_ext16u(s, COND_AL, A, arg)
1013DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg arg)
1014#undef TCG_OUT_ARG_GET_ARG
1015
1016/* We don't use the macro for this one to avoid an unnecessary reg-reg
1017 * move when storing to the stack.
1018 */
1019static TCGReg tcg_out_arg_reg32(TCGContext *s, TCGReg argreg, TCGReg arg)
1020{
1021 if (argreg < 4) {
1022 tcg_out_mov_reg(s, COND_AL, argreg, arg);
1023 } else if (argreg == 4) {
1024 /* str arg, [sp, #-0x10]! */
1025 tcg_out32(s, (COND_AL << 28) | 0x052d0010 | (arg << 12));
1026 } else {
1027 assert(argreg < 8);
1028 /* str arg, [sp, #0xNN] */
1029 tcg_out32(s, (COND_AL << 28) | 0x058d0000 |
1030 (arg << 12) | (argreg - 4) * 4);
1031 }
1032 return argreg + 1;
1033}
1034
1035static inline TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
1036 TCGReg arglo, TCGReg arghi)
1037{
1038 /* 64 bit arguments must go in even/odd register pairs
1039 * and in 8-aligned stack slots.
1040 */
1041 if (argreg & 1) {
1042 argreg++;
1043 }
1044 argreg = tcg_out_arg_reg32(s, argreg, arglo);
1045 argreg = tcg_out_arg_reg32(s, argreg, arghi);
1046 return argreg;
1047}
1048
1049static inline void tcg_out_arg_stacktidy(TCGContext *s, TCGReg argreg)
1050{
1051 /* Output any necessary post-call cleanup of the stack */
1052 if (argreg > 4) {
1053 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10);
1054 }
1055}
1056
e141ab52 1057#endif
811d4cf4 1058
3979144c
PB		 1059#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
1060
7e0d9562 1061static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
811d4cf4 1062{
67dcab73 1063 int addr_reg, data_reg, data_reg2, bswap;
811d4cf4
AZ		 1064#ifdef CONFIG_SOFTMMU
1065 int mem_index, s_bits;
9716ef3b 1066 TCGReg argreg;
811d4cf4
AZ		 1067# if TARGET_LONG_BITS == 64
1068 int addr_reg2;
1069# endif
811d4cf4 1070 uint32_t *label_ptr;
811d4cf4
AZ		 1071#endif
1072
67dcab73
AJ		 1073#ifdef TARGET_WORDS_BIGENDIAN
1074 bswap = 1;
1075#else
1076 bswap = 0;
1077#endif
811d4cf4
AZ		 1078 data_reg = *args++;
1079 if (opc == 3)
1080 data_reg2 = *args++;
1081 else
d89c682f 1082 data_reg2 = 0; /* suppress warning */
811d4cf4 1083 addr_reg = *args++;
811d4cf4 1084#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 1085# if TARGET_LONG_BITS == 64
1086 addr_reg2 = *args++;
1087# endif
811d4cf4
AZ		 1088 mem_index = *args;
1089 s_bits = opc & 3;
1090
91a3c1b0 1091 /* Should generate something like the following:
3979144c 1092 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1093 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1094 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0
AZ		 1095 */
1096# if CPU_TLB_BITS > 8
1097# error
1098# endif
c8d80cef
AJ		 1099 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8,
1100 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 1101 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 1102 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1103 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
1104 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0 1105 /* In the
9349b4f9 1106 * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_read))]
91a3c1b0
AZ		 1107 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1108 * not exceed otherwise, so use an
9349b4f9 1109 * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
91a3c1b0
AZ		 1110 * before.
1111 */
225b4376 1112 if (mem_index)
c8d80cef 1113 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 1114 (mem_index << (TLB_SHIFT & 1)) |
1115 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 1116 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1117 offsetof(CPUArchState, tlb_table[0][0].addr_read));
c8d80cef
AJ		 1118 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1119 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 1120 /* Check alignment. */
1121 if (s_bits)
1122 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1123 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 1124# if TARGET_LONG_BITS == 64
1125 /* XXX: possibly we could use a block data load or writeback in
1126 * the first access. */
c8d80cef 1127 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1128 offsetof(CPUArchState, tlb_table[0][0].addr_read) + 4);
c8d80cef
AJ		 1129 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1130 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1131# endif
c8d80cef 1132 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1133 offsetof(CPUArchState, tlb_table[0][0].addend));
811d4cf4
AZ		 1134
1135 switch (opc) {
1136 case 0:
c8d80cef 1137 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1138 break;
1139 case 0 | 4:
c8d80cef 1140 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1141 break;
1142 case 1:
c8d80cef 1143 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
67dcab73
AJ		 1144 if (bswap) {
1145 tcg_out_bswap16(s, COND_EQ, data_reg, data_reg);
1146 }
811d4cf4
AZ		 1147 break;
1148 case 1 | 4:
67dcab73
AJ		 1149 if (bswap) {
1150 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1151 tcg_out_bswap16s(s, COND_EQ, data_reg, data_reg);
1152 } else {
1153 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1154 }
811d4cf4
AZ		 1155 break;
1156 case 2:
1157 default:
c8d80cef 1158 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
67dcab73
AJ		 1159 if (bswap) {
1160 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1161 }
811d4cf4
AZ		 1162 break;
1163 case 3:
67dcab73
AJ		 1164 if (bswap) {
1165 tcg_out_ld32_rwb(s, COND_EQ, data_reg2, TCG_REG_R1, addr_reg);
1166 tcg_out_ld32_12(s, COND_EQ, data_reg, TCG_REG_R1, 4);
1167 tcg_out_bswap32(s, COND_EQ, data_reg2, data_reg2);
1168 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1169 } else {
1170 tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1171 tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1172 }
811d4cf4
AZ		 1173 break;
1174 }
1175
1176 label_ptr = (void *) s->code_ptr;
c69806ab 1177 tcg_out_b_noaddr(s, COND_EQ);
811d4cf4 1178
811d4cf4 1179 /* TODO: move this code to where the constants pool will be */
9716ef3b
PM		 1180 /* Note that this code relies on the constraints we set in arm_op_defs[]
1181 * to ensure that later arguments are not passed to us in registers we
1182 * trash by moving the earlier arguments into them.
1183 */
1184 argreg = TCG_REG_R0;
9716ef3b 1185 argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
9716ef3b
PM		 1186#if TARGET_LONG_BITS == 64
1187 argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
1188#else
1189 argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
e141ab52 1190#endif
9716ef3b 1191 argreg = tcg_out_arg_imm32(s, argreg, mem_index);
24e838b7 1192 tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[s_bits]);
9716ef3b 1193 tcg_out_arg_stacktidy(s, argreg);
811d4cf4
AZ		 1194
1195 switch (opc) {
1196 case 0 | 4:
e854b6d3 1197 tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ		 1198 break;
1199 case 1 | 4:
e854b6d3 1200 tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ		 1201 break;
1202 case 0:
1203 case 1:
1204 case 2:
1205 default:
c8d80cef 1206 if (data_reg != TCG_REG_R0) {
7e0d9562 1207 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1208 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1209 }
811d4cf4
AZ		 1210 break;
1211 case 3:
c8d80cef 1212 if (data_reg != TCG_REG_R0) {
7e0d9562 1213 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1214 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1215 }
1216 if (data_reg2 != TCG_REG_R1) {
7e0d9562 1217 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1218 data_reg2, 0, TCG_REG_R1, SHIFT_IMM_LSL(0));
1219 }
811d4cf4
AZ		 1220 break;
1221 }
1222
c69806ab 1223 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
379f6698
PB		 1224#else /* !CONFIG_SOFTMMU */
1225 if (GUEST_BASE) {
1226 uint32_t offset = GUEST_BASE;
1227 int i;
1228 int rot;
1229
1230 while (offset) {
1231 i = ctz32(offset) & ~1;
1232 rot = ((32 - i) << 7) & 0xf00;
1233
c8d80cef 1234 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
379f6698 1235 ((offset >> i) & 0xff) | rot);
c8d80cef 1236 addr_reg = TCG_REG_R8;
379f6698
PB		 1237 offset &= ~(0xff << i);
1238 }
1239 }
811d4cf4
AZ		 1240 switch (opc) {
1241 case 0:
1242 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
1243 break;
1244 case 0 | 4:
1245 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1246 break;
1247 case 1:
1248 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
67dcab73
AJ		 1249 if (bswap) {
1250 tcg_out_bswap16(s, COND_AL, data_reg, data_reg);
1251 }
811d4cf4
AZ		 1252 break;
1253 case 1 | 4:
67dcab73
AJ		 1254 if (bswap) {
1255 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1256 tcg_out_bswap16s(s, COND_AL, data_reg, data_reg);
1257 } else {
1258 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1259 }
811d4cf4
AZ		 1260 break;
1261 case 2:
1262 default:
1263 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
67dcab73
AJ		 1264 if (bswap) {
1265 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1266 }
811d4cf4
AZ		 1267 break;
1268 case 3:
eae6ce52
AZ		 1269 /* TODO: use block load -
1270 * check that data_reg2 > data_reg or the other way */
419bafa5 1271 if (data_reg == addr_reg) {
67dcab73
AJ		 1272 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1273 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
419bafa5 1274 } else {
67dcab73
AJ		 1275 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
1276 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1277 }
1278 if (bswap) {
1279 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1280 tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2);
419bafa5 1281 }
811d4cf4
AZ		 1282 break;
1283 }
1284#endif
1285}
1286
7e0d9562 1287static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
811d4cf4 1288{
67dcab73 1289 int addr_reg, data_reg, data_reg2, bswap;
811d4cf4
AZ		 1290#ifdef CONFIG_SOFTMMU
1291 int mem_index, s_bits;
9716ef3b 1292 TCGReg argreg;
811d4cf4
AZ		 1293# if TARGET_LONG_BITS == 64
1294 int addr_reg2;
1295# endif
811d4cf4 1296 uint32_t *label_ptr;
811d4cf4
AZ		 1297#endif
1298
67dcab73
AJ		 1299#ifdef TARGET_WORDS_BIGENDIAN
1300 bswap = 1;
1301#else
1302 bswap = 0;
1303#endif
811d4cf4
AZ		 1304 data_reg = *args++;
1305 if (opc == 3)
1306 data_reg2 = *args++;
1307 else
d89c682f 1308 data_reg2 = 0; /* suppress warning */
811d4cf4 1309 addr_reg = *args++;
811d4cf4 1310#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 1311# if TARGET_LONG_BITS == 64
1312 addr_reg2 = *args++;
1313# endif
811d4cf4
AZ		 1314 mem_index = *args;
1315 s_bits = opc & 3;
1316
91a3c1b0 1317 /* Should generate something like the following:
3979144c 1318 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1319 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1320 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0 1321 */
811d4cf4 1322 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1323 TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 1324 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 1325 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1326 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
1327 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0 1328 /* In the
9349b4f9 1329 * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_write))]
91a3c1b0
AZ		 1330 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1331 * not exceed otherwise, so use an
9349b4f9 1332 * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
91a3c1b0
AZ		 1333 * before.
1334 */
225b4376 1335 if (mem_index)
c8d80cef 1336 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 1337 (mem_index << (TLB_SHIFT & 1)) |
1338 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 1339 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1340 offsetof(CPUArchState, tlb_table[0][0].addr_write));
c8d80cef
AJ		 1341 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1342 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 1343 /* Check alignment. */
1344 if (s_bits)
1345 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1346 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 1347# if TARGET_LONG_BITS == 64
1348 /* XXX: possibly we could use a block data load or writeback in
1349 * the first access. */
c8d80cef 1350 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1351 offsetof(CPUArchState, tlb_table[0][0].addr_write) + 4);
c8d80cef
AJ		 1352 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1353 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1354# endif
c8d80cef 1355 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
9349b4f9 1356 offsetof(CPUArchState, tlb_table[0][0].addend));
811d4cf4
AZ		 1357
1358 switch (opc) {
1359 case 0:
c8d80cef 1360 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4 1361 break;
811d4cf4 1362 case 1:
67dcab73
AJ		 1363 if (bswap) {
1364 tcg_out_bswap16(s, COND_EQ, TCG_REG_R0, data_reg);
1365 tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1366 } else {
1367 tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1368 }
811d4cf4
AZ		 1369 break;
1370 case 2:
1371 default:
67dcab73
AJ		 1372 if (bswap) {
1373 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
1374 tcg_out_st32_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1375 } else {
1376 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1377 }
811d4cf4
AZ		 1378 break;
1379 case 3:
67dcab73
AJ		 1380 if (bswap) {
1381 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2);
1382 tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, addr_reg);
1383 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
9a3abc21 1384 tcg_out_st32_12(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, 4);
67dcab73
AJ		 1385 } else {
1386 tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1387 tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1388 }
811d4cf4
AZ		 1389 break;
1390 }
1391
1392 label_ptr = (void *) s->code_ptr;
c69806ab 1393 tcg_out_b_noaddr(s, COND_EQ);
811d4cf4 1394
811d4cf4 1395 /* TODO: move this code to where the constants pool will be */
9716ef3b
PM		 1396 /* Note that this code relies on the constraints we set in arm_op_defs[]
1397 * to ensure that later arguments are not passed to us in registers we
1398 * trash by moving the earlier arguments into them.
1399 */
1400 argreg = TCG_REG_R0;
9716ef3b 1401 argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
9716ef3b
PM		 1402#if TARGET_LONG_BITS == 64
1403 argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
1404#else
1405 argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
1406#endif
1407
811d4cf4
AZ		 1408 switch (opc) {
1409 case 0:
9716ef3b 1410 argreg = tcg_out_arg_reg8(s, argreg, data_reg);
811d4cf4
AZ		 1411 break;
1412 case 1:
9716ef3b 1413 argreg = tcg_out_arg_reg16(s, argreg, data_reg);
811d4cf4
AZ		 1414 break;
1415 case 2:
9716ef3b 1416 argreg = tcg_out_arg_reg32(s, argreg, data_reg);
811d4cf4
AZ		 1417 break;
1418 case 3:
9716ef3b 1419 argreg = tcg_out_arg_reg64(s, argreg, data_reg, data_reg2);
811d4cf4
AZ		 1420 break;
1421 }
811d4cf4 1422
9716ef3b 1423 argreg = tcg_out_arg_imm32(s, argreg, mem_index);
24e838b7 1424 tcg_out_call(s, (tcg_target_long) qemu_st_helpers[s_bits]);
9716ef3b 1425 tcg_out_arg_stacktidy(s, argreg);
811d4cf4 1426
c69806ab 1427 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
379f6698
PB		 1428#else /* !CONFIG_SOFTMMU */
1429 if (GUEST_BASE) {
1430 uint32_t offset = GUEST_BASE;
1431 int i;
1432 int rot;
1433
1434 while (offset) {
1435 i = ctz32(offset) & ~1;
1436 rot = ((32 - i) << 7) & 0xf00;
1437
67dcab73 1438 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R1, addr_reg,
379f6698 1439 ((offset >> i) & 0xff) | rot);
67dcab73 1440 addr_reg = TCG_REG_R1;
379f6698
PB		 1441 offset &= ~(0xff << i);
1442 }
1443 }
811d4cf4
AZ		 1444 switch (opc) {
1445 case 0:
1446 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1447 break;
811d4cf4 1448 case 1:
67dcab73
AJ		 1449 if (bswap) {
1450 tcg_out_bswap16(s, COND_AL, TCG_REG_R0, data_reg);
1451 tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1452 } else {
1453 tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
1454 }
811d4cf4
AZ		 1455 break;
1456 case 2:
1457 default:
67dcab73
AJ		 1458 if (bswap) {
1459 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1460 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1461 } else {
1462 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1463 }
811d4cf4
AZ		 1464 break;
1465 case 3:
eae6ce52
AZ		 1466 /* TODO: use block store -
1467 * check that data_reg2 > data_reg or the other way */
67dcab73
AJ		 1468 if (bswap) {
1469 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2);
1470 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1471 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1472 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 4);
1473 } else {
1474 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1475 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1476 }
811d4cf4
AZ		 1477 break;
1478 }
1479#endif
1480}
1481
811d4cf4
AZ		 1482static uint8_t *tb_ret_addr;
1483
a9751609 1484static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
811d4cf4
AZ		 1485 const TCGArg *args, const int *const_args)
1486{
1487 int c;
1488
1489 switch (opc) {
1490 case INDEX_op_exit_tb:
fe33867b
AZ		 1491 {
1492 uint8_t *ld_ptr = s->code_ptr;
1493 if (args[0] >> 8)
c8d80cef 1494 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
fe33867b 1495 else
c8d80cef 1496 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
fe33867b
AZ		 1497 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1498 if (args[0] >> 8) {
1499 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1500 tcg_out32(s, args[0]);
1501 }
1502 }
811d4cf4
AZ		 1503 break;
1504 case INDEX_op_goto_tb:
1505 if (s->tb_jmp_offset) {
1506 /* Direct jump method */
fe33867b 1507#if defined(USE_DIRECT_JUMP)
811d4cf4 1508 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
c69806ab 1509 tcg_out_b_noaddr(s, COND_AL);
811d4cf4 1510#else
c8d80cef 1511 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 1512 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1513 tcg_out32(s, 0);
1514#endif
1515 } else {
1516 /* Indirect jump method */
1517#if 1
1518 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1519 if (c > 0xfff || c < -0xfff) {
1520 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1521 (tcg_target_long) (s->tb_next + args[0]));
c8d80cef 1522 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4 1523 } else
c8d80cef 1524 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c);
811d4cf4 1525#else
c8d80cef
AJ		 1526 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1527 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4
AZ		 1528 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1529#endif
1530 }
1531 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1532 break;
1533 case INDEX_op_call:
1534 if (const_args[0])
24e838b7 1535 tcg_out_call(s, args[0]);
811d4cf4
AZ		 1536 else
1537 tcg_out_callr(s, COND_AL, args[0]);
1538 break;
1539 case INDEX_op_jmp:
1540 if (const_args[0])
1541 tcg_out_goto(s, COND_AL, args[0]);
1542 else
1543 tcg_out_bx(s, COND_AL, args[0]);
1544 break;
1545 case INDEX_op_br:
1546 tcg_out_goto_label(s, COND_AL, args[0]);
1547 break;
1548
1549 case INDEX_op_ld8u_i32:
1550 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1551 break;
1552 case INDEX_op_ld8s_i32:
1553 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1554 break;
1555 case INDEX_op_ld16u_i32:
1556 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1557 break;
1558 case INDEX_op_ld16s_i32:
1559 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1560 break;
1561 case INDEX_op_ld_i32:
1562 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1563 break;
1564 case INDEX_op_st8_i32:
f694a27e 1565 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1566 break;
1567 case INDEX_op_st16_i32:
f694a27e 1568 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1569 break;
1570 case INDEX_op_st_i32:
1571 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1572 break;
1573
1574 case INDEX_op_mov_i32:
1575 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1576 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1577 break;
1578 case INDEX_op_movi_i32:
1579 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1580 break;
1581 case INDEX_op_add_i32:
1582 c = ARITH_ADD;
1583 goto gen_arith;
1584 case INDEX_op_sub_i32:
1585 c = ARITH_SUB;
1586 goto gen_arith;
1587 case INDEX_op_and_i32:
1588 c = ARITH_AND;
1589 goto gen_arith;
932234f6
AJ		 1590 case INDEX_op_andc_i32:
1591 c = ARITH_BIC;
1592 goto gen_arith;
811d4cf4
AZ		 1593 case INDEX_op_or_i32:
1594 c = ARITH_ORR;
1595 goto gen_arith;
1596 case INDEX_op_xor_i32:
1597 c = ARITH_EOR;
1598 /* Fall through. */
1599 gen_arith:
94953e6d
LD		 1600 if (const_args[2]) {
1601 int rot;
1602 rot = encode_imm(args[2]);
cb4e581f 1603 tcg_out_dat_imm(s, COND_AL, c,
94953e6d
LD		 1604 args[0], args[1], rotl(args[2], rot) | (rot << 7));
1605 } else
cb4e581f
LD		 1606 tcg_out_dat_reg(s, COND_AL, c,
1607 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1608 break;
1609 case INDEX_op_add2_i32:
1610 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1611 args[0], args[1], args[2], args[3],
1612 args[4], args[5], SHIFT_IMM_LSL(0));
1613 break;
1614 case INDEX_op_sub2_i32:
1615 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1616 args[0], args[1], args[2], args[3],
1617 args[4], args[5], SHIFT_IMM_LSL(0));
1618 break;
650bbb36
AZ		 1619 case INDEX_op_neg_i32:
1620 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1621 break;
f878d2d2
LD		 1622 case INDEX_op_not_i32:
1623 tcg_out_dat_reg(s, COND_AL,
1624 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1625 break;
811d4cf4
AZ		 1626 case INDEX_op_mul_i32:
1627 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1628 break;
1629 case INDEX_op_mulu2_i32:
1630 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1631 break;
811d4cf4
AZ		 1632 /* XXX: Perhaps args[2] & 0x1f is wrong */
1633 case INDEX_op_shl_i32:
1634 c = const_args[2] ?
1635 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1636 goto gen_shift32;
1637 case INDEX_op_shr_i32:
1638 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1639 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1640 goto gen_shift32;
1641 case INDEX_op_sar_i32:
1642 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1643 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
293579e5
AJ		 1644 goto gen_shift32;
1645 case INDEX_op_rotr_i32:
1646 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1647 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
811d4cf4
AZ		 1648 /* Fall through. */
1649 gen_shift32:
1650 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1651 break;
1652
293579e5
AJ		 1653 case INDEX_op_rotl_i32:
1654 if (const_args[2]) {
1655 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1656 ((0x20 - args[2]) & 0x1f) ?
1657 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1658 SHIFT_IMM_LSL(0));
1659 } else {
1660 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
1661 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1662 SHIFT_REG_ROR(TCG_REG_R8));
1663 }
1664 break;
1665
811d4cf4 1666 case INDEX_op_brcond_i32:
023e77f8
AJ		 1667 if (const_args[1]) {
1668 int rot;
1669 rot = encode_imm(args[1]);
c8d80cef
AJ		 1670 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1671 args[0], rotl(args[1], rot) | (rot << 7));
023e77f8
AJ		 1672 } else {
1673 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1674 args[0], args[1], SHIFT_IMM_LSL(0));
1675 }
811d4cf4
AZ		 1676 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1677 break;
1678 case INDEX_op_brcond2_i32:
1679 /* The resulting conditions are:
1680 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1681 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1682 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1683 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1684 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1685 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1686 */
1687 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1688 args[1], args[3], SHIFT_IMM_LSL(0));
1689 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1690 args[0], args[2], SHIFT_IMM_LSL(0));
1691 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1692 break;
f72a6cd7 1693 case INDEX_op_setcond_i32:
023e77f8
AJ		 1694 if (const_args[2]) {
1695 int rot;
1696 rot = encode_imm(args[2]);
c8d80cef
AJ		 1697 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1698 args[1], rotl(args[2], rot) | (rot << 7));
023e77f8
AJ		 1699 } else {
1700 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1701 args[1], args[2], SHIFT_IMM_LSL(0));
1702 }
f72a6cd7
AJ		 1703 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1704 ARITH_MOV, args[0], 0, 1);
1705 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1706 ARITH_MOV, args[0], 0, 0);
1707 break;
e0404769
AJ		 1708 case INDEX_op_setcond2_i32:
1709 /* See brcond2_i32 comment */
1710 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1711 args[2], args[4], SHIFT_IMM_LSL(0));
1712 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1713 args[1], args[3], SHIFT_IMM_LSL(0));
1714 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1715 ARITH_MOV, args[0], 0, 1);
1716 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1717 ARITH_MOV, args[0], 0, 0);
b525f0a9 1718 break;
811d4cf4
AZ		 1719
1720 case INDEX_op_qemu_ld8u:
7e0d9562 1721 tcg_out_qemu_ld(s, args, 0);
811d4cf4
AZ		 1722 break;
1723 case INDEX_op_qemu_ld8s:
7e0d9562 1724 tcg_out_qemu_ld(s, args, 0 | 4);
811d4cf4
AZ		 1725 break;
1726 case INDEX_op_qemu_ld16u:
7e0d9562 1727 tcg_out_qemu_ld(s, args, 1);
811d4cf4
AZ		 1728 break;
1729 case INDEX_op_qemu_ld16s:
7e0d9562 1730 tcg_out_qemu_ld(s, args, 1 | 4);
811d4cf4 1731 break;
86feb1c8 1732 case INDEX_op_qemu_ld32:
7e0d9562 1733 tcg_out_qemu_ld(s, args, 2);
811d4cf4
AZ		 1734 break;
1735 case INDEX_op_qemu_ld64:
7e0d9562 1736 tcg_out_qemu_ld(s, args, 3);
811d4cf4 1737 break;
650bbb36 1738
811d4cf4 1739 case INDEX_op_qemu_st8:
7e0d9562 1740 tcg_out_qemu_st(s, args, 0);
811d4cf4
AZ		 1741 break;
1742 case INDEX_op_qemu_st16:
7e0d9562 1743 tcg_out_qemu_st(s, args, 1);
811d4cf4
AZ		 1744 break;
1745 case INDEX_op_qemu_st32:
7e0d9562 1746 tcg_out_qemu_st(s, args, 2);
811d4cf4
AZ		 1747 break;
1748 case INDEX_op_qemu_st64:
7e0d9562 1749 tcg_out_qemu_st(s, args, 3);
811d4cf4
AZ		 1750 break;
1751
244b1e81
AJ		 1752 case INDEX_op_bswap16_i32:
1753 tcg_out_bswap16(s, COND_AL, args[0], args[1]);
1754 break;
1755 case INDEX_op_bswap32_i32:
1756 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
1757 break;
1758
811d4cf4 1759 case INDEX_op_ext8s_i32:
9517094f 1760 tcg_out_ext8s(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1761 break;
1762 case INDEX_op_ext16s_i32:
9517094f
AJ		 1763 tcg_out_ext16s(s, COND_AL, args[0], args[1]);
1764 break;
1765 case INDEX_op_ext16u_i32:
1766 tcg_out_ext16u(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1767 break;
1768
1769 default:
1770 tcg_abort();
1771 }
1772}
1773
1774static const TCGTargetOpDef arm_op_defs[] = {
1775 { INDEX_op_exit_tb, { } },
1776 { INDEX_op_goto_tb, { } },
1777 { INDEX_op_call, { "ri" } },
1778 { INDEX_op_jmp, { "ri" } },
1779 { INDEX_op_br, { } },
1780
1781 { INDEX_op_mov_i32, { "r", "r" } },
1782 { INDEX_op_movi_i32, { "r" } },
1783
1784 { INDEX_op_ld8u_i32, { "r", "r" } },
1785 { INDEX_op_ld8s_i32, { "r", "r" } },
1786 { INDEX_op_ld16u_i32, { "r", "r" } },
1787 { INDEX_op_ld16s_i32, { "r", "r" } },
1788 { INDEX_op_ld_i32, { "r", "r" } },
1789 { INDEX_op_st8_i32, { "r", "r" } },
1790 { INDEX_op_st16_i32, { "r", "r" } },
1791 { INDEX_op_st_i32, { "r", "r" } },
1792
1793 /* TODO: "r", "r", "ri" */
cb4e581f
LD		 1794 { INDEX_op_add_i32, { "r", "r", "rI" } },
1795 { INDEX_op_sub_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1796 { INDEX_op_mul_i32, { "r", "r", "r" } },
1797 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
cb4e581f 1798 { INDEX_op_and_i32, { "r", "r", "rI" } },
932234f6 1799 { INDEX_op_andc_i32, { "r", "r", "rI" } },
cb4e581f
LD		 1800 { INDEX_op_or_i32, { "r", "r", "rI" } },
1801 { INDEX_op_xor_i32, { "r", "r", "rI" } },
650bbb36 1802 { INDEX_op_neg_i32, { "r", "r" } },
f878d2d2 1803 { INDEX_op_not_i32, { "r", "r" } },
811d4cf4
AZ		 1804
1805 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1806 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1807 { INDEX_op_sar_i32, { "r", "r", "ri" } },
293579e5
AJ		 1808 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1809 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
811d4cf4 1810
023e77f8
AJ		 1811 { INDEX_op_brcond_i32, { "r", "rI" } },
1812 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1813
1814 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1815 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1816 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1817 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
e0404769 1818 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
811d4cf4 1819
26c5d372 1820#if TARGET_LONG_BITS == 32
67dcab73
AJ		 1821 { INDEX_op_qemu_ld8u, { "r", "l" } },
1822 { INDEX_op_qemu_ld8s, { "r", "l" } },
1823 { INDEX_op_qemu_ld16u, { "r", "l" } },
1824 { INDEX_op_qemu_ld16s, { "r", "l" } },
1825 { INDEX_op_qemu_ld32, { "r", "l" } },
1826 { INDEX_op_qemu_ld64, { "L", "L", "l" } },
1827
1828 { INDEX_op_qemu_st8, { "s", "s" } },
1829 { INDEX_op_qemu_st16, { "s", "s" } },
1830 { INDEX_op_qemu_st32, { "s", "s" } },
bf5675ef 1831 { INDEX_op_qemu_st64, { "S", "S", "s" } },
26c5d372 1832#else
67dcab73
AJ		 1833 { INDEX_op_qemu_ld8u, { "r", "l", "l" } },
1834 { INDEX_op_qemu_ld8s, { "r", "l", "l" } },
1835 { INDEX_op_qemu_ld16u, { "r", "l", "l" } },
1836 { INDEX_op_qemu_ld16s, { "r", "l", "l" } },
1837 { INDEX_op_qemu_ld32, { "r", "l", "l" } },
1838 { INDEX_op_qemu_ld64, { "L", "L", "l", "l" } },
1839
1840 { INDEX_op_qemu_st8, { "s", "s", "s" } },
1841 { INDEX_op_qemu_st16, { "s", "s", "s" } },
1842 { INDEX_op_qemu_st32, { "s", "s", "s" } },
bf5675ef 1843 { INDEX_op_qemu_st64, { "S", "S", "s", "s" } },
26c5d372 1844#endif
811d4cf4 1845
244b1e81
AJ		 1846 { INDEX_op_bswap16_i32, { "r", "r" } },
1847 { INDEX_op_bswap32_i32, { "r", "r" } },
1848
811d4cf4
AZ		 1849 { INDEX_op_ext8s_i32, { "r", "r" } },
1850 { INDEX_op_ext16s_i32, { "r", "r" } },
9517094f 1851 { INDEX_op_ext16u_i32, { "r", "r" } },
811d4cf4
AZ		 1852
1853 { -1 },
1854};
1855
e4d58b41 1856static void tcg_target_init(TCGContext *s)
811d4cf4 1857{
20cb400d 1858#if !defined(CONFIG_USER_ONLY)
811d4cf4
AZ		 1859 /* fail safe */
1860 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1861 tcg_abort();
20cb400d 1862#endif
811d4cf4 1863
e4a7d5e8 1864 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
811d4cf4 1865 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
e4a7d5e8
AJ		 1866 (1 << TCG_REG_R0) |
1867 (1 << TCG_REG_R1) |
1868 (1 << TCG_REG_R2) |
1869 (1 << TCG_REG_R3) |
1870 (1 << TCG_REG_R12) |
1871 (1 << TCG_REG_R14));
811d4cf4
AZ		 1872
1873 tcg_regset_clear(s->reserved_regs);
811d4cf4
AZ		 1874 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1875 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
e4a7d5e8 1876 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
811d4cf4
AZ		 1877
1878 tcg_add_target_add_op_defs(arm_op_defs);
9349b4f9 1879 tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
614f104d 1880 CPU_TEMP_BUF_NLONGS * sizeof(long));
811d4cf4
AZ		 1881}
1882
2a534aff
RH		 1883static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
1884 TCGReg arg1, tcg_target_long arg2)
811d4cf4
AZ		 1885{
1886 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1887}
1888
2a534aff
RH		 1889static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1890 TCGReg arg1, tcg_target_long arg2)
811d4cf4
AZ		 1891{
1892 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1893}
1894
2a534aff
RH		 1895static inline void tcg_out_mov(TCGContext *s, TCGType type,
1896 TCGReg ret, TCGReg arg)
811d4cf4
AZ		 1897{
1898 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1899}
1900
1901static inline void tcg_out_movi(TCGContext *s, TCGType type,
2a534aff 1902 TCGReg ret, tcg_target_long arg)
811d4cf4
AZ		 1903{
1904 tcg_out_movi32(s, COND_AL, ret, arg);
1905}
1906
e4d58b41 1907static void tcg_target_qemu_prologue(TCGContext *s)
811d4cf4 1908{
cea5f9a2
BS		 1909 /* Calling convention requires us to save r4-r11 and lr;
1910 * save also r12 to maintain stack 8-alignment.
1911 */
1912
1913 /* stmdb sp!, { r4 - r12, lr } */
1914 tcg_out32(s, (COND_AL << 28) | 0x092d5ff0);
4e17eae9 1915
cea5f9a2 1916 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
811d4cf4 1917
cea5f9a2 1918 tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]);
811d4cf4
AZ		 1919 tb_ret_addr = s->code_ptr;
1920
cea5f9a2
BS		 1921 /* ldmia sp!, { r4 - r12, pc } */
1922 tcg_out32(s, (COND_AL << 28) | 0x08bd9ff0);
811d4cf4 1923}
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