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tcg/arm: fix branch target change during code retranslation
[mirror_qemu.git] / tcg / arm / tcg-target.c
CommitLineData
811d4cf4
AZ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
d4a9eb1f 24
ac34fb5c
AJ		 25#if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30#define USE_ARMV7_INSTRUCTIONS
31#endif
32
33#if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39#define USE_ARMV6_INSTRUCTIONS
40#endif
41
42#if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46#define USE_ARMV5_INSTRUCTIONS
47#endif
48
49#ifdef USE_ARMV5_INSTRUCTIONS
50static const int use_armv5_instructions = 1;
51#else
52static const int use_armv5_instructions = 0;
53#endif
54#undef USE_ARMV5_INSTRUCTIONS
55
56#ifdef USE_ARMV6_INSTRUCTIONS
57static const int use_armv6_instructions = 1;
58#else
59static const int use_armv6_instructions = 0;
60#endif
61#undef USE_ARMV6_INSTRUCTIONS
62
63#ifdef USE_ARMV7_INSTRUCTIONS
64static const int use_armv7_instructions = 1;
65#else
66static const int use_armv7_instructions = 0;
67#endif
68#undef USE_ARMV7_INSTRUCTIONS
69
d4a9eb1f
BS		 70#ifndef NDEBUG
71static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
811d4cf4
AZ		 72 "%r0",
73 "%r1",
74 "%r2",
75 "%r3",
76 "%r4",
77 "%r5",
78 "%r6",
79 "%r7",
80 "%r8",
81 "%r9",
82 "%r10",
83 "%r11",
84 "%r12",
85 "%r13",
86 "%r14",
e4a7d5e8 87 "%pc",
811d4cf4 88};
d4a9eb1f 89#endif
811d4cf4 90
d4a9eb1f 91static const int tcg_target_reg_alloc_order[] = {
811d4cf4
AZ		 92 TCG_REG_R4,
93 TCG_REG_R5,
94 TCG_REG_R6,
95 TCG_REG_R7,
96 TCG_REG_R8,
97 TCG_REG_R9,
98 TCG_REG_R10,
99 TCG_REG_R11,
811d4cf4 100 TCG_REG_R13,
914ccf51
AJ		 101 TCG_REG_R0,
102 TCG_REG_R1,
103 TCG_REG_R2,
104 TCG_REG_R3,
105 TCG_REG_R12,
811d4cf4
AZ		 106 TCG_REG_R14,
107};
108
d4a9eb1f 109static const int tcg_target_call_iarg_regs[4] = {
811d4cf4
AZ		 110 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
111};
d4a9eb1f 112static const int tcg_target_call_oarg_regs[2] = {
811d4cf4
AZ		 113 TCG_REG_R0, TCG_REG_R1
114};
115
c69806ab
AJ		 116static inline void reloc_abs32(void *code_ptr, tcg_target_long target)
117{
118 *(uint32_t *) code_ptr = target;
119}
120
121static inline void reloc_pc24(void *code_ptr, tcg_target_long target)
122{
123 uint32_t offset = ((target - ((tcg_target_long) code_ptr + 8)) >> 2);
124
125 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & ~0xffffff)
126 | (offset & 0xffffff);
127}
128
650bbb36 129static void patch_reloc(uint8_t *code_ptr, int type,
811d4cf4
AZ		 130 tcg_target_long value, tcg_target_long addend)
131{
132 switch (type) {
133 case R_ARM_ABS32:
c69806ab 134 reloc_abs32(code_ptr, value);
811d4cf4
AZ		 135 break;
136
137 case R_ARM_CALL:
138 case R_ARM_JUMP24:
139 default:
140 tcg_abort();
141
142 case R_ARM_PC24:
c69806ab 143 reloc_pc24(code_ptr, value);
811d4cf4
AZ		 144 break;
145 }
146}
147
148/* maximum number of register used for input function arguments */
149static inline int tcg_target_get_call_iarg_regs_count(int flags)
150{
151 return 4;
152}
153
811d4cf4 154/* parse target specific constraints */
d4a9eb1f 155static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
811d4cf4
AZ		 156{
157 const char *ct_str;
158
159 ct_str = *pct_str;
160 switch (ct_str[0]) {
cb4e581f
LD		 161 case 'I':
162 ct->ct |= TCG_CT_CONST_ARM;
163 break;
164
811d4cf4 165 case 'r':
811d4cf4
AZ		 166 ct->ct |= TCG_CT_REG;
167 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
168 break;
169
67dcab73
AJ		 170 /* qemu_ld address */
171 case 'l':
811d4cf4
AZ		 172 ct->ct |= TCG_CT_REG;
173 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 174#ifdef CONFIG_SOFTMMU
175 /* r0 and r1 will be overwritten when reading the tlb entry,
176 so don't use these. */
811d4cf4
AZ		 177 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
178 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73 179#endif
811d4cf4 180 break;
67dcab73 181 case 'L':
d0660ed4
AZ		 182 ct->ct |= TCG_CT_REG;
183 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 184#ifdef CONFIG_SOFTMMU
185 /* r1 is still needed to load data_reg or data_reg2,
186 so don't use it. */
d0660ed4 187 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73 188#endif
d0660ed4
AZ		 189 break;
190
67dcab73
AJ		 191 /* qemu_st address & data_reg */
192 case 's':
811d4cf4
AZ		 193 ct->ct |= TCG_CT_REG;
194 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 195 /* r0 and r1 will be overwritten when reading the tlb entry
196 (softmmu only) and doing the byte swapping, so don't
197 use these. */
811d4cf4
AZ		 198 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
199 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4 200 break;
67dcab73
AJ		 201 /* qemu_st64 data_reg2 */
202 case 'S':
811d4cf4
AZ		 203 ct->ct |= TCG_CT_REG;
204 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 205 /* r0 and r1 will be overwritten when reading the tlb entry
206 (softmmu only) and doing the byte swapping, so don't
207 use these. */
811d4cf4 208 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
811d4cf4 209 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73
AJ		 210#ifdef CONFIG_SOFTMMU
211 /* r2 is still needed to load data_reg, so don't use it. */
212 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
811d4cf4 213#endif
67dcab73 214 break;
811d4cf4 215
811d4cf4
AZ		 216 default:
217 return -1;
218 }
219 ct_str++;
220 *pct_str = ct_str;
221
222 return 0;
223}
224
94953e6d
LD		 225static inline uint32_t rotl(uint32_t val, int n)
226{
227 return (val << n) | (val >> (32 - n));
228}
229
230/* ARM immediates for ALU instructions are made of an unsigned 8-bit
231 right-rotated by an even amount between 0 and 30. */
232static inline int encode_imm(uint32_t imm)
233{
4e6f6d4c
LD		 234 int shift;
235
94953e6d
LD		 236 /* simple case, only lower bits */
237 if ((imm & ~0xff) == 0)
238 return 0;
239 /* then try a simple even shift */
240 shift = ctz32(imm) & ~1;
241 if (((imm >> shift) & ~0xff) == 0)
242 return 32 - shift;
243 /* now try harder with rotations */
244 if ((rotl(imm, 2) & ~0xff) == 0)
245 return 2;
246 if ((rotl(imm, 4) & ~0xff) == 0)
247 return 4;
248 if ((rotl(imm, 6) & ~0xff) == 0)
249 return 6;
250 /* imm can't be encoded */
251 return -1;
252}
cb4e581f
LD		 253
254static inline int check_fit_imm(uint32_t imm)
255{
94953e6d 256 return encode_imm(imm) >= 0;
cb4e581f
LD		 257}
258
811d4cf4
AZ		 259/* Test if a constant matches the constraint.
260 * TODO: define constraints for:
261 *
262 * ldr/str offset: between -0xfff and 0xfff
263 * ldrh/strh offset: between -0xff and 0xff
264 * mov operand2: values represented with x << (2 * y), x < 0x100
265 * add, sub, eor...: ditto
266 */
267static inline int tcg_target_const_match(tcg_target_long val,
268 const TCGArgConstraint *arg_ct)
269{
270 int ct;
271 ct = arg_ct->ct;
272 if (ct & TCG_CT_CONST)
273 return 1;
cb4e581f
LD		 274 else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
275 return 1;
811d4cf4
AZ		 276 else
277 return 0;
278}
279
280enum arm_data_opc_e {
281 ARITH_AND = 0x0,
282 ARITH_EOR = 0x1,
283 ARITH_SUB = 0x2,
284 ARITH_RSB = 0x3,
285 ARITH_ADD = 0x4,
286 ARITH_ADC = 0x5,
287 ARITH_SBC = 0x6,
288 ARITH_RSC = 0x7,
3979144c 289 ARITH_TST = 0x8,
811d4cf4
AZ		 290 ARITH_CMP = 0xa,
291 ARITH_CMN = 0xb,
292 ARITH_ORR = 0xc,
293 ARITH_MOV = 0xd,
294 ARITH_BIC = 0xe,
295 ARITH_MVN = 0xf,
296};
297
3979144c
PB		 298#define TO_CPSR(opc) \
299 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
811d4cf4
AZ		 300
301#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
302#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
303#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
304#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
305#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
306#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
307#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
308#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
309
310enum arm_cond_code_e {
311 COND_EQ = 0x0,
312 COND_NE = 0x1,
313 COND_CS = 0x2, /* Unsigned greater or equal */
314 COND_CC = 0x3, /* Unsigned less than */
315 COND_MI = 0x4, /* Negative */
316 COND_PL = 0x5, /* Zero or greater */
317 COND_VS = 0x6, /* Overflow */
318 COND_VC = 0x7, /* No overflow */
319 COND_HI = 0x8, /* Unsigned greater than */
320 COND_LS = 0x9, /* Unsigned less or equal */
321 COND_GE = 0xa,
322 COND_LT = 0xb,
323 COND_GT = 0xc,
324 COND_LE = 0xd,
325 COND_AL = 0xe,
326};
327
328static const uint8_t tcg_cond_to_arm_cond[10] = {
329 [TCG_COND_EQ] = COND_EQ,
330 [TCG_COND_NE] = COND_NE,
331 [TCG_COND_LT] = COND_LT,
332 [TCG_COND_GE] = COND_GE,
333 [TCG_COND_LE] = COND_LE,
334 [TCG_COND_GT] = COND_GT,
335 /* unsigned */
336 [TCG_COND_LTU] = COND_CC,
337 [TCG_COND_GEU] = COND_CS,
338 [TCG_COND_LEU] = COND_LS,
339 [TCG_COND_GTU] = COND_HI,
340};
341
342static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
343{
344 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
345}
346
347static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
348{
349 tcg_out32(s, (cond << 28) | 0x0a000000 |
350 (((offset - 8) >> 2) & 0x00ffffff));
351}
352
e936243a
AZ		 353static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
354{
e2542fe2 355#ifdef HOST_WORDS_BIGENDIAN
e936243a
AZ		 356 tcg_out8(s, (cond << 4) | 0x0a);
357 s->code_ptr += 3;
358#else
359 s->code_ptr += 3;
360 tcg_out8(s, (cond << 4) | 0x0a);
361#endif
362}
363
811d4cf4
AZ		 364static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
365{
366 tcg_out32(s, (cond << 28) | 0x0b000000 |
367 (((offset - 8) >> 2) & 0x00ffffff));
368}
369
23401b58
AJ		 370static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
371{
372 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
373}
374
811d4cf4
AZ		 375static inline void tcg_out_dat_reg(TCGContext *s,
376 int cond, int opc, int rd, int rn, int rm, int shift)
377{
378 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
379 (rn << 16) | (rd << 12) | shift | rm);
380}
381
382static inline void tcg_out_dat_reg2(TCGContext *s,
383 int cond, int opc0, int opc1, int rd0, int rd1,
384 int rn0, int rn1, int rm0, int rm1, int shift)
385{
0c9c3a9e
AZ		 386 if (rd0 == rn1 || rd0 == rm1) {
387 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
388 (rn0 << 16) | (8 << 12) | shift | rm0);
389 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
390 (rn1 << 16) | (rd1 << 12) | shift | rm1);
391 tcg_out_dat_reg(s, cond, ARITH_MOV,
392 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
393 } else {
394 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
395 (rn0 << 16) | (rd0 << 12) | shift | rm0);
396 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
397 (rn1 << 16) | (rd1 << 12) | shift | rm1);
398 }
811d4cf4
AZ		 399}
400
401static inline void tcg_out_dat_imm(TCGContext *s,
402 int cond, int opc, int rd, int rn, int im)
403{
3979144c 404 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
811d4cf4
AZ		 405 (rn << 16) | (rd << 12) | im);
406}
407
408static inline void tcg_out_movi32(TCGContext *s,
409 int cond, int rd, int32_t arg)
410{
811d4cf4
AZ		 411 /* TODO: This is very suboptimal, we can easily have a constant
412 * pool somewhere after all the instructions. */
413
414 if (arg < 0 && arg > -0x100)
415 return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
416
ac34fb5c
AJ		 417 if (use_armv7_instructions) {
418 /* use movw/movt */
419 /* movw */
420 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
421 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
422 if (arg & 0xffff0000)
423 /* movt */
424 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
425 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
426 } else {
427 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
428 if (arg & 0x0000ff00)
429 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
430 ((arg >> 8) & 0xff) | 0xc00);
431 if (arg & 0x00ff0000)
432 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
433 ((arg >> 16) & 0xff) | 0x800);
434 if (arg & 0xff000000)
435 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
436 ((arg >> 24) & 0xff) | 0x400);
437 }
811d4cf4
AZ		 438}
439
440static inline void tcg_out_mul32(TCGContext *s,
441 int cond, int rd, int rs, int rm)
442{
443 if (rd != rm)
444 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
445 (rs << 8) | 0x90 | rm);
446 else if (rd != rs)
447 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
448 (rm << 8) | 0x90 | rs);
449 else {
450 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
451 (rs << 8) | 0x90 | rm);
452 tcg_out_dat_reg(s, cond, ARITH_MOV,
c8d80cef 453 rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 454 }
455}
456
457static inline void tcg_out_umull32(TCGContext *s,
458 int cond, int rd0, int rd1, int rs, int rm)
459{
460 if (rd0 != rm && rd1 != rm)
461 tcg_out32(s, (cond << 28) | 0x800090 |
462 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
463 else if (rd0 != rs && rd1 != rs)
464 tcg_out32(s, (cond << 28) | 0x800090 |
465 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
466 else {
467 tcg_out_dat_reg(s, cond, ARITH_MOV,
468 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
469 tcg_out32(s, (cond << 28) | 0x800098 |
470 (rd1 << 16) | (rd0 << 12) | (rs << 8));
471 }
472}
473
474static inline void tcg_out_smull32(TCGContext *s,
475 int cond, int rd0, int rd1, int rs, int rm)
476{
477 if (rd0 != rm && rd1 != rm)
478 tcg_out32(s, (cond << 28) | 0xc00090 |
479 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
480 else if (rd0 != rs && rd1 != rs)
481 tcg_out32(s, (cond << 28) | 0xc00090 |
482 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
483 else {
484 tcg_out_dat_reg(s, cond, ARITH_MOV,
485 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
486 tcg_out32(s, (cond << 28) | 0xc00098 |
487 (rd1 << 16) | (rd0 << 12) | (rs << 8));
488 }
489}
490
9517094f
AJ		 491static inline void tcg_out_ext8s(TCGContext *s, int cond,
492 int rd, int rn)
493{
494 if (use_armv6_instructions) {
495 /* sxtb */
496 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
497 } else {
e23886a9 498 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 499 rd, 0, rn, SHIFT_IMM_LSL(24));
e23886a9 500 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 501 rd, 0, rd, SHIFT_IMM_ASR(24));
502 }
503}
504
e854b6d3
AJ		 505static inline void tcg_out_ext8u(TCGContext *s, int cond,
506 int rd, int rn)
507{
508 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
509}
510
9517094f
AJ		 511static inline void tcg_out_ext16s(TCGContext *s, int cond,
512 int rd, int rn)
513{
514 if (use_armv6_instructions) {
515 /* sxth */
516 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
517 } else {
e23886a9 518 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 519 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 520 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 521 rd, 0, rd, SHIFT_IMM_ASR(16));
522 }
523}
524
525static inline void tcg_out_ext16u(TCGContext *s, int cond,
526 int rd, int rn)
527{
528 if (use_armv6_instructions) {
529 /* uxth */
530 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
531 } else {
e23886a9 532 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 533 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 534 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 535 rd, 0, rd, SHIFT_IMM_LSR(16));
536 }
537}
538
67dcab73
AJ		 539static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
540{
541 if (use_armv6_instructions) {
542 /* revsh */
543 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
544 } else {
545 tcg_out_dat_reg(s, cond, ARITH_MOV,
546 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
547 tcg_out_dat_reg(s, cond, ARITH_MOV,
548 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_ASR(16));
549 tcg_out_dat_reg(s, cond, ARITH_ORR,
550 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
551 }
552}
553
244b1e81
AJ		 554static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
555{
556 if (use_armv6_instructions) {
557 /* rev16 */
558 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
559 } else {
560 tcg_out_dat_reg(s, cond, ARITH_MOV,
561 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
562 tcg_out_dat_reg(s, cond, ARITH_MOV,
563 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
564 tcg_out_dat_reg(s, cond, ARITH_ORR,
565 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
566 }
567}
568
569static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
570{
571 if (use_armv6_instructions) {
572 /* rev */
573 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
574 } else {
575 tcg_out_dat_reg(s, cond, ARITH_EOR,
576 TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
577 tcg_out_dat_imm(s, cond, ARITH_BIC,
578 TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
579 tcg_out_dat_reg(s, cond, ARITH_MOV,
580 rd, 0, rn, SHIFT_IMM_ROR(8));
581 tcg_out_dat_reg(s, cond, ARITH_EOR,
582 rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
583 }
584}
585
811d4cf4
AZ		 586static inline void tcg_out_ld32_12(TCGContext *s, int cond,
587 int rd, int rn, tcg_target_long im)
588{
589 if (im >= 0)
590 tcg_out32(s, (cond << 28) | 0x05900000 |
591 (rn << 16) | (rd << 12) | (im & 0xfff));
592 else
593 tcg_out32(s, (cond << 28) | 0x05100000 |
594 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
595}
596
597static inline void tcg_out_st32_12(TCGContext *s, int cond,
598 int rd, int rn, tcg_target_long im)
599{
600 if (im >= 0)
601 tcg_out32(s, (cond << 28) | 0x05800000 |
602 (rn << 16) | (rd << 12) | (im & 0xfff));
603 else
604 tcg_out32(s, (cond << 28) | 0x05000000 |
605 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
606}
607
608static inline void tcg_out_ld32_r(TCGContext *s, int cond,
609 int rd, int rn, int rm)
610{
611 tcg_out32(s, (cond << 28) | 0x07900000 |
612 (rn << 16) | (rd << 12) | rm);
613}
614
615static inline void tcg_out_st32_r(TCGContext *s, int cond,
616 int rd, int rn, int rm)
617{
618 tcg_out32(s, (cond << 28) | 0x07800000 |
619 (rn << 16) | (rd << 12) | rm);
620}
621
3979144c
PB		 622/* Register pre-increment with base writeback. */
623static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
624 int rd, int rn, int rm)
625{
626 tcg_out32(s, (cond << 28) | 0x07b00000 |
627 (rn << 16) | (rd << 12) | rm);
628}
629
630static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
631 int rd, int rn, int rm)
632{
633 tcg_out32(s, (cond << 28) | 0x07a00000 |
634 (rn << 16) | (rd << 12) | rm);
635}
636
811d4cf4
AZ		 637static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
638 int rd, int rn, tcg_target_long im)
639{
640 if (im >= 0)
641 tcg_out32(s, (cond << 28) | 0x01d000b0 |
642 (rn << 16) | (rd << 12) |
643 ((im & 0xf0) << 4) | (im & 0xf));
644 else
645 tcg_out32(s, (cond << 28) | 0x015000b0 |
646 (rn << 16) | (rd << 12) |
647 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
648}
649
f694a27e 650static inline void tcg_out_st16_8(TCGContext *s, int cond,
811d4cf4
AZ		 651 int rd, int rn, tcg_target_long im)
652{
653 if (im >= 0)
654 tcg_out32(s, (cond << 28) | 0x01c000b0 |
655 (rn << 16) | (rd << 12) |
656 ((im & 0xf0) << 4) | (im & 0xf));
657 else
658 tcg_out32(s, (cond << 28) | 0x014000b0 |
659 (rn << 16) | (rd << 12) |
660 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
661}
662
663static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
664 int rd, int rn, int rm)
665{
666 tcg_out32(s, (cond << 28) | 0x019000b0 |
667 (rn << 16) | (rd << 12) | rm);
668}
669
f694a27e 670static inline void tcg_out_st16_r(TCGContext *s, int cond,
811d4cf4
AZ		 671 int rd, int rn, int rm)
672{
673 tcg_out32(s, (cond << 28) | 0x018000b0 |
674 (rn << 16) | (rd << 12) | rm);
675}
676
677static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
678 int rd, int rn, tcg_target_long im)
679{
680 if (im >= 0)
681 tcg_out32(s, (cond << 28) | 0x01d000f0 |
682 (rn << 16) | (rd << 12) |
683 ((im & 0xf0) << 4) | (im & 0xf));
684 else
685 tcg_out32(s, (cond << 28) | 0x015000f0 |
686 (rn << 16) | (rd << 12) |
687 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
688}
689
811d4cf4
AZ		 690static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
691 int rd, int rn, int rm)
692{
693 tcg_out32(s, (cond << 28) | 0x019000f0 |
694 (rn << 16) | (rd << 12) | rm);
695}
696
811d4cf4
AZ		 697static inline void tcg_out_ld8_12(TCGContext *s, int cond,
698 int rd, int rn, tcg_target_long im)
699{
700 if (im >= 0)
701 tcg_out32(s, (cond << 28) | 0x05d00000 |
702 (rn << 16) | (rd << 12) | (im & 0xfff));
703 else
704 tcg_out32(s, (cond << 28) | 0x05500000 |
705 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
706}
707
708static inline void tcg_out_st8_12(TCGContext *s, int cond,
709 int rd, int rn, tcg_target_long im)
710{
711 if (im >= 0)
712 tcg_out32(s, (cond << 28) | 0x05c00000 |
713 (rn << 16) | (rd << 12) | (im & 0xfff));
714 else
715 tcg_out32(s, (cond << 28) | 0x05400000 |
716 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
717}
718
719static inline void tcg_out_ld8_r(TCGContext *s, int cond,
720 int rd, int rn, int rm)
721{
722 tcg_out32(s, (cond << 28) | 0x07d00000 |
723 (rn << 16) | (rd << 12) | rm);
724}
725
726static inline void tcg_out_st8_r(TCGContext *s, int cond,
727 int rd, int rn, int rm)
728{
729 tcg_out32(s, (cond << 28) | 0x07c00000 |
730 (rn << 16) | (rd << 12) | rm);
731}
732
733static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
734 int rd, int rn, tcg_target_long im)
735{
736 if (im >= 0)
737 tcg_out32(s, (cond << 28) | 0x01d000d0 |
738 (rn << 16) | (rd << 12) |
739 ((im & 0xf0) << 4) | (im & 0xf));
740 else
741 tcg_out32(s, (cond << 28) | 0x015000d0 |
742 (rn << 16) | (rd << 12) |
743 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
744}
745
811d4cf4
AZ		 746static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
747 int rd, int rn, int rm)
748{
204c1674 749 tcg_out32(s, (cond << 28) | 0x019000d0 |
811d4cf4
AZ		 750 (rn << 16) | (rd << 12) | rm);
751}
752
811d4cf4
AZ		 753static inline void tcg_out_ld32u(TCGContext *s, int cond,
754 int rd, int rn, int32_t offset)
755{
756 if (offset > 0xfff || offset < -0xfff) {
757 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
758 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
759 } else
760 tcg_out_ld32_12(s, cond, rd, rn, offset);
761}
762
763static inline void tcg_out_st32(TCGContext *s, int cond,
764 int rd, int rn, int32_t offset)
765{
766 if (offset > 0xfff || offset < -0xfff) {
767 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
768 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
769 } else
770 tcg_out_st32_12(s, cond, rd, rn, offset);
771}
772
773static inline void tcg_out_ld16u(TCGContext *s, int cond,
774 int rd, int rn, int32_t offset)
775{
776 if (offset > 0xff || offset < -0xff) {
777 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
778 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
779 } else
780 tcg_out_ld16u_8(s, cond, rd, rn, offset);
781}
782
783static inline void tcg_out_ld16s(TCGContext *s, int cond,
784 int rd, int rn, int32_t offset)
785{
786 if (offset > 0xff || offset < -0xff) {
787 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
788 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
789 } else
790 tcg_out_ld16s_8(s, cond, rd, rn, offset);
791}
792
f694a27e 793static inline void tcg_out_st16(TCGContext *s, int cond,
811d4cf4
AZ		 794 int rd, int rn, int32_t offset)
795{
796 if (offset > 0xff || offset < -0xff) {
797 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
f694a27e 798 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
811d4cf4 799 } else
f694a27e 800 tcg_out_st16_8(s, cond, rd, rn, offset);
811d4cf4
AZ		 801}
802
803static inline void tcg_out_ld8u(TCGContext *s, int cond,
804 int rd, int rn, int32_t offset)
805{
806 if (offset > 0xfff || offset < -0xfff) {
807 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
808 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
809 } else
810 tcg_out_ld8_12(s, cond, rd, rn, offset);
811}
812
813static inline void tcg_out_ld8s(TCGContext *s, int cond,
814 int rd, int rn, int32_t offset)
815{
816 if (offset > 0xff || offset < -0xff) {
817 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
818 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
819 } else
820 tcg_out_ld8s_8(s, cond, rd, rn, offset);
821}
822
f694a27e 823static inline void tcg_out_st8(TCGContext *s, int cond,
811d4cf4
AZ		 824 int rd, int rn, int32_t offset)
825{
826 if (offset > 0xfff || offset < -0xfff) {
827 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
828 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
829 } else
830 tcg_out_st8_12(s, cond, rd, rn, offset);
831}
832
833static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
834{
835 int32_t val;
836
837 val = addr - (tcg_target_long) s->code_ptr;
838 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
839 tcg_out_b(s, cond, val);
840 else {
841#if 1
842 tcg_abort();
843#else
844 if (cond == COND_AL) {
c8d80cef 845 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 846 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
847 } else {
848 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
849 tcg_out_dat_reg(s, cond, ARITH_ADD,
c8d80cef
AJ		 850 TCG_REG_PC, TCG_REG_PC,
851 TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 852 }
853#endif
854 }
855}
856
857static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
858{
859 int32_t val;
860
811d4cf4
AZ		 861 val = addr - (tcg_target_long) s->code_ptr;
862 if (val < 0x01fffffd && val > -0x01fffffd)
863 tcg_out_bl(s, cond, val);
864 else {
865#if 1
866 tcg_abort();
867#else
868 if (cond == COND_AL) {
c8d80cef
AJ		 869 tcg_out_dat_imm(s, cond, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
870 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 871 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
872 } else {
873 tcg_out_movi32(s, cond, TCG_REG_R9, addr);
c8d80cef
AJ		 874 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
875 TCG_REG_PC, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 876 tcg_out_bx(s, cond, TCG_REG_R9);
877 }
878#endif
879 }
811d4cf4
AZ		 880}
881
882static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
883{
23401b58
AJ		 884 if (use_armv5_instructions) {
885 tcg_out_blx(s, cond, arg);
886 } else {
887 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
888 TCG_REG_PC, SHIFT_IMM_LSL(0));
889 tcg_out_bx(s, cond, arg);
890 }
811d4cf4
AZ		 891}
892
893static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
894{
895 TCGLabel *l = &s->labels[label_index];
896
897 if (l->has_value)
898 tcg_out_goto(s, cond, l->u.value);
899 else if (cond == COND_AL) {
c8d80cef 900 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 901 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
902 s->code_ptr += 4;
903 } else {
904 /* Probably this should be preferred even for COND_AL... */
905 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
e936243a 906 tcg_out_b_noaddr(s, cond);
811d4cf4
AZ		 907 }
908}
909
811d4cf4 910#ifdef CONFIG_SOFTMMU
79383c9c
BS		 911
912#include "../../softmmu_defs.h"
811d4cf4
AZ		 913
914static void *qemu_ld_helpers[4] = {
915 __ldb_mmu,
916 __ldw_mmu,
917 __ldl_mmu,
918 __ldq_mmu,
919};
920
921static void *qemu_st_helpers[4] = {
922 __stb_mmu,
923 __stw_mmu,
924 __stl_mmu,
925 __stq_mmu,
926};
927#endif
928
3979144c
PB		 929#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
930
7e0d9562 931static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
811d4cf4 932{
67dcab73 933 int addr_reg, data_reg, data_reg2, bswap;
811d4cf4
AZ		 934#ifdef CONFIG_SOFTMMU
935 int mem_index, s_bits;
936# if TARGET_LONG_BITS == 64
937 int addr_reg2;
938# endif
811d4cf4 939 uint32_t *label_ptr;
811d4cf4
AZ		 940#endif
941
67dcab73
AJ		 942#ifdef TARGET_WORDS_BIGENDIAN
943 bswap = 1;
944#else
945 bswap = 0;
946#endif
811d4cf4
AZ		 947 data_reg = *args++;
948 if (opc == 3)
949 data_reg2 = *args++;
950 else
d89c682f 951 data_reg2 = 0; /* suppress warning */
811d4cf4 952 addr_reg = *args++;
811d4cf4 953#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 954# if TARGET_LONG_BITS == 64
955 addr_reg2 = *args++;
956# endif
811d4cf4
AZ		 957 mem_index = *args;
958 s_bits = opc & 3;
959
91a3c1b0 960 /* Should generate something like the following:
3979144c 961 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 962 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 963 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0
AZ		 964 */
965# if CPU_TLB_BITS > 8
966# error
967# endif
c8d80cef
AJ		 968 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8,
969 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 970 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 971 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
972 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
973 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 974 /* In the
975 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
976 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
977 * not exceed otherwise, so use an
978 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
979 * before.
980 */
225b4376 981 if (mem_index)
c8d80cef 982 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 983 (mem_index << (TLB_SHIFT & 1)) |
984 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 985 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
225b4376 986 offsetof(CPUState, tlb_table[0][0].addr_read));
c8d80cef
AJ		 987 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
988 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 989 /* Check alignment. */
990 if (s_bits)
991 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
992 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 993# if TARGET_LONG_BITS == 64
994 /* XXX: possibly we could use a block data load or writeback in
995 * the first access. */
c8d80cef 996 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 997 offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
c8d80cef
AJ		 998 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
999 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1000# endif
c8d80cef 1001 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 1002 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 1003
1004 switch (opc) {
1005 case 0:
c8d80cef 1006 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1007 break;
1008 case 0 | 4:
c8d80cef 1009 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1010 break;
1011 case 1:
c8d80cef 1012 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
67dcab73
AJ		 1013 if (bswap) {
1014 tcg_out_bswap16(s, COND_EQ, data_reg, data_reg);
1015 }
811d4cf4
AZ		 1016 break;
1017 case 1 | 4:
67dcab73
AJ		 1018 if (bswap) {
1019 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1020 tcg_out_bswap16s(s, COND_EQ, data_reg, data_reg);
1021 } else {
1022 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1023 }
811d4cf4
AZ		 1024 break;
1025 case 2:
1026 default:
c8d80cef 1027 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
67dcab73
AJ		 1028 if (bswap) {
1029 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1030 }
811d4cf4
AZ		 1031 break;
1032 case 3:
67dcab73
AJ		 1033 if (bswap) {
1034 tcg_out_ld32_rwb(s, COND_EQ, data_reg2, TCG_REG_R1, addr_reg);
1035 tcg_out_ld32_12(s, COND_EQ, data_reg, TCG_REG_R1, 4);
1036 tcg_out_bswap32(s, COND_EQ, data_reg2, data_reg2);
1037 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1038 } else {
1039 tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1040 tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1041 }
811d4cf4
AZ		 1042 break;
1043 }
1044
1045 label_ptr = (void *) s->code_ptr;
c69806ab 1046 tcg_out_b_noaddr(s, COND_EQ);
811d4cf4 1047
811d4cf4 1048 /* TODO: move this code to where the constants pool will be */
c8d80cef 1049 if (addr_reg != TCG_REG_R0) {
7e0d9562 1050 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1051 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1052 }
811d4cf4 1053# if TARGET_LONG_BITS == 32
7e0d9562 1054 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R1, 0, mem_index);
811d4cf4 1055# else
2633a2d0
AJ		 1056 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1057 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
7e0d9562 1058 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4 1059# endif
7e0d9562 1060 tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_ld_helpers[s_bits] -
811d4cf4
AZ		 1061 (tcg_target_long) s->code_ptr);
1062
1063 switch (opc) {
1064 case 0 | 4:
e854b6d3 1065 tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ		 1066 break;
1067 case 1 | 4:
e854b6d3 1068 tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ		 1069 break;
1070 case 0:
1071 case 1:
1072 case 2:
1073 default:
c8d80cef 1074 if (data_reg != TCG_REG_R0) {
7e0d9562 1075 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1076 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1077 }
811d4cf4
AZ		 1078 break;
1079 case 3:
c8d80cef 1080 if (data_reg != TCG_REG_R0) {
7e0d9562 1081 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1082 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1083 }
1084 if (data_reg2 != TCG_REG_R1) {
7e0d9562 1085 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1086 data_reg2, 0, TCG_REG_R1, SHIFT_IMM_LSL(0));
1087 }
811d4cf4
AZ		 1088 break;
1089 }
1090
c69806ab 1091 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
379f6698
PB		 1092#else /* !CONFIG_SOFTMMU */
1093 if (GUEST_BASE) {
1094 uint32_t offset = GUEST_BASE;
1095 int i;
1096 int rot;
1097
1098 while (offset) {
1099 i = ctz32(offset) & ~1;
1100 rot = ((32 - i) << 7) & 0xf00;
1101
c8d80cef 1102 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
379f6698 1103 ((offset >> i) & 0xff) | rot);
c8d80cef 1104 addr_reg = TCG_REG_R8;
379f6698
PB		 1105 offset &= ~(0xff << i);
1106 }
1107 }
811d4cf4
AZ		 1108 switch (opc) {
1109 case 0:
1110 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
1111 break;
1112 case 0 | 4:
1113 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1114 break;
1115 case 1:
1116 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
67dcab73
AJ		 1117 if (bswap) {
1118 tcg_out_bswap16(s, COND_AL, data_reg, data_reg);
1119 }
811d4cf4
AZ		 1120 break;
1121 case 1 | 4:
67dcab73
AJ		 1122 if (bswap) {
1123 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1124 tcg_out_bswap16s(s, COND_AL, data_reg, data_reg);
1125 } else {
1126 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1127 }
811d4cf4
AZ		 1128 break;
1129 case 2:
1130 default:
1131 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
67dcab73
AJ		 1132 if (bswap) {
1133 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1134 }
811d4cf4
AZ		 1135 break;
1136 case 3:
eae6ce52
AZ		 1137 /* TODO: use block load -
1138 * check that data_reg2 > data_reg or the other way */
419bafa5 1139 if (data_reg == addr_reg) {
67dcab73
AJ		 1140 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1141 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
419bafa5 1142 } else {
67dcab73
AJ		 1143 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
1144 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1145 }
1146 if (bswap) {
1147 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1148 tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2);
419bafa5 1149 }
811d4cf4
AZ		 1150 break;
1151 }
1152#endif
1153}
1154
7e0d9562 1155static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
811d4cf4 1156{
67dcab73 1157 int addr_reg, data_reg, data_reg2, bswap;
811d4cf4
AZ		 1158#ifdef CONFIG_SOFTMMU
1159 int mem_index, s_bits;
1160# if TARGET_LONG_BITS == 64
1161 int addr_reg2;
1162# endif
811d4cf4 1163 uint32_t *label_ptr;
811d4cf4
AZ		 1164#endif
1165
67dcab73
AJ		 1166#ifdef TARGET_WORDS_BIGENDIAN
1167 bswap = 1;
1168#else
1169 bswap = 0;
1170#endif
811d4cf4
AZ		 1171 data_reg = *args++;
1172 if (opc == 3)
1173 data_reg2 = *args++;
1174 else
d89c682f 1175 data_reg2 = 0; /* suppress warning */
811d4cf4 1176 addr_reg = *args++;
811d4cf4 1177#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 1178# if TARGET_LONG_BITS == 64
1179 addr_reg2 = *args++;
1180# endif
811d4cf4
AZ		 1181 mem_index = *args;
1182 s_bits = opc & 3;
1183
91a3c1b0 1184 /* Should generate something like the following:
3979144c 1185 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1186 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1187 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0 1188 */
811d4cf4 1189 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1190 TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 1191 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 1192 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1193 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
1194 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 1195 /* In the
1196 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1197 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1198 * not exceed otherwise, so use an
1199 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1200 * before.
1201 */
225b4376 1202 if (mem_index)
c8d80cef 1203 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 1204 (mem_index << (TLB_SHIFT & 1)) |
1205 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 1206 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
225b4376 1207 offsetof(CPUState, tlb_table[0][0].addr_write));
c8d80cef
AJ		 1208 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1209 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 1210 /* Check alignment. */
1211 if (s_bits)
1212 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1213 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 1214# if TARGET_LONG_BITS == 64
1215 /* XXX: possibly we could use a block data load or writeback in
1216 * the first access. */
c8d80cef
AJ		 1217 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1218 offsetof(CPUState, tlb_table[0][0].addr_write) + 4);
1219 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1220 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1221# endif
c8d80cef 1222 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 1223 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 1224
1225 switch (opc) {
1226 case 0:
c8d80cef 1227 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4 1228 break;
811d4cf4 1229 case 1:
67dcab73
AJ		 1230 if (bswap) {
1231 tcg_out_bswap16(s, COND_EQ, TCG_REG_R0, data_reg);
1232 tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1233 } else {
1234 tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1235 }
811d4cf4
AZ		 1236 break;
1237 case 2:
1238 default:
67dcab73
AJ		 1239 if (bswap) {
1240 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
1241 tcg_out_st32_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1242 } else {
1243 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1244 }
811d4cf4
AZ		 1245 break;
1246 case 3:
67dcab73
AJ		 1247 if (bswap) {
1248 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2);
1249 tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, addr_reg);
1250 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
1251 tcg_out_st32_12(s, COND_EQ, data_reg, TCG_REG_R1, 4);
1252 } else {
1253 tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1254 tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1255 }
811d4cf4
AZ		 1256 break;
1257 }
1258
1259 label_ptr = (void *) s->code_ptr;
c69806ab 1260 tcg_out_b_noaddr(s, COND_EQ);
811d4cf4 1261
811d4cf4 1262 /* TODO: move this code to where the constants pool will be */
2633a2d0
AJ		 1263 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1264 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1265# if TARGET_LONG_BITS == 32
1266 switch (opc) {
1267 case 0:
e854b6d3 1268 tcg_out_ext8u(s, COND_AL, TCG_REG_R1, data_reg);
7e0d9562 1269 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1270 break;
1271 case 1:
e854b6d3 1272 tcg_out_ext16u(s, COND_AL, TCG_REG_R1, data_reg);
7e0d9562 1273 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1274 break;
1275 case 2:
2633a2d0
AJ		 1276 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1277 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
7e0d9562 1278 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1279 break;
1280 case 3:
bf5675ef
AJ		 1281 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R8, 0, mem_index);
1282 tcg_out32(s, (COND_AL << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1283 if (data_reg != TCG_REG_R2) {
7e0d9562 1284 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
bf5675ef
AJ		 1285 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1286 }
1287 if (data_reg2 != TCG_REG_R3) {
1288 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1289 TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
c8d80cef 1290 }
811d4cf4
AZ		 1291 break;
1292 }
1293# else
2633a2d0
AJ		 1294 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1295 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1296 switch (opc) {
1297 case 0:
e854b6d3 1298 tcg_out_ext8u(s, COND_AL, TCG_REG_R2, data_reg);
7e0d9562 1299 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1300 break;
1301 case 1:
e854b6d3 1302 tcg_out_ext16u(s, COND_AL, TCG_REG_R2, data_reg);
7e0d9562 1303 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1304 break;
1305 case 2:
c8d80cef 1306 if (data_reg != TCG_REG_R2) {
7e0d9562 1307 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1308 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1309 }
7e0d9562 1310 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1311 break;
1312 case 3:
7e0d9562
AJ		 1313 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R8, 0, mem_index);
1314 tcg_out32(s, (COND_AL << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
c8d80cef 1315 if (data_reg != TCG_REG_R2) {
7e0d9562 1316 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1317 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1318 }
1319 if (data_reg2 != TCG_REG_R3) {
7e0d9562 1320 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1321 TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
1322 }
811d4cf4
AZ		 1323 break;
1324 }
1325# endif
1326
7e0d9562 1327 tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_st_helpers[s_bits] -
811d4cf4 1328 (tcg_target_long) s->code_ptr);
811d4cf4 1329 if (opc == 3)
7e0d9562 1330 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10);
811d4cf4 1331
c69806ab 1332 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
379f6698
PB		 1333#else /* !CONFIG_SOFTMMU */
1334 if (GUEST_BASE) {
1335 uint32_t offset = GUEST_BASE;
1336 int i;
1337 int rot;
1338
1339 while (offset) {
1340 i = ctz32(offset) & ~1;
1341 rot = ((32 - i) << 7) & 0xf00;
1342
67dcab73 1343 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R1, addr_reg,
379f6698 1344 ((offset >> i) & 0xff) | rot);
67dcab73 1345 addr_reg = TCG_REG_R1;
379f6698
PB		 1346 offset &= ~(0xff << i);
1347 }
1348 }
811d4cf4
AZ		 1349 switch (opc) {
1350 case 0:
1351 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1352 break;
811d4cf4 1353 case 1:
67dcab73
AJ		 1354 if (bswap) {
1355 tcg_out_bswap16(s, COND_AL, TCG_REG_R0, data_reg);
1356 tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1357 } else {
1358 tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
1359 }
811d4cf4
AZ		 1360 break;
1361 case 2:
1362 default:
67dcab73
AJ		 1363 if (bswap) {
1364 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1365 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1366 } else {
1367 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1368 }
811d4cf4
AZ		 1369 break;
1370 case 3:
eae6ce52
AZ		 1371 /* TODO: use block store -
1372 * check that data_reg2 > data_reg or the other way */
67dcab73
AJ		 1373 if (bswap) {
1374 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2);
1375 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1376 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1377 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 4);
1378 } else {
1379 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1380 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1381 }
811d4cf4
AZ		 1382 break;
1383 }
1384#endif
1385}
1386
811d4cf4
AZ		 1387static uint8_t *tb_ret_addr;
1388
a9751609 1389static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
811d4cf4
AZ		 1390 const TCGArg *args, const int *const_args)
1391{
1392 int c;
1393
1394 switch (opc) {
1395 case INDEX_op_exit_tb:
fe33867b
AZ		 1396 {
1397 uint8_t *ld_ptr = s->code_ptr;
1398 if (args[0] >> 8)
c8d80cef 1399 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
fe33867b 1400 else
c8d80cef 1401 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
fe33867b
AZ		 1402 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1403 if (args[0] >> 8) {
1404 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1405 tcg_out32(s, args[0]);
1406 }
1407 }
811d4cf4
AZ		 1408 break;
1409 case INDEX_op_goto_tb:
1410 if (s->tb_jmp_offset) {
1411 /* Direct jump method */
fe33867b 1412#if defined(USE_DIRECT_JUMP)
811d4cf4 1413 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
c69806ab 1414 tcg_out_b_noaddr(s, COND_AL);
811d4cf4 1415#else
c8d80cef 1416 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 1417 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1418 tcg_out32(s, 0);
1419#endif
1420 } else {
1421 /* Indirect jump method */
1422#if 1
1423 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1424 if (c > 0xfff || c < -0xfff) {
1425 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1426 (tcg_target_long) (s->tb_next + args[0]));
c8d80cef 1427 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4 1428 } else
c8d80cef 1429 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c);
811d4cf4 1430#else
c8d80cef
AJ		 1431 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1432 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4
AZ		 1433 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1434#endif
1435 }
1436 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1437 break;
1438 case INDEX_op_call:
1439 if (const_args[0])
1440 tcg_out_call(s, COND_AL, args[0]);
1441 else
1442 tcg_out_callr(s, COND_AL, args[0]);
1443 break;
1444 case INDEX_op_jmp:
1445 if (const_args[0])
1446 tcg_out_goto(s, COND_AL, args[0]);
1447 else
1448 tcg_out_bx(s, COND_AL, args[0]);
1449 break;
1450 case INDEX_op_br:
1451 tcg_out_goto_label(s, COND_AL, args[0]);
1452 break;
1453
1454 case INDEX_op_ld8u_i32:
1455 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1456 break;
1457 case INDEX_op_ld8s_i32:
1458 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1459 break;
1460 case INDEX_op_ld16u_i32:
1461 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1462 break;
1463 case INDEX_op_ld16s_i32:
1464 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1465 break;
1466 case INDEX_op_ld_i32:
1467 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1468 break;
1469 case INDEX_op_st8_i32:
f694a27e 1470 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1471 break;
1472 case INDEX_op_st16_i32:
f694a27e 1473 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1474 break;
1475 case INDEX_op_st_i32:
1476 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1477 break;
1478
1479 case INDEX_op_mov_i32:
1480 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1481 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1482 break;
1483 case INDEX_op_movi_i32:
1484 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1485 break;
1486 case INDEX_op_add_i32:
1487 c = ARITH_ADD;
1488 goto gen_arith;
1489 case INDEX_op_sub_i32:
1490 c = ARITH_SUB;
1491 goto gen_arith;
1492 case INDEX_op_and_i32:
1493 c = ARITH_AND;
1494 goto gen_arith;
932234f6
AJ		 1495 case INDEX_op_andc_i32:
1496 c = ARITH_BIC;
1497 goto gen_arith;
811d4cf4
AZ		 1498 case INDEX_op_or_i32:
1499 c = ARITH_ORR;
1500 goto gen_arith;
1501 case INDEX_op_xor_i32:
1502 c = ARITH_EOR;
1503 /* Fall through. */
1504 gen_arith:
94953e6d
LD		 1505 if (const_args[2]) {
1506 int rot;
1507 rot = encode_imm(args[2]);
cb4e581f 1508 tcg_out_dat_imm(s, COND_AL, c,
94953e6d
LD		 1509 args[0], args[1], rotl(args[2], rot) | (rot << 7));
1510 } else
cb4e581f
LD		 1511 tcg_out_dat_reg(s, COND_AL, c,
1512 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1513 break;
1514 case INDEX_op_add2_i32:
1515 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1516 args[0], args[1], args[2], args[3],
1517 args[4], args[5], SHIFT_IMM_LSL(0));
1518 break;
1519 case INDEX_op_sub2_i32:
1520 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1521 args[0], args[1], args[2], args[3],
1522 args[4], args[5], SHIFT_IMM_LSL(0));
1523 break;
650bbb36
AZ		 1524 case INDEX_op_neg_i32:
1525 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1526 break;
f878d2d2
LD		 1527 case INDEX_op_not_i32:
1528 tcg_out_dat_reg(s, COND_AL,
1529 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1530 break;
811d4cf4
AZ		 1531 case INDEX_op_mul_i32:
1532 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1533 break;
1534 case INDEX_op_mulu2_i32:
1535 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1536 break;
811d4cf4
AZ		 1537 /* XXX: Perhaps args[2] & 0x1f is wrong */
1538 case INDEX_op_shl_i32:
1539 c = const_args[2] ?
1540 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1541 goto gen_shift32;
1542 case INDEX_op_shr_i32:
1543 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1544 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1545 goto gen_shift32;
1546 case INDEX_op_sar_i32:
1547 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1548 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
293579e5
AJ		 1549 goto gen_shift32;
1550 case INDEX_op_rotr_i32:
1551 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1552 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
811d4cf4
AZ		 1553 /* Fall through. */
1554 gen_shift32:
1555 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1556 break;
1557
293579e5
AJ		 1558 case INDEX_op_rotl_i32:
1559 if (const_args[2]) {
1560 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1561 ((0x20 - args[2]) & 0x1f) ?
1562 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1563 SHIFT_IMM_LSL(0));
1564 } else {
1565 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
1566 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1567 SHIFT_REG_ROR(TCG_REG_R8));
1568 }
1569 break;
1570
811d4cf4 1571 case INDEX_op_brcond_i32:
023e77f8
AJ		 1572 if (const_args[1]) {
1573 int rot;
1574 rot = encode_imm(args[1]);
c8d80cef
AJ		 1575 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1576 args[0], rotl(args[1], rot) | (rot << 7));
023e77f8
AJ		 1577 } else {
1578 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1579 args[0], args[1], SHIFT_IMM_LSL(0));
1580 }
811d4cf4
AZ		 1581 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1582 break;
1583 case INDEX_op_brcond2_i32:
1584 /* The resulting conditions are:
1585 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1586 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1587 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1588 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1589 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1590 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1591 */
1592 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1593 args[1], args[3], SHIFT_IMM_LSL(0));
1594 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1595 args[0], args[2], SHIFT_IMM_LSL(0));
1596 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1597 break;
f72a6cd7 1598 case INDEX_op_setcond_i32:
023e77f8
AJ		 1599 if (const_args[2]) {
1600 int rot;
1601 rot = encode_imm(args[2]);
c8d80cef
AJ		 1602 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1603 args[1], rotl(args[2], rot) | (rot << 7));
023e77f8
AJ		 1604 } else {
1605 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1606 args[1], args[2], SHIFT_IMM_LSL(0));
1607 }
f72a6cd7
AJ		 1608 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1609 ARITH_MOV, args[0], 0, 1);
1610 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1611 ARITH_MOV, args[0], 0, 0);
1612 break;
e0404769
AJ		 1613 case INDEX_op_setcond2_i32:
1614 /* See brcond2_i32 comment */
1615 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1616 args[2], args[4], SHIFT_IMM_LSL(0));
1617 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1618 args[1], args[3], SHIFT_IMM_LSL(0));
1619 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1620 ARITH_MOV, args[0], 0, 1);
1621 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1622 ARITH_MOV, args[0], 0, 0);
b525f0a9 1623 break;
811d4cf4
AZ		 1624
1625 case INDEX_op_qemu_ld8u:
7e0d9562 1626 tcg_out_qemu_ld(s, args, 0);
811d4cf4
AZ		 1627 break;
1628 case INDEX_op_qemu_ld8s:
7e0d9562 1629 tcg_out_qemu_ld(s, args, 0 | 4);
811d4cf4
AZ		 1630 break;
1631 case INDEX_op_qemu_ld16u:
7e0d9562 1632 tcg_out_qemu_ld(s, args, 1);
811d4cf4
AZ		 1633 break;
1634 case INDEX_op_qemu_ld16s:
7e0d9562 1635 tcg_out_qemu_ld(s, args, 1 | 4);
811d4cf4 1636 break;
86feb1c8 1637 case INDEX_op_qemu_ld32:
7e0d9562 1638 tcg_out_qemu_ld(s, args, 2);
811d4cf4
AZ		 1639 break;
1640 case INDEX_op_qemu_ld64:
7e0d9562 1641 tcg_out_qemu_ld(s, args, 3);
811d4cf4 1642 break;
650bbb36 1643
811d4cf4 1644 case INDEX_op_qemu_st8:
7e0d9562 1645 tcg_out_qemu_st(s, args, 0);
811d4cf4
AZ		 1646 break;
1647 case INDEX_op_qemu_st16:
7e0d9562 1648 tcg_out_qemu_st(s, args, 1);
811d4cf4
AZ		 1649 break;
1650 case INDEX_op_qemu_st32:
7e0d9562 1651 tcg_out_qemu_st(s, args, 2);
811d4cf4
AZ		 1652 break;
1653 case INDEX_op_qemu_st64:
7e0d9562 1654 tcg_out_qemu_st(s, args, 3);
811d4cf4
AZ		 1655 break;
1656
244b1e81
AJ		 1657 case INDEX_op_bswap16_i32:
1658 tcg_out_bswap16(s, COND_AL, args[0], args[1]);
1659 break;
1660 case INDEX_op_bswap32_i32:
1661 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
1662 break;
1663
811d4cf4 1664 case INDEX_op_ext8s_i32:
9517094f 1665 tcg_out_ext8s(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1666 break;
1667 case INDEX_op_ext16s_i32:
9517094f
AJ		 1668 tcg_out_ext16s(s, COND_AL, args[0], args[1]);
1669 break;
1670 case INDEX_op_ext16u_i32:
1671 tcg_out_ext16u(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1672 break;
1673
1674 default:
1675 tcg_abort();
1676 }
1677}
1678
1679static const TCGTargetOpDef arm_op_defs[] = {
1680 { INDEX_op_exit_tb, { } },
1681 { INDEX_op_goto_tb, { } },
1682 { INDEX_op_call, { "ri" } },
1683 { INDEX_op_jmp, { "ri" } },
1684 { INDEX_op_br, { } },
1685
1686 { INDEX_op_mov_i32, { "r", "r" } },
1687 { INDEX_op_movi_i32, { "r" } },
1688
1689 { INDEX_op_ld8u_i32, { "r", "r" } },
1690 { INDEX_op_ld8s_i32, { "r", "r" } },
1691 { INDEX_op_ld16u_i32, { "r", "r" } },
1692 { INDEX_op_ld16s_i32, { "r", "r" } },
1693 { INDEX_op_ld_i32, { "r", "r" } },
1694 { INDEX_op_st8_i32, { "r", "r" } },
1695 { INDEX_op_st16_i32, { "r", "r" } },
1696 { INDEX_op_st_i32, { "r", "r" } },
1697
1698 /* TODO: "r", "r", "ri" */
cb4e581f
LD		 1699 { INDEX_op_add_i32, { "r", "r", "rI" } },
1700 { INDEX_op_sub_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1701 { INDEX_op_mul_i32, { "r", "r", "r" } },
1702 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
cb4e581f 1703 { INDEX_op_and_i32, { "r", "r", "rI" } },
932234f6 1704 { INDEX_op_andc_i32, { "r", "r", "rI" } },
cb4e581f
LD		 1705 { INDEX_op_or_i32, { "r", "r", "rI" } },
1706 { INDEX_op_xor_i32, { "r", "r", "rI" } },
650bbb36 1707 { INDEX_op_neg_i32, { "r", "r" } },
f878d2d2 1708 { INDEX_op_not_i32, { "r", "r" } },
811d4cf4
AZ		 1709
1710 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1711 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1712 { INDEX_op_sar_i32, { "r", "r", "ri" } },
293579e5
AJ		 1713 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1714 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
811d4cf4 1715
023e77f8
AJ		 1716 { INDEX_op_brcond_i32, { "r", "rI" } },
1717 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1718
1719 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1720 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1721 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1722 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
e0404769 1723 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
811d4cf4 1724
26c5d372 1725#if TARGET_LONG_BITS == 32
67dcab73
AJ		 1726 { INDEX_op_qemu_ld8u, { "r", "l" } },
1727 { INDEX_op_qemu_ld8s, { "r", "l" } },
1728 { INDEX_op_qemu_ld16u, { "r", "l" } },
1729 { INDEX_op_qemu_ld16s, { "r", "l" } },
1730 { INDEX_op_qemu_ld32, { "r", "l" } },
1731 { INDEX_op_qemu_ld64, { "L", "L", "l" } },
1732
1733 { INDEX_op_qemu_st8, { "s", "s" } },
1734 { INDEX_op_qemu_st16, { "s", "s" } },
1735 { INDEX_op_qemu_st32, { "s", "s" } },
bf5675ef 1736 { INDEX_op_qemu_st64, { "S", "S", "s" } },
26c5d372 1737#else
67dcab73
AJ		 1738 { INDEX_op_qemu_ld8u, { "r", "l", "l" } },
1739 { INDEX_op_qemu_ld8s, { "r", "l", "l" } },
1740 { INDEX_op_qemu_ld16u, { "r", "l", "l" } },
1741 { INDEX_op_qemu_ld16s, { "r", "l", "l" } },
1742 { INDEX_op_qemu_ld32, { "r", "l", "l" } },
1743 { INDEX_op_qemu_ld64, { "L", "L", "l", "l" } },
1744
1745 { INDEX_op_qemu_st8, { "s", "s", "s" } },
1746 { INDEX_op_qemu_st16, { "s", "s", "s" } },
1747 { INDEX_op_qemu_st32, { "s", "s", "s" } },
bf5675ef 1748 { INDEX_op_qemu_st64, { "S", "S", "s", "s" } },
26c5d372 1749#endif
811d4cf4 1750
244b1e81
AJ		 1751 { INDEX_op_bswap16_i32, { "r", "r" } },
1752 { INDEX_op_bswap32_i32, { "r", "r" } },
1753
811d4cf4
AZ		 1754 { INDEX_op_ext8s_i32, { "r", "r" } },
1755 { INDEX_op_ext16s_i32, { "r", "r" } },
9517094f 1756 { INDEX_op_ext16u_i32, { "r", "r" } },
811d4cf4
AZ		 1757
1758 { -1 },
1759};
1760
e4d58b41 1761static void tcg_target_init(TCGContext *s)
811d4cf4 1762{
20cb400d 1763#if !defined(CONFIG_USER_ONLY)
811d4cf4
AZ		 1764 /* fail safe */
1765 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1766 tcg_abort();
20cb400d 1767#endif
811d4cf4 1768
e4a7d5e8 1769 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
811d4cf4 1770 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
e4a7d5e8
AJ		 1771 (1 << TCG_REG_R0) |
1772 (1 << TCG_REG_R1) |
1773 (1 << TCG_REG_R2) |
1774 (1 << TCG_REG_R3) |
1775 (1 << TCG_REG_R12) |
1776 (1 << TCG_REG_R14));
811d4cf4
AZ		 1777
1778 tcg_regset_clear(s->reserved_regs);
811d4cf4
AZ		 1779 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1780 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
e4a7d5e8 1781 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
811d4cf4
AZ		 1782
1783 tcg_add_target_add_op_defs(arm_op_defs);
1784}
1785
1786static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1787 int arg1, tcg_target_long arg2)
1788{
1789 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1790}
1791
1792static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1793 int arg1, tcg_target_long arg2)
1794{
1795 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1796}
1797
2d69f359 1798static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
811d4cf4
AZ		 1799{
1800 if (val > 0)
1801 if (val < 0x100)
1802 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1803 else
1804 tcg_abort();
1805 else if (val < 0) {
1806 if (val > -0x100)
1807 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1808 else
1809 tcg_abort();
1810 }
1811}
1812
3b6dac34 1813static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
811d4cf4
AZ		 1814{
1815 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1816}
1817
1818static inline void tcg_out_movi(TCGContext *s, TCGType type,
1819 int ret, tcg_target_long arg)
1820{
1821 tcg_out_movi32(s, COND_AL, ret, arg);
1822}
1823
e4d58b41 1824static void tcg_target_qemu_prologue(TCGContext *s)
811d4cf4 1825{
9e97d8e9
AJ		 1826 /* There is no need to save r7, it is used to store the address
1827 of the env structure and is not modified by GCC. */
4e17eae9 1828
9e97d8e9
AJ		 1829 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1830 tcg_out32(s, (COND_AL << 28) | 0x092d4f70);
811d4cf4
AZ		 1831
1832 tcg_out_bx(s, COND_AL, TCG_REG_R0);
1833 tb_ret_addr = s->code_ptr;
1834
9e97d8e9
AJ		 1835 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1836 tcg_out32(s, (COND_AL << 28) | 0x08bd8f70);
811d4cf4 1837}
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