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Swithc some MIPS CP0 accesses to TCG.
[mirror_qemu.git] / tcg / arm / tcg-target.c
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811d4cf4
AZ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
25 "%r0",
26 "%r1",
27 "%r2",
28 "%r3",
29 "%r4",
30 "%r5",
31 "%r6",
32 "%r7",
33 "%r8",
34 "%r9",
35 "%r10",
36 "%r11",
37 "%r12",
38 "%r13",
39 "%r14",
40};
41
42int tcg_target_reg_alloc_order[] = {
43 TCG_REG_R0,
44 TCG_REG_R1,
45 TCG_REG_R2,
46 TCG_REG_R3,
47 TCG_REG_R4,
48 TCG_REG_R5,
49 TCG_REG_R6,
50 TCG_REG_R7,
51 TCG_REG_R8,
52 TCG_REG_R9,
53 TCG_REG_R10,
54 TCG_REG_R11,
55 TCG_REG_R12,
56 TCG_REG_R13,
57 TCG_REG_R14,
58};
59
60const int tcg_target_call_iarg_regs[4] = {
61 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
62};
63const int tcg_target_call_oarg_regs[2] = {
64 TCG_REG_R0, TCG_REG_R1
65};
66
650bbb36 67static void patch_reloc(uint8_t *code_ptr, int type,
811d4cf4
AZ		 68 tcg_target_long value, tcg_target_long addend)
69{
70 switch (type) {
71 case R_ARM_ABS32:
72 *(uint32_t *) code_ptr = value;
73 break;
74
75 case R_ARM_CALL:
76 case R_ARM_JUMP24:
77 default:
78 tcg_abort();
79
80 case R_ARM_PC24:
81 *(uint32_t *) code_ptr |=
82 ((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff;
83 break;
84 }
85}
86
87/* maximum number of register used for input function arguments */
88static inline int tcg_target_get_call_iarg_regs_count(int flags)
89{
90 return 4;
91}
92
93#define USE_TLB
94
95/* parse target specific constraints */
96int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
97{
98 const char *ct_str;
99
100 ct_str = *pct_str;
101 switch (ct_str[0]) {
102 case 'r':
103#ifndef CONFIG_SOFTMMU
104 case 'd':
105 case 'D':
106 case 'x':
107 case 'X':
108#endif
109 ct->ct |= TCG_CT_REG;
110 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
111 break;
112
113#ifdef CONFIG_SOFTMMU
114 /* qemu_ld/st inputs (unless 'd', 'D' or 'X') */
115 case 'x':
116 ct->ct |= TCG_CT_REG;
117 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
118# ifdef USE_TLB
119 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
120 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
121# endif
122 break;
123
124 /* qemu_ld/st data_reg */
125 case 'd':
126 ct->ct |= TCG_CT_REG;
127 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
128 /* r0 and optionally r1 will be overwritten by the address
129 * so don't use these. */
130 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
131# if TARGET_LONG_BITS == 64 || defined(USE_TLB)
132 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
133# endif
134 break;
135
136 /* qemu_ld/st64 data_reg2 */
137 case 'D':
138 ct->ct |= TCG_CT_REG;
139 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
140 /* r0, r1 and optionally r2 will be overwritten by the address
141 * and the low word of data, so don't use these. */
142 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
143 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
144# if TARGET_LONG_BITS == 64
145 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
146# endif
147 break;
148
149# if TARGET_LONG_BITS == 64
150 /* qemu_ld/st addr_reg2 */
151 case 'X':
152 ct->ct |= TCG_CT_REG;
153 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
154 /* r0 will be overwritten by the low word of base, so don't use it. */
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
156# ifdef USE_TLB
157 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
158# endif
159 break;
160# endif
161#endif
162
163 case '1':
164 ct->ct |= TCG_CT_REG;
165 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
166 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
167 break;
168
169 case '2':
170 ct->ct |= TCG_CT_REG;
171 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
172 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
173 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
174 break;
175
176 default:
177 return -1;
178 }
179 ct_str++;
180 *pct_str = ct_str;
181
182 return 0;
183}
184
185/* Test if a constant matches the constraint.
186 * TODO: define constraints for:
187 *
188 * ldr/str offset: between -0xfff and 0xfff
189 * ldrh/strh offset: between -0xff and 0xff
190 * mov operand2: values represented with x << (2 * y), x < 0x100
191 * add, sub, eor...: ditto
192 */
193static inline int tcg_target_const_match(tcg_target_long val,
194 const TCGArgConstraint *arg_ct)
195{
196 int ct;
197 ct = arg_ct->ct;
198 if (ct & TCG_CT_CONST)
199 return 1;
200 else
201 return 0;
202}
203
204enum arm_data_opc_e {
205 ARITH_AND = 0x0,
206 ARITH_EOR = 0x1,
207 ARITH_SUB = 0x2,
208 ARITH_RSB = 0x3,
209 ARITH_ADD = 0x4,
210 ARITH_ADC = 0x5,
211 ARITH_SBC = 0x6,
212 ARITH_RSC = 0x7,
213 ARITH_CMP = 0xa,
214 ARITH_CMN = 0xb,
215 ARITH_ORR = 0xc,
216 ARITH_MOV = 0xd,
217 ARITH_BIC = 0xe,
218 ARITH_MVN = 0xf,
219};
220
221#define TO_CPSR(opc) ((opc == ARITH_CMP || opc == ARITH_CMN) << 20)
222
223#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
224#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
225#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
226#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
227#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
228#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
229#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
230#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
231
232enum arm_cond_code_e {
233 COND_EQ = 0x0,
234 COND_NE = 0x1,
235 COND_CS = 0x2, /* Unsigned greater or equal */
236 COND_CC = 0x3, /* Unsigned less than */
237 COND_MI = 0x4, /* Negative */
238 COND_PL = 0x5, /* Zero or greater */
239 COND_VS = 0x6, /* Overflow */
240 COND_VC = 0x7, /* No overflow */
241 COND_HI = 0x8, /* Unsigned greater than */
242 COND_LS = 0x9, /* Unsigned less or equal */
243 COND_GE = 0xa,
244 COND_LT = 0xb,
245 COND_GT = 0xc,
246 COND_LE = 0xd,
247 COND_AL = 0xe,
248};
249
250static const uint8_t tcg_cond_to_arm_cond[10] = {
251 [TCG_COND_EQ] = COND_EQ,
252 [TCG_COND_NE] = COND_NE,
253 [TCG_COND_LT] = COND_LT,
254 [TCG_COND_GE] = COND_GE,
255 [TCG_COND_LE] = COND_LE,
256 [TCG_COND_GT] = COND_GT,
257 /* unsigned */
258 [TCG_COND_LTU] = COND_CC,
259 [TCG_COND_GEU] = COND_CS,
260 [TCG_COND_LEU] = COND_LS,
261 [TCG_COND_GTU] = COND_HI,
262};
263
264static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
265{
266 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
267}
268
269static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
270{
271 tcg_out32(s, (cond << 28) | 0x0a000000 |
272 (((offset - 8) >> 2) & 0x00ffffff));
273}
274
275static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
276{
277 tcg_out32(s, (cond << 28) | 0x0b000000 |
278 (((offset - 8) >> 2) & 0x00ffffff));
279}
280
281static inline void tcg_out_dat_reg(TCGContext *s,
282 int cond, int opc, int rd, int rn, int rm, int shift)
283{
284 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
285 (rn << 16) | (rd << 12) | shift | rm);
286}
287
288static inline void tcg_out_dat_reg2(TCGContext *s,
289 int cond, int opc0, int opc1, int rd0, int rd1,
290 int rn0, int rn1, int rm0, int rm1, int shift)
291{
292 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
293 (rn0 << 16) | (rd0 << 12) | shift | rm0);
294 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
295 (rn1 << 16) | (rd1 << 12) | shift | rm1);
296}
297
298static inline void tcg_out_dat_imm(TCGContext *s,
299 int cond, int opc, int rd, int rn, int im)
300{
301 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) |
302 (rn << 16) | (rd << 12) | im);
303}
304
305static inline void tcg_out_movi32(TCGContext *s,
306 int cond, int rd, int32_t arg)
307{
308 int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);
309
310 /* TODO: This is very suboptimal, we can easily have a constant
311 * pool somewhere after all the instructions. */
312
313 if (arg < 0 && arg > -0x100)
314 return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
315
316 if (offset < 0x100 && offset > -0x100)
317 return offset >= 0 ?
318 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
319 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
320
321 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
322 if (arg & 0x0000ff00)
323 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
324 ((arg >> 8) & 0xff) | 0xc00);
325 if (arg & 0x00ff0000)
326 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
327 ((arg >> 16) & 0xff) | 0x800);
328 if (arg & 0xff000000)
329 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
330 ((arg >> 24) & 0xff) | 0x400);
331}
332
333static inline void tcg_out_mul32(TCGContext *s,
334 int cond, int rd, int rs, int rm)
335{
336 if (rd != rm)
337 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
338 (rs << 8) | 0x90 | rm);
339 else if (rd != rs)
340 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
341 (rm << 8) | 0x90 | rs);
342 else {
343 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
344 (rs << 8) | 0x90 | rm);
345 tcg_out_dat_reg(s, cond, ARITH_MOV,
346 rd, 0, 8, SHIFT_IMM_LSL(0));
347 }
348}
349
350static inline void tcg_out_umull32(TCGContext *s,
351 int cond, int rd0, int rd1, int rs, int rm)
352{
353 if (rd0 != rm && rd1 != rm)
354 tcg_out32(s, (cond << 28) | 0x800090 |
355 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
356 else if (rd0 != rs && rd1 != rs)
357 tcg_out32(s, (cond << 28) | 0x800090 |
358 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
359 else {
360 tcg_out_dat_reg(s, cond, ARITH_MOV,
361 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
362 tcg_out32(s, (cond << 28) | 0x800098 |
363 (rd1 << 16) | (rd0 << 12) | (rs << 8));
364 }
365}
366
367static inline void tcg_out_smull32(TCGContext *s,
368 int cond, int rd0, int rd1, int rs, int rm)
369{
370 if (rd0 != rm && rd1 != rm)
371 tcg_out32(s, (cond << 28) | 0xc00090 |
372 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
373 else if (rd0 != rs && rd1 != rs)
374 tcg_out32(s, (cond << 28) | 0xc00090 |
375 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
376 else {
377 tcg_out_dat_reg(s, cond, ARITH_MOV,
378 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
379 tcg_out32(s, (cond << 28) | 0xc00098 |
380 (rd1 << 16) | (rd0 << 12) | (rs << 8));
381 }
382}
383
384static inline void tcg_out_ld32_12(TCGContext *s, int cond,
385 int rd, int rn, tcg_target_long im)
386{
387 if (im >= 0)
388 tcg_out32(s, (cond << 28) | 0x05900000 |
389 (rn << 16) | (rd << 12) | (im & 0xfff));
390 else
391 tcg_out32(s, (cond << 28) | 0x05100000 |
392 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
393}
394
395static inline void tcg_out_st32_12(TCGContext *s, int cond,
396 int rd, int rn, tcg_target_long im)
397{
398 if (im >= 0)
399 tcg_out32(s, (cond << 28) | 0x05800000 |
400 (rn << 16) | (rd << 12) | (im & 0xfff));
401 else
402 tcg_out32(s, (cond << 28) | 0x05000000 |
403 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
404}
405
406static inline void tcg_out_ld32_r(TCGContext *s, int cond,
407 int rd, int rn, int rm)
408{
409 tcg_out32(s, (cond << 28) | 0x07900000 |
410 (rn << 16) | (rd << 12) | rm);
411}
412
413static inline void tcg_out_st32_r(TCGContext *s, int cond,
414 int rd, int rn, int rm)
415{
416 tcg_out32(s, (cond << 28) | 0x07800000 |
417 (rn << 16) | (rd << 12) | rm);
418}
419
420static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
421 int rd, int rn, tcg_target_long im)
422{
423 if (im >= 0)
424 tcg_out32(s, (cond << 28) | 0x01d000b0 |
425 (rn << 16) | (rd << 12) |
426 ((im & 0xf0) << 4) | (im & 0xf));
427 else
428 tcg_out32(s, (cond << 28) | 0x015000b0 |
429 (rn << 16) | (rd << 12) |
430 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
431}
432
433static inline void tcg_out_st16u_8(TCGContext *s, int cond,
434 int rd, int rn, tcg_target_long im)
435{
436 if (im >= 0)
437 tcg_out32(s, (cond << 28) | 0x01c000b0 |
438 (rn << 16) | (rd << 12) |
439 ((im & 0xf0) << 4) | (im & 0xf));
440 else
441 tcg_out32(s, (cond << 28) | 0x014000b0 |
442 (rn << 16) | (rd << 12) |
443 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
444}
445
446static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
447 int rd, int rn, int rm)
448{
449 tcg_out32(s, (cond << 28) | 0x019000b0 |
450 (rn << 16) | (rd << 12) | rm);
451}
452
453static inline void tcg_out_st16u_r(TCGContext *s, int cond,
454 int rd, int rn, int rm)
455{
456 tcg_out32(s, (cond << 28) | 0x018000b0 |
457 (rn << 16) | (rd << 12) | rm);
458}
459
460static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
461 int rd, int rn, tcg_target_long im)
462{
463 if (im >= 0)
464 tcg_out32(s, (cond << 28) | 0x01d000f0 |
465 (rn << 16) | (rd << 12) |
466 ((im & 0xf0) << 4) | (im & 0xf));
467 else
468 tcg_out32(s, (cond << 28) | 0x015000f0 |
469 (rn << 16) | (rd << 12) |
470 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
471}
472
473static inline void tcg_out_st16s_8(TCGContext *s, int cond,
474 int rd, int rn, tcg_target_long im)
475{
476 if (im >= 0)
477 tcg_out32(s, (cond << 28) | 0x01c000f0 |
478 (rn << 16) | (rd << 12) |
479 ((im & 0xf0) << 4) | (im & 0xf));
480 else
481 tcg_out32(s, (cond << 28) | 0x014000f0 |
482 (rn << 16) | (rd << 12) |
483 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
484}
485
486static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
487 int rd, int rn, int rm)
488{
489 tcg_out32(s, (cond << 28) | 0x019000f0 |
490 (rn << 16) | (rd << 12) | rm);
491}
492
493static inline void tcg_out_st16s_r(TCGContext *s, int cond,
494 int rd, int rn, int rm)
495{
496 tcg_out32(s, (cond << 28) | 0x018000f0 |
497 (rn << 16) | (rd << 12) | rm);
498}
499
500static inline void tcg_out_ld8_12(TCGContext *s, int cond,
501 int rd, int rn, tcg_target_long im)
502{
503 if (im >= 0)
504 tcg_out32(s, (cond << 28) | 0x05d00000 |
505 (rn << 16) | (rd << 12) | (im & 0xfff));
506 else
507 tcg_out32(s, (cond << 28) | 0x05500000 |
508 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
509}
510
511static inline void tcg_out_st8_12(TCGContext *s, int cond,
512 int rd, int rn, tcg_target_long im)
513{
514 if (im >= 0)
515 tcg_out32(s, (cond << 28) | 0x05c00000 |
516 (rn << 16) | (rd << 12) | (im & 0xfff));
517 else
518 tcg_out32(s, (cond << 28) | 0x05400000 |
519 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
520}
521
522static inline void tcg_out_ld8_r(TCGContext *s, int cond,
523 int rd, int rn, int rm)
524{
525 tcg_out32(s, (cond << 28) | 0x07d00000 |
526 (rn << 16) | (rd << 12) | rm);
527}
528
529static inline void tcg_out_st8_r(TCGContext *s, int cond,
530 int rd, int rn, int rm)
531{
532 tcg_out32(s, (cond << 28) | 0x07c00000 |
533 (rn << 16) | (rd << 12) | rm);
534}
535
536static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
537 int rd, int rn, tcg_target_long im)
538{
539 if (im >= 0)
540 tcg_out32(s, (cond << 28) | 0x01d000d0 |
541 (rn << 16) | (rd << 12) |
542 ((im & 0xf0) << 4) | (im & 0xf));
543 else
544 tcg_out32(s, (cond << 28) | 0x015000d0 |
545 (rn << 16) | (rd << 12) |
546 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
547}
548
549static inline void tcg_out_st8s_8(TCGContext *s, int cond,
550 int rd, int rn, tcg_target_long im)
551{
552 if (im >= 0)
553 tcg_out32(s, (cond << 28) | 0x01c000d0 |
554 (rn << 16) | (rd << 12) |
555 ((im & 0xf0) << 4) | (im & 0xf));
556 else
557 tcg_out32(s, (cond << 28) | 0x014000d0 |
558 (rn << 16) | (rd << 12) |
559 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
560}
561
562static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
563 int rd, int rn, int rm)
564{
204c1674 565 tcg_out32(s, (cond << 28) | 0x019000d0 |
811d4cf4
AZ		 566 (rn << 16) | (rd << 12) | rm);
567}
568
569static inline void tcg_out_st8s_r(TCGContext *s, int cond,
570 int rd, int rn, int rm)
571{
204c1674 572 tcg_out32(s, (cond << 28) | 0x018000d0 |
811d4cf4
AZ		 573 (rn << 16) | (rd << 12) | rm);
574}
575
576static inline void tcg_out_ld32u(TCGContext *s, int cond,
577 int rd, int rn, int32_t offset)
578{
579 if (offset > 0xfff || offset < -0xfff) {
580 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
581 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
582 } else
583 tcg_out_ld32_12(s, cond, rd, rn, offset);
584}
585
586static inline void tcg_out_st32(TCGContext *s, int cond,
587 int rd, int rn, int32_t offset)
588{
589 if (offset > 0xfff || offset < -0xfff) {
590 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
591 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
592 } else
593 tcg_out_st32_12(s, cond, rd, rn, offset);
594}
595
596static inline void tcg_out_ld16u(TCGContext *s, int cond,
597 int rd, int rn, int32_t offset)
598{
599 if (offset > 0xff || offset < -0xff) {
600 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
601 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
602 } else
603 tcg_out_ld16u_8(s, cond, rd, rn, offset);
604}
605
606static inline void tcg_out_ld16s(TCGContext *s, int cond,
607 int rd, int rn, int32_t offset)
608{
609 if (offset > 0xff || offset < -0xff) {
610 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
611 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
612 } else
613 tcg_out_ld16s_8(s, cond, rd, rn, offset);
614}
615
616static inline void tcg_out_st16u(TCGContext *s, int cond,
617 int rd, int rn, int32_t offset)
618{
619 if (offset > 0xff || offset < -0xff) {
620 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
621 tcg_out_st16u_r(s, cond, rd, rn, TCG_REG_R8);
622 } else
623 tcg_out_st16u_8(s, cond, rd, rn, offset);
624}
625
626static inline void tcg_out_ld8u(TCGContext *s, int cond,
627 int rd, int rn, int32_t offset)
628{
629 if (offset > 0xfff || offset < -0xfff) {
630 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
631 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
632 } else
633 tcg_out_ld8_12(s, cond, rd, rn, offset);
634}
635
636static inline void tcg_out_ld8s(TCGContext *s, int cond,
637 int rd, int rn, int32_t offset)
638{
639 if (offset > 0xff || offset < -0xff) {
640 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
641 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
642 } else
643 tcg_out_ld8s_8(s, cond, rd, rn, offset);
644}
645
646static inline void tcg_out_st8u(TCGContext *s, int cond,
647 int rd, int rn, int32_t offset)
648{
649 if (offset > 0xfff || offset < -0xfff) {
650 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
651 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
652 } else
653 tcg_out_st8_12(s, cond, rd, rn, offset);
654}
655
656static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
657{
658 int32_t val;
659
660 val = addr - (tcg_target_long) s->code_ptr;
661 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
662 tcg_out_b(s, cond, val);
663 else {
664#if 1
665 tcg_abort();
666#else
667 if (cond == COND_AL) {
668 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
669 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
670 } else {
671 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
672 tcg_out_dat_reg(s, cond, ARITH_ADD,
673 15, 15, TCG_REG_R8, SHIFT_IMM_LSL(0));
674 }
675#endif
676 }
677}
678
679static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
680{
681 int32_t val;
682
683#ifdef SAVE_LR
684 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
685#endif
686
687 val = addr - (tcg_target_long) s->code_ptr;
688 if (val < 0x01fffffd && val > -0x01fffffd)
689 tcg_out_bl(s, cond, val);
690 else {
691#if 1
692 tcg_abort();
693#else
694 if (cond == COND_AL) {
695 tcg_out_dat_imm(s, cond, ARITH_ADD, 14, 15, 4);
696 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
697 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
698 } else {
699 tcg_out_movi32(s, cond, TCG_REG_R9, addr);
700 tcg_out_dat_imm(s, cond, ARITH_MOV, 14, 0, 15);
701 tcg_out_bx(s, cond, TCG_REG_R9);
702 }
703#endif
704 }
705
706#ifdef SAVE_LR
707 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
708#endif
709}
710
711static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
712{
713#ifdef SAVE_LR
714 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
715#endif
716 /* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg); */
717 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 15, SHIFT_IMM_LSL(0));
718 tcg_out_bx(s, cond, arg);
719#ifdef SAVE_LR
720 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
721#endif
722}
723
724static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
725{
726 TCGLabel *l = &s->labels[label_index];
727
728 if (l->has_value)
729 tcg_out_goto(s, cond, l->u.value);
730 else if (cond == COND_AL) {
731 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
732 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
733 s->code_ptr += 4;
734 } else {
735 /* Probably this should be preferred even for COND_AL... */
736 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
737 tcg_out_b(s, cond, 8);
738 }
739}
740
741static void tcg_out_div_helper(TCGContext *s, int cond, const TCGArg *args,
742 void *helper_div, void *helper_rem, int shift)
743{
744 int div_reg = args[0];
745 int rem_reg = args[1];
746
747 /* stmdb sp!, { r0 - r3, ip, lr } */
748 /* (Note that we need an even number of registers as per EABI) */
749 tcg_out32(s, (cond << 28) | 0x092d500f);
750
751 tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0));
752 tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0));
753 tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0));
754 tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift);
755
756 tcg_out_call(s, cond, (uint32_t) helper_div);
757 tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 0, SHIFT_IMM_LSL(0));
758
759 /* ldmia sp, { r0 - r3, fp, lr } */
760 tcg_out32(s, (cond << 28) | 0x089d500f);
761
762 tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0));
763 tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0));
764 tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0));
765 tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift);
766
767 tcg_out_call(s, cond, (uint32_t) helper_rem);
768
769 tcg_out_dat_reg(s, cond, ARITH_MOV, rem_reg, 0, 0, SHIFT_IMM_LSL(0));
770 tcg_out_dat_reg(s, cond, ARITH_MOV, div_reg, 0, 8, SHIFT_IMM_LSL(0));
771
772 /* ldr r0, [sp], #4 */
773 if (rem_reg != 0 && div_reg != 0)
774 tcg_out32(s, (cond << 28) | 0x04bd0004);
775 /* ldr r1, [sp], #4 */
776 if (rem_reg != 1 && div_reg != 1)
777 tcg_out32(s, (cond << 28) | 0x04bd1004);
778 /* ldr r2, [sp], #4 */
779 if (rem_reg != 2 && div_reg != 2)
780 tcg_out32(s, (cond << 28) | 0x04bd2004);
781 /* ldr r3, [sp], #4 */
782 if (rem_reg != 3 && div_reg != 3)
783 tcg_out32(s, (cond << 28) | 0x04bd3004);
784 /* ldr ip, [sp], #4 */
785 if (rem_reg != 12 && div_reg != 12)
786 tcg_out32(s, (cond << 28) | 0x04bdc004);
787 /* ldr lr, [sp], #4 */
788 if (rem_reg != 14 && div_reg != 14)
789 tcg_out32(s, (cond << 28) | 0x04bde004);
790}
791
792#ifdef CONFIG_SOFTMMU
793extern void __ldb_mmu(void);
794extern void __ldw_mmu(void);
795extern void __ldl_mmu(void);
796extern void __ldq_mmu(void);
797
798extern void __stb_mmu(void);
799extern void __stw_mmu(void);
800extern void __stl_mmu(void);
801extern void __stq_mmu(void);
802
803static void *qemu_ld_helpers[4] = {
804 __ldb_mmu,
805 __ldw_mmu,
806 __ldl_mmu,
807 __ldq_mmu,
808};
809
810static void *qemu_st_helpers[4] = {
811 __stb_mmu,
812 __stw_mmu,
813 __stl_mmu,
814 __stq_mmu,
815};
816#endif
817
818static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
819 const TCGArg *args, int opc)
820{
821 int addr_reg, data_reg, data_reg2;
822#ifdef CONFIG_SOFTMMU
823 int mem_index, s_bits;
824# if TARGET_LONG_BITS == 64
825 int addr_reg2;
826# endif
827# ifdef USE_TLB
828 uint32_t *label_ptr;
829# endif
830#endif
831
832 data_reg = *args++;
833 if (opc == 3)
834 data_reg2 = *args++;
835 else
836 data_reg2 = 0; /* surpress warning */
837 addr_reg = *args++;
838#if TARGET_LONG_BITS == 64
839 addr_reg2 = *args++;
840#endif
841#ifdef CONFIG_SOFTMMU
842 mem_index = *args;
843 s_bits = opc & 3;
844
845# ifdef USE_TLB
846 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
847 8, 0, addr_reg, SHIFT_IMM_ROR(TARGET_PAGE_BITS));
848 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
849 0, 8, CPU_TLB_SIZE - 1);
850 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
851 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
225b4376
AZ		 852# define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
853 if (mem_index)
854 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
855 (mem_index << (TLB_SHIFT & 1)) |
856 ((16 - (TLB_SHIFT >> 1)) << 8));
811d4cf4 857 tcg_out_ld32_12(s, COND_AL, 1, 0,
225b4376 858 offsetof(CPUState, tlb_table[0][0].addr_read));
811d4cf4
AZ		 859 tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
860 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
861 /* TODO: alignment check?
862 * if (s_bits)
863 * tcg_out_data_reg(s, COND_EQ, ARITH_EOR,
864 * 0, 1, 8, SHIFT_IMM_LSR(32 - s_bits));
865 */
866# if TARGET_LONG_BITS == 64
867 /* XXX: possibly we could use a block data load or writeback in
868 * the first access. */
869 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 870 offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
811d4cf4
AZ		 871 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
872 0, 1, addr_reg2, SHIFT_IMM_LSL(0));
873# endif
874 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 875 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 876
877 switch (opc) {
878 case 0:
879 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, 1);
880 break;
881 case 0 | 4:
882 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, 1);
883 break;
884 case 1:
885 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, 1);
886 break;
887 case 1 | 4:
888 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, 1);
889 break;
890 case 2:
891 default:
892 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, 1);
893 break;
894 case 3:
895 /* TODO: must write back */
896 tcg_out_ld32_r(s, COND_EQ, data_reg, 1, addr_reg);
897 tcg_out_ld32_12(s, COND_EQ, data_reg2, 1, 4);
898 break;
899 }
900
901 label_ptr = (void *) s->code_ptr;
902 tcg_out_b(s, COND_EQ, 8);
903# endif
904
905# ifdef SAVE_LR
906 tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
907# endif
908
909 /* TODO: move this code to where the constants pool will be */
910 if (addr_reg)
911 tcg_out_dat_reg(s, cond, ARITH_MOV,
912 0, 0, addr_reg, SHIFT_IMM_LSL(0));
913# if TARGET_LONG_BITS == 32
914 tcg_out_dat_imm(s, cond, ARITH_MOV, 1, 0, mem_index);
915# else
916 if (addr_reg2 != 1)
917 tcg_out_dat_reg(s, cond, ARITH_MOV,
918 1, 0, addr_reg2, SHIFT_IMM_LSL(0));
919 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
920# endif
650bbb36 921 tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] -
811d4cf4
AZ		 922 (tcg_target_long) s->code_ptr);
923
924 switch (opc) {
925 case 0 | 4:
926 tcg_out_dat_reg(s, cond, ARITH_MOV,
927 0, 0, 0, SHIFT_IMM_LSL(24));
928 tcg_out_dat_reg(s, cond, ARITH_MOV,
929 data_reg, 0, 0, SHIFT_IMM_ASR(24));
930 break;
931 case 1 | 4:
932 tcg_out_dat_reg(s, cond, ARITH_MOV,
933 0, 0, 0, SHIFT_IMM_LSL(16));
934 tcg_out_dat_reg(s, cond, ARITH_MOV,
935 data_reg, 0, 0, SHIFT_IMM_ASR(16));
936 break;
937 case 0:
938 case 1:
939 case 2:
940 default:
941 if (data_reg)
942 tcg_out_dat_reg(s, cond, ARITH_MOV,
943 data_reg, 0, 0, SHIFT_IMM_LSL(0));
944 break;
945 case 3:
946 if (data_reg2 != 1)
947 tcg_out_dat_reg(s, cond, ARITH_MOV,
948 data_reg2, 0, 1, SHIFT_IMM_LSL(0));
949 if (data_reg != 0)
950 tcg_out_dat_reg(s, cond, ARITH_MOV,
951 data_reg, 0, 0, SHIFT_IMM_LSL(0));
952 break;
953 }
954
955# ifdef SAVE_LR
956 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
957# endif
958
959# ifdef USE_TLB
960 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
961# endif
962#else
963 switch (opc) {
964 case 0:
965 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
966 break;
967 case 0 | 4:
968 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
969 break;
970 case 1:
971 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
972 break;
973 case 1 | 4:
974 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
975 break;
976 case 2:
977 default:
978 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
979 break;
980 case 3:
981 /* TODO: use block load */
982 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
983 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
984 break;
985 }
986#endif
987}
988
989static inline void tcg_out_qemu_st(TCGContext *s, int cond,
990 const TCGArg *args, int opc)
991{
992 int addr_reg, data_reg, data_reg2;
993#ifdef CONFIG_SOFTMMU
994 int mem_index, s_bits;
995# if TARGET_LONG_BITS == 64
996 int addr_reg2;
997# endif
998# ifdef USE_TLB
999 uint32_t *label_ptr;
1000# endif
1001#endif
1002
1003 data_reg = *args++;
1004 if (opc == 3)
1005 data_reg2 = *args++;
1006 else
1007 data_reg2 = 0; /* surpress warning */
1008 addr_reg = *args++;
1009#if TARGET_LONG_BITS == 64
1010 addr_reg2 = *args++;
1011#endif
1012#ifdef CONFIG_SOFTMMU
1013 mem_index = *args;
1014 s_bits = opc & 3;
1015
1016# ifdef USE_TLB
1017 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1018 8, 0, addr_reg, SHIFT_IMM_ROR(TARGET_PAGE_BITS));
1019 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1020 0, 8, CPU_TLB_SIZE - 1);
1021 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
1022 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
225b4376
AZ		 1023 if (mem_index)
1024 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
1025 (mem_index << (TLB_SHIFT & 1)) |
1026 ((16 - (TLB_SHIFT >> 1)) << 8));
811d4cf4 1027 tcg_out_ld32_12(s, COND_AL, 1, 0,
225b4376 1028 offsetof(CPUState, tlb_table[0][0].addr_write));
811d4cf4
AZ		 1029 tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
1030 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1031 /* TODO: alignment check?
1032 * if (s_bits)
1033 * tcg_out_data_reg(s, COND_EQ, ARITH_EOR,
1034 * 0, 1, 8, SHIFT_IMM_LSR(32 - s_bits));
1035 */
1036# if TARGET_LONG_BITS == 64
1037 /* XXX: possibly we could use a block data load or writeback in
1038 * the first access. */
1039 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 1040 offsetof(CPUState, tlb_table[0][0].addr_write)
811d4cf4
AZ		 1041 + 4);
1042 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
1043 0, 1, addr_reg2, SHIFT_IMM_LSL(0));
1044# endif
1045 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 1046 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 1047
1048 switch (opc) {
1049 case 0:
1050 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, 1);
1051 break;
1052 case 0 | 4:
1053 tcg_out_st8s_r(s, COND_EQ, data_reg, addr_reg, 1);
1054 break;
1055 case 1:
1056 tcg_out_st16u_r(s, COND_EQ, data_reg, addr_reg, 1);
1057 break;
1058 case 1 | 4:
1059 tcg_out_st16s_r(s, COND_EQ, data_reg, addr_reg, 1);
1060 break;
1061 case 2:
1062 default:
1063 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, 1);
1064 break;
1065 case 3:
1066 /* TODO: must write back */
1067 tcg_out_st32_r(s, COND_EQ, data_reg, 1, addr_reg);
1068 tcg_out_st32_12(s, COND_EQ, data_reg2, 1, 4);
1069 break;
1070 }
1071
1072 label_ptr = (void *) s->code_ptr;
1073 tcg_out_b(s, COND_EQ, 8);
1074# endif
1075
1076# ifdef SAVE_LR
1077 tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
1078# endif
1079
1080 /* TODO: move this code to where the constants pool will be */
1081 if (addr_reg)
1082 tcg_out_dat_reg(s, cond, ARITH_MOV,
1083 0, 0, addr_reg, SHIFT_IMM_LSL(0));
1084# if TARGET_LONG_BITS == 32
1085 switch (opc) {
1086 case 0:
1087 tcg_out_dat_imm(s, cond, ARITH_AND, 1, data_reg, 0xff);
1088 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1089 break;
1090 case 1:
1091 tcg_out_dat_reg(s, cond, ARITH_MOV,
1092 1, 0, data_reg, SHIFT_IMM_LSL(16));
1093 tcg_out_dat_reg(s, cond, ARITH_MOV,
1094 1, 0, 1, SHIFT_IMM_LSR(16));
1095 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1096 break;
1097 case 2:
1098 if (data_reg != 1)
1099 tcg_out_dat_reg(s, cond, ARITH_MOV,
1100 1, 0, data_reg, SHIFT_IMM_LSL(0));
1101 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1102 break;
1103 case 3:
1104 if (data_reg != 1)
1105 tcg_out_dat_reg(s, cond, ARITH_MOV,
1106 1, 0, data_reg, SHIFT_IMM_LSL(0));
1107 if (data_reg2 != 2)
1108 tcg_out_dat_reg(s, cond, ARITH_MOV,
1109 2, 0, data_reg2, SHIFT_IMM_LSL(0));
1110 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1111 break;
1112 }
1113# else
1114 if (addr_reg2 != 1)
1115 tcg_out_dat_reg(s, cond, ARITH_MOV,
1116 1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1117 switch (opc) {
1118 case 0:
1119 tcg_out_dat_imm(s, cond, ARITH_AND, 2, data_reg, 0xff);
1120 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1121 break;
1122 case 1:
1123 tcg_out_dat_reg(s, cond, ARITH_MOV,
1124 2, 0, data_reg, SHIFT_IMM_LSL(16));
1125 tcg_out_dat_reg(s, cond, ARITH_MOV,
1126 2, 0, 2, SHIFT_IMM_LSR(16));
1127 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1128 break;
1129 case 2:
1130 if (data_reg != 2)
1131 tcg_out_dat_reg(s, cond, ARITH_MOV,
1132 2, 0, data_reg, SHIFT_IMM_LSL(0));
1133 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1134 break;
1135 case 3:
1136 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1137 tcg_out32(s, (cond << 28) | 0x052d3010); /* str r3, [sp, #-0x10]! */
1138 if (data_reg != 2)
1139 tcg_out_dat_reg(s, cond, ARITH_MOV,
1140 2, 0, data_reg, SHIFT_IMM_LSL(0));
1141 if (data_reg2 != 3)
1142 tcg_out_dat_reg(s, cond, ARITH_MOV,
1143 3, 0, data_reg2, SHIFT_IMM_LSL(0));
1144 break;
1145 }
1146# endif
1147
204c1674 1148 tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] -
811d4cf4
AZ		 1149 (tcg_target_long) s->code_ptr);
1150
1151# if TARGET_LONG_BITS == 64
1152 if (opc == 3)
1153 tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 0x10);
1154# endif
1155
1156# ifdef SAVE_LR
1157 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
1158# endif
1159
1160# ifdef USE_TLB
1161 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
1162# endif
1163#else
1164 switch (opc) {
1165 case 0:
1166 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1167 break;
1168 case 0 | 4:
204c1674 1169 tcg_out_st8s_8(s, COND_AL, data_reg, addr_reg, 0);
811d4cf4
AZ		 1170 break;
1171 case 1:
1172 tcg_out_st16u_8(s, COND_AL, data_reg, addr_reg, 0);
1173 break;
1174 case 1 | 4:
1175 tcg_out_st16s_8(s, COND_AL, data_reg, addr_reg, 0);
1176 break;
1177 case 2:
1178 default:
1179 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1180 break;
1181 case 3:
1182 /* TODO: use block store */
1183 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1184 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1185 break;
1186 }
1187#endif
1188}
1189
811d4cf4
AZ		 1190static uint8_t *tb_ret_addr;
1191
650bbb36 1192static inline void tcg_out_op(TCGContext *s, int opc,
811d4cf4
AZ		 1193 const TCGArg *args, const int *const_args)
1194{
1195 int c;
1196
1197 switch (opc) {
1198 case INDEX_op_exit_tb:
1199#ifdef SAVE_LR
1200 if (args[0] >> 8)
1201 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1202 else
1203 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
1204 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 15, 0, 14, SHIFT_IMM_LSL(0));
1205 if (args[0] >> 8)
1206 tcg_out32(s, args[0]);
1207#else
1208 if (args[0] >> 8)
1209 tcg_out_ld32_12(s, COND_AL, 0, 15, 0);
1210 else
1211 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, 0, 0, args[0]);
1212 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1213 if (args[0] >> 8)
1214 tcg_out32(s, args[0]);
1215#endif
1216 break;
1217 case INDEX_op_goto_tb:
1218 if (s->tb_jmp_offset) {
1219 /* Direct jump method */
1220#if 1
1221 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1222 tcg_out_b(s, COND_AL, 8);
1223#else
1224 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
1225 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1226 tcg_out32(s, 0);
1227#endif
1228 } else {
1229 /* Indirect jump method */
1230#if 1
1231 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1232 if (c > 0xfff || c < -0xfff) {
1233 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1234 (tcg_target_long) (s->tb_next + args[0]));
1235 tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1236 } else
1237 tcg_out_ld32_12(s, COND_AL, 15, 15, c);
1238#else
1239 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1240 tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1241 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1242#endif
1243 }
1244 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1245 break;
1246 case INDEX_op_call:
1247 if (const_args[0])
1248 tcg_out_call(s, COND_AL, args[0]);
1249 else
1250 tcg_out_callr(s, COND_AL, args[0]);
1251 break;
1252 case INDEX_op_jmp:
1253 if (const_args[0])
1254 tcg_out_goto(s, COND_AL, args[0]);
1255 else
1256 tcg_out_bx(s, COND_AL, args[0]);
1257 break;
1258 case INDEX_op_br:
1259 tcg_out_goto_label(s, COND_AL, args[0]);
1260 break;
1261
1262 case INDEX_op_ld8u_i32:
1263 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1264 break;
1265 case INDEX_op_ld8s_i32:
1266 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1267 break;
1268 case INDEX_op_ld16u_i32:
1269 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1270 break;
1271 case INDEX_op_ld16s_i32:
1272 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1273 break;
1274 case INDEX_op_ld_i32:
1275 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1276 break;
1277 case INDEX_op_st8_i32:
1278 tcg_out_st8u(s, COND_AL, args[0], args[1], args[2]);
1279 break;
1280 case INDEX_op_st16_i32:
1281 tcg_out_st16u(s, COND_AL, args[0], args[1], args[2]);
1282 break;
1283 case INDEX_op_st_i32:
1284 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1285 break;
1286
1287 case INDEX_op_mov_i32:
1288 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1289 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1290 break;
1291 case INDEX_op_movi_i32:
1292 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1293 break;
1294 case INDEX_op_add_i32:
1295 c = ARITH_ADD;
1296 goto gen_arith;
1297 case INDEX_op_sub_i32:
1298 c = ARITH_SUB;
1299 goto gen_arith;
1300 case INDEX_op_and_i32:
1301 c = ARITH_AND;
1302 goto gen_arith;
1303 case INDEX_op_or_i32:
1304 c = ARITH_ORR;
1305 goto gen_arith;
1306 case INDEX_op_xor_i32:
1307 c = ARITH_EOR;
1308 /* Fall through. */
1309 gen_arith:
1310 tcg_out_dat_reg(s, COND_AL, c,
1311 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
1312 break;
1313 case INDEX_op_add2_i32:
1314 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1315 args[0], args[1], args[2], args[3],
1316 args[4], args[5], SHIFT_IMM_LSL(0));
1317 break;
1318 case INDEX_op_sub2_i32:
1319 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1320 args[0], args[1], args[2], args[3],
1321 args[4], args[5], SHIFT_IMM_LSL(0));
1322 break;
650bbb36
AZ		 1323 case INDEX_op_neg_i32:
1324 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1325 break;
811d4cf4
AZ		 1326 case INDEX_op_mul_i32:
1327 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1328 break;
1329 case INDEX_op_mulu2_i32:
1330 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1331 break;
1332 case INDEX_op_div2_i32:
1333 tcg_out_div_helper(s, COND_AL, args,
1334 tcg_helper_div_i64, tcg_helper_rem_i64,
1335 SHIFT_IMM_ASR(31));
1336 break;
1337 case INDEX_op_divu2_i32:
1338 tcg_out_div_helper(s, COND_AL, args,
1339 tcg_helper_divu_i64, tcg_helper_remu_i64,
1340 SHIFT_IMM_LSR(31));
1341 break;
1342 /* XXX: Perhaps args[2] & 0x1f is wrong */
1343 case INDEX_op_shl_i32:
1344 c = const_args[2] ?
1345 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1346 goto gen_shift32;
1347 case INDEX_op_shr_i32:
1348 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1349 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1350 goto gen_shift32;
1351 case INDEX_op_sar_i32:
1352 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1353 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1354 /* Fall through. */
1355 gen_shift32:
1356 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1357 break;
1358
1359 case INDEX_op_brcond_i32:
1360 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1361 args[0], args[1], SHIFT_IMM_LSL(0));
1362 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1363 break;
1364 case INDEX_op_brcond2_i32:
1365 /* The resulting conditions are:
1366 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1367 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1368 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1369 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1370 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1371 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1372 */
1373 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1374 args[1], args[3], SHIFT_IMM_LSL(0));
1375 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1376 args[0], args[2], SHIFT_IMM_LSL(0));
1377 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1378 break;
1379
1380 case INDEX_op_qemu_ld8u:
1381 tcg_out_qemu_ld(s, COND_AL, args, 0);
1382 break;
1383 case INDEX_op_qemu_ld8s:
1384 tcg_out_qemu_ld(s, COND_AL, args, 0 | 4);
1385 break;
1386 case INDEX_op_qemu_ld16u:
1387 tcg_out_qemu_ld(s, COND_AL, args, 1);
1388 break;
1389 case INDEX_op_qemu_ld16s:
1390 tcg_out_qemu_ld(s, COND_AL, args, 1 | 4);
1391 break;
1392 case INDEX_op_qemu_ld32u:
1393 tcg_out_qemu_ld(s, COND_AL, args, 2);
1394 break;
1395 case INDEX_op_qemu_ld64:
1396 tcg_out_qemu_ld(s, COND_AL, args, 3);
1397 break;
650bbb36 1398
811d4cf4
AZ		 1399 case INDEX_op_qemu_st8:
1400 tcg_out_qemu_st(s, COND_AL, args, 0);
1401 break;
1402 case INDEX_op_qemu_st16:
1403 tcg_out_qemu_st(s, COND_AL, args, 1);
1404 break;
1405 case INDEX_op_qemu_st32:
1406 tcg_out_qemu_st(s, COND_AL, args, 2);
1407 break;
1408 case INDEX_op_qemu_st64:
1409 tcg_out_qemu_st(s, COND_AL, args, 3);
1410 break;
1411
1412 case INDEX_op_ext8s_i32:
1413 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1414 args[0], 0, args[1], SHIFT_IMM_LSL(24));
1415 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1416 args[0], 0, args[0], SHIFT_IMM_ASR(24));
1417 break;
1418 case INDEX_op_ext16s_i32:
1419 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1420 args[0], 0, args[1], SHIFT_IMM_LSL(16));
1421 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1422 args[0], 0, args[0], SHIFT_IMM_ASR(16));
1423 break;
1424
1425 default:
1426 tcg_abort();
1427 }
1428}
1429
1430static const TCGTargetOpDef arm_op_defs[] = {
1431 { INDEX_op_exit_tb, { } },
1432 { INDEX_op_goto_tb, { } },
1433 { INDEX_op_call, { "ri" } },
1434 { INDEX_op_jmp, { "ri" } },
1435 { INDEX_op_br, { } },
1436
1437 { INDEX_op_mov_i32, { "r", "r" } },
1438 { INDEX_op_movi_i32, { "r" } },
1439
1440 { INDEX_op_ld8u_i32, { "r", "r" } },
1441 { INDEX_op_ld8s_i32, { "r", "r" } },
1442 { INDEX_op_ld16u_i32, { "r", "r" } },
1443 { INDEX_op_ld16s_i32, { "r", "r" } },
1444 { INDEX_op_ld_i32, { "r", "r" } },
1445 { INDEX_op_st8_i32, { "r", "r" } },
1446 { INDEX_op_st16_i32, { "r", "r" } },
1447 { INDEX_op_st_i32, { "r", "r" } },
1448
1449 /* TODO: "r", "r", "ri" */
1450 { INDEX_op_add_i32, { "r", "r", "r" } },
1451 { INDEX_op_sub_i32, { "r", "r", "r" } },
1452 { INDEX_op_mul_i32, { "r", "r", "r" } },
1453 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1454 { INDEX_op_div2_i32, { "r", "r", "r", "1", "2" } },
1455 { INDEX_op_divu2_i32, { "r", "r", "r", "1", "2" } },
1456 { INDEX_op_and_i32, { "r", "r", "r" } },
1457 { INDEX_op_or_i32, { "r", "r", "r" } },
1458 { INDEX_op_xor_i32, { "r", "r", "r" } },
650bbb36 1459 { INDEX_op_neg_i32, { "r", "r" } },
811d4cf4
AZ		 1460
1461 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1462 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1463 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1464
1465 { INDEX_op_brcond_i32, { "r", "r" } },
1466
1467 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1468 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1469 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1470 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1471
1472 { INDEX_op_qemu_ld8u, { "r", "x", "X" } },
1473 { INDEX_op_qemu_ld8s, { "r", "x", "X" } },
1474 { INDEX_op_qemu_ld16u, { "r", "x", "X" } },
1475 { INDEX_op_qemu_ld16s, { "r", "x", "X" } },
1476 { INDEX_op_qemu_ld32u, { "r", "x", "X" } },
1477 { INDEX_op_qemu_ld64, { "r", "d", "x", "X" } },
1478
1479 { INDEX_op_qemu_st8, { "d", "x", "X" } },
1480 { INDEX_op_qemu_st16, { "d", "x", "X" } },
1481 { INDEX_op_qemu_st32, { "d", "x", "X" } },
1482 { INDEX_op_qemu_st64, { "d", "D", "x", "X" } },
1483
1484 { INDEX_op_ext8s_i32, { "r", "r" } },
1485 { INDEX_op_ext16s_i32, { "r", "r" } },
1486
1487 { -1 },
1488};
1489
1490void tcg_target_init(TCGContext *s)
1491{
1492 /* fail safe */
1493 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1494 tcg_abort();
1495
1496 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
1497 ((2 << TCG_REG_R14) - 1) & ~(1 << TCG_REG_R8));
1498 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1499 ((2 << TCG_REG_R3) - 1) |
1500 (1 << TCG_REG_R12) | (1 << TCG_REG_R14));
1501
1502 tcg_regset_clear(s->reserved_regs);
1503#ifdef SAVE_LR
1504 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R14);
1505#endif
1506 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1507 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
1508
1509 tcg_add_target_add_op_defs(arm_op_defs);
1510}
1511
1512static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1513 int arg1, tcg_target_long arg2)
1514{
1515 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1516}
1517
1518static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1519 int arg1, tcg_target_long arg2)
1520{
1521 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1522}
1523
1524void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
1525{
1526 if (val > 0)
1527 if (val < 0x100)
1528 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1529 else
1530 tcg_abort();
1531 else if (val < 0) {
1532 if (val > -0x100)
1533 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1534 else
1535 tcg_abort();
1536 }
1537}
1538
1539static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
1540{
1541 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1542}
1543
1544static inline void tcg_out_movi(TCGContext *s, TCGType type,
1545 int ret, tcg_target_long arg)
1546{
1547 tcg_out_movi32(s, COND_AL, ret, arg);
1548}
1549
1550void tcg_target_qemu_prologue(TCGContext *s)
1551{
1552 /* stmdb sp!, { r9 - r11, lr } */
1553 tcg_out32(s, (COND_AL << 28) | 0x092d4e00);
1554
1555 tcg_out_bx(s, COND_AL, TCG_REG_R0);
1556 tb_ret_addr = s->code_ptr;
1557
1558 /* ldmia sp!, { r9 - r11, pc } */
1559 tcg_out32(s, (COND_AL << 28) | 0x08bd8e00);
1560}
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