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tcg/arm: Restrict constant pool displacement to 12 bits
[mirror_qemu.git] / tcg / arm / tcg-target.inc.c
CommitLineData
811d4cf4
AZ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
d4a9eb1f 24
41d9ea80 25#include "elf.h"
880ad962 26#include "tcg-pool.inc.c"
9ecefc84 27
40b2ccb1 28int arm_arch = __ARM_ARCH;
ac34fb5c 29
72e1ccfc
RH		 30#ifndef use_idiv_instructions
31bool use_idiv_instructions;
32#endif
72e1ccfc 33
1a8e80d7
RH		 34/* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */
35#ifdef CONFIG_SOFTMMU
36# define USING_SOFTMMU 1
37#else
38# define USING_SOFTMMU 0
39#endif
40
8d8fdbae 41#ifdef CONFIG_DEBUG_TCG
d4a9eb1f 42static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
811d4cf4
AZ		 43 "%r0",
44 "%r1",
45 "%r2",
46 "%r3",
47 "%r4",
48 "%r5",
49 "%r6",
50 "%r7",
51 "%r8",
52 "%r9",
53 "%r10",
54 "%r11",
55 "%r12",
56 "%r13",
57 "%r14",
e4a7d5e8 58 "%pc",
811d4cf4 59};
d4a9eb1f 60#endif
811d4cf4 61
d4a9eb1f 62static const int tcg_target_reg_alloc_order[] = {
811d4cf4
AZ		 63 TCG_REG_R4,
64 TCG_REG_R5,
65 TCG_REG_R6,
66 TCG_REG_R7,
67 TCG_REG_R8,
68 TCG_REG_R9,
69 TCG_REG_R10,
70 TCG_REG_R11,
811d4cf4 71 TCG_REG_R13,
914ccf51
AJ		 72 TCG_REG_R0,
73 TCG_REG_R1,
74 TCG_REG_R2,
75 TCG_REG_R3,
76 TCG_REG_R12,
811d4cf4
AZ		 77 TCG_REG_R14,
78};
79
d4a9eb1f 80static const int tcg_target_call_iarg_regs[4] = {
811d4cf4
AZ		 81 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
82};
d4a9eb1f 83static const int tcg_target_call_oarg_regs[2] = {
811d4cf4
AZ		 84 TCG_REG_R0, TCG_REG_R1
85};
86
13dd6fb9 87#define TCG_REG_TMP TCG_REG_R12
4346457a 88
15070616
RH		 89enum arm_cond_code_e {
90 COND_EQ = 0x0,
91 COND_NE = 0x1,
92 COND_CS = 0x2, /* Unsigned greater or equal */
93 COND_CC = 0x3, /* Unsigned less than */
94 COND_MI = 0x4, /* Negative */
95 COND_PL = 0x5, /* Zero or greater */
96 COND_VS = 0x6, /* Overflow */
97 COND_VC = 0x7, /* No overflow */
98 COND_HI = 0x8, /* Unsigned greater than */
99 COND_LS = 0x9, /* Unsigned less or equal */
100 COND_GE = 0xa,
101 COND_LT = 0xb,
102 COND_GT = 0xc,
103 COND_LE = 0xd,
104 COND_AL = 0xe,
105};
106
107#define TO_CPSR (1 << 20)
108
109#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
110#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
111#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
112#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
113#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
114#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
115#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
116#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
117
118typedef enum {
119 ARITH_AND = 0x0 << 21,
120 ARITH_EOR = 0x1 << 21,
121 ARITH_SUB = 0x2 << 21,
122 ARITH_RSB = 0x3 << 21,
123 ARITH_ADD = 0x4 << 21,
124 ARITH_ADC = 0x5 << 21,
125 ARITH_SBC = 0x6 << 21,
126 ARITH_RSC = 0x7 << 21,
127 ARITH_TST = 0x8 << 21 | TO_CPSR,
128 ARITH_CMP = 0xa << 21 | TO_CPSR,
129 ARITH_CMN = 0xb << 21 | TO_CPSR,
130 ARITH_ORR = 0xc << 21,
131 ARITH_MOV = 0xd << 21,
132 ARITH_BIC = 0xe << 21,
133 ARITH_MVN = 0xf << 21,
134
135 INSN_CLZ = 0x016f0f10,
136 INSN_RBIT = 0x06ff0f30,
137
138 INSN_LDR_IMM = 0x04100000,
139 INSN_LDR_REG = 0x06100000,
140 INSN_STR_IMM = 0x04000000,
141 INSN_STR_REG = 0x06000000,
142
143 INSN_LDRH_IMM = 0x005000b0,
144 INSN_LDRH_REG = 0x001000b0,
145 INSN_LDRSH_IMM = 0x005000f0,
146 INSN_LDRSH_REG = 0x001000f0,
147 INSN_STRH_IMM = 0x004000b0,
148 INSN_STRH_REG = 0x000000b0,
149
150 INSN_LDRB_IMM = 0x04500000,
151 INSN_LDRB_REG = 0x06500000,
152 INSN_LDRSB_IMM = 0x005000d0,
153 INSN_LDRSB_REG = 0x001000d0,
154 INSN_STRB_IMM = 0x04400000,
155 INSN_STRB_REG = 0x06400000,
156
157 INSN_LDRD_IMM = 0x004000d0,
158 INSN_LDRD_REG = 0x000000d0,
159 INSN_STRD_IMM = 0x004000f0,
160 INSN_STRD_REG = 0x000000f0,
161
3f814b80
HW		 162 INSN_DMB_ISH = 0xf57ff05b,
163 INSN_DMB_MCR = 0xee070fba,
2a8ab93c
RH		 164
165 /* Architected nop introduced in v6k. */
166 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
167 also Just So Happened to do nothing on pre-v6k so that we
168 don't need to conditionalize it? */
169 INSN_NOP_v6k = 0xe320f000,
170 /* Otherwise the assembler uses mov r0,r0 */
171 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
15070616
RH		 172} ARMInsn;
173
2a8ab93c
RH		 174#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
175
15070616
RH		 176static const uint8_t tcg_cond_to_arm_cond[] = {
177 [TCG_COND_EQ] = COND_EQ,
178 [TCG_COND_NE] = COND_NE,
179 [TCG_COND_LT] = COND_LT,
180 [TCG_COND_GE] = COND_GE,
181 [TCG_COND_LE] = COND_LE,
182 [TCG_COND_GT] = COND_GT,
183 /* unsigned */
184 [TCG_COND_LTU] = COND_CC,
185 [TCG_COND_GEU] = COND_CS,
186 [TCG_COND_LEU] = COND_LS,
187 [TCG_COND_GTU] = COND_HI,
188};
189
43fabd30 190static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
c69806ab 191{
267c9319 192 ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2;
43fabd30
RH		 193 if (offset == sextract32(offset, 0, 24)) {
194 *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff);
195 return true;
196 }
197 return false;
c69806ab
AJ		 198}
199
b4b82d7e
RH		 200static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
201{
202 ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8;
203
204 if (offset >= -0xfff && offset <= 0xfff) {
205 tcg_insn_unit insn = *code_ptr;
206 bool u = (offset >= 0);
207 if (!u) {
208 offset = -offset;
209 }
210 insn = deposit32(insn, 23, 1, u);
211 insn = deposit32(insn, 0, 12, offset);
212 *code_ptr = insn;
213 return true;
214 }
215 return false;
216}
217
6ac17786 218static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
2ba7fae2 219 intptr_t value, intptr_t addend)
811d4cf4 220{
eabb7b91 221 tcg_debug_assert(addend == 0);
880ad962
RH		 222
223 if (type == R_ARM_PC24) {
43fabd30 224 return reloc_pc24(code_ptr, (tcg_insn_unit *)value);
880ad962 225 } else if (type == R_ARM_PC13) {
b4b82d7e 226 return reloc_pc13(code_ptr, (tcg_insn_unit *)value);
880ad962
RH		 227 } else {
228 g_assert_not_reached();
229 }
811d4cf4
AZ		 230}
231
b6b24cb0
RH		 232#define TCG_CT_CONST_ARM 0x100
233#define TCG_CT_CONST_INV 0x200
234#define TCG_CT_CONST_NEG 0x400
235#define TCG_CT_CONST_ZERO 0x800
19b62bf4 236
811d4cf4 237/* parse target specific constraints */
069ea736
RH		 238static const char *target_parse_constraint(TCGArgConstraint *ct,
239 const char *ct_str, TCGType type)
811d4cf4 240{
069ea736 241 switch (*ct_str++) {
cb4e581f 242 case 'I':
19b62bf4
RH		 243 ct->ct |= TCG_CT_CONST_ARM;
244 break;
245 case 'K':
246 ct->ct |= TCG_CT_CONST_INV;
247 break;
a9a86ae9
RH		 248 case 'N': /* The gcc constraint letter is L, already used here. */
249 ct->ct |= TCG_CT_CONST_NEG;
250 break;
b6b24cb0
RH		 251 case 'Z':
252 ct->ct |= TCG_CT_CONST_ZERO;
253 break;
cb4e581f 254
811d4cf4 255 case 'r':
811d4cf4 256 ct->ct |= TCG_CT_REG;
f46934df 257 ct->u.regs = 0xffff;
811d4cf4
AZ		 258 break;
259
67dcab73
AJ		 260 /* qemu_ld address */
261 case 'l':
811d4cf4 262 ct->ct |= TCG_CT_REG;
f46934df 263 ct->u.regs = 0xffff;
67dcab73 264#ifdef CONFIG_SOFTMMU
d9f4dde4 265 /* r0-r2,lr will be overwritten when reading the tlb entry,
67dcab73 266 so don't use these. */
811d4cf4
AZ		 267 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
268 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
9716ef3b 269 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
d9f4dde4 270 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
67dcab73 271#endif
d0660ed4
AZ		 272 break;
273
a485cff0 274 /* qemu_st address & data */
67dcab73 275 case 's':
811d4cf4 276 ct->ct |= TCG_CT_REG;
f46934df 277 ct->u.regs = 0xffff;
702b33b1
RH		 278 /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
279 and r0-r1 doing the byte swapping, so don't use these. */
811d4cf4 280 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
811d4cf4 281 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
702b33b1
RH		 282#if defined(CONFIG_SOFTMMU)
283 /* Avoid clashes with registers being used for helper args */
67dcab73 284 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
89c33337 285#if TARGET_LONG_BITS == 64
9716ef3b
PM		 286 /* Avoid clashes with registers being used for helper args */
287 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
288#endif
d9f4dde4 289 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
811d4cf4 290#endif
67dcab73 291 break;
811d4cf4 292
811d4cf4 293 default:
069ea736 294 return NULL;
811d4cf4 295 }
069ea736 296 return ct_str;
811d4cf4
AZ		 297}
298
94953e6d
LD		 299static inline uint32_t rotl(uint32_t val, int n)
300{
301 return (val << n) | (val >> (32 - n));
302}
303
304/* ARM immediates for ALU instructions are made of an unsigned 8-bit
305 right-rotated by an even amount between 0 and 30. */
306static inline int encode_imm(uint32_t imm)
307{
4e6f6d4c
LD		 308 int shift;
309
94953e6d
LD		 310 /* simple case, only lower bits */
311 if ((imm & ~0xff) == 0)
312 return 0;
313 /* then try a simple even shift */
314 shift = ctz32(imm) & ~1;
315 if (((imm >> shift) & ~0xff) == 0)
316 return 32 - shift;
317 /* now try harder with rotations */
318 if ((rotl(imm, 2) & ~0xff) == 0)
319 return 2;
320 if ((rotl(imm, 4) & ~0xff) == 0)
321 return 4;
322 if ((rotl(imm, 6) & ~0xff) == 0)
323 return 6;
324 /* imm can't be encoded */
325 return -1;
326}
cb4e581f
LD		 327
328static inline int check_fit_imm(uint32_t imm)
329{
94953e6d 330 return encode_imm(imm) >= 0;
cb4e581f
LD		 331}
332
811d4cf4
AZ		 333/* Test if a constant matches the constraint.
334 * TODO: define constraints for:
335 *
336 * ldr/str offset: between -0xfff and 0xfff
337 * ldrh/strh offset: between -0xff and 0xff
338 * mov operand2: values represented with x << (2 * y), x < 0x100
339 * add, sub, eor...: ditto
340 */
f6c6afc1 341static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
19b62bf4 342 const TCGArgConstraint *arg_ct)
811d4cf4
AZ		 343{
344 int ct;
345 ct = arg_ct->ct;
19b62bf4 346 if (ct & TCG_CT_CONST) {
811d4cf4 347 return 1;
19b62bf4 348 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
cb4e581f 349 return 1;
19b62bf4
RH		 350 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) {
351 return 1;
a9a86ae9
RH		 352 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) {
353 return 1;
b6b24cb0
RH		 354 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
355 return 1;
19b62bf4 356 } else {
811d4cf4 357 return 0;
19b62bf4 358 }
811d4cf4
AZ		 359}
360
15070616
RH		 361static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
362{
363 tcg_out32(s, (cond << 28) | 0x0a000000 |
364 (((offset - 8) >> 2) & 0x00ffffff));
365}
2df3f1ee 366
15070616
RH		 367static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
368{
369 tcg_out32(s, (cond << 28) | 0x0b000000 |
370 (((offset - 8) >> 2) & 0x00ffffff));
371}
9feac1d7 372
15070616
RH		 373static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
374{
375 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
376}
9feac1d7 377
15070616
RH		 378static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset)
379{
380 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |
381 (((offset - 8) >> 2) & 0x00ffffff));
382}
702b33b1 383
15070616
RH		 384static inline void tcg_out_dat_reg(TCGContext *s,
385 int cond, int opc, int rd, int rn, int rm, int shift)
386{
387 tcg_out32(s, (cond << 28) | (0 << 25) | opc |
388 (rn << 16) | (rd << 12) | shift | rm);
389}
40f191ab 390
15070616
RH		 391static inline void tcg_out_nop(TCGContext *s)
392{
2a8ab93c 393 tcg_out32(s, INSN_NOP);
15070616 394}
40f191ab 395
15070616
RH		 396static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
397{
398 /* Simple reg-reg move, optimising out the 'do nothing' case */
399 if (rd != rm) {
400 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0));
401 }
402}
811d4cf4 403
15070616
RH		 404static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn)
405{
406 /* Unless the C portion of QEMU is compiled as thumb, we don't
407 actually need true BX semantics; merely a branch to an address
408 held in a register. */
409 if (use_armv5t_instructions) {
410 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
411 } else {
412 tcg_out_mov_reg(s, cond, TCG_REG_PC, rn);
413 }
414}
811d4cf4 415
15070616
RH		 416static inline void tcg_out_dat_imm(TCGContext *s,
417 int cond, int opc, int rd, int rn, int im)
418{
419 tcg_out32(s, (cond << 28) | (1 << 25) | opc |
420 (rn << 16) | (rd << 12) | im);
421}
811d4cf4 422
15070616
RH		 423/* Note that this routine is used for both LDR and LDRH formats, so we do
424 not wish to include an immediate shift at this point. */
425static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
426 TCGReg rn, TCGReg rm, bool u, bool p, bool w)
427{
428 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24)
429 | (w << 21) | (rn << 16) | (rt << 12) | rm);
430}
431
432static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
433 TCGReg rn, int imm8, bool p, bool w)
434{
435 bool u = 1;
436 if (imm8 < 0) {
437 imm8 = -imm8;
438 u = 0;
439 }
440 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
441 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf));
442}
443
444static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
445 TCGReg rn, int imm12, bool p, bool w)
446{
447 bool u = 1;
448 if (imm12 < 0) {
449 imm12 = -imm12;
450 u = 0;
451 }
452 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
453 (rn << 16) | (rt << 12) | imm12);
454}
455
456static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt,
457 TCGReg rn, int imm12)
458{
459 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0);
460}
461
462static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt,
463 TCGReg rn, int imm12)
464{
465 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0);
466}
467
468static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt,
469 TCGReg rn, TCGReg rm)
470{
471 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0);
472}
473
474static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt,
475 TCGReg rn, TCGReg rm)
476{
477 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0);
478}
479
480static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt,
481 TCGReg rn, int imm8)
482{
483 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0);
484}
485
486static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt,
487 TCGReg rn, TCGReg rm)
488{
489 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0);
490}
491
cd7d3cb7
RH		 492static inline void tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt,
493 TCGReg rn, TCGReg rm)
494{
495 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1);
496}
497
15070616
RH		 498static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt,
499 TCGReg rn, int imm8)
500{
501 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0);
502}
503
504static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt,
505 TCGReg rn, TCGReg rm)
506{
507 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0);
508}
509
510/* Register pre-increment with base writeback. */
511static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt,
512 TCGReg rn, TCGReg rm)
513{
514 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1);
515}
516
517static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt,
518 TCGReg rn, TCGReg rm)
519{
520 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1);
521}
522
523static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt,
524 TCGReg rn, int imm8)
525{
526 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0);
527}
811d4cf4 528
15070616
RH		 529static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt,
530 TCGReg rn, int imm8)
811d4cf4 531{
15070616 532 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0);
811d4cf4
AZ		 533}
534
15070616
RH		 535static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt,
536 TCGReg rn, TCGReg rm)
e936243a 537{
15070616 538 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0);
d9f4dde4
RH		 539}
540
15070616
RH		 541static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt,
542 TCGReg rn, TCGReg rm)
d9f4dde4 543{
15070616 544 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0);
e936243a
AZ		 545}
546
15070616
RH		 547static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt,
548 TCGReg rn, int imm8)
811d4cf4 549{
15070616 550 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0);
811d4cf4
AZ		 551}
552
15070616
RH		 553static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt,
554 TCGReg rn, TCGReg rm)
23401b58 555{
15070616 556 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0);
23401b58
AJ		 557}
558
15070616
RH		 559static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt,
560 TCGReg rn, int imm12)
24e838b7 561{
15070616 562 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0);
24e838b7
PM		 563}
564
15070616
RH		 565static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt,
566 TCGReg rn, int imm12)
811d4cf4 567{
15070616 568 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0);
811d4cf4
AZ		 569}
570
15070616
RH		 571static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt,
572 TCGReg rn, TCGReg rm)
df5e0ef7 573{
15070616 574 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0);
df5e0ef7
RH		 575}
576
15070616
RH		 577static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt,
578 TCGReg rn, TCGReg rm)
9716ef3b 579{
15070616 580 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0);
9716ef3b
PM		 581}
582
15070616
RH		 583static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt,
584 TCGReg rn, int imm8)
702a9474 585{
15070616 586 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0);
702a9474
RH		 587}
588
15070616
RH		 589static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt,
590 TCGReg rn, TCGReg rm)
811d4cf4 591{
15070616 592 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0);
811d4cf4
AZ		 593}
594
880ad962
RH		 595static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg)
596{
880ad962
RH		 597 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0);
598 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0);
880ad962
RH		 599}
600
e86e0f28 601static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg)
811d4cf4 602{
880ad962
RH		 603 int rot, diff, opc, sh1, sh2;
604 uint32_t tt0, tt1, tt2;
9c39b94f
RH		 605
606 /* Check a single MOV/MVN before anything else. */
607 rot = encode_imm(arg);
608 if (rot >= 0) {
609 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0,
610 rotl(arg, rot) | (rot << 7));
611 return;
612 }
613 rot = encode_imm(~arg);
614 if (rot >= 0) {
615 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0,
616 rotl(~arg, rot) | (rot << 7));
617 return;
618 }
619
620 /* Check for a pc-relative address. This will usually be the TB,
621 or within the TB, which is immediately before the code block. */
622 diff = arg - ((intptr_t)s->code_ptr + 8);
623 if (diff >= 0) {
624 rot = encode_imm(diff);
e86e0f28 625 if (rot >= 0) {
9c39b94f
RH		 626 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC,
627 rotl(diff, rot) | (rot << 7));
e86e0f28
RH		 628 return;
629 }
9c39b94f
RH		 630 } else {
631 rot = encode_imm(-diff);
e86e0f28 632 if (rot >= 0) {
9c39b94f
RH		 633 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC,
634 rotl(-diff, rot) | (rot << 7));
e86e0f28
RH		 635 return;
636 }
637 }
638
639 /* Use movw + movt. */
640 if (use_armv7_instructions) {
ac34fb5c
AJ		 641 /* movw */
642 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
643 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
0f11f25a 644 if (arg & 0xffff0000) {
ac34fb5c
AJ		 645 /* movt */
646 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
647 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
ac34fb5c 648 }
e86e0f28
RH		 649 return;
650 }
0f11f25a 651
880ad962
RH		 652 /* Look for sequences of two insns. If we have lots of 1's, we can
653 shorten the sequence by beginning with mvn and then clearing
654 higher bits with eor. */
655 tt0 = arg;
e86e0f28 656 opc = ARITH_MOV;
880ad962
RH		 657 if (ctpop32(arg) > 16) {
658 tt0 = ~arg;
659 opc = ARITH_MVN;
660 }
661 sh1 = ctz32(tt0) & ~1;
662 tt1 = tt0 & ~(0xff << sh1);
663 sh2 = ctz32(tt1) & ~1;
664 tt2 = tt1 & ~(0xff << sh2);
665 if (tt2 == 0) {
666 rot = ((32 - sh1) << 7) & 0xf00;
667 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot);
668 rot = ((32 - sh2) << 7) & 0xf00;
669 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd,
670 ((tt0 >> sh2) & 0xff) | rot);
671 return;
0f11f25a 672 }
e86e0f28 673
880ad962
RH		 674 /* Otherwise, drop it into the constant pool. */
675 tcg_out_movi_pool(s, cond, rd, arg);
811d4cf4
AZ		 676}
677
7fc645bf
PM		 678static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst,
679 TCGArg lhs, TCGArg rhs, int rhs_is_const)
680{
681 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
682 * rhs must satisfy the "rI" constraint.
683 */
684 if (rhs_is_const) {
685 int rot = encode_imm(rhs);
eabb7b91 686 tcg_debug_assert(rot >= 0);
7fc645bf
PM		 687 tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
688 } else {
689 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
690 }
691}
692
19b62bf4
RH		 693static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv,
694 TCGReg dst, TCGReg lhs, TCGArg rhs,
695 bool rhs_is_const)
696{
697 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
698 * rhs must satisfy the "rIK" constraint.
699 */
700 if (rhs_is_const) {
701 int rot = encode_imm(rhs);
702 if (rot < 0) {
703 rhs = ~rhs;
704 rot = encode_imm(rhs);
eabb7b91 705 tcg_debug_assert(rot >= 0);
19b62bf4
RH		 706 opc = opinv;
707 }
708 tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
709 } else {
710 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
711 }
712}
713
a9a86ae9
RH		 714static void tcg_out_dat_rIN(TCGContext *s, int cond, int opc, int opneg,
715 TCGArg dst, TCGArg lhs, TCGArg rhs,
716 bool rhs_is_const)
717{
718 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
719 * rhs must satisfy the "rIN" constraint.
720 */
721 if (rhs_is_const) {
722 int rot = encode_imm(rhs);
723 if (rot < 0) {
724 rhs = -rhs;
725 rot = encode_imm(rhs);
eabb7b91 726 tcg_debug_assert(rot >= 0);
a9a86ae9
RH		 727 opc = opneg;
728 }
729 tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
730 } else {
731 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
732 }
733}
734
34358a12
RH		 735static inline void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd,
736 TCGReg rn, TCGReg rm)
811d4cf4 737{
34358a12
RH		 738 /* if ArchVersion() < 6 && d == n then UNPREDICTABLE; */
739 if (!use_armv6_instructions && rd == rn) {
740 if (rd == rm) {
741 /* rd == rn == rm; copy an input to tmp first. */
742 tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
743 rm = rn = TCG_REG_TMP;
744 } else {
745 rn = rm;
746 rm = rd;
747 }
811d4cf4 748 }
34358a12
RH		 749 /* mul */
750 tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn);
811d4cf4
AZ		 751}
752
34358a12
RH		 753static inline void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0,
754 TCGReg rd1, TCGReg rn, TCGReg rm)
811d4cf4 755{
34358a12
RH		 756 /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
757 if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) {
758 if (rd0 == rm || rd1 == rm) {
759 tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
760 rn = TCG_REG_TMP;
761 } else {
762 TCGReg t = rn;
763 rn = rm;
764 rm = t;
765 }
811d4cf4 766 }
34358a12
RH		 767 /* umull */
768 tcg_out32(s, (cond << 28) | 0x00800090 |
769 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
811d4cf4
AZ		 770}
771
34358a12
RH		 772static inline void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0,
773 TCGReg rd1, TCGReg rn, TCGReg rm)
811d4cf4 774{
34358a12
RH		 775 /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
776 if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) {
777 if (rd0 == rm || rd1 == rm) {
778 tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
779 rn = TCG_REG_TMP;
780 } else {
781 TCGReg t = rn;
782 rn = rm;
783 rm = t;
784 }
811d4cf4 785 }
34358a12
RH		 786 /* smull */
787 tcg_out32(s, (cond << 28) | 0x00c00090 |
788 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
811d4cf4
AZ		 789}
790
0637c56c
RH		 791static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm)
792{
793 tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
794}
795
796static inline void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm)
797{
798 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
799}
800
9517094f
AJ		 801static inline void tcg_out_ext8s(TCGContext *s, int cond,
802 int rd, int rn)
803{
804 if (use_armv6_instructions) {
805 /* sxtb */
806 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
807 } else {
e23886a9 808 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 809 rd, 0, rn, SHIFT_IMM_LSL(24));
e23886a9 810 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 811 rd, 0, rd, SHIFT_IMM_ASR(24));
812 }
813}
814
e854b6d3
AJ		 815static inline void tcg_out_ext8u(TCGContext *s, int cond,
816 int rd, int rn)
817{
818 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
819}
820
9517094f
AJ		 821static inline void tcg_out_ext16s(TCGContext *s, int cond,
822 int rd, int rn)
823{
824 if (use_armv6_instructions) {
825 /* sxth */
826 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
827 } else {
e23886a9 828 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 829 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 830 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 831 rd, 0, rd, SHIFT_IMM_ASR(16));
832 }
833}
834
835static inline void tcg_out_ext16u(TCGContext *s, int cond,
836 int rd, int rn)
837{
838 if (use_armv6_instructions) {
839 /* uxth */
840 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
841 } else {
e23886a9 842 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 843 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 844 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 845 rd, 0, rd, SHIFT_IMM_LSR(16));
846 }
847}
848
67dcab73
AJ		 849static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
850{
851 if (use_armv6_instructions) {
852 /* revsh */
853 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
854 } else {
855 tcg_out_dat_reg(s, cond, ARITH_MOV,
4346457a 856 TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24));
67dcab73 857 tcg_out_dat_reg(s, cond, ARITH_MOV,
4346457a 858 TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_ASR(16));
67dcab73 859 tcg_out_dat_reg(s, cond, ARITH_ORR,
4346457a 860 rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8));
67dcab73
AJ		 861 }
862}
863
244b1e81
AJ		 864static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
865{
866 if (use_armv6_instructions) {
867 /* rev16 */
868 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
869 } else {
870 tcg_out_dat_reg(s, cond, ARITH_MOV,
4346457a 871 TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24));
244b1e81 872 tcg_out_dat_reg(s, cond, ARITH_MOV,
4346457a 873 TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_LSR(16));
244b1e81 874 tcg_out_dat_reg(s, cond, ARITH_ORR,
4346457a 875 rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8));
244b1e81
AJ		 876 }
877}
878
7aab08aa
AJ		 879/* swap the two low bytes assuming that the two high input bytes and the
880 two high output bit can hold any value. */
881static inline void tcg_out_bswap16st(TCGContext *s, int cond, int rd, int rn)
882{
883 if (use_armv6_instructions) {
884 /* rev16 */
885 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
886 } else {
887 tcg_out_dat_reg(s, cond, ARITH_MOV,
4346457a
RH		 888 TCG_REG_TMP, 0, rn, SHIFT_IMM_LSR(8));
889 tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, 0xff);
7aab08aa 890 tcg_out_dat_reg(s, cond, ARITH_ORR,
4346457a 891 rd, TCG_REG_TMP, rn, SHIFT_IMM_LSL(8));
7aab08aa
AJ		 892 }
893}
894
244b1e81
AJ		 895static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
896{
897 if (use_armv6_instructions) {
898 /* rev */
899 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
900 } else {
901 tcg_out_dat_reg(s, cond, ARITH_EOR,
4346457a 902 TCG_REG_TMP, rn, rn, SHIFT_IMM_ROR(16));
244b1e81 903 tcg_out_dat_imm(s, cond, ARITH_BIC,
4346457a 904 TCG_REG_TMP, TCG_REG_TMP, 0xff | 0x800);
244b1e81
AJ		 905 tcg_out_dat_reg(s, cond, ARITH_MOV,
906 rd, 0, rn, SHIFT_IMM_ROR(8));
907 tcg_out_dat_reg(s, cond, ARITH_EOR,
4346457a 908 rd, rd, TCG_REG_TMP, SHIFT_IMM_LSR(8));
244b1e81
AJ		 909 }
910}
911
b6b24cb0
RH		 912static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd,
913 TCGArg a1, int ofs, int len, bool const_a1)
914{
915 if (const_a1) {
916 /* bfi becomes bfc with rn == 15. */
917 a1 = 15;
918 }
919 /* bfi/bfc */
920 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1
921 | (ofs << 7) | ((ofs + len - 1) << 16));
922}
923
ec903af1
RH		 924static inline void tcg_out_extract(TCGContext *s, int cond, TCGReg rd,
925 TCGArg a1, int ofs, int len)
926{
927 /* ubfx */
928 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1
929 | (ofs << 7) | ((len - 1) << 16));
930}
931
932static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd,
933 TCGArg a1, int ofs, int len)
934{
935 /* sbfx */
936 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1
937 | (ofs << 7) | ((len - 1) << 16));
938}
939
811d4cf4
AZ		 940static inline void tcg_out_ld32u(TCGContext *s, int cond,
941 int rd, int rn, int32_t offset)
942{
943 if (offset > 0xfff || offset < -0xfff) {
4346457a
RH		 944 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
945 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP);
811d4cf4
AZ		 946 } else
947 tcg_out_ld32_12(s, cond, rd, rn, offset);
948}
949
950static inline void tcg_out_st32(TCGContext *s, int cond,
951 int rd, int rn, int32_t offset)
952{
953 if (offset > 0xfff || offset < -0xfff) {
4346457a
RH		 954 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
955 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP);
811d4cf4
AZ		 956 } else
957 tcg_out_st32_12(s, cond, rd, rn, offset);
958}
959
960static inline void tcg_out_ld16u(TCGContext *s, int cond,
961 int rd, int rn, int32_t offset)
962{
963 if (offset > 0xff || offset < -0xff) {
4346457a
RH		 964 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
965 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP);
811d4cf4
AZ		 966 } else
967 tcg_out_ld16u_8(s, cond, rd, rn, offset);
968}
969
970static inline void tcg_out_ld16s(TCGContext *s, int cond,
971 int rd, int rn, int32_t offset)
972{
973 if (offset > 0xff || offset < -0xff) {
4346457a
RH		 974 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
975 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP);
811d4cf4
AZ		 976 } else
977 tcg_out_ld16s_8(s, cond, rd, rn, offset);
978}
979
f694a27e 980static inline void tcg_out_st16(TCGContext *s, int cond,
811d4cf4
AZ		 981 int rd, int rn, int32_t offset)
982{
983 if (offset > 0xff || offset < -0xff) {
4346457a
RH		 984 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
985 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP);
811d4cf4 986 } else
f694a27e 987 tcg_out_st16_8(s, cond, rd, rn, offset);
811d4cf4
AZ		 988}
989
990static inline void tcg_out_ld8u(TCGContext *s, int cond,
991 int rd, int rn, int32_t offset)
992{
993 if (offset > 0xfff || offset < -0xfff) {
4346457a
RH		 994 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
995 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP);
811d4cf4
AZ		 996 } else
997 tcg_out_ld8_12(s, cond, rd, rn, offset);
998}
999
1000static inline void tcg_out_ld8s(TCGContext *s, int cond,
1001 int rd, int rn, int32_t offset)
1002{
1003 if (offset > 0xff || offset < -0xff) {
4346457a
RH		 1004 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1005 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP);
811d4cf4
AZ		 1006 } else
1007 tcg_out_ld8s_8(s, cond, rd, rn, offset);
1008}
1009
f694a27e 1010static inline void tcg_out_st8(TCGContext *s, int cond,
811d4cf4
AZ		 1011 int rd, int rn, int32_t offset)
1012{
1013 if (offset > 0xfff || offset < -0xfff) {
4346457a
RH		 1014 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1015 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP);
811d4cf4
AZ		 1016 } else
1017 tcg_out_st8_12(s, cond, rd, rn, offset);
1018}
1019
d9f4dde4
RH		 1020/* The _goto case is normally between TBs within the same code buffer, and
1021 * with the code buffer limited to 16MB we wouldn't need the long case.
1022 * But we also use it for the tail-call to the qemu_ld/st helpers, which does.
222f23f5 1023 */
702a9474 1024static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr)
811d4cf4 1025{
267c9319
RH		 1026 intptr_t addri = (intptr_t)addr;
1027 ptrdiff_t disp = tcg_pcrel_diff(s, addr);
811d4cf4 1028
267c9319 1029 if ((addri & 1) == 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) {
d9f4dde4
RH		 1030 tcg_out_b(s, cond, disp);
1031 return;
24e838b7 1032 }
afe74dbd 1033 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri);
811d4cf4
AZ		 1034}
1035
222f23f5
DDAG		 1036/* The call case is mostly used for helpers - so it's not unreasonable
1037 * for them to be beyond branch range */
267c9319 1038static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr)
811d4cf4 1039{
267c9319
RH		 1040 intptr_t addri = (intptr_t)addr;
1041 ptrdiff_t disp = tcg_pcrel_diff(s, addr);
811d4cf4 1042
267c9319
RH		 1043 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) {
1044 if (addri & 1) {
24e838b7 1045 /* Use BLX if the target is in Thumb mode */
fb822738 1046 if (!use_armv5t_instructions) {
24e838b7
PM		 1047 tcg_abort();
1048 }
267c9319 1049 tcg_out_blx_imm(s, disp);
24e838b7 1050 } else {
267c9319 1051 tcg_out_bl(s, COND_AL, disp);
24e838b7 1052 }
302fdde7 1053 } else if (use_armv7_instructions) {
267c9319 1054 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
302fdde7 1055 tcg_out_blx(s, COND_AL, TCG_REG_TMP);
24e838b7 1056 } else {
b4b82d7e
RH		 1057 /* ??? Know that movi_pool emits exactly 1 insn. */
1058 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0);
afe74dbd 1059 tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri);
811d4cf4 1060 }
811d4cf4
AZ		 1061}
1062
bec16311 1063static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
811d4cf4 1064{
96fbd7de 1065 if (l->has_value) {
267c9319 1066 tcg_out_goto(s, cond, l->u.value_ptr);
811d4cf4 1067 } else {
bec16311 1068 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0);
37ee93a9 1069 tcg_out_b(s, cond, 0);
811d4cf4
AZ		 1070 }
1071}
1072
40f191ab
PK		 1073static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
1074{
1075 if (use_armv7_instructions) {
1076 tcg_out32(s, INSN_DMB_ISH);
1077 } else if (use_armv6_instructions) {
1078 tcg_out32(s, INSN_DMB_MCR);
1079 }
1080}
1081
7170ac33
RH		 1082static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1083 const int *const_args)
1084{
1085 TCGReg al = args[0];
1086 TCGReg ah = args[1];
1087 TCGArg bl = args[2];
1088 TCGArg bh = args[3];
1089 TCGCond cond = args[4];
1090 int const_bl = const_args[2];
1091 int const_bh = const_args[3];
1092
1093 switch (cond) {
1094 case TCG_COND_EQ:
1095 case TCG_COND_NE:
1096 case TCG_COND_LTU:
1097 case TCG_COND_LEU:
1098 case TCG_COND_GTU:
1099 case TCG_COND_GEU:
1100 /* We perform a conditional comparision. If the high half is
1101 equal, then overwrite the flags with the comparison of the
1102 low half. The resulting flags cover the whole. */
1103 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh);
1104 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl);
1105 return cond;
1106
1107 case TCG_COND_LT:
1108 case TCG_COND_GE:
1109 /* We perform a double-word subtraction and examine the result.
1110 We do not actually need the result of the subtract, so the
1111 low part "subtract" is a compare. For the high half we have
1112 no choice but to compute into a temporary. */
1113 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl);
1114 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR,
1115 TCG_REG_TMP, ah, bh, const_bh);
1116 return cond;
1117
1118 case TCG_COND_LE:
1119 case TCG_COND_GT:
1120 /* Similar, but with swapped arguments, via reversed subtract. */
1121 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR,
1122 TCG_REG_TMP, al, bl, const_bl);
1123 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR,
1124 TCG_REG_TMP, ah, bh, const_bh);
1125 return tcg_swap_cond(cond);
1126
1127 default:
1128 g_assert_not_reached();
1129 }
1130}
1131
811d4cf4 1132#ifdef CONFIG_SOFTMMU
659ef5cb
RH		 1133#include "tcg-ldst.inc.c"
1134
d9f4dde4
RH		 1135/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
1136 * int mmu_idx, uintptr_t ra)
1137 */
267c9319 1138static void * const qemu_ld_helpers[16] = {
0315c51e
RH		 1139 [MO_UB] = helper_ret_ldub_mmu,
1140 [MO_SB] = helper_ret_ldsb_mmu,
1141
1142 [MO_LEUW] = helper_le_lduw_mmu,
1143 [MO_LEUL] = helper_le_ldul_mmu,
1144 [MO_LEQ] = helper_le_ldq_mmu,
1145 [MO_LESW] = helper_le_ldsw_mmu,
1146 [MO_LESL] = helper_le_ldul_mmu,
1147
1148 [MO_BEUW] = helper_be_lduw_mmu,
1149 [MO_BEUL] = helper_be_ldul_mmu,
1150 [MO_BEQ] = helper_be_ldq_mmu,
1151 [MO_BESW] = helper_be_ldsw_mmu,
1152 [MO_BESL] = helper_be_ldul_mmu,
e141ab52
BS		 1153};
1154
d9f4dde4
RH		 1155/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
1156 * uintxx_t val, int mmu_idx, uintptr_t ra)
1157 */
267c9319 1158static void * const qemu_st_helpers[16] = {
0315c51e
RH		 1159 [MO_UB] = helper_ret_stb_mmu,
1160 [MO_LEUW] = helper_le_stw_mmu,
1161 [MO_LEUL] = helper_le_stl_mmu,
1162 [MO_LEQ] = helper_le_stq_mmu,
1163 [MO_BEUW] = helper_be_stw_mmu,
1164 [MO_BEUL] = helper_be_stl_mmu,
1165 [MO_BEQ] = helper_be_stq_mmu,
e141ab52 1166};
9716ef3b
PM		 1167
1168/* Helper routines for marshalling helper function arguments into
1169 * the correct registers and stack.
1170 * argreg is where we want to put this argument, arg is the argument itself.
1171 * Return value is the updated argreg ready for the next call.
1172 * Note that argreg 0..3 is real registers, 4+ on stack.
9716ef3b
PM		 1173 *
1174 * We provide routines for arguments which are: immediate, 32 bit
1175 * value in register, 16 and 8 bit values in register (which must be zero
1176 * extended before use) and 64 bit value in a lo:hi register pair.
1177 */
fc4d60ee
RH		 1178#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \
1179static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \
1180{ \
1181 if (argreg < 4) { \
1182 MOV_ARG(s, COND_AL, argreg, arg); \
1183 } else { \
1184 int ofs = (argreg - 4) * 4; \
1185 EXT_ARG; \
eabb7b91 1186 tcg_debug_assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \
fc4d60ee
RH		 1187 tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \
1188 } \
1189 return argreg + 1; \
1190}
1191
1192DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32,
4346457a 1193 (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
fc4d60ee 1194DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u,
4346457a 1195 (tcg_out_ext8u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
fc4d60ee 1196DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u,
4346457a 1197 (tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
fc4d60ee
RH		 1198DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, )
1199
1200static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
1201 TCGReg arglo, TCGReg arghi)
9716ef3b
PM		 1202{
1203 /* 64 bit arguments must go in even/odd register pairs
1204 * and in 8-aligned stack slots.
1205 */
1206 if (argreg & 1) {
1207 argreg++;
1208 }
e5e2e4a7
RH		 1209 if (use_armv6_instructions && argreg >= 4
1210 && (arglo & 1) == 0 && arghi == arglo + 1) {
1211 tcg_out_strd_8(s, COND_AL, arglo,
1212 TCG_REG_CALL_STACK, (argreg - 4) * 4);
1213 return argreg + 2;
1214 } else {
1215 argreg = tcg_out_arg_reg32(s, argreg, arglo);
1216 argreg = tcg_out_arg_reg32(s, argreg, arghi);
1217 return argreg;
1218 }
9716ef3b 1219}
811d4cf4 1220
3979144c
PB		 1221#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
1222
cd7d3cb7
RH		 1223/* We expect tlb_mask to be before tlb_table. */
1224QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
1225 offsetof(CPUArchState, tlb_mask));
1226
1227/* We expect to use a 20-bit unsigned offset from ENV. */
1228QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1])
1229 > 0xfffff);
f2488736 1230
d3e440be
RH		 1231/* Load and compare a TLB entry, leaving the flags set. Returns the register
1232 containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
811d4cf4 1233
d3e440be 1234static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
85aa8081 1235 TCGMemOp opc, int mem_index, bool is_load)
cee87be8 1236{
cd7d3cb7
RH		 1237 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
1238 : offsetof(CPUTLBEntry, addr_write));
1239 int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
1240 int table_off = offsetof(CPUArchState, tlb_table[mem_index]);
1241 TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
85aa8081
RH		 1242 unsigned s_bits = opc & MO_SIZE;
1243 unsigned a_bits = get_alignment_bits(opc);
702b33b1 1244
cd7d3cb7
RH		 1245 if (table_off > 0xfff) {
1246 int mask_hi = mask_off & ~0xfff;
1247 int table_hi = table_off & ~0xfff;
1248 int rot;
1249
1250 table_base = TCG_REG_R2;
1251 if (mask_hi == table_hi) {
1252 mask_base = table_base;
1253 } else if (mask_hi) {
1254 mask_base = TCG_REG_TMP;
1255 rot = encode_imm(mask_hi);
1256 assert(rot >= 0);
1257 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, mask_base, TCG_AREG0,
1258 rotl(mask_hi, rot) | (rot << 7));
1259 }
1260 rot = encode_imm(table_hi);
1261 assert(rot >= 0);
1262 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, table_base, TCG_AREG0,
1263 rotl(table_hi, rot) | (rot << 7));
702b33b1 1264
cd7d3cb7
RH		 1265 mask_off -= mask_hi;
1266 table_off -= table_hi;
702b33b1 1267 }
71f9cee9 1268
cd7d3cb7
RH		 1269 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1270 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, mask_base, mask_off);
1271 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, table_base, table_off);
1272
1273 /* Extract the tlb index from the address into TMP. */
1274 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrlo,
1275 SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
1276
1277 /*
1278 * Add the tlb_table pointer, creating the CPUTLBEntry address in R2.
1279 * Load the tlb comparator into R0/R1 and the fast path addend into R2.
1280 */
1281 if (cmp_off == 0) {
1282 if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
1283 tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_TMP);
1284 } else {
1285 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_TMP);
702b33b1 1286 }
cd7d3cb7
RH		 1287 } else {
1288 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
1289 TCG_REG_R2, TCG_REG_R2, TCG_REG_TMP, 0);
1290 if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
1291 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off);
1292 } else {
1293 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off);
1294 }
1295 }
1296 if (!use_armv6_instructions && TARGET_LONG_BITS == 64) {
1297 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2, cmp_off + 4);
d17bd1d8 1298 }
cee87be8 1299
647ab96a 1300 /* Load the tlb addend. */
cd7d3cb7
RH		 1301 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2,
1302 offsetof(CPUTLBEntry, addend));
647ab96a 1303
85aa8081
RH		 1304 /* Check alignment. We don't support inline unaligned acceses,
1305 but we can easily support overalignment checks. */
1306 if (a_bits < s_bits) {
1307 a_bits = s_bits;
1308 }
cee87be8 1309
647ab96a
RH		 1310 if (use_armv7_instructions) {
1311 tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));
1312 int rot = encode_imm(mask);
ee06e230 1313
647ab96a
RH		 1314 if (rot >= 0) {
1315 tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo,
1316 rotl(mask, rot) | (rot << 7));
1317 } else {
1318 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
1319 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
1320 addrlo, TCG_REG_TMP, 0);
1321 }
1322 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP, 0);
1323 } else {
1324 if (a_bits) {
1325 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo,
1326 (1 << a_bits) - 1);
1327 }
1328 tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP,
1329 0, TCG_REG_R0, TCG_REG_TMP,
1330 SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1331 }
702b33b1 1332
cee87be8 1333 if (TARGET_LONG_BITS == 64) {
647ab96a 1334 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0);
cee87be8 1335 }
d0ebde22 1336
ee06e230 1337 return TCG_REG_R2;
cee87be8 1338}
df5e0ef7
RH		 1339
1340/* Record the context of a call to the out of line helper code for the slow
1341 path for a load or store, so that we can later generate the correct
1342 helper code. */
3972ef6f 1343static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
a485cff0 1344 TCGReg datalo, TCGReg datahi, TCGReg addrlo,
3972ef6f
RH		 1345 TCGReg addrhi, tcg_insn_unit *raddr,
1346 tcg_insn_unit *label_ptr)
df5e0ef7 1347{
9ecefc84 1348 TCGLabelQemuLdst *label = new_ldst_label(s);
df5e0ef7 1349
df5e0ef7 1350 label->is_ld = is_ld;
3972ef6f 1351 label->oi = oi;
a485cff0
RH		 1352 label->datalo_reg = datalo;
1353 label->datahi_reg = datahi;
1354 label->addrlo_reg = addrlo;
1355 label->addrhi_reg = addrhi;
df5e0ef7
RH		 1356 label->raddr = raddr;
1357 label->label_ptr[0] = label_ptr;
1358}
1359
aeee05f5 1360static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
df5e0ef7 1361{
a485cff0 1362 TCGReg argreg, datalo, datahi;
3972ef6f
RH		 1363 TCGMemOpIdx oi = lb->oi;
1364 TCGMemOp opc = get_memop(oi);
267c9319 1365 void *func;
df5e0ef7 1366
aeee05f5
RH		 1367 if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
1368 return false;
1369 }
df5e0ef7
RH		 1370
1371 argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0);
1372 if (TARGET_LONG_BITS == 64) {
1373 argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg);
1374 } else {
1375 argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg);
1376 }
3972ef6f 1377 argreg = tcg_out_arg_imm32(s, argreg, oi);
d9f4dde4
RH		 1378 argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
1379
1380 /* For armv6 we can use the canonical unsigned helpers and minimize
1381 icache usage. For pre-armv6, use the signed helpers since we do
1382 not have a single insn sign-extend. */
1383 if (use_armv6_instructions) {
2b7ec66f 1384 func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)];
d9f4dde4 1385 } else {
2b7ec66f 1386 func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)];
099fcf2e
RH		 1387 if (opc & MO_SIGN) {
1388 opc = MO_UL;
d9f4dde4
RH		 1389 }
1390 }
1391 tcg_out_call(s, func);
df5e0ef7 1392
a485cff0
RH		 1393 datalo = lb->datalo_reg;
1394 datahi = lb->datahi_reg;
0315c51e 1395 switch (opc & MO_SSIZE) {
099fcf2e 1396 case MO_SB:
a485cff0 1397 tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0);
df5e0ef7 1398 break;
099fcf2e 1399 case MO_SW:
a485cff0 1400 tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0);
df5e0ef7 1401 break;
df5e0ef7 1402 default:
a485cff0 1403 tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
df5e0ef7 1404 break;
099fcf2e 1405 case MO_Q:
a485cff0
RH		 1406 if (datalo != TCG_REG_R1) {
1407 tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
1408 tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
1409 } else if (datahi != TCG_REG_R0) {
1410 tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
1411 tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
66c2056f
RH		 1412 } else {
1413 tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0);
a485cff0
RH		 1414 tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
1415 tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP);
66c2056f 1416 }
df5e0ef7
RH		 1417 break;
1418 }
1419
267c9319 1420 tcg_out_goto(s, COND_AL, lb->raddr);
aeee05f5 1421 return true;
df5e0ef7
RH		 1422}
1423
aeee05f5 1424static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
df5e0ef7 1425{
a485cff0 1426 TCGReg argreg, datalo, datahi;
3972ef6f
RH		 1427 TCGMemOpIdx oi = lb->oi;
1428 TCGMemOp opc = get_memop(oi);
df5e0ef7 1429
aeee05f5
RH		 1430 if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
1431 return false;
1432 }
df5e0ef7
RH		 1433
1434 argreg = TCG_REG_R0;
1435 argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
1436 if (TARGET_LONG_BITS == 64) {
1437 argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg);
1438 } else {
1439 argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg);
1440 }
1441
a485cff0
RH		 1442 datalo = lb->datalo_reg;
1443 datahi = lb->datahi_reg;
0315c51e 1444 switch (opc & MO_SIZE) {
099fcf2e 1445 case MO_8:
a485cff0 1446 argreg = tcg_out_arg_reg8(s, argreg, datalo);
df5e0ef7 1447 break;
099fcf2e 1448 case MO_16:
a485cff0 1449 argreg = tcg_out_arg_reg16(s, argreg, datalo);
df5e0ef7 1450 break;
099fcf2e
RH		 1451 case MO_32:
1452 default:
a485cff0 1453 argreg = tcg_out_arg_reg32(s, argreg, datalo);
df5e0ef7 1454 break;
099fcf2e 1455 case MO_64:
a485cff0 1456 argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi);
df5e0ef7
RH		 1457 break;
1458 }
1459
3972ef6f 1460 argreg = tcg_out_arg_imm32(s, argreg, oi);
d9f4dde4 1461 argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
df5e0ef7 1462
d9f4dde4 1463 /* Tail-call to the helper, which will return to the fast path. */
2b7ec66f 1464 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
aeee05f5 1465 return true;
df5e0ef7 1466}
cee87be8
RH		 1467#endif /* SOFTMMU */
1468
091d5677
RH		 1469static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc,
1470 TCGReg datalo, TCGReg datahi,
1471 TCGReg addrlo, TCGReg addend)
cee87be8 1472{
091d5677 1473 TCGMemOp bswap = opc & MO_BSWAP;
df5e0ef7 1474
099fcf2e
RH		 1475 switch (opc & MO_SSIZE) {
1476 case MO_UB:
a485cff0 1477 tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend);
811d4cf4 1478 break;
099fcf2e 1479 case MO_SB:
a485cff0 1480 tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend);
811d4cf4 1481 break;
099fcf2e 1482 case MO_UW:
a485cff0 1483 tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
67dcab73 1484 if (bswap) {
a485cff0 1485 tcg_out_bswap16(s, COND_AL, datalo, datalo);
67dcab73 1486 }
811d4cf4 1487 break;
099fcf2e 1488 case MO_SW:
67dcab73 1489 if (bswap) {
a485cff0
RH		 1490 tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
1491 tcg_out_bswap16s(s, COND_AL, datalo, datalo);
67dcab73 1492 } else {
a485cff0 1493 tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
67dcab73 1494 }
811d4cf4 1495 break;
099fcf2e 1496 case MO_UL:
811d4cf4 1497 default:
a485cff0 1498 tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend);
67dcab73 1499 if (bswap) {
a485cff0 1500 tcg_out_bswap32(s, COND_AL, datalo, datalo);
67dcab73 1501 }
811d4cf4 1502 break;
099fcf2e 1503 case MO_Q:
66c2056f 1504 {
a485cff0
RH		 1505 TCGReg dl = (bswap ? datahi : datalo);
1506 TCGReg dh = (bswap ? datalo : datahi);
66c2056f 1507
1a8e80d7
RH		 1508 /* Avoid ldrd for user-only emulation, to handle unaligned. */
1509 if (USING_SOFTMMU && use_armv6_instructions
1510 && (dl & 1) == 0 && dh == dl + 1) {
a485cff0 1511 tcg_out_ldrd_r(s, COND_AL, dl, addrlo, addend);
66c2056f 1512 } else if (dl != addend) {
a485cff0 1513 tcg_out_ld32_rwb(s, COND_AL, dl, addend, addrlo);
66c2056f
RH		 1514 tcg_out_ld32_12(s, COND_AL, dh, addend, 4);
1515 } else {
1516 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP,
a485cff0 1517 addend, addrlo, SHIFT_IMM_LSL(0));
66c2056f
RH		 1518 tcg_out_ld32_12(s, COND_AL, dl, TCG_REG_TMP, 0);
1519 tcg_out_ld32_12(s, COND_AL, dh, TCG_REG_TMP, 4);
1520 }
1521 if (bswap) {
66c2056f 1522 tcg_out_bswap32(s, COND_AL, dl, dl);
091d5677 1523 tcg_out_bswap32(s, COND_AL, dh, dh);
66c2056f 1524 }
67dcab73 1525 }
811d4cf4
AZ		 1526 break;
1527 }
091d5677 1528}
811d4cf4 1529
091d5677
RH		 1530static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc,
1531 TCGReg datalo, TCGReg datahi,
1532 TCGReg addrlo)
1533{
1534 TCGMemOp bswap = opc & MO_BSWAP;
379f6698 1535
099fcf2e
RH		 1536 switch (opc & MO_SSIZE) {
1537 case MO_UB:
a485cff0 1538 tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0);
811d4cf4 1539 break;
099fcf2e 1540 case MO_SB:
a485cff0 1541 tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0);
811d4cf4 1542 break;
099fcf2e 1543 case MO_UW:
a485cff0 1544 tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
67dcab73 1545 if (bswap) {
a485cff0 1546 tcg_out_bswap16(s, COND_AL, datalo, datalo);
67dcab73 1547 }
811d4cf4 1548 break;
099fcf2e 1549 case MO_SW:
67dcab73 1550 if (bswap) {
a485cff0
RH		 1551 tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
1552 tcg_out_bswap16s(s, COND_AL, datalo, datalo);
67dcab73 1553 } else {
a485cff0 1554 tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
67dcab73 1555 }
811d4cf4 1556 break;
099fcf2e 1557 case MO_UL:
811d4cf4 1558 default:
a485cff0 1559 tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
67dcab73 1560 if (bswap) {
a485cff0 1561 tcg_out_bswap32(s, COND_AL, datalo, datalo);
67dcab73 1562 }
811d4cf4 1563 break;
099fcf2e 1564 case MO_Q:
091d5677
RH		 1565 {
1566 TCGReg dl = (bswap ? datahi : datalo);
1567 TCGReg dh = (bswap ? datalo : datahi);
1568
1a8e80d7
RH		 1569 /* Avoid ldrd for user-only emulation, to handle unaligned. */
1570 if (USING_SOFTMMU && use_armv6_instructions
1571 && (dl & 1) == 0 && dh == dl + 1) {
091d5677
RH		 1572 tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0);
1573 } else if (dl == addrlo) {
1574 tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
1575 tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
1576 } else {
1577 tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
1578 tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
1579 }
1580 if (bswap) {
1581 tcg_out_bswap32(s, COND_AL, dl, dl);
1582 tcg_out_bswap32(s, COND_AL, dh, dh);
1583 }
419bafa5 1584 }
811d4cf4
AZ		 1585 break;
1586 }
811d4cf4
AZ		 1587}
1588
091d5677 1589static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
811d4cf4 1590{
15ecf6e3 1591 TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
59227d5d 1592 TCGMemOpIdx oi;
091d5677 1593 TCGMemOp opc;
811d4cf4 1594#ifdef CONFIG_SOFTMMU
099fcf2e 1595 int mem_index;
15ecf6e3 1596 TCGReg addend;
267c9319 1597 tcg_insn_unit *label_ptr;
811d4cf4 1598#endif
cee87be8 1599
a485cff0 1600 datalo = *args++;
15ecf6e3 1601 datahi = (is64 ? *args++ : 0);
a485cff0 1602 addrlo = *args++;
a485cff0 1603 addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
59227d5d
RH		 1604 oi = *args++;
1605 opc = get_memop(oi);
811d4cf4 1606
15ecf6e3 1607#ifdef CONFIG_SOFTMMU
59227d5d 1608 mem_index = get_mmuidx(oi);
85aa8081 1609 addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1);
091d5677
RH		 1610
1611 /* This a conditional BL only to load a pointer within this opcode into LR
1612 for the slow path. We will not be using the value for a tail call. */
1613 label_ptr = s->code_ptr;
37ee93a9 1614 tcg_out_bl(s, COND_NE, 0);
091d5677
RH		 1615
1616 tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend);
811d4cf4 1617
3972ef6f
RH		 1618 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1619 s->code_ptr, label_ptr);
091d5677 1620#else /* !CONFIG_SOFTMMU */
b76f21a7
LV		 1621 if (guest_base) {
1622 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base);
091d5677
RH		 1623 tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP);
1624 } else {
1625 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo);
1626 }
1627#endif
1628}
1629
1630static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,
1631 TCGReg datalo, TCGReg datahi,
1632 TCGReg addrlo, TCGReg addend)
1633{
1634 TCGMemOp bswap = opc & MO_BSWAP;
1635
1636 switch (opc & MO_SIZE) {
099fcf2e 1637 case MO_8:
091d5677 1638 tcg_out_st8_r(s, cond, datalo, addrlo, addend);
811d4cf4 1639 break;
099fcf2e 1640 case MO_16:
67dcab73 1641 if (bswap) {
091d5677
RH		 1642 tcg_out_bswap16st(s, cond, TCG_REG_R0, datalo);
1643 tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend);
67dcab73 1644 } else {
091d5677 1645 tcg_out_st16_r(s, cond, datalo, addrlo, addend);
67dcab73 1646 }
811d4cf4 1647 break;
099fcf2e 1648 case MO_32:
811d4cf4 1649 default:
67dcab73 1650 if (bswap) {
091d5677
RH		 1651 tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
1652 tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend);
67dcab73 1653 } else {
091d5677 1654 tcg_out_st32_r(s, cond, datalo, addrlo, addend);
67dcab73 1655 }
811d4cf4 1656 break;
099fcf2e 1657 case MO_64:
1a8e80d7 1658 /* Avoid strd for user-only emulation, to handle unaligned. */
67dcab73 1659 if (bswap) {
091d5677
RH		 1660 tcg_out_bswap32(s, cond, TCG_REG_R0, datahi);
1661 tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo);
1662 tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
1663 tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4);
1a8e80d7 1664 } else if (USING_SOFTMMU && use_armv6_instructions
a485cff0 1665 && (datalo & 1) == 0 && datahi == datalo + 1) {
091d5677 1666 tcg_out_strd_r(s, cond, datalo, addrlo, addend);
67dcab73 1667 } else {
091d5677
RH		 1668 tcg_out_st32_rwb(s, cond, datalo, addend, addrlo);
1669 tcg_out_st32_12(s, cond, datahi, addend, 4);
67dcab73 1670 }
811d4cf4
AZ		 1671 break;
1672 }
091d5677 1673}
811d4cf4 1674
091d5677
RH		 1675static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,
1676 TCGReg datalo, TCGReg datahi,
1677 TCGReg addrlo)
1678{
1679 TCGMemOp bswap = opc & MO_BSWAP;
d9f4dde4 1680
091d5677 1681 switch (opc & MO_SIZE) {
099fcf2e 1682 case MO_8:
a485cff0 1683 tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);
811d4cf4 1684 break;
099fcf2e 1685 case MO_16:
67dcab73 1686 if (bswap) {
a485cff0
RH		 1687 tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo);
1688 tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0);
67dcab73 1689 } else {
a485cff0 1690 tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
67dcab73 1691 }
811d4cf4 1692 break;
099fcf2e 1693 case MO_32:
811d4cf4 1694 default:
67dcab73 1695 if (bswap) {
a485cff0
RH		 1696 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
1697 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
67dcab73 1698 } else {
a485cff0 1699 tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
67dcab73 1700 }
811d4cf4 1701 break;
099fcf2e 1702 case MO_64:
1a8e80d7 1703 /* Avoid strd for user-only emulation, to handle unaligned. */
67dcab73 1704 if (bswap) {
a485cff0
RH		 1705 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi);
1706 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
1707 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
1708 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4);
1a8e80d7 1709 } else if (USING_SOFTMMU && use_armv6_instructions
a485cff0
RH		 1710 && (datalo & 1) == 0 && datahi == datalo + 1) {
1711 tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0);
67dcab73 1712 } else {
a485cff0
RH		 1713 tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
1714 tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4);
67dcab73 1715 }
811d4cf4
AZ		 1716 break;
1717 }
091d5677
RH		 1718}
1719
1720static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
1721{
1722 TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
59227d5d 1723 TCGMemOpIdx oi;
091d5677
RH		 1724 TCGMemOp opc;
1725#ifdef CONFIG_SOFTMMU
1726 int mem_index;
1727 TCGReg addend;
267c9319 1728 tcg_insn_unit *label_ptr;
091d5677
RH		 1729#endif
1730
1731 datalo = *args++;
1732 datahi = (is64 ? *args++ : 0);
1733 addrlo = *args++;
1734 addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
59227d5d
RH		 1735 oi = *args++;
1736 opc = get_memop(oi);
091d5677
RH		 1737
1738#ifdef CONFIG_SOFTMMU
59227d5d 1739 mem_index = get_mmuidx(oi);
85aa8081 1740 addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0);
091d5677
RH		 1741
1742 tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend);
1743
1744 /* The conditional call must come last, as we're going to return here. */
1745 label_ptr = s->code_ptr;
37ee93a9 1746 tcg_out_bl(s, COND_NE, 0);
091d5677 1747
3972ef6f
RH		 1748 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1749 s->code_ptr, label_ptr);
091d5677 1750#else /* !CONFIG_SOFTMMU */
b76f21a7
LV		 1751 if (guest_base) {
1752 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base);
091d5677
RH		 1753 tcg_out_qemu_st_index(s, COND_AL, opc, datalo,
1754 datahi, addrlo, TCG_REG_TMP);
1755 } else {
1756 tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo);
1757 }
811d4cf4
AZ		 1758#endif
1759}
1760
267c9319 1761static tcg_insn_unit *tb_ret_addr;
811d4cf4 1762
a9751609 1763static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
811d4cf4
AZ		 1764 const TCGArg *args, const int *const_args)
1765{
2df3f1ee 1766 TCGArg a0, a1, a2, a3, a4, a5;
811d4cf4
AZ		 1767 int c;
1768
1769 switch (opc) {
1770 case INDEX_op_exit_tb:
085c648b
RH		 1771 /* Reuse the zeroing that exists for goto_ptr. */
1772 a0 = args[0];
1773 if (a0 == 0) {
1774 tcg_out_goto(s, COND_AL, s->code_gen_epilogue);
1775 } else {
1776 tcg_out_movi32(s, COND_AL, TCG_REG_R0, args[0]);
1777 tcg_out_goto(s, COND_AL, tb_ret_addr);
1778 }
811d4cf4
AZ		 1779 break;
1780 case INDEX_op_goto_tb:
3fb53fb4 1781 {
811d4cf4 1782 /* Indirect jump method */
308714e6
RH		 1783 intptr_t ptr, dif, dil;
1784 TCGReg base = TCG_REG_PC;
1785
1786 tcg_debug_assert(s->tb_jmp_insn_offset == 0);
1787 ptr = (intptr_t)(s->tb_jmp_target_addr + args[0]);
1788 dif = ptr - ((intptr_t)s->code_ptr + 8);
1789 dil = sextract32(dif, 0, 12);
1790 if (dif != dil) {
1791 /* The TB is close, but outside the 12 bits addressable by
1792 the load. We can extend this to 20 bits with a sub of a
1793 shifted immediate from pc. In the vastly unlikely event
1794 the code requires more than 1MB, we'll use 2 insns and
1795 be no worse off. */
1796 base = TCG_REG_R0;
1797 tcg_out_movi32(s, COND_AL, base, ptr - dil);
1798 }
1799 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil);
9f754620 1800 set_jmp_reset_offset(s, args[0]);
811d4cf4 1801 }
811d4cf4 1802 break;
085c648b
RH		 1803 case INDEX_op_goto_ptr:
1804 tcg_out_bx(s, COND_AL, args[0]);
1805 break;
811d4cf4 1806 case INDEX_op_br:
bec16311 1807 tcg_out_goto_label(s, COND_AL, arg_label(args[0]));
811d4cf4
AZ		 1808 break;
1809
1810 case INDEX_op_ld8u_i32:
1811 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1812 break;
1813 case INDEX_op_ld8s_i32:
1814 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1815 break;
1816 case INDEX_op_ld16u_i32:
1817 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1818 break;
1819 case INDEX_op_ld16s_i32:
1820 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1821 break;
1822 case INDEX_op_ld_i32:
1823 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1824 break;
1825 case INDEX_op_st8_i32:
f694a27e 1826 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1827 break;
1828 case INDEX_op_st16_i32:
f694a27e 1829 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1830 break;
1831 case INDEX_op_st_i32:
1832 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1833 break;
1834
4a1d241e
PM		 1835 case INDEX_op_movcond_i32:
1836 /* Constraints mean that v2 is always in the same register as dest,
1837 * so we only need to do "if condition passed, move v1 to dest".
1838 */
5d53b4c9
RH		 1839 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
1840 args[1], args[2], const_args[2]);
1841 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV,
1842 ARITH_MVN, args[0], 0, args[3], const_args[3]);
4a1d241e 1843 break;
811d4cf4 1844 case INDEX_op_add_i32:
a9a86ae9
RH		 1845 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
1846 args[0], args[1], args[2], const_args[2]);
1847 break;
811d4cf4 1848 case INDEX_op_sub_i32:
d9fda575
RH		 1849 if (const_args[1]) {
1850 if (const_args[2]) {
1851 tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]);
1852 } else {
1853 tcg_out_dat_rI(s, COND_AL, ARITH_RSB,
1854 args[0], args[2], args[1], 1);
1855 }
1856 } else {
1857 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD,
1858 args[0], args[1], args[2], const_args[2]);
1859 }
a9a86ae9 1860 break;
811d4cf4 1861 case INDEX_op_and_i32:
19b62bf4
RH		 1862 tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC,
1863 args[0], args[1], args[2], const_args[2]);
1864 break;
932234f6 1865 case INDEX_op_andc_i32:
19b62bf4
RH		 1866 tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND,
1867 args[0], args[1], args[2], const_args[2]);
1868 break;
811d4cf4
AZ		 1869 case INDEX_op_or_i32:
1870 c = ARITH_ORR;
1871 goto gen_arith;
1872 case INDEX_op_xor_i32:
1873 c = ARITH_EOR;
1874 /* Fall through. */
1875 gen_arith:
7fc645bf 1876 tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]);
811d4cf4
AZ		 1877 break;
1878 case INDEX_op_add2_i32:
2df3f1ee
RH		 1879 a0 = args[0], a1 = args[1], a2 = args[2];
1880 a3 = args[3], a4 = args[4], a5 = args[5];
1881 if (a0 == a3 || (a0 == a5 && !const_args[5])) {
4346457a 1882 a0 = TCG_REG_TMP;
2df3f1ee
RH		 1883 }
1884 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR,
1885 a0, a2, a4, const_args[4]);
1886 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC,
1887 a1, a3, a5, const_args[5]);
1888 tcg_out_mov_reg(s, COND_AL, args[0], a0);
811d4cf4
AZ		 1889 break;
1890 case INDEX_op_sub2_i32:
2df3f1ee
RH		 1891 a0 = args[0], a1 = args[1], a2 = args[2];
1892 a3 = args[3], a4 = args[4], a5 = args[5];
1893 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) {
4346457a 1894 a0 = TCG_REG_TMP;
2df3f1ee
RH		 1895 }
1896 if (const_args[2]) {
1897 if (const_args[4]) {
1898 tcg_out_movi32(s, COND_AL, a0, a4);
1899 a4 = a0;
1900 }
1901 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1);
1902 } else {
1903 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR,
1904 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]);
1905 }
1906 if (const_args[3]) {
1907 if (const_args[5]) {
1908 tcg_out_movi32(s, COND_AL, a1, a5);
1909 a5 = a1;
1910 }
1911 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1);
1912 } else {
1913 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC,
1914 a1, a3, a5, const_args[5]);
1915 }
1916 tcg_out_mov_reg(s, COND_AL, args[0], a0);
811d4cf4 1917 break;
650bbb36
AZ		 1918 case INDEX_op_neg_i32:
1919 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1920 break;
f878d2d2
LD		 1921 case INDEX_op_not_i32:
1922 tcg_out_dat_reg(s, COND_AL,
1923 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1924 break;
811d4cf4
AZ		 1925 case INDEX_op_mul_i32:
1926 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1927 break;
1928 case INDEX_op_mulu2_i32:
1929 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1930 break;
d693e147
RH		 1931 case INDEX_op_muls2_i32:
1932 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1933 break;
811d4cf4
AZ		 1934 /* XXX: Perhaps args[2] & 0x1f is wrong */
1935 case INDEX_op_shl_i32:
1936 c = const_args[2] ?
1937 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1938 goto gen_shift32;
1939 case INDEX_op_shr_i32:
1940 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1941 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1942 goto gen_shift32;
1943 case INDEX_op_sar_i32:
1944 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1945 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
293579e5
AJ		 1946 goto gen_shift32;
1947 case INDEX_op_rotr_i32:
1948 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1949 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
811d4cf4
AZ		 1950 /* Fall through. */
1951 gen_shift32:
1952 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1953 break;
1954
293579e5
AJ		 1955 case INDEX_op_rotl_i32:
1956 if (const_args[2]) {
1957 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1958 ((0x20 - args[2]) & 0x1f) ?
1959 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1960 SHIFT_IMM_LSL(0));
1961 } else {
7a3a0097 1962 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20);
293579e5 1963 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
4346457a 1964 SHIFT_REG_ROR(TCG_REG_TMP));
293579e5
AJ		 1965 }
1966 break;
1967
cc0fec8a
RH		 1968 case INDEX_op_ctz_i32:
1969 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0);
1970 a1 = TCG_REG_TMP;
1971 goto do_clz;
1972
1973 case INDEX_op_clz_i32:
1974 a1 = args[1];
1975 do_clz:
1976 a0 = args[0];
1977 a2 = args[2];
1978 c = const_args[2];
1979 if (c && a2 == 32) {
1980 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0);
1981 break;
1982 }
1983 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0);
1984 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0);
1985 if (c || a0 != a2) {
1986 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c);
1987 }
1988 break;
1989
811d4cf4 1990 case INDEX_op_brcond_i32:
5d53b4c9 1991 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
7fc645bf 1992 args[0], args[1], const_args[1]);
bec16311
RH		 1993 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]],
1994 arg_label(args[3]));
811d4cf4 1995 break;
f72a6cd7 1996 case INDEX_op_setcond_i32:
5d53b4c9
RH		 1997 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
1998 args[1], args[2], const_args[2]);
f72a6cd7
AJ		 1999 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
2000 ARITH_MOV, args[0], 0, 1);
2001 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
2002 ARITH_MOV, args[0], 0, 0);
2003 break;
7170ac33
RH		 2004
2005 case INDEX_op_brcond2_i32:
2006 c = tcg_out_cmp2(s, args, const_args);
2007 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5]));
2008 break;
e0404769 2009 case INDEX_op_setcond2_i32:
7170ac33
RH		 2010 c = tcg_out_cmp2(s, args + 1, const_args + 1);
2011 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1);
2012 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)],
e0404769 2013 ARITH_MOV, args[0], 0, 0);
b525f0a9 2014 break;
811d4cf4 2015
15ecf6e3
RH		 2016 case INDEX_op_qemu_ld_i32:
2017 tcg_out_qemu_ld(s, args, 0);
811d4cf4 2018 break;
15ecf6e3
RH		 2019 case INDEX_op_qemu_ld_i64:
2020 tcg_out_qemu_ld(s, args, 1);
811d4cf4 2021 break;
15ecf6e3
RH		 2022 case INDEX_op_qemu_st_i32:
2023 tcg_out_qemu_st(s, args, 0);
811d4cf4 2024 break;
15ecf6e3
RH		 2025 case INDEX_op_qemu_st_i64:
2026 tcg_out_qemu_st(s, args, 1);
811d4cf4
AZ		 2027 break;
2028
244b1e81
AJ		 2029 case INDEX_op_bswap16_i32:
2030 tcg_out_bswap16(s, COND_AL, args[0], args[1]);
2031 break;
2032 case INDEX_op_bswap32_i32:
2033 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
2034 break;
2035
811d4cf4 2036 case INDEX_op_ext8s_i32:
9517094f 2037 tcg_out_ext8s(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 2038 break;
2039 case INDEX_op_ext16s_i32:
9517094f
AJ		 2040 tcg_out_ext16s(s, COND_AL, args[0], args[1]);
2041 break;
2042 case INDEX_op_ext16u_i32:
2043 tcg_out_ext16u(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 2044 break;
2045
b6b24cb0
RH		 2046 case INDEX_op_deposit_i32:
2047 tcg_out_deposit(s, COND_AL, args[0], args[2],
2048 args[3], args[4], const_args[2]);
2049 break;
ec903af1
RH		 2050 case INDEX_op_extract_i32:
2051 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]);
2052 break;
2053 case INDEX_op_sextract_i32:
2054 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
2055 break;
3b832d67
RH		 2056 case INDEX_op_extract2_i32:
2057 /* ??? These optimization vs zero should be generic. */
2058 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
2059 if (const_args[1]) {
2060 if (const_args[2]) {
2061 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0);
2062 } else {
2063 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
2064 args[2], SHIFT_IMM_LSL(32 - args[3]));
2065 }
2066 } else if (const_args[2]) {
2067 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
2068 args[1], SHIFT_IMM_LSR(args[3]));
2069 } else {
2070 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */
2071 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0,
2072 args[2], SHIFT_IMM_LSL(32 - args[3]));
2073 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP,
2074 args[1], SHIFT_IMM_LSR(args[3]));
2075 }
2076 break;
b6b24cb0 2077
0637c56c
RH		 2078 case INDEX_op_div_i32:
2079 tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]);
2080 break;
2081 case INDEX_op_divu_i32:
2082 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
2083 break;
0637c56c 2084
40f191ab
PK		 2085 case INDEX_op_mb:
2086 tcg_out_mb(s, args[0]);
2087 break;
2088
96d0ee7f
RH		 2089 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2090 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2091 case INDEX_op_call: /* Always emitted via tcg_out_call. */
811d4cf4
AZ		 2092 default:
2093 tcg_abort();
2094 }
2095}
2096
7536b82d
RH		 2097static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2098{
2099 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2100 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2101 static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
2102 static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
2103 static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
2104 static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
2105 static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
2106 static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
2107 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2108 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2109 static const TCGTargetOpDef r_r_rIN
2110 = { .args_ct_str = { "r", "r", "rIN" } };
2111 static const TCGTargetOpDef r_r_rIK
2112 = { .args_ct_str = { "r", "r", "rIK" } };
2113 static const TCGTargetOpDef r_r_r_r
2114 = { .args_ct_str = { "r", "r", "r", "r" } };
2115 static const TCGTargetOpDef r_r_l_l
2116 = { .args_ct_str = { "r", "r", "l", "l" } };
2117 static const TCGTargetOpDef s_s_s_s
2118 = { .args_ct_str = { "s", "s", "s", "s" } };
2119 static const TCGTargetOpDef br
2120 = { .args_ct_str = { "r", "rIN" } };
3b832d67
RH		 2121 static const TCGTargetOpDef ext2
2122 = { .args_ct_str = { "r", "rZ", "rZ" } };
7536b82d
RH		 2123 static const TCGTargetOpDef dep
2124 = { .args_ct_str = { "r", "0", "rZ" } };
2125 static const TCGTargetOpDef movc
2126 = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
2127 static const TCGTargetOpDef add2
2128 = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
2129 static const TCGTargetOpDef sub2
2130 = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
2131 static const TCGTargetOpDef br2
7170ac33 2132 = { .args_ct_str = { "r", "r", "rI", "rI" } };
7536b82d 2133 static const TCGTargetOpDef setc2
7170ac33 2134 = { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
7536b82d
RH		 2135
2136 switch (op) {
2137 case INDEX_op_goto_ptr:
2138 return &r;
811d4cf4 2139
7536b82d
RH		 2140 case INDEX_op_ld8u_i32:
2141 case INDEX_op_ld8s_i32:
2142 case INDEX_op_ld16u_i32:
2143 case INDEX_op_ld16s_i32:
2144 case INDEX_op_ld_i32:
2145 case INDEX_op_st8_i32:
2146 case INDEX_op_st16_i32:
2147 case INDEX_op_st_i32:
2148 case INDEX_op_neg_i32:
2149 case INDEX_op_not_i32:
2150 case INDEX_op_bswap16_i32:
2151 case INDEX_op_bswap32_i32:
2152 case INDEX_op_ext8s_i32:
2153 case INDEX_op_ext16s_i32:
2154 case INDEX_op_ext16u_i32:
2155 case INDEX_op_extract_i32:
2156 case INDEX_op_sextract_i32:
2157 return &r_r;
b6b24cb0 2158
7536b82d
RH		 2159 case INDEX_op_add_i32:
2160 case INDEX_op_sub_i32:
2161 case INDEX_op_setcond_i32:
2162 return &r_r_rIN;
2163 case INDEX_op_and_i32:
2164 case INDEX_op_andc_i32:
2165 case INDEX_op_clz_i32:
2166 case INDEX_op_ctz_i32:
2167 return &r_r_rIK;
2168 case INDEX_op_mul_i32:
2169 case INDEX_op_div_i32:
2170 case INDEX_op_divu_i32:
2171 return &r_r_r;
2172 case INDEX_op_mulu2_i32:
2173 case INDEX_op_muls2_i32:
2174 return &r_r_r_r;
2175 case INDEX_op_or_i32:
2176 case INDEX_op_xor_i32:
2177 return &r_r_rI;
2178 case INDEX_op_shl_i32:
2179 case INDEX_op_shr_i32:
2180 case INDEX_op_sar_i32:
2181 case INDEX_op_rotl_i32:
2182 case INDEX_op_rotr_i32:
2183 return &r_r_ri;
0637c56c 2184
7536b82d
RH		 2185 case INDEX_op_brcond_i32:
2186 return &br;
2187 case INDEX_op_deposit_i32:
2188 return &dep;
3b832d67
RH		 2189 case INDEX_op_extract2_i32:
2190 return &ext2;
7536b82d
RH		 2191 case INDEX_op_movcond_i32:
2192 return &movc;
2193 case INDEX_op_add2_i32:
2194 return &add2;
2195 case INDEX_op_sub2_i32:
2196 return &sub2;
2197 case INDEX_op_brcond2_i32:
2198 return &br2;
2199 case INDEX_op_setcond2_i32:
2200 return &setc2;
811d4cf4 2201
7536b82d
RH		 2202 case INDEX_op_qemu_ld_i32:
2203 return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
2204 case INDEX_op_qemu_ld_i64:
2205 return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
2206 case INDEX_op_qemu_st_i32:
2207 return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
2208 case INDEX_op_qemu_st_i64:
2209 return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
f69d277e 2210
7536b82d
RH		 2211 default:
2212 return NULL;
f69d277e 2213 }
f69d277e
RH		 2214}
2215
e4d58b41 2216static void tcg_target_init(TCGContext *s)
811d4cf4 2217{
1e709f38
RH		 2218 /* Only probe for the platform and capabilities if we havn't already
2219 determined maximum values at compile time. */
41d9ea80 2220#ifndef use_idiv_instructions
72e1ccfc 2221 {
41d9ea80 2222 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
72e1ccfc
RH		 2223 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
2224 }
41d9ea80 2225#endif
1e709f38 2226 if (__ARM_ARCH < 7) {
41d9ea80 2227 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
1e709f38
RH		 2228 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
2229 arm_arch = pl[1] - '0';
2230 }
2231 }
72e1ccfc 2232
f46934df
RH		 2233 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
2234
2235 tcg_target_call_clobber_regs = 0;
2236 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
2237 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
2238 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
2239 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
2240 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
2241 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
811d4cf4 2242
ccb1bb66 2243 s->reserved_regs = 0;
811d4cf4 2244 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
4346457a 2245 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
e4a7d5e8 2246 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
811d4cf4
AZ		 2247}
2248
2a534aff 2249static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
a05b5b9b 2250 TCGReg arg1, intptr_t arg2)
811d4cf4
AZ		 2251{
2252 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
2253}
2254
2a534aff 2255static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
a05b5b9b 2256 TCGReg arg1, intptr_t arg2)
811d4cf4
AZ		 2257{
2258 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
2259}
2260
59d7c14e
RH		 2261static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
2262 TCGReg base, intptr_t ofs)
2263{
2264 return false;
2265}
2266
2a534aff
RH		 2267static inline void tcg_out_mov(TCGContext *s, TCGType type,
2268 TCGReg ret, TCGReg arg)
811d4cf4
AZ		 2269{
2270 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
2271}
2272
2273static inline void tcg_out_movi(TCGContext *s, TCGType type,
2a534aff 2274 TCGReg ret, tcg_target_long arg)
811d4cf4
AZ		 2275{
2276 tcg_out_movi32(s, COND_AL, ret, arg);
2277}
2278
880ad962
RH		 2279static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
2280{
2281 int i;
2282 for (i = 0; i < count; ++i) {
2283 p[i] = INSN_NOP;
2284 }
2285}
2286
0caa91fe
RH		 2287/* Compute frame size via macros, to share between tcg_target_qemu_prologue
2288 and tcg_register_jit. */
2289
2290#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long))
2291
2292#define FRAME_SIZE \
2293 ((PUSH_SIZE \
2294 + TCG_STATIC_CALL_ARGS_SIZE \
2295 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
2296 + TCG_TARGET_STACK_ALIGN - 1) \
2297 & -TCG_TARGET_STACK_ALIGN)
2298
e4d58b41 2299static void tcg_target_qemu_prologue(TCGContext *s)
811d4cf4 2300{
0caa91fe 2301 int stack_addend;
fc4d60ee
RH		 2302
2303 /* Calling convention requires us to save r4-r11 and lr. */
2304 /* stmdb sp!, { r4 - r11, lr } */
2305 tcg_out32(s, (COND_AL << 28) | 0x092d4ff0);
cea5f9a2 2306
0caa91fe
RH		 2307 /* Reserve callee argument and tcg temp space. */
2308 stack_addend = FRAME_SIZE - PUSH_SIZE;
fc4d60ee
RH		 2309
2310 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK,
0caa91fe 2311 TCG_REG_CALL_STACK, stack_addend, 1);
fc4d60ee
RH		 2312 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2313 CPU_TEMP_BUF_NLONGS * sizeof(long));
4e17eae9 2314
cea5f9a2 2315 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
811d4cf4 2316
cea5f9a2 2317 tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]);
811d4cf4 2318
085c648b
RH		 2319 /*
2320 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2321 * and fall through to the rest of the epilogue.
2322 */
2323 s->code_gen_epilogue = s->code_ptr;
2324 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0);
2325
2326 /* TB epilogue */
2327 tb_ret_addr = s->code_ptr;
fc4d60ee 2328 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK,
0caa91fe 2329 TCG_REG_CALL_STACK, stack_addend, 1);
fc4d60ee
RH		 2330
2331 /* ldmia sp!, { r4 - r11, pc } */
2332 tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0);
811d4cf4 2333}
0caa91fe
RH		 2334
2335typedef struct {
16959741 2336 DebugFrameHeader h;
0caa91fe
RH		 2337 uint8_t fde_def_cfa[4];
2338 uint8_t fde_reg_ofs[18];
2339} DebugFrame;
2340
2341#define ELF_HOST_MACHINE EM_ARM
2342
2343/* We're expecting a 2 byte uleb128 encoded value. */
2344QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2345
16959741
RH		 2346static const DebugFrame debug_frame = {
2347 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2348 .h.cie.id = -1,
2349 .h.cie.version = 1,
2350 .h.cie.code_align = 1,
2351 .h.cie.data_align = 0x7c, /* sleb128 -4 */
2352 .h.cie.return_column = 14,
0caa91fe
RH		 2353
2354 /* Total FDE size does not include the "len" member. */
16959741 2355 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
0caa91fe
RH		 2356
2357 .fde_def_cfa = {
2358 12, 13, /* DW_CFA_def_cfa sp, ... */
2359 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2360 (FRAME_SIZE >> 7)
2361 },
2362 .fde_reg_ofs = {
2363 /* The following must match the stmdb in the prologue. */
2364 0x8e, 1, /* DW_CFA_offset, lr, -4 */
2365 0x8b, 2, /* DW_CFA_offset, r11, -8 */
2366 0x8a, 3, /* DW_CFA_offset, r10, -12 */
2367 0x89, 4, /* DW_CFA_offset, r9, -16 */
2368 0x88, 5, /* DW_CFA_offset, r8, -20 */
2369 0x87, 6, /* DW_CFA_offset, r7, -24 */
2370 0x86, 7, /* DW_CFA_offset, r6, -28 */
2371 0x85, 8, /* DW_CFA_offset, r5, -32 */
2372 0x84, 9, /* DW_CFA_offset, r4, -36 */
2373 }
2374};
2375
2376void tcg_register_jit(void *buf, size_t buf_size)
2377{
0caa91fe
RH		 2378 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2379}
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