projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 1bcfbf03 WX |
1 | /* |
| 2 | * Tiny Code Generator for QEMU | |
| 3 | * | |
| 4 | * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> | |
| 5 | * | |
| 6 | * Based on tcg/riscv/tcg-target.c.inc | |
| 7 | * | |
| 8 | * Copyright (c) 2018 SiFive, Inc | |
| 9 | * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> | |
| 10 | * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> | |
| 11 | * Copyright (c) 2008 Fabrice Bellard | |
| 12 | * | |
| 13 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 14 | * of this software and associated documentation files (the "Software"), to deal | |
| 15 | * in the Software without restriction, including without limitation the rights | |
| 16 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 17 | * copies of the Software, and to permit persons to whom the Software is | |
| 18 | * furnished to do so, subject to the following conditions: | |
| 19 | * | |
| 20 | * The above copyright notice and this permission notice shall be included in | |
| 21 | * all copies or substantial portions of the Software. | |
| 22 | * | |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 26 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 27 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 28 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 29 | * THE SOFTWARE. | |
| 30 | */ | |
| 31 | ||
| 32 | #ifdef CONFIG_DEBUG_TCG | |
| 33 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { | |
| 34 | "zero", | |
| 35 | "ra", | |
| 36 | "tp", | |
| 37 | "sp", | |
| 38 | "a0", | |
| 39 | "a1", | |
| 40 | "a2", | |
| 41 | "a3", | |
| 42 | "a4", | |
| 43 | "a5", | |
| 44 | "a6", | |
| 45 | "a7", | |
| 46 | "t0", | |
| 47 | "t1", | |
| 48 | "t2", | |
| 49 | "t3", | |
| 50 | "t4", | |
| 51 | "t5", | |
| 52 | "t6", | |
| 53 | "t7", | |
| 54 | "t8", | |
| 55 | "r21", /* reserved in the LP64* ABI, hence no ABI name */ | |
| 56 | "s9", | |
| 57 | "s0", | |
| 58 | "s1", | |
| 59 | "s2", | |
| 60 | "s3", | |
| 61 | "s4", | |
| 62 | "s5", | |
| 63 | "s6", | |
| 64 | "s7", | |
| 65 | "s8" | |
| 66 | }; | |
| 67 | #endif | |
| 68 | ||
| 69 | static const int tcg_target_reg_alloc_order[] = { | |
| 70 | /* Registers preserved across calls */ | |
| 71 | /* TCG_REG_S0 reserved for TCG_AREG0 */ | |
| 72 | TCG_REG_S1, | |
| 73 | TCG_REG_S2, | |
| 74 | TCG_REG_S3, | |
| 75 | TCG_REG_S4, | |
| 76 | TCG_REG_S5, | |
| 77 | TCG_REG_S6, | |
| 78 | TCG_REG_S7, | |
| 79 | TCG_REG_S8, | |
| 80 | TCG_REG_S9, | |
| 81 | ||
| 82 | /* Registers (potentially) clobbered across calls */ | |
| 83 | TCG_REG_T0, | |
| 84 | TCG_REG_T1, | |
| 85 | TCG_REG_T2, | |
| 86 | TCG_REG_T3, | |
| 87 | TCG_REG_T4, | |
| 88 | TCG_REG_T5, | |
| 89 | TCG_REG_T6, | |
| 90 | TCG_REG_T7, | |
| 91 | TCG_REG_T8, | |
| 92 | ||
| 93 | /* Argument registers, opposite order of allocation. */ | |
| 94 | TCG_REG_A7, | |
| 95 | TCG_REG_A6, | |
| 96 | TCG_REG_A5, | |
| 97 | TCG_REG_A4, | |
| 98 | TCG_REG_A3, | |
| 99 | TCG_REG_A2, | |
| 100 | TCG_REG_A1, | |
| 101 | TCG_REG_A0, | |
| 102 | }; | |
| 103 | ||
| 104 | static const int tcg_target_call_iarg_regs[] = { | |
| 105 | TCG_REG_A0, | |
| 106 | TCG_REG_A1, | |
| 107 | TCG_REG_A2, | |
| 108 | TCG_REG_A3, | |
| 109 | TCG_REG_A4, | |
| 110 | TCG_REG_A5, | |
| 111 | TCG_REG_A6, | |
| 112 | TCG_REG_A7, | |
| 113 | }; | |
| 114 | ||
| 115 | static const int tcg_target_call_oarg_regs[] = { | |
| 116 | TCG_REG_A0, | |
| 117 | TCG_REG_A1, | |
| 118 | }; | |
| ba0cdd80 WX |
119 | |
| 120 | #define TCG_CT_CONST_ZERO 0x100 | |
| 121 | #define TCG_CT_CONST_S12 0x200 | |
| 122 | #define TCG_CT_CONST_N12 0x400 | |
| 123 | #define TCG_CT_CONST_U12 0x800 | |
| 124 | #define TCG_CT_CONST_C12 0x1000 | |
| 125 | #define TCG_CT_CONST_WSZ 0x2000 | |
| 126 | ||
| 127 | #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) | |
| 128 | /* | |
| 129 | * For softmmu, we need to avoid conflicts with the first 5 | |
| 130 | * argument registers to call the helper. Some of these are | |
| 131 | * also used for the tlb lookup. | |
| 132 | */ | |
| 133 | #ifdef CONFIG_SOFTMMU | |
| 134 | #define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) | |
| 135 | #else | |
| 136 | #define SOFTMMU_RESERVE_REGS 0 | |
| 137 | #endif | |
| 138 | ||
| 139 | ||
| 140 | static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) | |
| 141 | { | |
| 142 | return sextract64(val, pos, len); | |
| 143 | } | |
| 144 | ||
| 145 | /* test if a constant matches the constraint */ | |
| 146 | static bool tcg_target_const_match(int64_t val, TCGType type, int ct) | |
| 147 | { | |
| 148 | if (ct & TCG_CT_CONST) { | |
| 149 | return true; | |
| 150 | } | |
| 151 | if ((ct & TCG_CT_CONST_ZERO) && val == 0) { | |
| 152 | return true; | |
| 153 | } | |
| 154 | if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { | |
| 155 | return true; | |
| 156 | } | |
| 157 | if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { | |
| 158 | return true; | |
| 159 | } | |
| 160 | if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { | |
| 161 | return true; | |
| 162 | } | |
| 163 | if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { | |
| 164 | return true; | |
| 165 | } | |
| 166 | if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { | |
| 167 | return true; | |
| 168 | } | |
| 169 | return false; | |
| 170 | } | |
| bf8c1c81 WX |
171 | |
| 172 | /* | |
| 173 | * Relocations | |
| 174 | */ | |
| 175 | ||
| 176 | /* | |
| 177 | * Relocation records defined in LoongArch ELF psABI v1.00 is way too | |
| 178 | * complicated; a whopping stack machine is needed to stuff the fields, at | |
| 179 | * the very least one SOP_PUSH and one SOP_POP (of the correct format) are | |
| 180 | * needed. | |
| 181 | * | |
| 182 | * Hence, define our own simpler relocation types. Numbers are chosen as to | |
| 183 | * not collide with potential future additions to the true ELF relocation | |
| 184 | * type enum. | |
| 185 | */ | |
| 186 | ||
| 187 | /* Field Sk16, shifted right by 2; suitable for conditional jumps */ | |
| 188 | #define R_LOONGARCH_BR_SK16 256 | |
| 189 | /* Field Sd10k16, shifted right by 2; suitable for B and BL */ | |
| 190 | #define R_LOONGARCH_BR_SD10K16 257 | |
| 191 | ||
| 192 | static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) | |
| 193 | { | |
| 194 | const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); | |
| 195 | intptr_t offset = (intptr_t)target - (intptr_t)src_rx; | |
| 196 | ||
| 197 | tcg_debug_assert((offset & 3) == 0); | |
| 198 | offset >>= 2; | |
| 199 | if (offset == sextreg(offset, 0, 16)) { | |
| 200 | *src_rw = deposit64(*src_rw, 10, 16, offset); | |
| 201 | return true; | |
| 202 | } | |
| 203 | ||
| 204 | return false; | |
| 205 | } | |
| 206 | ||
| 207 | static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, | |
| 208 | const tcg_insn_unit *target) | |
| 209 | { | |
| 210 | const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); | |
| 211 | intptr_t offset = (intptr_t)target - (intptr_t)src_rx; | |
| 212 | ||
| 213 | tcg_debug_assert((offset & 3) == 0); | |
| 214 | offset >>= 2; | |
| 215 | if (offset == sextreg(offset, 0, 26)) { | |
| 216 | *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ | |
| 217 | *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ | |
| 218 | return true; | |
| 219 | } | |
| 220 | ||
| 221 | return false; | |
| 222 | } | |
| 223 | ||
| 224 | static bool patch_reloc(tcg_insn_unit *code_ptr, int type, | |
| 225 | intptr_t value, intptr_t addend) | |
| 226 | { | |
| 227 | tcg_debug_assert(addend == 0); | |
| 228 | switch (type) { | |
| 229 | case R_LOONGARCH_BR_SK16: | |
| 230 | return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); | |
| 231 | case R_LOONGARCH_BR_SD10K16: | |
| 232 | return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); | |
| 233 | default: | |
| 234 | g_assert_not_reached(); | |
| 235 | } | |
| 236 | } | |
| fae2361d WX |
237 | |
| 238 | #include "tcg-insn-defs.c.inc" | |
| 239 | ||
| 240 | /* | |
| 241 | * TCG intrinsics | |
| 242 | */ | |
| 243 | ||
| 244 | static void tcg_out_mb(TCGContext *s, TCGArg a0) | |
| 245 | { | |
| 246 | /* Baseline LoongArch only has the full barrier, unfortunately. */ | |
| 247 | tcg_out_opc_dbar(s, 0); | |
| 248 | } | |
| 249 | ||
| dacc5172 WX |
250 | static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) |
| 251 | { | |
| 252 | if (ret == arg) { | |
| 253 | return true; | |
| 254 | } | |
| 255 | switch (type) { | |
| 256 | case TCG_TYPE_I32: | |
| 257 | case TCG_TYPE_I64: | |
| 258 | /* | |
| 259 | * Conventional register-register move used in LoongArch is | |
| 260 | * `or dst, src, zero`. | |
| 261 | */ | |
| 262 | tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); | |
| 263 | break; | |
| 264 | default: | |
| 265 | g_assert_not_reached(); | |
| 266 | } | |
| 267 | return true; | |
| 268 | } | |
| 269 | ||
| 270 | static bool imm_part_needs_loading(bool high_bits_are_ones, | |
| 271 | tcg_target_long part) | |
| 272 | { | |
| 273 | if (high_bits_are_ones) { | |
| 274 | return part != -1; | |
| 275 | } else { | |
| 276 | return part != 0; | |
| 277 | } | |
| 278 | } | |
| 279 | ||
| 280 | /* Loads a 32-bit immediate into rd, sign-extended. */ | |
| 281 | static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) | |
| 282 | { | |
| 283 | tcg_target_long lo = sextreg(val, 0, 12); | |
| 284 | tcg_target_long hi12 = sextreg(val, 12, 20); | |
| 285 | ||
| 286 | /* Single-instruction cases. */ | |
| 287 | if (lo == val) { | |
| 288 | /* val fits in simm12: addi.w rd, zero, val */ | |
| 289 | tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); | |
| 290 | return; | |
| 291 | } | |
| 292 | if (0x800 <= val && val <= 0xfff) { | |
| 293 | /* val fits in uimm12: ori rd, zero, val */ | |
| 294 | tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); | |
| 295 | return; | |
| 296 | } | |
| 297 | ||
| 298 | /* High bits must be set; load with lu12i.w + optional ori. */ | |
| 299 | tcg_out_opc_lu12i_w(s, rd, hi12); | |
| 300 | if (lo != 0) { | |
| 301 | tcg_out_opc_ori(s, rd, rd, lo & 0xfff); | |
| 302 | } | |
| 303 | } | |
| 304 | ||
| 305 | static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, | |
| 306 | tcg_target_long val) | |
| 307 | { | |
| 308 | /* | |
| 309 | * LoongArch conventionally loads 64-bit immediates in at most 4 steps, | |
| 310 | * with dedicated instructions for filling the respective bitfields | |
| 311 | * below: | |
| 312 | * | |
| 313 | * 6 5 4 3 | |
| 314 | * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 | |
| 315 | * +-----------------------+---------------------------------------+... | |
| 316 | * | hi52 | hi32 | | |
| 317 | * +-----------------------+---------------------------------------+... | |
| 318 | * 3 2 1 | |
| 319 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
| 320 | * ...+-------------------------------------+-------------------------+ | |
| 321 | * | hi12 | lo | | |
| 322 | * ...+-------------------------------------+-------------------------+ | |
| 323 | * | |
| 324 | * Check if val belong to one of the several fast cases, before falling | |
| 325 | * back to the slow path. | |
| 326 | */ | |
| 327 | ||
| 328 | intptr_t pc_offset; | |
| 329 | tcg_target_long val_lo, val_hi, pc_hi, offset_hi; | |
| 330 | tcg_target_long hi32, hi52; | |
| 331 | bool rd_high_bits_are_ones; | |
| 332 | ||
| 333 | /* Value fits in signed i32. */ | |
| 334 | if (type == TCG_TYPE_I32 || val == (int32_t)val) { | |
| 335 | tcg_out_movi_i32(s, rd, val); | |
| 336 | return; | |
| 337 | } | |
| 338 | ||
| 339 | /* PC-relative cases. */ | |
| 340 | pc_offset = tcg_pcrel_diff(s, (void *)val); | |
| 341 | if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) { | |
| 342 | /* Single pcaddu2i. */ | |
| 343 | tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); | |
| 344 | return; | |
| 345 | } | |
| 346 | ||
| 347 | if (pc_offset == (int32_t)pc_offset) { | |
| 348 | /* Offset within 32 bits; load with pcalau12i + ori. */ | |
| 349 | val_lo = sextreg(val, 0, 12); | |
| 350 | val_hi = val >> 12; | |
| 351 | pc_hi = (val - pc_offset) >> 12; | |
| 352 | offset_hi = val_hi - pc_hi; | |
| 353 | ||
| 354 | tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20)); | |
| 355 | tcg_out_opc_pcalau12i(s, rd, offset_hi); | |
| 356 | if (val_lo != 0) { | |
| 357 | tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff); | |
| 358 | } | |
| 359 | return; | |
| 360 | } | |
| 361 | ||
| 362 | hi32 = sextreg(val, 32, 20); | |
| 363 | hi52 = sextreg(val, 52, 12); | |
| 364 | ||
| 365 | /* Single cu52i.d case. */ | |
| 366 | if (ctz64(val) >= 52) { | |
| 367 | tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); | |
| 368 | return; | |
| 369 | } | |
| 370 | ||
| 371 | /* Slow path. Initialize the low 32 bits, then concat high bits. */ | |
| 372 | tcg_out_movi_i32(s, rd, val); | |
| 373 | rd_high_bits_are_ones = (int32_t)val < 0; | |
| 374 | ||
| 375 | if (imm_part_needs_loading(rd_high_bits_are_ones, hi32)) { | |
| 376 | tcg_out_opc_cu32i_d(s, rd, hi32); | |
| 377 | rd_high_bits_are_ones = hi32 < 0; | |
| 378 | } | |
| 379 | ||
| 380 | if (imm_part_needs_loading(rd_high_bits_are_ones, hi52)) { | |
| 381 | tcg_out_opc_cu52i_d(s, rd, rd, hi52); | |
| 382 | } | |
| 383 | } | |
| 384 | ||
| 6be08fcf WX |
385 | static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) |
| 386 | { | |
| 387 | tcg_out_opc_andi(s, ret, arg, 0xff); | |
| 388 | } | |
| 389 | ||
| 390 | static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) | |
| 391 | { | |
| 392 | tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); | |
| 393 | } | |
| 394 | ||
| 395 | static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) | |
| 396 | { | |
| 397 | tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); | |
| 398 | } | |
| 399 | ||
| 400 | static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) | |
| 401 | { | |
| 402 | tcg_out_opc_sext_b(s, ret, arg); | |
| 403 | } | |
| 404 | ||
| 405 | static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) | |
| 406 | { | |
| 407 | tcg_out_opc_sext_h(s, ret, arg); | |
| 408 | } | |
| 409 | ||
| 410 | static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) | |
| 411 | { | |
| 412 | tcg_out_opc_addi_w(s, ret, arg, 0); | |
| 413 | } | |
| 414 | ||
| fde69301 WX |
415 | static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, |
| 416 | TCGReg a0, TCGReg a1, TCGReg a2, | |
| 417 | bool c2, bool is_32bit) | |
| 418 | { | |
| 419 | if (c2) { | |
| 420 | /* | |
| 421 | * Fast path: semantics already satisfied due to constraint and | |
| 422 | * insn behavior, single instruction is enough. | |
| 423 | */ | |
| 424 | tcg_debug_assert(a2 == (is_32bit ? 32 : 64)); | |
| 425 | /* all clz/ctz insns belong to DJ-format */ | |
| 426 | tcg_out32(s, encode_dj_insn(opc, a0, a1)); | |
| 427 | return; | |
| 428 | } | |
| 429 | ||
| 430 | tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1)); | |
| 431 | /* a0 = a1 ? REG_TMP0 : a2 */ | |
| 432 | tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); | |
| 433 | tcg_out_opc_masknez(s, a0, a2, a1); | |
| 434 | tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); | |
| 435 | } | |
| 436 | ||
| 94505c02 WX |
437 | /* |
| 438 | * Branch helpers | |
| 439 | */ | |
| 440 | ||
| 441 | static const struct { | |
| 442 | LoongArchInsn op; | |
| 443 | bool swap; | |
| 444 | } tcg_brcond_to_loongarch[] = { | |
| 445 | [TCG_COND_EQ] = { OPC_BEQ, false }, | |
| 446 | [TCG_COND_NE] = { OPC_BNE, false }, | |
| 447 | [TCG_COND_LT] = { OPC_BGT, true }, | |
| 448 | [TCG_COND_GE] = { OPC_BLE, true }, | |
| 449 | [TCG_COND_LE] = { OPC_BLE, false }, | |
| 450 | [TCG_COND_GT] = { OPC_BGT, false }, | |
| 451 | [TCG_COND_LTU] = { OPC_BGTU, true }, | |
| 452 | [TCG_COND_GEU] = { OPC_BLEU, true }, | |
| 453 | [TCG_COND_LEU] = { OPC_BLEU, false }, | |
| 454 | [TCG_COND_GTU] = { OPC_BGTU, false } | |
| 455 | }; | |
| 456 | ||
| 457 | static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, | |
| 458 | TCGReg arg2, TCGLabel *l) | |
| 459 | { | |
| 460 | LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; | |
| 461 | ||
| 462 | tcg_debug_assert(op != 0); | |
| 463 | ||
| 464 | if (tcg_brcond_to_loongarch[cond].swap) { | |
| 465 | TCGReg t = arg1; | |
| 466 | arg1 = arg2; | |
| 467 | arg2 = t; | |
| 468 | } | |
| 469 | ||
| 470 | /* all conditional branch insns belong to DJSk16-format */ | |
| 471 | tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); | |
| 472 | tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); | |
| 473 | } | |
| 474 | ||
| fae2361d WX |
475 | /* |
| 476 | * Entry-points | |
| 477 | */ | |
| 478 | ||
| 479 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, | |
| 480 | const TCGArg args[TCG_MAX_OP_ARGS], | |
| 481 | const int const_args[TCG_MAX_OP_ARGS]) | |
| 482 | { | |
| 483 | TCGArg a0 = args[0]; | |
| 6be08fcf | 484 | TCGArg a1 = args[1]; |
| 97b2fafb WX |
485 | TCGArg a2 = args[2]; |
| 486 | int c2 = const_args[2]; | |
| fae2361d WX |
487 | |
| 488 | switch (opc) { | |
| 489 | case INDEX_op_mb: | |
| 490 | tcg_out_mb(s, a0); | |
| 491 | break; | |
| 492 | ||
| e3b15766 WX |
493 | case INDEX_op_goto_ptr: |
| 494 | tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); | |
| 495 | break; | |
| 496 | ||
| 94505c02 WX |
497 | case INDEX_op_br: |
| 498 | tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), | |
| 499 | 0); | |
| 500 | tcg_out_opc_b(s, 0); | |
| 501 | break; | |
| 502 | ||
| 503 | case INDEX_op_brcond_i32: | |
| 504 | case INDEX_op_brcond_i64: | |
| 505 | tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); | |
| 506 | break; | |
| 507 | ||
| 6be08fcf WX |
508 | case INDEX_op_ext8s_i32: |
| 509 | case INDEX_op_ext8s_i64: | |
| 510 | tcg_out_ext8s(s, a0, a1); | |
| 511 | break; | |
| 512 | ||
| 513 | case INDEX_op_ext8u_i32: | |
| 514 | case INDEX_op_ext8u_i64: | |
| 515 | tcg_out_ext8u(s, a0, a1); | |
| 516 | break; | |
| 517 | ||
| 518 | case INDEX_op_ext16s_i32: | |
| 519 | case INDEX_op_ext16s_i64: | |
| 520 | tcg_out_ext16s(s, a0, a1); | |
| 521 | break; | |
| 522 | ||
| 523 | case INDEX_op_ext16u_i32: | |
| 524 | case INDEX_op_ext16u_i64: | |
| 525 | tcg_out_ext16u(s, a0, a1); | |
| 526 | break; | |
| 527 | ||
| 528 | case INDEX_op_ext32u_i64: | |
| 529 | case INDEX_op_extu_i32_i64: | |
| 530 | tcg_out_ext32u(s, a0, a1); | |
| 531 | break; | |
| 532 | ||
| 533 | case INDEX_op_ext32s_i64: | |
| 534 | case INDEX_op_extrl_i64_i32: | |
| 535 | case INDEX_op_ext_i32_i64: | |
| 536 | tcg_out_ext32s(s, a0, a1); | |
| 537 | break; | |
| 538 | ||
| 539 | case INDEX_op_extrh_i64_i32: | |
| 540 | tcg_out_opc_srai_d(s, a0, a1, 32); | |
| 541 | break; | |
| 542 | ||
| 97b2fafb WX |
543 | case INDEX_op_not_i32: |
| 544 | case INDEX_op_not_i64: | |
| 545 | tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO); | |
| 546 | break; | |
| 547 | ||
| 548 | case INDEX_op_nor_i32: | |
| 549 | case INDEX_op_nor_i64: | |
| 550 | if (c2) { | |
| 551 | tcg_out_opc_ori(s, a0, a1, a2); | |
| 552 | tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO); | |
| 553 | } else { | |
| 554 | tcg_out_opc_nor(s, a0, a1, a2); | |
| 555 | } | |
| 556 | break; | |
| 557 | ||
| 558 | case INDEX_op_andc_i32: | |
| 559 | case INDEX_op_andc_i64: | |
| 560 | if (c2) { | |
| 561 | /* guaranteed to fit due to constraint */ | |
| 562 | tcg_out_opc_andi(s, a0, a1, ~a2); | |
| 563 | } else { | |
| 564 | tcg_out_opc_andn(s, a0, a1, a2); | |
| 565 | } | |
| 566 | break; | |
| 567 | ||
| 568 | case INDEX_op_orc_i32: | |
| 569 | case INDEX_op_orc_i64: | |
| 570 | if (c2) { | |
| 571 | /* guaranteed to fit due to constraint */ | |
| 572 | tcg_out_opc_ori(s, a0, a1, ~a2); | |
| 573 | } else { | |
| 574 | tcg_out_opc_orn(s, a0, a1, a2); | |
| 575 | } | |
| 576 | break; | |
| 577 | ||
| 578 | case INDEX_op_and_i32: | |
| 579 | case INDEX_op_and_i64: | |
| 580 | if (c2) { | |
| 581 | tcg_out_opc_andi(s, a0, a1, a2); | |
| 582 | } else { | |
| 583 | tcg_out_opc_and(s, a0, a1, a2); | |
| 584 | } | |
| 585 | break; | |
| 586 | ||
| 587 | case INDEX_op_or_i32: | |
| 588 | case INDEX_op_or_i64: | |
| 589 | if (c2) { | |
| 590 | tcg_out_opc_ori(s, a0, a1, a2); | |
| 591 | } else { | |
| 592 | tcg_out_opc_or(s, a0, a1, a2); | |
| 593 | } | |
| 594 | break; | |
| 595 | ||
| 596 | case INDEX_op_xor_i32: | |
| 597 | case INDEX_op_xor_i64: | |
| 598 | if (c2) { | |
| 599 | tcg_out_opc_xori(s, a0, a1, a2); | |
| 600 | } else { | |
| 601 | tcg_out_opc_xor(s, a0, a1, a2); | |
| 602 | } | |
| 603 | break; | |
| 604 | ||
| 7257809f WX |
605 | case INDEX_op_extract_i32: |
| 606 | tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); | |
| 607 | break; | |
| 608 | case INDEX_op_extract_i64: | |
| 609 | tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); | |
| 610 | break; | |
| 611 | ||
| 612 | case INDEX_op_deposit_i32: | |
| 613 | tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); | |
| 614 | break; | |
| 615 | case INDEX_op_deposit_i64: | |
| 616 | tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); | |
| 617 | break; | |
| 618 | ||
| 4ab2aff0 WX |
619 | case INDEX_op_bswap16_i32: |
| 620 | case INDEX_op_bswap16_i64: | |
| 621 | tcg_out_opc_revb_2h(s, a0, a1); | |
| 622 | if (a2 & TCG_BSWAP_OS) { | |
| 623 | tcg_out_ext16s(s, a0, a0); | |
| 624 | } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { | |
| 625 | tcg_out_ext16u(s, a0, a0); | |
| 626 | } | |
| 627 | break; | |
| 628 | ||
| 629 | case INDEX_op_bswap32_i32: | |
| 630 | /* All 32-bit values are computed sign-extended in the register. */ | |
| 631 | a2 = TCG_BSWAP_OS; | |
| 632 | /* fallthrough */ | |
| 633 | case INDEX_op_bswap32_i64: | |
| 634 | tcg_out_opc_revb_2w(s, a0, a1); | |
| 635 | if (a2 & TCG_BSWAP_OS) { | |
| 636 | tcg_out_ext32s(s, a0, a0); | |
| 637 | } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { | |
| 638 | tcg_out_ext32u(s, a0, a0); | |
| 639 | } | |
| 640 | break; | |
| 641 | ||
| 642 | case INDEX_op_bswap64_i64: | |
| 643 | tcg_out_opc_revb_d(s, a0, a1); | |
| 644 | break; | |
| 645 | ||
| fde69301 WX |
646 | case INDEX_op_clz_i32: |
| 647 | tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true); | |
| 648 | break; | |
| 649 | case INDEX_op_clz_i64: | |
| 650 | tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false); | |
| 651 | break; | |
| 652 | ||
| 653 | case INDEX_op_ctz_i32: | |
| 654 | tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true); | |
| 655 | break; | |
| 656 | case INDEX_op_ctz_i64: | |
| 657 | tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false); | |
| 658 | break; | |
| 659 | ||
| a164010b WX |
660 | case INDEX_op_shl_i32: |
| 661 | if (c2) { | |
| 662 | tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); | |
| 663 | } else { | |
| 664 | tcg_out_opc_sll_w(s, a0, a1, a2); | |
| 665 | } | |
| 666 | break; | |
| 667 | case INDEX_op_shl_i64: | |
| 668 | if (c2) { | |
| 669 | tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); | |
| 670 | } else { | |
| 671 | tcg_out_opc_sll_d(s, a0, a1, a2); | |
| 672 | } | |
| 673 | break; | |
| 674 | ||
| 675 | case INDEX_op_shr_i32: | |
| 676 | if (c2) { | |
| 677 | tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); | |
| 678 | } else { | |
| 679 | tcg_out_opc_srl_w(s, a0, a1, a2); | |
| 680 | } | |
| 681 | break; | |
| 682 | case INDEX_op_shr_i64: | |
| 683 | if (c2) { | |
| 684 | tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); | |
| 685 | } else { | |
| 686 | tcg_out_opc_srl_d(s, a0, a1, a2); | |
| 687 | } | |
| 688 | break; | |
| 689 | ||
| 690 | case INDEX_op_sar_i32: | |
| 691 | if (c2) { | |
| 692 | tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); | |
| 693 | } else { | |
| 694 | tcg_out_opc_sra_w(s, a0, a1, a2); | |
| 695 | } | |
| 696 | break; | |
| 697 | case INDEX_op_sar_i64: | |
| 698 | if (c2) { | |
| 699 | tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); | |
| 700 | } else { | |
| 701 | tcg_out_opc_sra_d(s, a0, a1, a2); | |
| 702 | } | |
| 703 | break; | |
| 704 | ||
| 705 | case INDEX_op_rotl_i32: | |
| 706 | /* transform into equivalent rotr/rotri */ | |
| 707 | if (c2) { | |
| 708 | tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f); | |
| 709 | } else { | |
| 710 | tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); | |
| 711 | tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0); | |
| 712 | } | |
| 713 | break; | |
| 714 | case INDEX_op_rotl_i64: | |
| 715 | /* transform into equivalent rotr/rotri */ | |
| 716 | if (c2) { | |
| 717 | tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f); | |
| 718 | } else { | |
| 719 | tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); | |
| 720 | tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0); | |
| 721 | } | |
| 722 | break; | |
| 723 | ||
| 724 | case INDEX_op_rotr_i32: | |
| 725 | if (c2) { | |
| 726 | tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); | |
| 727 | } else { | |
| 728 | tcg_out_opc_rotr_w(s, a0, a1, a2); | |
| 729 | } | |
| 730 | break; | |
| 731 | case INDEX_op_rotr_i64: | |
| 732 | if (c2) { | |
| 733 | tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); | |
| 734 | } else { | |
| 735 | tcg_out_opc_rotr_d(s, a0, a1, a2); | |
| 736 | } | |
| 737 | break; | |
| 738 | ||
| 39f54ce5 WX |
739 | case INDEX_op_add_i32: |
| 740 | if (c2) { | |
| 741 | tcg_out_opc_addi_w(s, a0, a1, a2); | |
| 742 | } else { | |
| 743 | tcg_out_opc_add_w(s, a0, a1, a2); | |
| 744 | } | |
| 745 | break; | |
| 746 | case INDEX_op_add_i64: | |
| 747 | if (c2) { | |
| 748 | tcg_out_opc_addi_d(s, a0, a1, a2); | |
| 749 | } else { | |
| 750 | tcg_out_opc_add_d(s, a0, a1, a2); | |
| 751 | } | |
| 752 | break; | |
| 753 | ||
| 754 | case INDEX_op_sub_i32: | |
| 755 | if (c2) { | |
| 756 | tcg_out_opc_addi_w(s, a0, a1, -a2); | |
| 757 | } else { | |
| 758 | tcg_out_opc_sub_w(s, a0, a1, a2); | |
| 759 | } | |
| 760 | break; | |
| 761 | case INDEX_op_sub_i64: | |
| 762 | if (c2) { | |
| 763 | tcg_out_opc_addi_d(s, a0, a1, -a2); | |
| 764 | } else { | |
| 765 | tcg_out_opc_sub_d(s, a0, a1, a2); | |
| 766 | } | |
| 767 | break; | |
| 768 | ||
| ff13c196 WX |
769 | case INDEX_op_mul_i32: |
| 770 | tcg_out_opc_mul_w(s, a0, a1, a2); | |
| 771 | break; | |
| 772 | case INDEX_op_mul_i64: | |
| 773 | tcg_out_opc_mul_d(s, a0, a1, a2); | |
| 774 | break; | |
| 775 | ||
| 776 | case INDEX_op_mulsh_i32: | |
| 777 | tcg_out_opc_mulh_w(s, a0, a1, a2); | |
| 778 | break; | |
| 779 | case INDEX_op_mulsh_i64: | |
| 780 | tcg_out_opc_mulh_d(s, a0, a1, a2); | |
| 781 | break; | |
| 782 | ||
| 783 | case INDEX_op_muluh_i32: | |
| 784 | tcg_out_opc_mulh_wu(s, a0, a1, a2); | |
| 785 | break; | |
| 786 | case INDEX_op_muluh_i64: | |
| 787 | tcg_out_opc_mulh_du(s, a0, a1, a2); | |
| 788 | break; | |
| 789 | ||
| 790 | case INDEX_op_div_i32: | |
| 791 | tcg_out_opc_div_w(s, a0, a1, a2); | |
| 792 | break; | |
| 793 | case INDEX_op_div_i64: | |
| 794 | tcg_out_opc_div_d(s, a0, a1, a2); | |
| 795 | break; | |
| 796 | ||
| 797 | case INDEX_op_divu_i32: | |
| 798 | tcg_out_opc_div_wu(s, a0, a1, a2); | |
| 799 | break; | |
| 800 | case INDEX_op_divu_i64: | |
| 801 | tcg_out_opc_div_du(s, a0, a1, a2); | |
| 802 | break; | |
| 803 | ||
| 804 | case INDEX_op_rem_i32: | |
| 805 | tcg_out_opc_mod_w(s, a0, a1, a2); | |
| 806 | break; | |
| 807 | case INDEX_op_rem_i64: | |
| 808 | tcg_out_opc_mod_d(s, a0, a1, a2); | |
| 809 | break; | |
| 810 | ||
| 811 | case INDEX_op_remu_i32: | |
| 812 | tcg_out_opc_mod_wu(s, a0, a1, a2); | |
| 813 | break; | |
| 814 | case INDEX_op_remu_i64: | |
| 815 | tcg_out_opc_mod_du(s, a0, a1, a2); | |
| 816 | break; | |
| 817 | ||
| dacc5172 WX |
818 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ |
| 819 | case INDEX_op_mov_i64: | |
| fae2361d WX |
820 | default: |
| 821 | g_assert_not_reached(); | |
| 822 | } | |
| 823 | } | |
| e3b15766 WX |
824 | |
| 825 | static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) | |
| 826 | { | |
| 827 | switch (op) { | |
| 828 | case INDEX_op_goto_ptr: | |
| 829 | return C_O0_I1(r); | |
| 830 | ||
| 94505c02 WX |
831 | case INDEX_op_brcond_i32: |
| 832 | case INDEX_op_brcond_i64: | |
| 833 | return C_O0_I2(rZ, rZ); | |
| 834 | ||
| 6be08fcf WX |
835 | case INDEX_op_ext8s_i32: |
| 836 | case INDEX_op_ext8s_i64: | |
| 837 | case INDEX_op_ext8u_i32: | |
| 838 | case INDEX_op_ext8u_i64: | |
| 839 | case INDEX_op_ext16s_i32: | |
| 840 | case INDEX_op_ext16s_i64: | |
| 841 | case INDEX_op_ext16u_i32: | |
| 842 | case INDEX_op_ext16u_i64: | |
| 843 | case INDEX_op_ext32s_i64: | |
| 844 | case INDEX_op_ext32u_i64: | |
| 845 | case INDEX_op_extu_i32_i64: | |
| 846 | case INDEX_op_extrl_i64_i32: | |
| 847 | case INDEX_op_extrh_i64_i32: | |
| 848 | case INDEX_op_ext_i32_i64: | |
| 97b2fafb WX |
849 | case INDEX_op_not_i32: |
| 850 | case INDEX_op_not_i64: | |
| 7257809f WX |
851 | case INDEX_op_extract_i32: |
| 852 | case INDEX_op_extract_i64: | |
| 4ab2aff0 WX |
853 | case INDEX_op_bswap16_i32: |
| 854 | case INDEX_op_bswap16_i64: | |
| 855 | case INDEX_op_bswap32_i32: | |
| 856 | case INDEX_op_bswap32_i64: | |
| 857 | case INDEX_op_bswap64_i64: | |
| 6be08fcf WX |
858 | return C_O1_I1(r, r); |
| 859 | ||
| 97b2fafb WX |
860 | case INDEX_op_andc_i32: |
| 861 | case INDEX_op_andc_i64: | |
| 862 | case INDEX_op_orc_i32: | |
| 863 | case INDEX_op_orc_i64: | |
| 864 | /* | |
| 865 | * LoongArch insns for these ops don't have reg-imm forms, but we | |
| 866 | * can express using andi/ori if ~constant satisfies | |
| 867 | * TCG_CT_CONST_U12. | |
| 868 | */ | |
| 869 | return C_O1_I2(r, r, rC); | |
| 870 | ||
| a164010b WX |
871 | case INDEX_op_shl_i32: |
| 872 | case INDEX_op_shl_i64: | |
| 873 | case INDEX_op_shr_i32: | |
| 874 | case INDEX_op_shr_i64: | |
| 875 | case INDEX_op_sar_i32: | |
| 876 | case INDEX_op_sar_i64: | |
| 877 | case INDEX_op_rotl_i32: | |
| 878 | case INDEX_op_rotl_i64: | |
| 879 | case INDEX_op_rotr_i32: | |
| 880 | case INDEX_op_rotr_i64: | |
| 881 | return C_O1_I2(r, r, ri); | |
| 882 | ||
| 39f54ce5 WX |
883 | case INDEX_op_add_i32: |
| 884 | case INDEX_op_add_i64: | |
| 885 | return C_O1_I2(r, r, rI); | |
| 886 | ||
| 97b2fafb WX |
887 | case INDEX_op_and_i32: |
| 888 | case INDEX_op_and_i64: | |
| 889 | case INDEX_op_nor_i32: | |
| 890 | case INDEX_op_nor_i64: | |
| 891 | case INDEX_op_or_i32: | |
| 892 | case INDEX_op_or_i64: | |
| 893 | case INDEX_op_xor_i32: | |
| 894 | case INDEX_op_xor_i64: | |
| 895 | /* LoongArch reg-imm bitops have their imms ZERO-extended */ | |
| 896 | return C_O1_I2(r, r, rU); | |
| 897 | ||
| fde69301 WX |
898 | case INDEX_op_clz_i32: |
| 899 | case INDEX_op_clz_i64: | |
| 900 | case INDEX_op_ctz_i32: | |
| 901 | case INDEX_op_ctz_i64: | |
| 902 | return C_O1_I2(r, r, rW); | |
| 903 | ||
| 7257809f WX |
904 | case INDEX_op_deposit_i32: |
| 905 | case INDEX_op_deposit_i64: | |
| 906 | /* Must deposit into the same register as input */ | |
| 907 | return C_O1_I2(r, 0, rZ); | |
| 908 | ||
| 39f54ce5 WX |
909 | case INDEX_op_sub_i32: |
| 910 | case INDEX_op_sub_i64: | |
| 911 | return C_O1_I2(r, rZ, rN); | |
| 912 | ||
| ff13c196 WX |
913 | case INDEX_op_mul_i32: |
| 914 | case INDEX_op_mul_i64: | |
| 915 | case INDEX_op_mulsh_i32: | |
| 916 | case INDEX_op_mulsh_i64: | |
| 917 | case INDEX_op_muluh_i32: | |
| 918 | case INDEX_op_muluh_i64: | |
| 919 | case INDEX_op_div_i32: | |
| 920 | case INDEX_op_div_i64: | |
| 921 | case INDEX_op_divu_i32: | |
| 922 | case INDEX_op_divu_i64: | |
| 923 | case INDEX_op_rem_i32: | |
| 924 | case INDEX_op_rem_i64: | |
| 925 | case INDEX_op_remu_i32: | |
| 926 | case INDEX_op_remu_i64: | |
| 927 | return C_O1_I2(r, rZ, rZ); | |
| 928 | ||
| e3b15766 WX |
929 | default: |
| 930 | g_assert_not_reached(); | |
| 931 | } | |
| 932 | } |