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Merge tag 'pull-ppc-20230918' of https://gitlab.com/danielhb/qemu into staging
[mirror_qemu.git] / tcg / mips / tcg-target.c.inc
CommitLineData
afa05235
AJ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
23a79c11 27#include "../tcg-ldst.c.inc"
48c12ba7 28#include "../tcg-pool.c.inc"
23a79c11 29
f0d70331 30#if TCG_TARGET_REG_BITS == 32
b56d5a8a 31# define LO_OFF (HOST_BIG_ENDIAN * 4)
f0d70331
JG		 32# define HI_OFF (4 - LO_OFF)
33#else
c64ed451
RH		 34/* Assert at compile-time that these values are never used for 64-bit. */
35# define LO_OFF ({ qemu_build_not_reached(); 0; })
36# define HI_OFF ({ qemu_build_not_reached(); 0; })
f0d70331 37#endif
9d8bf2d1 38
8d8fdbae 39#ifdef CONFIG_DEBUG_TCG
afa05235
AJ		 40static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
41 "zero",
42 "at",
43 "v0",
44 "v1",
45 "a0",
46 "a1",
47 "a2",
48 "a3",
49 "t0",
50 "t1",
51 "t2",
52 "t3",
53 "t4",
54 "t5",
55 "t6",
56 "t7",
57 "s0",
58 "s1",
59 "s2",
60 "s3",
61 "s4",
62 "s5",
63 "s6",
64 "s7",
65 "t8",
66 "t9",
67 "k0",
68 "k1",
69 "gp",
70 "sp",
41883904 71 "s8",
afa05235
AJ		 72 "ra",
73};
74#endif
75
6c530e32 76#define TCG_TMP0 TCG_REG_AT
f216a35f 77#define TCG_TMP1 TCG_REG_T9
bb08afe9
JG		 78#define TCG_TMP2 TCG_REG_T8
79#define TCG_TMP3 TCG_REG_T7
6c530e32 80
4df9cac5 81#ifndef CONFIG_SOFTMMU
43b4cd97 82#define TCG_GUEST_BASE_REG TCG_REG_S7
4df9cac5 83#endif
53c4fa27
RH		 84#if TCG_TARGET_REG_BITS == 64
85#define TCG_REG_TB TCG_REG_S6
86#else
87#define TCG_REG_TB (qemu_build_not_reached(), TCG_REG_ZERO)
88#endif
4df9cac5 89
afa05235 90/* check if we really need so many registers :P */
2dc7553d 91static const int tcg_target_reg_alloc_order[] = {
41883904 92 /* Call saved registers. */
afa05235
AJ		 93 TCG_REG_S0,
94 TCG_REG_S1,
95 TCG_REG_S2,
96 TCG_REG_S3,
97 TCG_REG_S4,
98 TCG_REG_S5,
99 TCG_REG_S6,
100 TCG_REG_S7,
41883904
RH		 101 TCG_REG_S8,
102
103 /* Call clobbered registers. */
afa05235
AJ		 104 TCG_REG_T4,
105 TCG_REG_T5,
106 TCG_REG_T6,
107 TCG_REG_T7,
108 TCG_REG_T8,
109 TCG_REG_T9,
41883904 110 TCG_REG_V1,
afa05235 111 TCG_REG_V0,
41883904
RH		 112
113 /* Argument registers, opposite order of allocation. */
999b9416
JG		 114 TCG_REG_T3,
115 TCG_REG_T2,
116 TCG_REG_T1,
117 TCG_REG_T0,
41883904
RH		 118 TCG_REG_A3,
119 TCG_REG_A2,
120 TCG_REG_A1,
121 TCG_REG_A0,
afa05235
AJ		 122};
123
999b9416 124static const TCGReg tcg_target_call_iarg_regs[] = {
afa05235
AJ		 125 TCG_REG_A0,
126 TCG_REG_A1,
127 TCG_REG_A2,
999b9416
JG		 128 TCG_REG_A3,
129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
130 TCG_REG_T0,
131 TCG_REG_T1,
132 TCG_REG_T2,
133 TCG_REG_T3,
134#endif
afa05235
AJ		 135};
136
5e3d0c19
RH		 137static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
138{
139 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
140 tcg_debug_assert(slot >= 0 && slot <= 1);
141 return TCG_REG_V0 + slot;
142}
afa05235 143
df5af130
RH		 144static const tcg_insn_unit *tb_ret_addr;
145static const tcg_insn_unit *bswap32_addr;
146static const tcg_insn_unit *bswap32u_addr;
147static const tcg_insn_unit *bswap64_addr;
afa05235 148
df5af130 149static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
afa05235 150{
ae0218e3 151 /* Let the compiler perform the right-shift as part of the arithmetic. */
df5af130
RH		 152 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
153 ptrdiff_t disp = target - (src_rx + 1);
91a7fd1f 154 if (disp == (int16_t)disp) {
df5af130 155 *src_rw = deposit32(*src_rw, 0, 16, disp);
91a7fd1f
RH		 156 return true;
157 }
158 return false;
afa05235
AJ		 159}
160
6ac17786 161static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
2ba7fae2 162 intptr_t value, intptr_t addend)
afa05235 163{
48c12ba7
RH		 164 value += addend;
165 switch (type) {
166 case R_MIPS_PC16:
167 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
168 case R_MIPS_16:
169 if (value != (int16_t)value) {
170 return false;
171 }
172 *code_ptr = deposit32(*code_ptr, 0, 16, value);
173 return true;
174 }
175 g_assert_not_reached();
afa05235
AJ		 176}
177
1c418268 178#define TCG_CT_CONST_ZERO 0x100
070603f6
RH		 179#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
180#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
181#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
182#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
2a1d9d41 183#define TCG_CT_CONST_WSZ 0x2000 /* word size */
1c418268 184
51800e43 185#define ALL_GENERAL_REGS 0xffffffffu
51800e43 186
10d4af58 187static bool is_p2m1(tcg_target_long val)
1c418268
RH		 188{
189 return val && ((val + 1) & val) == 0;
190}
191
afa05235 192/* test if a constant matches the constraint */
ebe92db2 193static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
afa05235 194{
1c418268 195 if (ct & TCG_CT_CONST) {
afa05235 196 return 1;
1c418268 197 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
afa05235 198 return 1;
1c418268 199 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
afa05235 200 return 1;
1c418268 201 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
afa05235 202 return 1;
070603f6
RH		 203 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
204 return 1;
1c418268
RH		 205 } else if ((ct & TCG_CT_CONST_P2M1)
206 && use_mips32r2_instructions && is_p2m1(val)) {
207 return 1;
2a1d9d41
RH		 208 } else if ((ct & TCG_CT_CONST_WSZ)
209 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
210 return 1;
1c418268
RH		 211 }
212 return 0;
afa05235
AJ		 213}
214
215/* instruction opcodes */
ac0f3b12 216typedef enum {
57a701fc
JG		 217 OPC_J = 002 << 26,
218 OPC_JAL = 003 << 26,
219 OPC_BEQ = 004 << 26,
220 OPC_BNE = 005 << 26,
221 OPC_BLEZ = 006 << 26,
222 OPC_BGTZ = 007 << 26,
223 OPC_ADDIU = 011 << 26,
224 OPC_SLTI = 012 << 26,
225 OPC_SLTIU = 013 << 26,
226 OPC_ANDI = 014 << 26,
227 OPC_ORI = 015 << 26,
228 OPC_XORI = 016 << 26,
229 OPC_LUI = 017 << 26,
23a79c11
RH		 230 OPC_BNEL = 025 << 26,
231 OPC_BNEZALC_R6 = 030 << 26,
57a701fc 232 OPC_DADDIU = 031 << 26,
23a79c11
RH		 233 OPC_LDL = 032 << 26,
234 OPC_LDR = 033 << 26,
57a701fc
JG		 235 OPC_LB = 040 << 26,
236 OPC_LH = 041 << 26,
23a79c11 237 OPC_LWL = 042 << 26,
57a701fc
JG		 238 OPC_LW = 043 << 26,
239 OPC_LBU = 044 << 26,
240 OPC_LHU = 045 << 26,
23a79c11 241 OPC_LWR = 046 << 26,
57a701fc
JG		 242 OPC_LWU = 047 << 26,
243 OPC_SB = 050 << 26,
244 OPC_SH = 051 << 26,
23a79c11 245 OPC_SWL = 052 << 26,
57a701fc 246 OPC_SW = 053 << 26,
23a79c11
RH		 247 OPC_SDL = 054 << 26,
248 OPC_SDR = 055 << 26,
249 OPC_SWR = 056 << 26,
57a701fc
JG		 250 OPC_LD = 067 << 26,
251 OPC_SD = 077 << 26,
252
253 OPC_SPECIAL = 000 << 26,
254 OPC_SLL = OPC_SPECIAL | 000,
255 OPC_SRL = OPC_SPECIAL | 002,
256 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
257 OPC_SRA = OPC_SPECIAL | 003,
258 OPC_SLLV = OPC_SPECIAL | 004,
259 OPC_SRLV = OPC_SPECIAL | 006,
260 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
261 OPC_SRAV = OPC_SPECIAL | 007,
262 OPC_JR_R5 = OPC_SPECIAL | 010,
263 OPC_JALR = OPC_SPECIAL | 011,
264 OPC_MOVZ = OPC_SPECIAL | 012,
265 OPC_MOVN = OPC_SPECIAL | 013,
266 OPC_SYNC = OPC_SPECIAL | 017,
267 OPC_MFHI = OPC_SPECIAL | 020,
268 OPC_MFLO = OPC_SPECIAL | 022,
269 OPC_DSLLV = OPC_SPECIAL | 024,
270 OPC_DSRLV = OPC_SPECIAL | 026,
271 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
272 OPC_DSRAV = OPC_SPECIAL | 027,
273 OPC_MULT = OPC_SPECIAL | 030,
274 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
275 OPC_MUH = OPC_SPECIAL | 030 | 0300,
276 OPC_MULTU = OPC_SPECIAL | 031,
277 OPC_MULU = OPC_SPECIAL | 031 | 0200,
278 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
279 OPC_DIV = OPC_SPECIAL | 032,
280 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
281 OPC_MOD = OPC_SPECIAL | 032 | 0300,
282 OPC_DIVU = OPC_SPECIAL | 033,
283 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
284 OPC_MODU = OPC_SPECIAL | 033 | 0300,
285 OPC_DMULT = OPC_SPECIAL | 034,
286 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
287 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
288 OPC_DMULTU = OPC_SPECIAL | 035,
289 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
290 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
291 OPC_DDIV = OPC_SPECIAL | 036,
292 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
293 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
294 OPC_DDIVU = OPC_SPECIAL | 037,
295 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
296 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
297 OPC_ADDU = OPC_SPECIAL | 041,
298 OPC_SUBU = OPC_SPECIAL | 043,
299 OPC_AND = OPC_SPECIAL | 044,
300 OPC_OR = OPC_SPECIAL | 045,
301 OPC_XOR = OPC_SPECIAL | 046,
302 OPC_NOR = OPC_SPECIAL | 047,
303 OPC_SLT = OPC_SPECIAL | 052,
304 OPC_SLTU = OPC_SPECIAL | 053,
305 OPC_DADDU = OPC_SPECIAL | 055,
306 OPC_DSUBU = OPC_SPECIAL | 057,
307 OPC_SELEQZ = OPC_SPECIAL | 065,
308 OPC_SELNEZ = OPC_SPECIAL | 067,
309 OPC_DSLL = OPC_SPECIAL | 070,
310 OPC_DSRL = OPC_SPECIAL | 072,
311 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
312 OPC_DSRA = OPC_SPECIAL | 073,
313 OPC_DSLL32 = OPC_SPECIAL | 074,
314 OPC_DSRL32 = OPC_SPECIAL | 076,
315 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
316 OPC_DSRA32 = OPC_SPECIAL | 077,
2a1d9d41
RH		 317 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
318 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
57a701fc
JG		 319
320 OPC_REGIMM = 001 << 26,
321 OPC_BLTZ = OPC_REGIMM | (000 << 16),
322 OPC_BGEZ = OPC_REGIMM | (001 << 16),
323
324 OPC_SPECIAL2 = 034 << 26,
325 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
2a1d9d41
RH		 326 OPC_CLZ = OPC_SPECIAL2 | 040,
327 OPC_DCLZ = OPC_SPECIAL2 | 044,
57a701fc
JG		 328
329 OPC_SPECIAL3 = 037 << 26,
330 OPC_EXT = OPC_SPECIAL3 | 000,
331 OPC_DEXTM = OPC_SPECIAL3 | 001,
332 OPC_DEXTU = OPC_SPECIAL3 | 002,
333 OPC_DEXT = OPC_SPECIAL3 | 003,
334 OPC_INS = OPC_SPECIAL3 | 004,
335 OPC_DINSM = OPC_SPECIAL3 | 005,
336 OPC_DINSU = OPC_SPECIAL3 | 006,
337 OPC_DINS = OPC_SPECIAL3 | 007,
338 OPC_WSBH = OPC_SPECIAL3 | 00240,
339 OPC_DSBH = OPC_SPECIAL3 | 00244,
340 OPC_DSHD = OPC_SPECIAL3 | 00544,
341 OPC_SEB = OPC_SPECIAL3 | 02040,
342 OPC_SEH = OPC_SPECIAL3 | 03040,
6e0d0969
JH		 343
344 /* MIPS r6 doesn't have JR, JALR should be used instead */
345 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
bc6d0c22
JH		 346
347 /*
348 * MIPS r6 replaces MUL with an alternative encoding which is
349 * backwards-compatible at the assembly level.
350 */
351 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
6f0b9910
PK		 352
353 /* MIPS r6 introduced names for weaker variants of SYNC. These are
354 backward compatible to previous architecture revisions. */
a4e57084 355 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
356 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
357 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
358 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
359 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
57a701fc
JG		 360
361 /* Aliases for convenience. */
362 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
363 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
ac0f3b12 364} MIPSInsn;
afa05235
AJ		 365
366/*
367 * Type reg
368 */
10d4af58
RH		 369static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
370 TCGReg rd, TCGReg rs, TCGReg rt)
afa05235
AJ		 371{
372 int32_t inst;
373
374 inst = opc;
375 inst |= (rs & 0x1F) << 21;
376 inst |= (rt & 0x1F) << 16;
377 inst |= (rd & 0x1F) << 11;
378 tcg_out32(s, inst);
379}
380
381/*
382 * Type immediate
383 */
10d4af58
RH		 384static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
385 TCGReg rt, TCGReg rs, TCGArg imm)
afa05235
AJ		 386{
387 int32_t inst;
388
389 inst = opc;
390 inst |= (rs & 0x1F) << 21;
391 inst |= (rt & 0x1F) << 16;
392 inst |= (imm & 0xffff);
393 tcg_out32(s, inst);
394}
395
1c418268
RH		 396/*
397 * Type bitfield
398 */
10d4af58
RH		 399static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
400 TCGReg rs, int msb, int lsb)
1c418268
RH		 401{
402 int32_t inst;
403
404 inst = opc;
405 inst |= (rs & 0x1F) << 21;
406 inst |= (rt & 0x1F) << 16;
407 inst |= (msb & 0x1F) << 11;
408 inst |= (lsb & 0x1F) << 6;
409 tcg_out32(s, inst);
410}
411
10d4af58
RH		 412static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
413 MIPSInsn oph, TCGReg rt, TCGReg rs,
0119b192
JG		 414 int msb, int lsb)
415{
416 if (lsb >= 32) {
417 opc = oph;
418 msb -= 32;
419 lsb -= 32;
420 } else if (msb >= 32) {
421 opc = opm;
422 msb -= 32;
423 }
424 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
425}
426
6d8ff4d8
AJ		 427/*
428 * Type branch
429 */
10d4af58 430static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
6d8ff4d8 431{
8c1b0792 432 tcg_out_opc_imm(s, opc, rt, rs, 0);
6d8ff4d8
AJ		 433}
434
afa05235
AJ		 435/*
436 * Type sa
437 */
10d4af58
RH		 438static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
439 TCGReg rd, TCGReg rt, TCGArg sa)
afa05235
AJ		 440{
441 int32_t inst;
442
443 inst = opc;
444 inst |= (rt & 0x1F) << 16;
445 inst |= (rd & 0x1F) << 11;
446 inst |= (sa & 0x1F) << 6;
447 tcg_out32(s, inst);
448
449}
450
0119b192
JG		 451static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
452 TCGReg rd, TCGReg rt, TCGArg sa)
453{
454 int32_t inst;
455
456 inst = (sa & 32 ? opc2 : opc1);
457 inst |= (rt & 0x1F) << 16;
458 inst |= (rd & 0x1F) << 11;
459 inst |= (sa & 0x1F) << 6;
460 tcg_out32(s, inst);
461}
462
f8c9eddb
RH		 463/*
464 * Type jump.
465 * Returns true if the branch was in range and the insn was emitted.
466 */
2be7d76b 467static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
f8c9eddb
RH		 468{
469 uintptr_t dest = (uintptr_t)target;
df5af130 470 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4;
f8c9eddb
RH		 471 int32_t inst;
472
473 /* The pc-region branch happens within the 256MB region of
474 the delay slot (thus the +4). */
475 if ((from ^ dest) & -(1 << 28)) {
476 return false;
477 }
eabb7b91 478 tcg_debug_assert((dest & 3) == 0);
f8c9eddb
RH		 479
480 inst = opc;
481 inst |= (dest >> 2) & 0x3ffffff;
482 tcg_out32(s, inst);
483 return true;
484}
485
10d4af58 486static void tcg_out_nop(TCGContext *s)
afa05235
AJ		 487{
488 tcg_out32(s, 0);
489}
490
48c12ba7
RH		 491static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
492{
493 memset(p, 0, count * sizeof(tcg_insn_unit));
494}
495
10d4af58 496static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
0119b192
JG		 497{
498 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
499}
500
10d4af58 501static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
0119b192
JG		 502{
503 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
504}
505
10d4af58 506static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
0119b192
JG		 507{
508 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
509}
510
10d4af58 511static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
afa05235 512{
18fec301
AJ		 513 /* Simple reg-reg move, optimising out the 'do nothing' case */
514 if (ret != arg) {
2294d05d 515 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
18fec301 516 }
78113e83 517 return true;
afa05235
AJ		 518}
519
47a57286 520static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
afa05235
AJ		 521{
522 if (arg == (int16_t)arg) {
2294d05d 523 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
47a57286 524 return true;
2294d05d
JG		 525 }
526 if (arg == (uint16_t)arg) {
527 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
47a57286
RH		 528 return true;
529 }
530 if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
531 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
532 return true;
533 }
534 return false;
535}
536
1d9c5b30
RH		 537static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg)
538{
539 /*
540 * All signed 32-bit constants are loadable with two immediates,
541 * and everything else requires more work.
542 */
543 if (arg == (int32_t)arg) {
544 if (!tcg_out_movi_one(s, ret, arg)) {
545 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
546 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
547 }
548 return true;
549 }
550 return false;
551}
552
48c12ba7
RH		 553static void tcg_out_movi_pool(TCGContext *s, TCGReg ret,
554 tcg_target_long arg, TCGReg tbreg)
555{
556 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL));
557 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0);
558}
559
560static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
561 tcg_target_long arg, TCGReg tbreg)
47a57286 562{
1d159e64 563 tcg_target_long tmp;
269e93ab 564 int sh, lo;
1d159e64 565
47a57286
RH		 566 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
567 arg = (int32_t)arg;
568 }
569
1d9c5b30
RH		 570 /* Load all 32-bit constants. */
571 if (tcg_out_movi_two(s, ret, arg)) {
2294d05d
JG		 572 return;
573 }
48c12ba7 574 assert(TCG_TARGET_REG_BITS == 64);
47a57286 575
1d159e64
RH		 576 /* Load addresses within 2GB of TB with 1 or 3 insns. */
577 tmp = tcg_tbrel_diff(s, (void *)arg);
578 if (tmp == (int16_t)tmp) {
579 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp);
580 return;
581 }
582 if (tcg_out_movi_two(s, ret, tmp)) {
583 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg);
584 return;
585 }
586
269e93ab
RH		 587 /*
588 * Load bitmasks with a right-shift. This is good for things
589 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4.
590 * or similarly using LUI. For this to work, bit 31 must be set.
591 */
592 if (arg > 0 && (int32_t)arg < 0) {
593 sh = clz64(arg);
594 if (tcg_out_movi_one(s, ret, arg << sh)) {
595 tcg_out_dsrl(s, ret, ret, sh);
596 return;
597 }
598 }
599
600 /*
601 * Load slightly larger constants using left-shift.
602 * Limit this sequence to 3 insns to avoid too much expansion.
603 */
604 sh = ctz64(arg);
605 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) {
606 tcg_out_dsll(s, ret, ret, sh);
607 return;
608 }
609
610 /*
611 * Load slightly larger constants using left-shift and add/or.
612 * Prefer addi with a negative immediate when that would produce
613 * a larger shift. For this to work, bits 15 and 16 must be set.
614 */
615 lo = arg & 0xffff;
616 if (lo) {
617 if ((arg & 0x18000) == 0x18000) {
618 lo = (int16_t)arg;
619 }
620 tmp = arg - lo;
621 sh = ctz64(tmp);
622 tmp >>= sh;
623 if (tcg_out_movi_one(s, ret, tmp)) {
624 tcg_out_dsll(s, ret, ret, sh);
625 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo);
626 return;
627 }
628 }
629
48c12ba7
RH		 630 /* Otherwise, put 64-bit constants into the constant pool. */
631 tcg_out_movi_pool(s, ret, arg, tbreg);
632}
633
634static void tcg_out_movi(TCGContext *s, TCGType type,
635 TCGReg ret, tcg_target_long arg)
636{
637 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0;
638 tcg_out_movi_int(s, type, ret, arg, tbreg);
afa05235
AJ		 639}
640
678155b2
RH		 641static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
642{
643 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32);
644 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs);
645}
646
d0e66c89
RH		 647static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs)
648{
649 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff);
650}
651
753e42ea
RH		 652static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
653{
654 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32);
655 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs);
656}
657
379afdff
RH		 658static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs)
659{
660 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff);
661}
662
52bf3398
RH		 663static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs)
664{
665 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
666 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0);
667}
668
9c6aa274
RH		 669static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
670{
c6a98619
RH		 671 if (rd != rs) {
672 tcg_out_ext32s(s, rd, rs);
673 }
9c6aa274
RH		 674}
675
b9bfe000
RH		 676static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
677{
678 tcg_out_ext32u(s, rd, rs);
679}
680
b8b94ac6
RH		 681static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
682{
683 tcg_out_ext32s(s, rd, rs);
684}
685
767c2503
RH		 686static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
687{
688 return false;
689}
690
6a6d772e
RH		 691static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
692 tcg_target_long imm)
693{
694 /* This function is only used for passing structs by reference. */
695 g_assert_not_reached();
696}
697
27362b7b 698static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
afa05235 699{
27362b7b
RH		 700 /* ret and arg can't be register tmp0 */
701 tcg_debug_assert(ret != TCG_TMP0);
702 tcg_debug_assert(arg != TCG_TMP0);
703
704 /* With arg = abcd: */
988902fc 705 if (use_mips32r2_instructions) {
27362b7b
RH		 706 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
707 if (flags & TCG_BSWAP_OS) {
708 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
709 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
710 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
988902fc 711 }
27362b7b 712 return;
988902fc 713 }
afa05235 714
27362b7b
RH		 715 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
716 if (!(flags & TCG_BSWAP_IZ)) {
717 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
718 }
719 if (flags & TCG_BSWAP_OS) {
720 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
721 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
988902fc 722 } else {
27362b7b
RH		 723 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
724 if (flags & TCG_BSWAP_OZ) {
725 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
988902fc 726 }
988902fc 727 }
27362b7b 728 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
afa05235
AJ		 729}
730
df5af130 731static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
bb08afe9 732{
d7fc9f48
RH		 733 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) {
734 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub);
735 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0);
736 }
bb08afe9
JG		 737}
738
1fce6534 739static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
afa05235 740{
988902fc
AJ		 741 if (use_mips32r2_instructions) {
742 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
743 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
1fce6534
RH		 744 if (flags & TCG_BSWAP_OZ) {
745 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
746 }
988902fc 747 } else {
1fce6534
RH		 748 if (flags & TCG_BSWAP_OZ) {
749 tcg_out_bswap_subr(s, bswap32u_addr);
750 } else {
751 tcg_out_bswap_subr(s, bswap32_addr);
752 }
7f54eaa3
JG		 753 /* delay slot -- never omit the insn, like tcg_out_mov might. */
754 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
755 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
0119b192
JG		 756 }
757}
758
759static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
760{
761 if (use_mips32r2_instructions) {
762 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
763 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
764 } else {
7f54eaa3
JG		 765 tcg_out_bswap_subr(s, bswap64_addr);
766 /* delay slot -- never omit the insn, like tcg_out_mov might. */
767 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
768 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
0119b192
JG		 769 }
770}
771
10d4af58 772static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
0119b192 773{
9ecf5f61 774 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
0119b192
JG		 775 if (use_mips32r2_instructions) {
776 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
777 } else {
778 tcg_out_dsll(s, ret, arg, 32);
779 tcg_out_dsrl(s, ret, ret, 32);
780 }
781}
782
ac0f3b12 783static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
f9a71632 784 TCGReg addr, intptr_t ofs)
afa05235 785{
f9a71632
RH		 786 int16_t lo = ofs;
787 if (ofs != lo) {
6c530e32 788 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
f9a71632 789 if (addr != TCG_REG_ZERO) {
32b69707 790 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
f9a71632 791 }
6c530e32 792 addr = TCG_TMP0;
afa05235 793 }
f9a71632 794 tcg_out_opc_imm(s, opc, data, addr, lo);
afa05235
AJ		 795}
796
10d4af58
RH		 797static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
798 TCGReg arg1, intptr_t arg2)
afa05235 799{
32b69707
JG		 800 MIPSInsn opc = OPC_LD;
801 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
802 opc = OPC_LW;
803 }
804 tcg_out_ldst(s, opc, arg, arg1, arg2);
afa05235
AJ		 805}
806
10d4af58
RH		 807static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
808 TCGReg arg1, intptr_t arg2)
afa05235 809{
32b69707
JG		 810 MIPSInsn opc = OPC_SD;
811 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
812 opc = OPC_SW;
813 }
814 tcg_out_ldst(s, opc, arg, arg1, arg2);
afa05235
AJ		 815}
816
10d4af58
RH		 817static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
818 TCGReg base, intptr_t ofs)
59d7c14e
RH		 819{
820 if (val == 0) {
821 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
822 return true;
823 }
824 return false;
825}
826
d9f26847
AJ		 827static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
828 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
829 bool cbh, bool is_sub)
830{
831 TCGReg th = TCG_TMP1;
832
833 /* If we have a negative constant such that negating it would
834 make the high part zero, we can (usually) eliminate one insn. */
835 if (cbl && cbh && bh == -1 && bl != 0) {
836 bl = -bl;
837 bh = 0;
838 is_sub = !is_sub;
839 }
840
841 /* By operating on the high part first, we get to use the final
842 carry operation to move back from the temporary. */
843 if (!cbh) {
844 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
845 } else if (bh != 0 || ah == rl) {
846 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
847 } else {
848 th = ah;
849 }
850
851 /* Note that tcg optimization should eliminate the bl == 0 case. */
852 if (is_sub) {
853 if (cbl) {
854 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
855 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
856 } else {
857 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
858 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
859 }
860 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
861 } else {
862 if (cbl) {
863 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
864 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
865 } else if (rl == al && rl == bl) {
161dec9d 866 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
d9f26847
AJ		 867 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
868 } else {
869 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
870 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
871 }
872 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
873 }
874}
875
fd1cf666
RH		 876/* Bit 0 set if inversion required; bit 1 set if swapping required. */
877#define MIPS_CMP_INV 1
878#define MIPS_CMP_SWAP 2
879
880static const uint8_t mips_cmp_map[16] = {
881 [TCG_COND_LT] = 0,
882 [TCG_COND_LTU] = 0,
883 [TCG_COND_GE] = MIPS_CMP_INV,
884 [TCG_COND_GEU] = MIPS_CMP_INV,
885 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
886 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
887 [TCG_COND_GT] = MIPS_CMP_SWAP,
888 [TCG_COND_GTU] = MIPS_CMP_SWAP,
889};
890
891static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
892 TCGReg arg1, TCGReg arg2)
893{
894 MIPSInsn s_opc = OPC_SLTU;
895 int cmp_map;
896
897 switch (cond) {
898 case TCG_COND_EQ:
899 if (arg2 != 0) {
900 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
901 arg1 = ret;
902 }
903 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
904 break;
905
906 case TCG_COND_NE:
907 if (arg2 != 0) {
908 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
909 arg1 = ret;
910 }
911 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
912 break;
913
914 case TCG_COND_LT:
915 case TCG_COND_GE:
916 case TCG_COND_LE:
917 case TCG_COND_GT:
918 s_opc = OPC_SLT;
919 /* FALLTHRU */
920
921 case TCG_COND_LTU:
922 case TCG_COND_GEU:
923 case TCG_COND_LEU:
924 case TCG_COND_GTU:
925 cmp_map = mips_cmp_map[cond];
926 if (cmp_map & MIPS_CMP_SWAP) {
927 TCGReg t = arg1;
928 arg1 = arg2;
929 arg2 = t;
930 }
931 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
932 if (cmp_map & MIPS_CMP_INV) {
933 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
934 }
935 break;
936
937 default:
732e89f4 938 g_assert_not_reached();
fd1cf666
RH		 939 break;
940 }
941}
942
c068896f 943static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
bec16311 944 TCGReg arg2, TCGLabel *l)
afa05235 945{
c068896f
RH		 946 static const MIPSInsn b_zero[16] = {
947 [TCG_COND_LT] = OPC_BLTZ,
948 [TCG_COND_GT] = OPC_BGTZ,
949 [TCG_COND_LE] = OPC_BLEZ,
950 [TCG_COND_GE] = OPC_BGEZ,
951 };
952
c068896f
RH		 953 MIPSInsn s_opc = OPC_SLTU;
954 MIPSInsn b_opc;
955 int cmp_map;
afa05235
AJ		 956
957 switch (cond) {
958 case TCG_COND_EQ:
c068896f 959 b_opc = OPC_BEQ;
afa05235
AJ		 960 break;
961 case TCG_COND_NE:
c068896f 962 b_opc = OPC_BNE;
afa05235 963 break;
c068896f 964
afa05235 965 case TCG_COND_LT:
c068896f 966 case TCG_COND_GT:
afa05235 967 case TCG_COND_LE:
c068896f 968 case TCG_COND_GE:
0f46c064 969 if (arg2 == 0) {
c068896f
RH		 970 b_opc = b_zero[cond];
971 arg2 = arg1;
972 arg1 = 0;
973 break;
0f46c064 974 }
c068896f
RH		 975 s_opc = OPC_SLT;
976 /* FALLTHRU */
977
978 case TCG_COND_LTU:
979 case TCG_COND_GTU:
afa05235 980 case TCG_COND_LEU:
c068896f
RH		 981 case TCG_COND_GEU:
982 cmp_map = mips_cmp_map[cond];
983 if (cmp_map & MIPS_CMP_SWAP) {
984 TCGReg t = arg1;
985 arg1 = arg2;
986 arg2 = t;
0f46c064 987 }
c068896f
RH		 988 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
989 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
990 arg1 = TCG_TMP0;
991 arg2 = TCG_REG_ZERO;
afa05235 992 break;
c068896f 993
afa05235 994 default:
732e89f4 995 g_assert_not_reached();
afa05235
AJ		 996 break;
997 }
c068896f
RH		 998
999 tcg_out_opc_br(s, b_opc, arg1, arg2);
91a7fd1f 1000 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
afa05235
AJ		 1001 tcg_out_nop(s);
1002}
1003
1db1c4d7
RH		 1004static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
1005 TCGReg al, TCGReg ah,
1006 TCGReg bl, TCGReg bh)
1007{
1008 /* Merge highpart comparison into AH. */
1009 if (bh != 0) {
1010 if (ah != 0) {
1011 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
1012 ah = tmp0;
1013 } else {
1014 ah = bh;
1015 }
1016 }
1017 /* Merge lowpart comparison into AL. */
1018 if (bl != 0) {
1019 if (al != 0) {
1020 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
1021 al = tmp1;
1022 } else {
1023 al = bl;
1024 }
1025 }
1026 /* Merge high and low part comparisons into AL. */
1027 if (ah != 0) {
1028 if (al != 0) {
1029 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
1030 al = tmp0;
1031 } else {
1032 al = ah;
1033 }
1034 }
1035 return al;
1036}
1037
9a2f0bfe
RH		 1038static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
1039 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
1040{
1041 TCGReg tmp0 = TCG_TMP0;
1042 TCGReg tmp1 = ret;
1043
eabb7b91 1044 tcg_debug_assert(ret != TCG_TMP0);
9a2f0bfe 1045 if (ret == ah || ret == bh) {
eabb7b91 1046 tcg_debug_assert(ret != TCG_TMP1);
9a2f0bfe
RH		 1047 tmp1 = TCG_TMP1;
1048 }
1049
1050 switch (cond) {
1051 case TCG_COND_EQ:
1052 case TCG_COND_NE:
1db1c4d7
RH		 1053 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
1054 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
9a2f0bfe
RH		 1055 break;
1056
1057 default:
1058 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
1059 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
1060 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
1061 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
1062 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
1063 break;
1064 }
1065}
1066
3401fd25 1067static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
bec16311 1068 TCGReg bl, TCGReg bh, TCGLabel *l)
3401fd25
RH		 1069{
1070 TCGCond b_cond = TCG_COND_NE;
1071 TCGReg tmp = TCG_TMP1;
1072
1073 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
1074 With setcond, we emit between 3 and 10 insns and only 1 branch,
1075 which ought to get better branch prediction. */
1076 switch (cond) {
1077 case TCG_COND_EQ:
1078 case TCG_COND_NE:
1079 b_cond = cond;
1080 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
afa05235 1081 break;
afa05235 1082
afa05235 1083 default:
5d831be2 1084 /* Minimize code size by preferring a compare not requiring INV. */
3401fd25
RH		 1085 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1086 cond = tcg_invert_cond(cond);
1087 b_cond = TCG_COND_EQ;
1088 }
1089 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
1090 break;
afa05235
AJ		 1091 }
1092
bec16311 1093 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
afa05235
AJ		 1094}
1095
7d7c4930 1096static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
137d6390 1097 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
7d7c4930 1098{
137d6390
JH		 1099 bool eqz = false;
1100
1101 /* If one of the values is zero, put it last to match SEL*Z instructions */
1102 if (use_mips32r6_instructions && v1 == 0) {
1103 v1 = v2;
1104 v2 = 0;
1105 cond = tcg_invert_cond(cond);
1106 }
33fac20b 1107
7d7c4930
AJ		 1108 switch (cond) {
1109 case TCG_COND_EQ:
137d6390 1110 eqz = true;
33fac20b 1111 /* FALLTHRU */
7d7c4930 1112 case TCG_COND_NE:
33fac20b 1113 if (c2 != 0) {
6c530e32 1114 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
33fac20b 1115 c1 = TCG_TMP0;
7d7c4930
AJ		 1116 }
1117 break;
33fac20b 1118
7d7c4930 1119 default:
5d831be2 1120 /* Minimize code size by preferring a compare not requiring INV. */
33fac20b
RH		 1121 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1122 cond = tcg_invert_cond(cond);
137d6390 1123 eqz = true;
33fac20b
RH		 1124 }
1125 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1126 c1 = TCG_TMP0;
7d7c4930
AJ		 1127 break;
1128 }
33fac20b 1129
137d6390
JH		 1130 if (use_mips32r6_instructions) {
1131 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1132 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1133
1134 if (v2 != 0) {
1135 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1136 }
1137 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1138 if (v2 != 0) {
1139 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1140 }
1141 } else {
1142 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1143
1144 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1145
1146 /* This should be guaranteed via constraints */
1147 tcg_debug_assert(v2 == ret);
1148 }
7d7c4930
AJ		 1149}
1150
2be7d76b 1151static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
9d8bf2d1 1152{
4316de32
RH		 1153 /*
1154 * Note that __mips_abicalls requires the called function's address
1155 * to be loaded into $25 (t9), even if a direct branch is in range.
1156 *
1157 * For n64, always drop the pointer into the constant pool.
1158 * We can re-use helper addresses often and do not want any
1159 * of the longer sequences tcg_out_movi may try.
1160 */
1161 if (sizeof(uintptr_t) == 8) {
1162 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB);
1163 } else {
1164 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1165 }
9d8bf2d1
RH		 1166
1167 /* But do try a direct branch, allowing the cpu better insn prefetch. */
ce0236cf
RH		 1168 if (tail) {
1169 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1170 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1171 }
1172 } else {
1173 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1174 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1175 }
9d8bf2d1 1176 }
ce0236cf 1177}
9d8bf2d1 1178
cee44b03
RH		 1179static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
1180 const TCGHelperInfo *info)
ce0236cf
RH		 1181{
1182 tcg_out_call_int(s, arg, false);
9d8bf2d1
RH		 1183 tcg_out_nop(s);
1184}
1185
f07aaf48
RH		 1186/* We have four temps, we might as well expose three of them. */
1187static const TCGLdstHelperParam ldst_helper_param = {
1188 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 }
1189};
9d8bf2d1 1190
aeee05f5 1191static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
9d8bf2d1 1192{
df5af130 1193 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
f07aaf48 1194 MemOp opc = get_memop(l->oi);
9d8bf2d1
RH		 1195
1196 /* resolve label address */
df5af130 1197 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
30feb7ee 1198 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
91a7fd1f 1199 return false;
9d8bf2d1
RH		 1200 }
1201
f07aaf48
RH		 1202 tcg_out_ld_helper_args(s, l, &ldst_helper_param);
1203
a7995621 1204 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false);
ce0236cf 1205 /* delay slot */
f07aaf48
RH		 1206 tcg_out_nop(s);
1207
1208 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param);
afa05235 1209
6d8ff4d8 1210 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
91a7fd1f
RH		 1211 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1212 return false;
1213 }
a31aa4ce 1214
ce0236cf 1215 /* delay slot */
f07aaf48 1216 tcg_out_nop(s);
aeee05f5 1217 return true;
9d8bf2d1 1218}
afa05235 1219
aeee05f5 1220static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
9d8bf2d1 1221{
df5af130 1222 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
f07aaf48 1223 MemOp opc = get_memop(l->oi);
9d8bf2d1
RH		 1224
1225 /* resolve label address */
df5af130 1226 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
30feb7ee 1227 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
91a7fd1f 1228 return false;
9d8bf2d1 1229 }
afa05235 1230
f07aaf48
RH		 1231 tcg_out_st_helper_args(s, l, &ldst_helper_param);
1232
a7995621 1233 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false);
f07aaf48
RH		 1234 /* delay slot */
1235 tcg_out_nop(s);
1236
1237 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1238 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1239 return false;
cc01cc8e 1240 }
9d8bf2d1 1241
ce0236cf 1242 /* delay slot */
f07aaf48 1243 tcg_out_nop(s);
aeee05f5 1244 return true;
9d8bf2d1 1245}
23a79c11 1246
5b7208da
RH		 1247typedef struct {
1248 TCGReg base;
c0cafab5 1249 TCGAtomAlign aa;
5b7208da
RH		 1250} HostAddress;
1251
7b880107
RH		 1252bool tcg_target_has_memory_bswap(MemOp memop)
1253{
1254 return false;
1255}
1256
d0a9bb5e
RH		 1257/* We expect to use a 16-bit negative offset from ENV. */
1258#define MIN_TLB_MASK_TABLE_OFS -32768
1259
5b7208da
RH		 1260/*
1261 * For softmmu, perform the TLB load and compare.
1262 * For useronly, perform any required alignment tests.
1263 * In both cases, return a TCGLabelQemuLdst structure if the slow path
1264 * is required and fill in @h with the host address for the fast path.
1265 */
1266static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1267 TCGReg addrlo, TCGReg addrhi,
1268 MemOpIdx oi, bool is_ld)
1269{
5e983cbc 1270 TCGType addr_type = s->addr_type;
5b7208da
RH		 1271 TCGLabelQemuLdst *ldst = NULL;
1272 MemOp opc = get_memop(oi);
c0cafab5 1273 MemOp a_bits;
5b7208da 1274 unsigned s_bits = opc & MO_SIZE;
c0cafab5 1275 unsigned a_mask;
5b7208da
RH		 1276 TCGReg base;
1277
c0cafab5
RH		 1278 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
1279 a_bits = h->aa.align;
1280 a_mask = (1 << a_bits) - 1;
1281
5b7208da
RH		 1282#ifdef CONFIG_SOFTMMU
1283 unsigned s_mask = (1 << s_bits) - 1;
1284 int mem_index = get_mmuidx(oi);
d0a9bb5e 1285 int fast_off = tlb_mask_table_ofs(s, mem_index);
5b7208da
RH		 1286 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1287 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1288 int add_off = offsetof(CPUTLBEntry, addend);
1289 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
1290 : offsetof(CPUTLBEntry, addr_write);
5b7208da
RH		 1291
1292 ldst = new_ldst_label(s);
1293 ldst->is_ld = is_ld;
1294 ldst->oi = oi;
1295 ldst->addrlo_reg = addrlo;
1296 ldst->addrhi_reg = addrhi;
5b7208da
RH		 1297
1298 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
5b7208da
RH		 1299 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1300 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
1301
1302 /* Extract the TLB index from the address into TMP3. */
5e983cbc
RH		 1303 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
1304 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo,
aece72b7 1305 s->page_bits - CPU_TLB_ENTRY_BITS);
5e983cbc
RH		 1306 } else {
1307 tcg_out_dsrl(s, TCG_TMP3, addrlo,
aece72b7 1308 s->page_bits - CPU_TLB_ENTRY_BITS);
5e983cbc 1309 }
5b7208da
RH		 1310 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1311
1312 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1313 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1314
238f4380
RH		 1315 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
1316 /* Load the (low half) tlb comparator. */
1317 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
1318 cmp_off + HOST_BIG_ENDIAN * 4);
1319 } else {
1320 tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off);
1321 }
1322
5e983cbc 1323 if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
2f2a3d1d
RH		 1324 /* Load the tlb addend for the fast path. */
1325 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
5b7208da
RH		 1326 }
1327
1328 /*
1329 * Mask the page bits, keeping the alignment bits to compare against.
1330 * For unaligned accesses, compare against the end of the access to
1331 * verify that it does not cross a page boundary.
1332 */
aece72b7 1333 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask);
2f2a3d1d 1334 if (a_mask < s_mask) {
5e983cbc
RH		 1335 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
1336 tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP2, addrlo, s_mask - a_mask);
1337 } else {
1338 tcg_out_opc_imm(s, OPC_DADDIU, TCG_TMP2, addrlo, s_mask - a_mask);
1339 }
5b7208da 1340 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
2f2a3d1d
RH		 1341 } else {
1342 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
5b7208da
RH		 1343 }
1344
2f2a3d1d 1345 /* Zero extend a 32-bit guest address for a 64-bit host. */
5e983cbc 1346 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
2f2a3d1d
RH		 1347 tcg_out_ext32u(s, TCG_TMP2, addrlo);
1348 addrlo = TCG_TMP2;
5b7208da
RH		 1349 }
1350
1351 ldst->label_ptr[0] = s->code_ptr;
1352 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1353
1354 /* Load and test the high half tlb comparator. */
5e983cbc 1355 if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
5b7208da
RH		 1356 /* delay slot */
1357 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1358
1359 /* Load the tlb addend for the fast path. */
2f2a3d1d 1360 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
5b7208da
RH		 1361
1362 ldst->label_ptr[1] = s->code_ptr;
1363 tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
1364 }
1365
1366 /* delay slot */
2f2a3d1d
RH		 1367 base = TCG_TMP3;
1368 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
5b7208da
RH		 1369#else
1370 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
1371 ldst = new_ldst_label(s);
1372
1373 ldst->is_ld = is_ld;
1374 ldst->oi = oi;
1375 ldst->addrlo_reg = addrlo;
1376 ldst->addrhi_reg = addrhi;
1377
1378 /* We are expecting a_bits to max out at 7, much lower than ANDI. */
1379 tcg_debug_assert(a_bits < 16);
1380 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
1381
1382 ldst->label_ptr[0] = s->code_ptr;
1383 if (use_mips32r6_instructions) {
1384 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
1385 } else {
1386 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
1387 tcg_out_nop(s);
1388 }
1389 }
1390
1391 base = addrlo;
5e983cbc 1392 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
5b7208da
RH		 1393 tcg_out_ext32u(s, TCG_REG_A0, base);
1394 base = TCG_REG_A0;
1395 }
1396 if (guest_base) {
1397 if (guest_base == (int16_t)guest_base) {
1398 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
1399 } else {
1400 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
1401 TCG_GUEST_BASE_REG);
1402 }
1403 base = TCG_REG_A0;
1404 }
1405#endif
1406
1407 h->base = base;
5b7208da
RH		 1408 return ldst;
1409}
1410
bb08afe9 1411static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
eb664d0c 1412 TCGReg base, MemOp opc, TCGType type)
9d8bf2d1 1413{
a7995621 1414 switch (opc & MO_SSIZE) {
9d8bf2d1 1415 case MO_UB:
bb08afe9 1416 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
afa05235 1417 break;
9d8bf2d1 1418 case MO_SB:
bb08afe9 1419 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
afa05235 1420 break;
9d8bf2d1 1421 case MO_UW:
bb08afe9 1422 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
afa05235 1423 break;
9d8bf2d1 1424 case MO_SW:
bb08afe9 1425 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
9d8bf2d1 1426 break;
9d8bf2d1 1427 case MO_UL:
eb664d0c 1428 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
f0d70331
JG		 1429 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1430 break;
1431 }
1432 /* FALLTHRU */
1433 case MO_SL:
bb08afe9 1434 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
9d8bf2d1 1435 break;
fc313c64 1436 case MO_UQ:
bb08afe9 1437 /* Prefer to load from offset 0 first, but allow for overlap. */
f0d70331
JG		 1438 if (TCG_TARGET_REG_BITS == 64) {
1439 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
b56d5a8a 1440 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) {
bb08afe9
JG		 1441 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1442 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1443 } else {
1444 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1445 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1446 }
afa05235
AJ		 1447 break;
1448 default:
732e89f4 1449 g_assert_not_reached();
afa05235 1450 }
afa05235
AJ		 1451}
1452
d9e52834 1453static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
eb664d0c 1454 TCGReg base, MemOp opc, TCGType type)
23a79c11 1455{
b56d5a8a
RH		 1456 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR;
1457 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL;
1458 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR;
1459 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL;
a7995621 1460 bool sgn = opc & MO_SIGN;
23a79c11 1461
a7995621
RH		 1462 switch (opc & MO_SIZE) {
1463 case MO_16:
1464 if (HOST_BIG_ENDIAN) {
1465 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0);
1466 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1);
1467 if (use_mips32r2_instructions) {
1468 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1469 } else {
1470 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8);
1471 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0);
1472 }
1473 } else if (use_mips32r2_instructions && lo != base) {
23a79c11
RH		 1474 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1475 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1);
1476 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1477 } else {
1478 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0);
1479 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1);
1480 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8);
1481 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1482 }
1483 break;
1484
a7995621 1485 case MO_32:
23a79c11
RH		 1486 tcg_out_opc_imm(s, lw1, lo, base, 0);
1487 tcg_out_opc_imm(s, lw2, lo, base, 3);
eb664d0c 1488 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) {
23a79c11
RH		 1489 tcg_out_ext32u(s, lo, lo);
1490 }
1491 break;
1492
a7995621 1493 case MO_64:
23a79c11
RH		 1494 if (TCG_TARGET_REG_BITS == 64) {
1495 tcg_out_opc_imm(s, ld1, lo, base, 0);
1496 tcg_out_opc_imm(s, ld2, lo, base, 7);
1497 } else {
b56d5a8a
RH		 1498 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
1499 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
1500 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
1501 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
23a79c11
RH		 1502 }
1503 break;
1504
23a79c11
RH		 1505 default:
1506 g_assert_not_reached();
1507 }
1508}
1509
eb664d0c
RH		 1510static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
1511 TCGReg addrlo, TCGReg addrhi,
1512 MemOpIdx oi, TCGType data_type)
afa05235 1513{
eb664d0c 1514 MemOp opc = get_memop(oi);
5b7208da
RH		 1515 TCGLabelQemuLdst *ldst;
1516 HostAddress h;
9d8bf2d1 1517
5b7208da 1518 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
eb664d0c 1519
c0cafab5 1520 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
5b7208da 1521 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
d9e52834 1522 } else {
5b7208da 1523 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type);
f0d70331 1524 }
5b7208da
RH		 1525
1526 if (ldst) {
1527 ldst->type = data_type;
1528 ldst->datalo_reg = datalo;
1529 ldst->datahi_reg = datahi;
1530 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
23a79c11 1531 }
9d8bf2d1 1532}
afa05235 1533
bb08afe9 1534static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
14776ab5 1535 TCGReg base, MemOp opc)
9d8bf2d1 1536{
a7995621 1537 switch (opc & MO_SIZE) {
9d8bf2d1 1538 case MO_8:
bb08afe9 1539 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
9d8bf2d1 1540 break;
9d8bf2d1 1541 case MO_16:
bb08afe9 1542 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
afa05235 1543 break;
9d8bf2d1 1544 case MO_32:
bb08afe9 1545 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
afa05235 1546 break;
9d8bf2d1 1547 case MO_64:
f0d70331
JG		 1548 if (TCG_TARGET_REG_BITS == 64) {
1549 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1550 } else {
b56d5a8a
RH		 1551 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0);
1552 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4);
f0d70331 1553 }
afa05235
AJ		 1554 break;
1555 default:
732e89f4 1556 g_assert_not_reached();
afa05235 1557 }
9d8bf2d1 1558}
afa05235 1559
d9e52834 1560static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
23a79c11
RH		 1561 TCGReg base, MemOp opc)
1562{
b56d5a8a
RH		 1563 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR;
1564 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL;
1565 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR;
1566 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL;
23a79c11 1567
a7995621
RH		 1568 switch (opc & MO_SIZE) {
1569 case MO_16:
23a79c11 1570 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
a7995621
RH		 1571 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0);
1572 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1);
23a79c11
RH		 1573 break;
1574
23a79c11
RH		 1575 case MO_32:
1576 tcg_out_opc_imm(s, sw1, lo, base, 0);
1577 tcg_out_opc_imm(s, sw2, lo, base, 3);
1578 break;
1579
23a79c11
RH		 1580 case MO_64:
1581 if (TCG_TARGET_REG_BITS == 64) {
1582 tcg_out_opc_imm(s, sd1, lo, base, 0);
1583 tcg_out_opc_imm(s, sd2, lo, base, 7);
1584 } else {
b56d5a8a
RH		 1585 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
1586 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
1587 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
1588 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
23a79c11
RH		 1589 }
1590 break;
1591
1592 default:
732e89f4 1593 g_assert_not_reached();
23a79c11
RH		 1594 }
1595}
eb664d0c
RH		 1596
1597static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
1598 TCGReg addrlo, TCGReg addrhi,
1599 MemOpIdx oi, TCGType data_type)
9d8bf2d1 1600{
eb664d0c 1601 MemOp opc = get_memop(oi);
5b7208da
RH		 1602 TCGLabelQemuLdst *ldst;
1603 HostAddress h;
afa05235 1604
5b7208da 1605 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
eb664d0c 1606
c0cafab5 1607 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
5b7208da 1608 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
d9e52834 1609 } else {
5b7208da 1610 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc);
d9e52834 1611 }
5b7208da
RH		 1612
1613 if (ldst) {
1614 ldst->type = data_type;
1615 ldst->datalo_reg = datalo;
1616 ldst->datahi_reg = datahi;
1617 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
23a79c11 1618 }
afa05235
AJ		 1619}
1620
6f0b9910
PK		 1621static void tcg_out_mb(TCGContext *s, TCGArg a0)
1622{
1623 static const MIPSInsn sync[] = {
1624 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1625 as the former is an ordering barrier and the latter
1626 is a completion barrier. */
1627 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1628 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1629 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1630 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1631 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1632 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1633 };
1634 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1635}
1636
2a1d9d41
RH		 1637static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1638 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1639{
1640 if (use_mips32r6_instructions) {
1641 if (a2 == width) {
1642 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1643 } else {
1644 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1645 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1646 }
1647 } else {
1648 if (a2 == width) {
1649 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1650 } else if (a0 == a2) {
1651 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1652 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1653 } else if (a0 != a1) {
1654 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1655 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1656 } else {
1657 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1658 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1659 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1660 }
1661 }
1662}
1663
b55a8d9d
RH		 1664static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1665{
53c4fa27
RH		 1666 TCGReg base = TCG_REG_ZERO;
1667 int16_t lo = 0;
b55a8d9d 1668
53c4fa27
RH		 1669 if (a0) {
1670 intptr_t ofs;
1671 if (TCG_TARGET_REG_BITS == 64) {
1672 ofs = tcg_tbrel_diff(s, (void *)a0);
1673 lo = ofs;
1674 if (ofs == lo) {
1675 base = TCG_REG_TB;
1676 } else {
1677 base = TCG_REG_V0;
1678 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
1679 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB);
1680 }
1681 } else {
1682 ofs = a0;
1683 lo = ofs;
1684 base = TCG_REG_V0;
1685 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
1686 }
b55a8d9d
RH		 1687 }
1688 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1689 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr);
1690 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1691 }
53c4fa27
RH		 1692 /* delay slot */
1693 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo);
b55a8d9d
RH		 1694}
1695
cf7d6b8e
RH		 1696static void tcg_out_goto_tb(TCGContext *s, int which)
1697{
53c4fa27
RH		 1698 intptr_t ofs = get_jmp_target_addr(s, which);
1699 TCGReg base, dest;
1700
cf7d6b8e 1701 /* indirect jump method */
53c4fa27
RH		 1702 if (TCG_TARGET_REG_BITS == 64) {
1703 dest = TCG_REG_TB;
1704 base = TCG_REG_TB;
1705 ofs = tcg_tbrel_diff(s, (void *)ofs);
1706 } else {
1707 dest = TCG_TMP0;
1708 base = TCG_REG_ZERO;
1709 }
1710 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs);
1711 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0);
1712 /* delay slot */
cf7d6b8e 1713 tcg_out_nop(s);
53c4fa27 1714
cf7d6b8e 1715 set_jmp_reset_offset(s, which);
53c4fa27
RH		 1716 if (TCG_TARGET_REG_BITS == 64) {
1717 /* For the unlinked case, need to reset TCG_REG_TB. */
1718 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB,
1719 -tcg_current_code_size(s));
1720 }
cf7d6b8e
RH		 1721}
1722
90c0fee3
RH		 1723void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1724 uintptr_t jmp_rx, uintptr_t jmp_rw)
1725{
1726 /* Always indirect, nothing to do */
1727}
1728
10d4af58
RH		 1729static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1730 const TCGArg args[TCG_MAX_OP_ARGS],
1731 const int const_args[TCG_MAX_OP_ARGS])
afa05235 1732{
4f048535 1733 MIPSInsn i1, i2;
22ee3a98
RH		 1734 TCGArg a0, a1, a2;
1735 int c2;
1736
51800e43
RH		 1737 /*
1738 * Note that many operands use the constraint set "rZ".
1739 * We make use of the fact that 0 is the ZERO register,
1740 * and hence such cases need not check for const_args.
1741 */
22ee3a98
RH		 1742 a0 = args[0];
1743 a1 = args[1];
1744 a2 = args[2];
1745 c2 = const_args[2];
1746
1747 switch (opc) {
5786e068
AJ		 1748 case INDEX_op_goto_ptr:
1749 /* jmp to the given host address (could be epilogue) */
1750 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
53c4fa27
RH		 1751 if (TCG_TARGET_REG_BITS == 64) {
1752 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
1753 } else {
1754 tcg_out_nop(s);
1755 }
5786e068 1756 break;
afa05235 1757 case INDEX_op_br:
bec16311
RH		 1758 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1759 arg_label(a0));
afa05235
AJ		 1760 break;
1761
afa05235 1762 case INDEX_op_ld8u_i32:
0119b192 1763 case INDEX_op_ld8u_i64:
4f048535
RH		 1764 i1 = OPC_LBU;
1765 goto do_ldst;
afa05235 1766 case INDEX_op_ld8s_i32:
0119b192 1767 case INDEX_op_ld8s_i64:
4f048535
RH		 1768 i1 = OPC_LB;
1769 goto do_ldst;
afa05235 1770 case INDEX_op_ld16u_i32:
0119b192 1771 case INDEX_op_ld16u_i64:
4f048535
RH		 1772 i1 = OPC_LHU;
1773 goto do_ldst;
afa05235 1774 case INDEX_op_ld16s_i32:
0119b192 1775 case INDEX_op_ld16s_i64:
4f048535
RH		 1776 i1 = OPC_LH;
1777 goto do_ldst;
afa05235 1778 case INDEX_op_ld_i32:
0119b192 1779 case INDEX_op_ld32s_i64:
4f048535
RH		 1780 i1 = OPC_LW;
1781 goto do_ldst;
0119b192
JG		 1782 case INDEX_op_ld32u_i64:
1783 i1 = OPC_LWU;
1784 goto do_ldst;
1785 case INDEX_op_ld_i64:
1786 i1 = OPC_LD;
1787 goto do_ldst;
afa05235 1788 case INDEX_op_st8_i32:
0119b192 1789 case INDEX_op_st8_i64:
4f048535
RH		 1790 i1 = OPC_SB;
1791 goto do_ldst;
afa05235 1792 case INDEX_op_st16_i32:
0119b192 1793 case INDEX_op_st16_i64:
4f048535
RH		 1794 i1 = OPC_SH;
1795 goto do_ldst;
afa05235 1796 case INDEX_op_st_i32:
0119b192 1797 case INDEX_op_st32_i64:
4f048535 1798 i1 = OPC_SW;
0119b192
JG		 1799 goto do_ldst;
1800 case INDEX_op_st_i64:
1801 i1 = OPC_SD;
4f048535
RH		 1802 do_ldst:
1803 tcg_out_ldst(s, i1, a0, a1, a2);
afa05235
AJ		 1804 break;
1805
1806 case INDEX_op_add_i32:
4f048535
RH		 1807 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1808 goto do_binary;
0119b192
JG		 1809 case INDEX_op_add_i64:
1810 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1811 goto do_binary;
4f048535 1812 case INDEX_op_or_i32:
0119b192 1813 case INDEX_op_or_i64:
4f048535
RH		 1814 i1 = OPC_OR, i2 = OPC_ORI;
1815 goto do_binary;
1816 case INDEX_op_xor_i32:
0119b192 1817 case INDEX_op_xor_i64:
4f048535
RH		 1818 i1 = OPC_XOR, i2 = OPC_XORI;
1819 do_binary:
22ee3a98 1820 if (c2) {
4f048535
RH		 1821 tcg_out_opc_imm(s, i2, a0, a1, a2);
1822 break;
afa05235 1823 }
4f048535
RH		 1824 do_binaryv:
1825 tcg_out_opc_reg(s, i1, a0, a1, a2);
afa05235 1826 break;
4f048535 1827
afa05235 1828 case INDEX_op_sub_i32:
0119b192
JG		 1829 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1830 goto do_subtract;
1831 case INDEX_op_sub_i64:
1832 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1833 do_subtract:
22ee3a98 1834 if (c2) {
0119b192 1835 tcg_out_opc_imm(s, i2, a0, a1, -a2);
4f048535 1836 break;
afa05235 1837 }
0119b192 1838 goto do_binaryv;
4f048535
RH		 1839 case INDEX_op_and_i32:
1840 if (c2 && a2 != (uint16_t)a2) {
1841 int msb = ctz32(~a2) - 1;
eabb7b91
AJ		 1842 tcg_debug_assert(use_mips32r2_instructions);
1843 tcg_debug_assert(is_p2m1(a2));
4f048535
RH		 1844 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1845 break;
1846 }
1847 i1 = OPC_AND, i2 = OPC_ANDI;
1848 goto do_binary;
0119b192
JG		 1849 case INDEX_op_and_i64:
1850 if (c2 && a2 != (uint16_t)a2) {
1851 int msb = ctz64(~a2) - 1;
1852 tcg_debug_assert(use_mips32r2_instructions);
1853 tcg_debug_assert(is_p2m1(a2));
1854 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1855 break;
1856 }
1857 i1 = OPC_AND, i2 = OPC_ANDI;
1858 goto do_binary;
4f048535 1859 case INDEX_op_nor_i32:
0119b192 1860 case INDEX_op_nor_i64:
4f048535
RH		 1861 i1 = OPC_NOR;
1862 goto do_binaryv;
1863
afa05235 1864 case INDEX_op_mul_i32:
988902fc 1865 if (use_mips32_instructions) {
22ee3a98 1866 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
4f048535 1867 break;
988902fc 1868 }
4f048535
RH		 1869 i1 = OPC_MULT, i2 = OPC_MFLO;
1870 goto do_hilo1;
3c9a8f17 1871 case INDEX_op_mulsh_i32:
bc6d0c22
JH		 1872 if (use_mips32r6_instructions) {
1873 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1874 break;
1875 }
4f048535
RH		 1876 i1 = OPC_MULT, i2 = OPC_MFHI;
1877 goto do_hilo1;
3c9a8f17 1878 case INDEX_op_muluh_i32:
bc6d0c22
JH		 1879 if (use_mips32r6_instructions) {
1880 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1881 break;
1882 }
4f048535
RH		 1883 i1 = OPC_MULTU, i2 = OPC_MFHI;
1884 goto do_hilo1;
afa05235 1885 case INDEX_op_div_i32:
bc6d0c22
JH		 1886 if (use_mips32r6_instructions) {
1887 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1888 break;
1889 }
4f048535
RH		 1890 i1 = OPC_DIV, i2 = OPC_MFLO;
1891 goto do_hilo1;
afa05235 1892 case INDEX_op_divu_i32:
bc6d0c22
JH		 1893 if (use_mips32r6_instructions) {
1894 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1895 break;
1896 }
4f048535
RH		 1897 i1 = OPC_DIVU, i2 = OPC_MFLO;
1898 goto do_hilo1;
afa05235 1899 case INDEX_op_rem_i32:
bc6d0c22
JH		 1900 if (use_mips32r6_instructions) {
1901 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1902 break;
1903 }
4f048535
RH		 1904 i1 = OPC_DIV, i2 = OPC_MFHI;
1905 goto do_hilo1;
afa05235 1906 case INDEX_op_remu_i32:
bc6d0c22
JH		 1907 if (use_mips32r6_instructions) {
1908 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1909 break;
1910 }
4f048535 1911 i1 = OPC_DIVU, i2 = OPC_MFHI;
0119b192
JG		 1912 goto do_hilo1;
1913 case INDEX_op_mul_i64:
1914 if (use_mips32r6_instructions) {
1915 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1916 break;
1917 }
1918 i1 = OPC_DMULT, i2 = OPC_MFLO;
1919 goto do_hilo1;
1920 case INDEX_op_mulsh_i64:
1921 if (use_mips32r6_instructions) {
1922 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1923 break;
1924 }
1925 i1 = OPC_DMULT, i2 = OPC_MFHI;
1926 goto do_hilo1;
1927 case INDEX_op_muluh_i64:
1928 if (use_mips32r6_instructions) {
1929 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1930 break;
1931 }
1932 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1933 goto do_hilo1;
1934 case INDEX_op_div_i64:
1935 if (use_mips32r6_instructions) {
1936 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1937 break;
1938 }
1939 i1 = OPC_DDIV, i2 = OPC_MFLO;
1940 goto do_hilo1;
1941 case INDEX_op_divu_i64:
1942 if (use_mips32r6_instructions) {
1943 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1944 break;
1945 }
1946 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1947 goto do_hilo1;
1948 case INDEX_op_rem_i64:
1949 if (use_mips32r6_instructions) {
1950 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1951 break;
1952 }
1953 i1 = OPC_DDIV, i2 = OPC_MFHI;
1954 goto do_hilo1;
1955 case INDEX_op_remu_i64:
1956 if (use_mips32r6_instructions) {
1957 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1958 break;
1959 }
1960 i1 = OPC_DDIVU, i2 = OPC_MFHI;
4f048535
RH		 1961 do_hilo1:
1962 tcg_out_opc_reg(s, i1, 0, a1, a2);
1963 tcg_out_opc_reg(s, i2, a0, 0, 0);
afa05235
AJ		 1964 break;
1965
4f048535
RH		 1966 case INDEX_op_muls2_i32:
1967 i1 = OPC_MULT;
1968 goto do_hilo2;
1969 case INDEX_op_mulu2_i32:
1970 i1 = OPC_MULTU;
0119b192
JG		 1971 goto do_hilo2;
1972 case INDEX_op_muls2_i64:
1973 i1 = OPC_DMULT;
1974 goto do_hilo2;
1975 case INDEX_op_mulu2_i64:
1976 i1 = OPC_DMULTU;
4f048535
RH		 1977 do_hilo2:
1978 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1979 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1980 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
2b79487a 1981 break;
4f048535 1982
afa05235 1983 case INDEX_op_not_i32:
0119b192 1984 case INDEX_op_not_i64:
4f048535
RH		 1985 i1 = OPC_NOR;
1986 goto do_unary;
4f048535
RH		 1987 do_unary:
1988 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
afa05235
AJ		 1989 break;
1990
27362b7b
RH		 1991 case INDEX_op_bswap16_i32:
1992 case INDEX_op_bswap16_i64:
1993 tcg_out_bswap16(s, a0, a1, a2);
1994 break;
0119b192 1995 case INDEX_op_bswap32_i32:
1fce6534 1996 tcg_out_bswap32(s, a0, a1, 0);
0119b192
JG		 1997 break;
1998 case INDEX_op_bswap32_i64:
1fce6534 1999 tcg_out_bswap32(s, a0, a1, a2);
0119b192
JG		 2000 break;
2001 case INDEX_op_bswap64_i64:
2002 tcg_out_bswap64(s, a0, a1);
2003 break;
2004 case INDEX_op_extrh_i64_i32:
2005 tcg_out_dsra(s, a0, a1, 32);
2006 break;
0119b192 2007
afa05235 2008 case INDEX_op_sar_i32:
4f048535
RH		 2009 i1 = OPC_SRAV, i2 = OPC_SRA;
2010 goto do_shift;
afa05235 2011 case INDEX_op_shl_i32:
4f048535
RH		 2012 i1 = OPC_SLLV, i2 = OPC_SLL;
2013 goto do_shift;
afa05235 2014 case INDEX_op_shr_i32:
4f048535
RH		 2015 i1 = OPC_SRLV, i2 = OPC_SRL;
2016 goto do_shift;
2017 case INDEX_op_rotr_i32:
2018 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2019 do_shift:
22ee3a98 2020 if (c2) {
4f048535 2021 tcg_out_opc_sa(s, i2, a0, a1, a2);
0119b192 2022 break;
afa05235 2023 }
0119b192
JG		 2024 do_shiftv:
2025 tcg_out_opc_reg(s, i1, a0, a2, a1);
afa05235 2026 break;
9a152519 2027 case INDEX_op_rotl_i32:
22ee3a98
RH		 2028 if (c2) {
2029 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
9a152519 2030 } else {
22ee3a98
RH		 2031 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2032 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
9a152519
AJ		 2033 }
2034 break;
0119b192
JG		 2035 case INDEX_op_sar_i64:
2036 if (c2) {
2037 tcg_out_dsra(s, a0, a1, a2);
2038 break;
2039 }
2040 i1 = OPC_DSRAV;
2041 goto do_shiftv;
2042 case INDEX_op_shl_i64:
2043 if (c2) {
2044 tcg_out_dsll(s, a0, a1, a2);
2045 break;
2046 }
2047 i1 = OPC_DSLLV;
2048 goto do_shiftv;
2049 case INDEX_op_shr_i64:
2050 if (c2) {
2051 tcg_out_dsrl(s, a0, a1, a2);
2052 break;
2053 }
2054 i1 = OPC_DSRLV;
2055 goto do_shiftv;
2056 case INDEX_op_rotr_i64:
2057 if (c2) {
2058 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2059 break;
2060 }
2061 i1 = OPC_DROTRV;
2062 goto do_shiftv;
2063 case INDEX_op_rotl_i64:
2064 if (c2) {
2065 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2066 } else {
2067 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2068 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2069 }
c1cf85c9
AJ		 2070 break;
2071
2a1d9d41
RH		 2072 case INDEX_op_clz_i32:
2073 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2074 break;
2075 case INDEX_op_clz_i64:
2076 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2077 break;
2078
04f71aa3 2079 case INDEX_op_deposit_i32:
22ee3a98 2080 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
04f71aa3 2081 break;
0119b192
JG		 2082 case INDEX_op_deposit_i64:
2083 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2084 args[3] + args[4] - 1, args[3]);
2085 break;
befbb3ce 2086 case INDEX_op_extract_i32:
2f5a5f57 2087 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
befbb3ce
RH		 2088 break;
2089 case INDEX_op_extract_i64:
2090 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2f5a5f57 2091 args[3] - 1, a2);
befbb3ce 2092 break;
04f71aa3 2093
afa05235 2094 case INDEX_op_brcond_i32:
0119b192 2095 case INDEX_op_brcond_i64:
bec16311 2096 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
afa05235
AJ		 2097 break;
2098 case INDEX_op_brcond2_i32:
bec16311 2099 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
afa05235
AJ		 2100 break;
2101
7d7c4930 2102 case INDEX_op_movcond_i32:
0119b192 2103 case INDEX_op_movcond_i64:
137d6390 2104 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
7d7c4930
AJ		 2105 break;
2106
4cb26382 2107 case INDEX_op_setcond_i32:
0119b192 2108 case INDEX_op_setcond_i64:
22ee3a98 2109 tcg_out_setcond(s, args[3], a0, a1, a2);
4cb26382 2110 break;
434254aa 2111 case INDEX_op_setcond2_i32:
22ee3a98 2112 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
434254aa 2113 break;
4cb26382 2114
fecccfcc
RH		 2115 case INDEX_op_qemu_ld_a64_i32:
2116 if (TCG_TARGET_REG_BITS == 32) {
eb664d0c 2117 tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
fecccfcc 2118 break;
eb664d0c 2119 }
fecccfcc
RH		 2120 /* fall through */
2121 case INDEX_op_qemu_ld_a32_i32:
2122 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
afa05235 2123 break;
fecccfcc 2124 case INDEX_op_qemu_ld_a32_i64:
eb664d0c
RH		 2125 if (TCG_TARGET_REG_BITS == 64) {
2126 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
fecccfcc 2127 } else {
eb664d0c 2128 tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
fecccfcc
RH		 2129 }
2130 break;
2131 case INDEX_op_qemu_ld_a64_i64:
2132 if (TCG_TARGET_REG_BITS == 64) {
2133 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
eb664d0c
RH		 2134 } else {
2135 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
2136 }
afa05235 2137 break;
fecccfcc
RH		 2138
2139 case INDEX_op_qemu_st_a64_i32:
2140 if (TCG_TARGET_REG_BITS == 32) {
eb664d0c 2141 tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
fecccfcc 2142 break;
eb664d0c 2143 }
fecccfcc
RH		 2144 /* fall through */
2145 case INDEX_op_qemu_st_a32_i32:
2146 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
afa05235 2147 break;
fecccfcc 2148 case INDEX_op_qemu_st_a32_i64:
eb664d0c
RH		 2149 if (TCG_TARGET_REG_BITS == 64) {
2150 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
fecccfcc 2151 } else {
eb664d0c 2152 tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
fecccfcc
RH		 2153 }
2154 break;
2155 case INDEX_op_qemu_st_a64_i64:
2156 if (TCG_TARGET_REG_BITS == 64) {
2157 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
eb664d0c
RH		 2158 } else {
2159 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
2160 }
afa05235
AJ		 2161 break;
2162
741f117d
RH		 2163 case INDEX_op_add2_i32:
2164 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2165 const_args[4], const_args[5], false);
2166 break;
2167 case INDEX_op_sub2_i32:
2168 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2169 const_args[4], const_args[5], true);
2170 break;
2171
6f0b9910
PK		 2172 case INDEX_op_mb:
2173 tcg_out_mb(s, a0);
2174 break;
96d0ee7f 2175 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
0119b192 2176 case INDEX_op_mov_i64:
96d0ee7f 2177 case INDEX_op_call: /* Always emitted via tcg_out_call. */
b55a8d9d 2178 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
cf7d6b8e 2179 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
678155b2
RH		 2180 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
2181 case INDEX_op_ext8s_i64:
d0e66c89
RH		 2182 case INDEX_op_ext8u_i32:
2183 case INDEX_op_ext8u_i64:
753e42ea
RH		 2184 case INDEX_op_ext16s_i32:
2185 case INDEX_op_ext16s_i64:
52bf3398 2186 case INDEX_op_ext32s_i64:
9ecf5f61 2187 case INDEX_op_ext32u_i64:
9c6aa274 2188 case INDEX_op_ext_i32_i64:
b9bfe000 2189 case INDEX_op_extu_i32_i64:
b8b94ac6 2190 case INDEX_op_extrl_i64_i32:
afa05235 2191 default:
732e89f4 2192 g_assert_not_reached();
afa05235
AJ		 2193 }
2194}
2195
0263330b 2196static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
89b2e37e 2197{
89b2e37e
RH		 2198 switch (op) {
2199 case INDEX_op_goto_ptr:
0263330b 2200 return C_O0_I1(r);
afa05235 2201
89b2e37e
RH		 2202 case INDEX_op_ld8u_i32:
2203 case INDEX_op_ld8s_i32:
2204 case INDEX_op_ld16u_i32:
2205 case INDEX_op_ld16s_i32:
2206 case INDEX_op_ld_i32:
2207 case INDEX_op_not_i32:
2208 case INDEX_op_bswap16_i32:
2209 case INDEX_op_bswap32_i32:
2210 case INDEX_op_ext8s_i32:
2211 case INDEX_op_ext16s_i32:
2212 case INDEX_op_extract_i32:
2213 case INDEX_op_ld8u_i64:
2214 case INDEX_op_ld8s_i64:
2215 case INDEX_op_ld16u_i64:
2216 case INDEX_op_ld16s_i64:
2217 case INDEX_op_ld32s_i64:
2218 case INDEX_op_ld32u_i64:
2219 case INDEX_op_ld_i64:
2220 case INDEX_op_not_i64:
2221 case INDEX_op_bswap16_i64:
2222 case INDEX_op_bswap32_i64:
2223 case INDEX_op_bswap64_i64:
2224 case INDEX_op_ext8s_i64:
2225 case INDEX_op_ext16s_i64:
2226 case INDEX_op_ext32s_i64:
2227 case INDEX_op_ext32u_i64:
2228 case INDEX_op_ext_i32_i64:
2229 case INDEX_op_extu_i32_i64:
2230 case INDEX_op_extrl_i64_i32:
2231 case INDEX_op_extrh_i64_i32:
2232 case INDEX_op_extract_i64:
0263330b 2233 return C_O1_I1(r, r);
afa05235 2234
89b2e37e
RH		 2235 case INDEX_op_st8_i32:
2236 case INDEX_op_st16_i32:
2237 case INDEX_op_st_i32:
2238 case INDEX_op_st8_i64:
2239 case INDEX_op_st16_i64:
2240 case INDEX_op_st32_i64:
2241 case INDEX_op_st_i64:
0263330b 2242 return C_O0_I2(rZ, r);
6f0b9910 2243
89b2e37e
RH		 2244 case INDEX_op_add_i32:
2245 case INDEX_op_add_i64:
0263330b 2246 return C_O1_I2(r, r, rJ);
89b2e37e
RH		 2247 case INDEX_op_sub_i32:
2248 case INDEX_op_sub_i64:
0263330b 2249 return C_O1_I2(r, rZ, rN);
89b2e37e
RH		 2250 case INDEX_op_mul_i32:
2251 case INDEX_op_mulsh_i32:
2252 case INDEX_op_muluh_i32:
2253 case INDEX_op_div_i32:
2254 case INDEX_op_divu_i32:
2255 case INDEX_op_rem_i32:
2256 case INDEX_op_remu_i32:
2257 case INDEX_op_nor_i32:
2258 case INDEX_op_setcond_i32:
2259 case INDEX_op_mul_i64:
2260 case INDEX_op_mulsh_i64:
2261 case INDEX_op_muluh_i64:
2262 case INDEX_op_div_i64:
2263 case INDEX_op_divu_i64:
2264 case INDEX_op_rem_i64:
2265 case INDEX_op_remu_i64:
2266 case INDEX_op_nor_i64:
2267 case INDEX_op_setcond_i64:
0263330b 2268 return C_O1_I2(r, rZ, rZ);
89b2e37e
RH		 2269 case INDEX_op_muls2_i32:
2270 case INDEX_op_mulu2_i32:
2271 case INDEX_op_muls2_i64:
2272 case INDEX_op_mulu2_i64:
0263330b 2273 return C_O2_I2(r, r, r, r);
89b2e37e
RH		 2274 case INDEX_op_and_i32:
2275 case INDEX_op_and_i64:
0263330b 2276 return C_O1_I2(r, r, rIK);
89b2e37e
RH		 2277 case INDEX_op_or_i32:
2278 case INDEX_op_xor_i32:
2279 case INDEX_op_or_i64:
2280 case INDEX_op_xor_i64:
0263330b 2281 return C_O1_I2(r, r, rI);
89b2e37e
RH		 2282 case INDEX_op_shl_i32:
2283 case INDEX_op_shr_i32:
2284 case INDEX_op_sar_i32:
2285 case INDEX_op_rotr_i32:
2286 case INDEX_op_rotl_i32:
2287 case INDEX_op_shl_i64:
2288 case INDEX_op_shr_i64:
2289 case INDEX_op_sar_i64:
2290 case INDEX_op_rotr_i64:
2291 case INDEX_op_rotl_i64:
0263330b 2292 return C_O1_I2(r, r, ri);
89b2e37e
RH		 2293 case INDEX_op_clz_i32:
2294 case INDEX_op_clz_i64:
0263330b 2295 return C_O1_I2(r, r, rWZ);
afa05235 2296
89b2e37e
RH		 2297 case INDEX_op_deposit_i32:
2298 case INDEX_op_deposit_i64:
0263330b 2299 return C_O1_I2(r, 0, rZ);
89b2e37e
RH		 2300 case INDEX_op_brcond_i32:
2301 case INDEX_op_brcond_i64:
0263330b 2302 return C_O0_I2(rZ, rZ);
89b2e37e
RH		 2303 case INDEX_op_movcond_i32:
2304 case INDEX_op_movcond_i64:
0263330b
RH		 2305 return (use_mips32r6_instructions
2306 ? C_O1_I4(r, rZ, rZ, rZ, rZ)
2307 : C_O1_I4(r, rZ, rZ, rZ, 0));
89b2e37e
RH		 2308 case INDEX_op_add2_i32:
2309 case INDEX_op_sub2_i32:
0263330b 2310 return C_O2_I4(r, r, rZ, rZ, rN, rN);
89b2e37e 2311 case INDEX_op_setcond2_i32:
0263330b 2312 return C_O1_I4(r, rZ, rZ, rZ, rZ);
89b2e37e 2313 case INDEX_op_brcond2_i32:
0263330b 2314 return C_O0_I4(rZ, rZ, rZ, rZ);
89b2e37e 2315
fecccfcc
RH		 2316 case INDEX_op_qemu_ld_a32_i32:
2317 return C_O1_I1(r, r);
2318 case INDEX_op_qemu_ld_a64_i32:
2319 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
2320 case INDEX_op_qemu_st_a32_i32:
2321 return C_O0_I2(rZ, r);
2322 case INDEX_op_qemu_st_a64_i32:
2323 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r);
2324 case INDEX_op_qemu_ld_a32_i64:
2325 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
2326 case INDEX_op_qemu_ld_a64_i64:
2327 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
2328 case INDEX_op_qemu_st_a32_i64:
2329 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r);
2330 case INDEX_op_qemu_st_a64_i64:
f48cc902 2331 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r)
f48cc902 2332 : C_O0_I4(rZ, rZ, r, r));
89b2e37e
RH		 2333
2334 default:
0263330b 2335 g_assert_not_reached();
f69d277e 2336 }
f69d277e
RH		 2337}
2338
d453ec78 2339static const int tcg_target_callee_save_regs[] = {
d721cc94 2340 TCG_REG_S0,
afa05235
AJ		 2341 TCG_REG_S1,
2342 TCG_REG_S2,
2343 TCG_REG_S3,
2344 TCG_REG_S4,
2345 TCG_REG_S5,
53c4fa27 2346 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */
43b4cd97 2347 TCG_REG_S7, /* used for guest_base */
d721cc94 2348 TCG_REG_S8, /* used for the global env (TCG_AREG0) */
afa05235
AJ		 2349 TCG_REG_RA, /* should be last for ABI compliance */
2350};
2351
988902fc
AJ		 2352/* The Linux kernel doesn't provide any information about the available
2353 instruction set. Probe it using a signal handler. */
2354
988902fc
AJ		 2355
2356#ifndef use_movnz_instructions
2357bool use_movnz_instructions = false;
2358#endif
2359
2360#ifndef use_mips32_instructions
2361bool use_mips32_instructions = false;
2362#endif
2363
2364#ifndef use_mips32r2_instructions
2365bool use_mips32r2_instructions = false;
2366#endif
2367
2368static volatile sig_atomic_t got_sigill;
2369
2370static void sigill_handler(int signo, siginfo_t *si, void *data)
2371{
2372 /* Skip the faulty instruction */
2373 ucontext_t *uc = (ucontext_t *)data;
2374 uc->uc_mcontext.pc += 4;
2375
2376 got_sigill = 1;
2377}
2378
2379static void tcg_target_detect_isa(void)
2380{
2381 struct sigaction sa_old, sa_new;
2382
2383 memset(&sa_new, 0, sizeof(sa_new));
2384 sa_new.sa_flags = SA_SIGINFO;
2385 sa_new.sa_sigaction = sigill_handler;
2386 sigaction(SIGILL, &sa_new, &sa_old);
2387
2388 /* Probe for movn/movz, necessary to implement movcond. */
2389#ifndef use_movnz_instructions
2390 got_sigill = 0;
2391 asm volatile(".set push\n"
2392 ".set mips32\n"
2393 "movn $zero, $zero, $zero\n"
2394 "movz $zero, $zero, $zero\n"
2395 ".set pop\n"
2396 : : : );
2397 use_movnz_instructions = !got_sigill;
2398#endif
2399
2400 /* Probe for MIPS32 instructions. As no subsetting is allowed
2401 by the specification, it is only necessary to probe for one
2402 of the instructions. */
2403#ifndef use_mips32_instructions
2404 got_sigill = 0;
2405 asm volatile(".set push\n"
2406 ".set mips32\n"
2407 "mul $zero, $zero\n"
2408 ".set pop\n"
2409 : : : );
2410 use_mips32_instructions = !got_sigill;
2411#endif
2412
2413 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2414 available. As no subsetting is allowed by the specification,
2415 it is only necessary to probe for one of the instructions. */
2416#ifndef use_mips32r2_instructions
2417 if (use_mips32_instructions) {
2418 got_sigill = 0;
2419 asm volatile(".set push\n"
2420 ".set mips32r2\n"
2421 "seb $zero, $zero\n"
2422 ".set pop\n"
2423 : : : );
2424 use_mips32r2_instructions = !got_sigill;
2425 }
2426#endif
2427
2428 sigaction(SIGILL, &sa_old, NULL);
2429}
2430
bb08afe9
JG		 2431static tcg_insn_unit *align_code_ptr(TCGContext *s)
2432{
2433 uintptr_t p = (uintptr_t)s->code_ptr;
2434 if (p & 15) {
2435 p = (p + 15) & -16;
2436 s->code_ptr = (void *)p;
2437 }
2438 return s->code_ptr;
2439}
2440
0973b1cf
JG		 2441/* Stack frame parameters. */
2442#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2443#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2444#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2445
2446#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2447 + TCG_TARGET_STACK_ALIGN - 1) \
2448 & -TCG_TARGET_STACK_ALIGN)
2449#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2450
2451/* We're expecting to be able to use an immediate for frame allocation. */
2452QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2453
afa05235 2454/* Generate global QEMU prologue and epilogue code */
e4d58b41 2455static void tcg_target_qemu_prologue(TCGContext *s)
afa05235 2456{
0973b1cf
JG		 2457 int i;
2458
2459 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
afa05235
AJ		 2460
2461 /* TB prologue */
0973b1cf
JG		 2462 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2463 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2464 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2465 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
afa05235
AJ		 2466 }
2467
4df9cac5 2468#ifndef CONFIG_SOFTMMU
f63eb2e5 2469 if (guest_base != (int16_t)guest_base) {
48c12ba7
RH		 2470 /*
2471 * The function call abi for n32 and n64 will have loaded $25 (t9)
2472 * with the address of the prologue, so we can use that instead
2473 * of TCG_REG_TB.
2474 */
2475#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls)
2476# error "Unknown mips abi"
2477#endif
2478 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base,
2479 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0);
4df9cac5
JB		 2480 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2481 }
2482#endif
48c12ba7 2483
53c4fa27
RH		 2484 if (TCG_TARGET_REG_BITS == 64) {
2485 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
2486 }
4df9cac5 2487
afa05235 2488 /* Call generated code */
ea15fb06 2489 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
0973b1cf 2490 /* delay slot */
cea5f9a2 2491 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
afa05235 2492
5786e068
AJ		 2493 /*
2494 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2495 * and fall through to the rest of the epilogue.
2496 */
c8bc1168 2497 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
5786e068
AJ		 2498 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2499
afa05235 2500 /* TB epilogue */
df5af130 2501 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
0973b1cf
JG		 2502 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2503 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2504 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
afa05235
AJ		 2505 }
2506
2507 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
bb08afe9 2508 /* delay slot */
0973b1cf 2509 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
bb08afe9
JG		 2510
2511 if (use_mips32r2_instructions) {
2512 return;
2513 }
2514
7f54eaa3 2515 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
bb08afe9
JG		 2516 clobbers TCG_TMP1, TCG_TMP2. */
2517
2518 /*
2519 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2520 */
df5af130 2521 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s));
bb08afe9
JG		 2522 /* t3 = (ssss)d000 */
2523 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2524 /* t1 = 000a */
2525 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2526 /* t2 = 00c0 */
2527 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2528 /* t3 = d00a */
2529 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2530 /* t1 = 0abc */
2531 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2532 /* t2 = 0c00 */
2533 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2534 /* t1 = 00b0 */
2535 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2536 /* t3 = dc0a */
2537 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2538 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2539 /* t3 = dcba -- delay slot */
2540 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
7f54eaa3
JG		 2541
2542 if (TCG_TARGET_REG_BITS == 32) {
2543 return;
2544 }
2545
2546 /*
2547 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2548 */
df5af130 2549 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s));
7f54eaa3
JG		 2550 /* t1 = (0000)000d */
2551 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2552 /* t3 = 000a */
2553 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2554 /* t1 = (0000)d000 */
2555 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2556 /* t2 = 00c0 */
2557 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2558 /* t3 = d00a */
2559 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2560 /* t1 = 0abc */
2561 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2562 /* t2 = 0c00 */
2563 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2564 /* t1 = 00b0 */
2565 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2566 /* t3 = dc0a */
2567 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2568 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2569 /* t3 = dcba -- delay slot */
2570 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2571
2572 /*
2573 * bswap64 -- 64-bit swap. a0 = abcdefgh
2574 */
df5af130 2575 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s));
7f54eaa3
JG		 2576 /* t3 = h0000000 */
2577 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2578 /* t1 = 0000000a */
2579 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2580
2581 /* t2 = 000000g0 */
2582 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2583 /* t3 = h000000a */
2584 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2585 /* t1 = 00000abc */
2586 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2587 /* t2 = 0g000000 */
2588 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2589 /* t1 = 000000b0 */
2590 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2591
2592 /* t3 = hg00000a */
2593 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2594 /* t2 = 0000abcd */
2595 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2596 /* t3 = hg0000ba */
2597 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2598
2599 /* t1 = 000000c0 */
2600 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2601 /* t2 = 0000000d */
2602 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2603 /* t1 = 00000c00 */
2604 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2605 /* t2 = 0000d000 */
2606 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2607
2608 /* t3 = hg000cba */
2609 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2610 /* t1 = 00abcdef */
2611 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2612 /* t3 = hg00dcba */
2613 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2614
2615 /* t2 = 0000000f */
2616 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2617 /* t1 = 000000e0 */
2618 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2619 /* t2 = 00f00000 */
2620 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2621 /* t1 = 000e0000 */
2622 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2623
2624 /* t3 = hgf0dcba */
2625 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2626 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2627 /* t3 = hgfedcba -- delay slot */
2628 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
afa05235
AJ		 2629}
2630
9358fbbf
RH		 2631static void tcg_out_tb_start(TCGContext *s)
2632{
2633 /* nothing to do */
2634}
2635
e4d58b41 2636static void tcg_target_init(TCGContext *s)
afa05235 2637{
988902fc 2638 tcg_target_detect_isa();
d21369f5 2639 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
999b9416 2640 if (TCG_TARGET_REG_BITS == 64) {
d21369f5
RH		 2641 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2642 }
2643
2644 tcg_target_call_clobber_regs = 0;
2645 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2646 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2647 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2648 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2649 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2650 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2651 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2652 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2653 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2654 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2655 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2656 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2657 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2658 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2659 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2660 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
afa05235 2661
ccb1bb66 2662 s->reserved_regs = 0;
afa05235
AJ		 2663 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2664 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2665 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
6c530e32
RH		 2666 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2667 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
bb08afe9
JG		 2668 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2669 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
afa05235
AJ		 2670 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2671 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
3314e008 2672 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
53c4fa27
RH		 2673 if (TCG_TARGET_REG_BITS == 64) {
2674 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */
2675 }
afa05235 2676}
b6bfeea9 2677
98d69076
JG		 2678typedef struct {
2679 DebugFrameHeader h;
2680 uint8_t fde_def_cfa[4];
2681 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2682} DebugFrame;
2683
2684#define ELF_HOST_MACHINE EM_MIPS
2685/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2686 which is good because they're really quite complicated for MIPS. */
2687
2688static const DebugFrame debug_frame = {
2689 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2690 .h.cie.id = -1,
2691 .h.cie.version = 1,
2692 .h.cie.code_align = 1,
2693 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2694 .h.cie.return_column = TCG_REG_RA,
2695
2696 /* Total FDE size does not include the "len" member. */
2697 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2698
2699 .fde_def_cfa = {
2700 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2701 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2702 (FRAME_SIZE >> 7)
2703 },
2704 .fde_reg_ofs = {
2705 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2706 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2707 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2708 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2709 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2710 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2711 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2712 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2713 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2714 }
2715};
2716
755bf9e5 2717void tcg_register_jit(const void *buf, size_t buf_size)
98d69076
JG		 2718{
2719 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2720}
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