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afa05235 AJ |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> | |
5 | * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> | |
6 | * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
26 | ||
9d8bf2d1 RH |
27 | #ifdef HOST_WORDS_BIGENDIAN |
28 | # define MIPS_BE 1 | |
afa05235 | 29 | #else |
9d8bf2d1 | 30 | # define MIPS_BE 0 |
afa05235 AJ |
31 | #endif |
32 | ||
f0d70331 JG |
33 | #if TCG_TARGET_REG_BITS == 32 |
34 | # define LO_OFF (MIPS_BE * 4) | |
35 | # define HI_OFF (4 - LO_OFF) | |
36 | #else | |
37 | /* To assert at compile-time that these values are never used | |
38 | for TCG_TARGET_REG_BITS == 64. */ | |
8df8d529 | 39 | int link_error(void); |
f0d70331 JG |
40 | # define LO_OFF link_error() |
41 | # define HI_OFF link_error() | |
42 | #endif | |
9d8bf2d1 | 43 | |
8d8fdbae | 44 | #ifdef CONFIG_DEBUG_TCG |
afa05235 AJ |
45 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
46 | "zero", | |
47 | "at", | |
48 | "v0", | |
49 | "v1", | |
50 | "a0", | |
51 | "a1", | |
52 | "a2", | |
53 | "a3", | |
54 | "t0", | |
55 | "t1", | |
56 | "t2", | |
57 | "t3", | |
58 | "t4", | |
59 | "t5", | |
60 | "t6", | |
61 | "t7", | |
62 | "s0", | |
63 | "s1", | |
64 | "s2", | |
65 | "s3", | |
66 | "s4", | |
67 | "s5", | |
68 | "s6", | |
69 | "s7", | |
70 | "t8", | |
71 | "t9", | |
72 | "k0", | |
73 | "k1", | |
74 | "gp", | |
75 | "sp", | |
41883904 | 76 | "s8", |
afa05235 AJ |
77 | "ra", |
78 | }; | |
79 | #endif | |
80 | ||
6c530e32 | 81 | #define TCG_TMP0 TCG_REG_AT |
f216a35f | 82 | #define TCG_TMP1 TCG_REG_T9 |
bb08afe9 JG |
83 | #define TCG_TMP2 TCG_REG_T8 |
84 | #define TCG_TMP3 TCG_REG_T7 | |
6c530e32 | 85 | |
4df9cac5 JB |
86 | #ifndef CONFIG_SOFTMMU |
87 | #define TCG_GUEST_BASE_REG TCG_REG_S1 | |
88 | #endif | |
89 | ||
afa05235 | 90 | /* check if we really need so many registers :P */ |
2dc7553d | 91 | static const int tcg_target_reg_alloc_order[] = { |
41883904 | 92 | /* Call saved registers. */ |
afa05235 AJ |
93 | TCG_REG_S0, |
94 | TCG_REG_S1, | |
95 | TCG_REG_S2, | |
96 | TCG_REG_S3, | |
97 | TCG_REG_S4, | |
98 | TCG_REG_S5, | |
99 | TCG_REG_S6, | |
100 | TCG_REG_S7, | |
41883904 RH |
101 | TCG_REG_S8, |
102 | ||
103 | /* Call clobbered registers. */ | |
afa05235 AJ |
104 | TCG_REG_T4, |
105 | TCG_REG_T5, | |
106 | TCG_REG_T6, | |
107 | TCG_REG_T7, | |
108 | TCG_REG_T8, | |
109 | TCG_REG_T9, | |
41883904 | 110 | TCG_REG_V1, |
afa05235 | 111 | TCG_REG_V0, |
41883904 RH |
112 | |
113 | /* Argument registers, opposite order of allocation. */ | |
999b9416 JG |
114 | TCG_REG_T3, |
115 | TCG_REG_T2, | |
116 | TCG_REG_T1, | |
117 | TCG_REG_T0, | |
41883904 RH |
118 | TCG_REG_A3, |
119 | TCG_REG_A2, | |
120 | TCG_REG_A1, | |
121 | TCG_REG_A0, | |
afa05235 AJ |
122 | }; |
123 | ||
999b9416 | 124 | static const TCGReg tcg_target_call_iarg_regs[] = { |
afa05235 AJ |
125 | TCG_REG_A0, |
126 | TCG_REG_A1, | |
127 | TCG_REG_A2, | |
999b9416 JG |
128 | TCG_REG_A3, |
129 | #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 | |
130 | TCG_REG_T0, | |
131 | TCG_REG_T1, | |
132 | TCG_REG_T2, | |
133 | TCG_REG_T3, | |
134 | #endif | |
afa05235 AJ |
135 | }; |
136 | ||
5a0eed37 | 137 | static const TCGReg tcg_target_call_oarg_regs[2] = { |
afa05235 AJ |
138 | TCG_REG_V0, |
139 | TCG_REG_V1 | |
140 | }; | |
141 | ||
df5af130 RH |
142 | static const tcg_insn_unit *tb_ret_addr; |
143 | static const tcg_insn_unit *bswap32_addr; | |
144 | static const tcg_insn_unit *bswap32u_addr; | |
145 | static const tcg_insn_unit *bswap64_addr; | |
afa05235 | 146 | |
df5af130 | 147 | static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) |
afa05235 | 148 | { |
ae0218e3 | 149 | /* Let the compiler perform the right-shift as part of the arithmetic. */ |
df5af130 RH |
150 | const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); |
151 | ptrdiff_t disp = target - (src_rx + 1); | |
91a7fd1f | 152 | if (disp == (int16_t)disp) { |
df5af130 | 153 | *src_rw = deposit32(*src_rw, 0, 16, disp); |
91a7fd1f RH |
154 | return true; |
155 | } | |
156 | return false; | |
afa05235 AJ |
157 | } |
158 | ||
6ac17786 | 159 | static bool patch_reloc(tcg_insn_unit *code_ptr, int type, |
2ba7fae2 | 160 | intptr_t value, intptr_t addend) |
afa05235 | 161 | { |
eabb7b91 AJ |
162 | tcg_debug_assert(type == R_MIPS_PC16); |
163 | tcg_debug_assert(addend == 0); | |
91a7fd1f | 164 | return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); |
afa05235 AJ |
165 | } |
166 | ||
1c418268 | 167 | #define TCG_CT_CONST_ZERO 0x100 |
070603f6 RH |
168 | #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ |
169 | #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ | |
170 | #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ | |
171 | #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ | |
2a1d9d41 | 172 | #define TCG_CT_CONST_WSZ 0x2000 /* word size */ |
1c418268 | 173 | |
51800e43 RH |
174 | #define ALL_GENERAL_REGS 0xffffffffu |
175 | #define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) | |
176 | ||
177 | #ifdef CONFIG_SOFTMMU | |
178 | #define ALL_QLOAD_REGS \ | |
179 | (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) | |
180 | #define ALL_QSTORE_REGS \ | |
181 | (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ | |
182 | ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ | |
183 | : (1 << TCG_REG_A1))) | |
184 | #else | |
185 | #define ALL_QLOAD_REGS NOA0_REGS | |
186 | #define ALL_QSTORE_REGS NOA0_REGS | |
187 | #endif | |
188 | ||
189 | ||
10d4af58 | 190 | static bool is_p2m1(tcg_target_long val) |
1c418268 RH |
191 | { |
192 | return val && ((val + 1) & val) == 0; | |
193 | } | |
194 | ||
afa05235 | 195 | /* test if a constant matches the constraint */ |
a4fbbd77 | 196 | static bool tcg_target_const_match(int64_t val, TCGType type, int ct) |
afa05235 | 197 | { |
1c418268 | 198 | if (ct & TCG_CT_CONST) { |
afa05235 | 199 | return 1; |
1c418268 | 200 | } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { |
afa05235 | 201 | return 1; |
1c418268 | 202 | } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { |
afa05235 | 203 | return 1; |
1c418268 | 204 | } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { |
afa05235 | 205 | return 1; |
070603f6 RH |
206 | } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { |
207 | return 1; | |
1c418268 RH |
208 | } else if ((ct & TCG_CT_CONST_P2M1) |
209 | && use_mips32r2_instructions && is_p2m1(val)) { | |
210 | return 1; | |
2a1d9d41 RH |
211 | } else if ((ct & TCG_CT_CONST_WSZ) |
212 | && val == (type == TCG_TYPE_I32 ? 32 : 64)) { | |
213 | return 1; | |
1c418268 RH |
214 | } |
215 | return 0; | |
afa05235 AJ |
216 | } |
217 | ||
218 | /* instruction opcodes */ | |
ac0f3b12 | 219 | typedef enum { |
57a701fc JG |
220 | OPC_J = 002 << 26, |
221 | OPC_JAL = 003 << 26, | |
222 | OPC_BEQ = 004 << 26, | |
223 | OPC_BNE = 005 << 26, | |
224 | OPC_BLEZ = 006 << 26, | |
225 | OPC_BGTZ = 007 << 26, | |
226 | OPC_ADDIU = 011 << 26, | |
227 | OPC_SLTI = 012 << 26, | |
228 | OPC_SLTIU = 013 << 26, | |
229 | OPC_ANDI = 014 << 26, | |
230 | OPC_ORI = 015 << 26, | |
231 | OPC_XORI = 016 << 26, | |
232 | OPC_LUI = 017 << 26, | |
233 | OPC_DADDIU = 031 << 26, | |
234 | OPC_LB = 040 << 26, | |
235 | OPC_LH = 041 << 26, | |
236 | OPC_LW = 043 << 26, | |
237 | OPC_LBU = 044 << 26, | |
238 | OPC_LHU = 045 << 26, | |
239 | OPC_LWU = 047 << 26, | |
240 | OPC_SB = 050 << 26, | |
241 | OPC_SH = 051 << 26, | |
242 | OPC_SW = 053 << 26, | |
243 | OPC_LD = 067 << 26, | |
244 | OPC_SD = 077 << 26, | |
245 | ||
246 | OPC_SPECIAL = 000 << 26, | |
247 | OPC_SLL = OPC_SPECIAL | 000, | |
248 | OPC_SRL = OPC_SPECIAL | 002, | |
249 | OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), | |
250 | OPC_SRA = OPC_SPECIAL | 003, | |
251 | OPC_SLLV = OPC_SPECIAL | 004, | |
252 | OPC_SRLV = OPC_SPECIAL | 006, | |
253 | OPC_ROTRV = OPC_SPECIAL | 006 | 0100, | |
254 | OPC_SRAV = OPC_SPECIAL | 007, | |
255 | OPC_JR_R5 = OPC_SPECIAL | 010, | |
256 | OPC_JALR = OPC_SPECIAL | 011, | |
257 | OPC_MOVZ = OPC_SPECIAL | 012, | |
258 | OPC_MOVN = OPC_SPECIAL | 013, | |
259 | OPC_SYNC = OPC_SPECIAL | 017, | |
260 | OPC_MFHI = OPC_SPECIAL | 020, | |
261 | OPC_MFLO = OPC_SPECIAL | 022, | |
262 | OPC_DSLLV = OPC_SPECIAL | 024, | |
263 | OPC_DSRLV = OPC_SPECIAL | 026, | |
264 | OPC_DROTRV = OPC_SPECIAL | 026 | 0100, | |
265 | OPC_DSRAV = OPC_SPECIAL | 027, | |
266 | OPC_MULT = OPC_SPECIAL | 030, | |
267 | OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, | |
268 | OPC_MUH = OPC_SPECIAL | 030 | 0300, | |
269 | OPC_MULTU = OPC_SPECIAL | 031, | |
270 | OPC_MULU = OPC_SPECIAL | 031 | 0200, | |
271 | OPC_MUHU = OPC_SPECIAL | 031 | 0300, | |
272 | OPC_DIV = OPC_SPECIAL | 032, | |
273 | OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, | |
274 | OPC_MOD = OPC_SPECIAL | 032 | 0300, | |
275 | OPC_DIVU = OPC_SPECIAL | 033, | |
276 | OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, | |
277 | OPC_MODU = OPC_SPECIAL | 033 | 0300, | |
278 | OPC_DMULT = OPC_SPECIAL | 034, | |
279 | OPC_DMUL = OPC_SPECIAL | 034 | 0200, | |
280 | OPC_DMUH = OPC_SPECIAL | 034 | 0300, | |
281 | OPC_DMULTU = OPC_SPECIAL | 035, | |
282 | OPC_DMULU = OPC_SPECIAL | 035 | 0200, | |
283 | OPC_DMUHU = OPC_SPECIAL | 035 | 0300, | |
284 | OPC_DDIV = OPC_SPECIAL | 036, | |
285 | OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, | |
286 | OPC_DMOD = OPC_SPECIAL | 036 | 0300, | |
287 | OPC_DDIVU = OPC_SPECIAL | 037, | |
288 | OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, | |
289 | OPC_DMODU = OPC_SPECIAL | 037 | 0300, | |
290 | OPC_ADDU = OPC_SPECIAL | 041, | |
291 | OPC_SUBU = OPC_SPECIAL | 043, | |
292 | OPC_AND = OPC_SPECIAL | 044, | |
293 | OPC_OR = OPC_SPECIAL | 045, | |
294 | OPC_XOR = OPC_SPECIAL | 046, | |
295 | OPC_NOR = OPC_SPECIAL | 047, | |
296 | OPC_SLT = OPC_SPECIAL | 052, | |
297 | OPC_SLTU = OPC_SPECIAL | 053, | |
298 | OPC_DADDU = OPC_SPECIAL | 055, | |
299 | OPC_DSUBU = OPC_SPECIAL | 057, | |
300 | OPC_SELEQZ = OPC_SPECIAL | 065, | |
301 | OPC_SELNEZ = OPC_SPECIAL | 067, | |
302 | OPC_DSLL = OPC_SPECIAL | 070, | |
303 | OPC_DSRL = OPC_SPECIAL | 072, | |
304 | OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), | |
305 | OPC_DSRA = OPC_SPECIAL | 073, | |
306 | OPC_DSLL32 = OPC_SPECIAL | 074, | |
307 | OPC_DSRL32 = OPC_SPECIAL | 076, | |
308 | OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), | |
309 | OPC_DSRA32 = OPC_SPECIAL | 077, | |
2a1d9d41 RH |
310 | OPC_CLZ_R6 = OPC_SPECIAL | 0120, |
311 | OPC_DCLZ_R6 = OPC_SPECIAL | 0122, | |
57a701fc JG |
312 | |
313 | OPC_REGIMM = 001 << 26, | |
314 | OPC_BLTZ = OPC_REGIMM | (000 << 16), | |
315 | OPC_BGEZ = OPC_REGIMM | (001 << 16), | |
316 | ||
317 | OPC_SPECIAL2 = 034 << 26, | |
318 | OPC_MUL_R5 = OPC_SPECIAL2 | 002, | |
2a1d9d41 RH |
319 | OPC_CLZ = OPC_SPECIAL2 | 040, |
320 | OPC_DCLZ = OPC_SPECIAL2 | 044, | |
57a701fc JG |
321 | |
322 | OPC_SPECIAL3 = 037 << 26, | |
323 | OPC_EXT = OPC_SPECIAL3 | 000, | |
324 | OPC_DEXTM = OPC_SPECIAL3 | 001, | |
325 | OPC_DEXTU = OPC_SPECIAL3 | 002, | |
326 | OPC_DEXT = OPC_SPECIAL3 | 003, | |
327 | OPC_INS = OPC_SPECIAL3 | 004, | |
328 | OPC_DINSM = OPC_SPECIAL3 | 005, | |
329 | OPC_DINSU = OPC_SPECIAL3 | 006, | |
330 | OPC_DINS = OPC_SPECIAL3 | 007, | |
331 | OPC_WSBH = OPC_SPECIAL3 | 00240, | |
332 | OPC_DSBH = OPC_SPECIAL3 | 00244, | |
333 | OPC_DSHD = OPC_SPECIAL3 | 00544, | |
334 | OPC_SEB = OPC_SPECIAL3 | 02040, | |
335 | OPC_SEH = OPC_SPECIAL3 | 03040, | |
6e0d0969 JH |
336 | |
337 | /* MIPS r6 doesn't have JR, JALR should be used instead */ | |
338 | OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, | |
bc6d0c22 JH |
339 | |
340 | /* | |
341 | * MIPS r6 replaces MUL with an alternative encoding which is | |
342 | * backwards-compatible at the assembly level. | |
343 | */ | |
344 | OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, | |
6f0b9910 PK |
345 | |
346 | /* MIPS r6 introduced names for weaker variants of SYNC. These are | |
347 | backward compatible to previous architecture revisions. */ | |
a4e57084 | 348 | OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, |
349 | OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, | |
350 | OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, | |
351 | OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, | |
352 | OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, | |
57a701fc JG |
353 | |
354 | /* Aliases for convenience. */ | |
355 | ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, | |
356 | ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, | |
357 | ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 | |
358 | ? OPC_SRL : OPC_DSRL, | |
ac0f3b12 | 359 | } MIPSInsn; |
afa05235 AJ |
360 | |
361 | /* | |
362 | * Type reg | |
363 | */ | |
10d4af58 RH |
364 | static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, |
365 | TCGReg rd, TCGReg rs, TCGReg rt) | |
afa05235 AJ |
366 | { |
367 | int32_t inst; | |
368 | ||
369 | inst = opc; | |
370 | inst |= (rs & 0x1F) << 21; | |
371 | inst |= (rt & 0x1F) << 16; | |
372 | inst |= (rd & 0x1F) << 11; | |
373 | tcg_out32(s, inst); | |
374 | } | |
375 | ||
376 | /* | |
377 | * Type immediate | |
378 | */ | |
10d4af58 RH |
379 | static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, |
380 | TCGReg rt, TCGReg rs, TCGArg imm) | |
afa05235 AJ |
381 | { |
382 | int32_t inst; | |
383 | ||
384 | inst = opc; | |
385 | inst |= (rs & 0x1F) << 21; | |
386 | inst |= (rt & 0x1F) << 16; | |
387 | inst |= (imm & 0xffff); | |
388 | tcg_out32(s, inst); | |
389 | } | |
390 | ||
1c418268 RH |
391 | /* |
392 | * Type bitfield | |
393 | */ | |
10d4af58 RH |
394 | static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, |
395 | TCGReg rs, int msb, int lsb) | |
1c418268 RH |
396 | { |
397 | int32_t inst; | |
398 | ||
399 | inst = opc; | |
400 | inst |= (rs & 0x1F) << 21; | |
401 | inst |= (rt & 0x1F) << 16; | |
402 | inst |= (msb & 0x1F) << 11; | |
403 | inst |= (lsb & 0x1F) << 6; | |
404 | tcg_out32(s, inst); | |
405 | } | |
406 | ||
10d4af58 RH |
407 | static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, |
408 | MIPSInsn oph, TCGReg rt, TCGReg rs, | |
0119b192 JG |
409 | int msb, int lsb) |
410 | { | |
411 | if (lsb >= 32) { | |
412 | opc = oph; | |
413 | msb -= 32; | |
414 | lsb -= 32; | |
415 | } else if (msb >= 32) { | |
416 | opc = opm; | |
417 | msb -= 32; | |
418 | } | |
419 | tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); | |
420 | } | |
421 | ||
6d8ff4d8 AJ |
422 | /* |
423 | * Type branch | |
424 | */ | |
10d4af58 | 425 | static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) |
6d8ff4d8 | 426 | { |
8c1b0792 | 427 | tcg_out_opc_imm(s, opc, rt, rs, 0); |
6d8ff4d8 AJ |
428 | } |
429 | ||
afa05235 AJ |
430 | /* |
431 | * Type sa | |
432 | */ | |
10d4af58 RH |
433 | static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, |
434 | TCGReg rd, TCGReg rt, TCGArg sa) | |
afa05235 AJ |
435 | { |
436 | int32_t inst; | |
437 | ||
438 | inst = opc; | |
439 | inst |= (rt & 0x1F) << 16; | |
440 | inst |= (rd & 0x1F) << 11; | |
441 | inst |= (sa & 0x1F) << 6; | |
442 | tcg_out32(s, inst); | |
443 | ||
444 | } | |
445 | ||
0119b192 JG |
446 | static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, |
447 | TCGReg rd, TCGReg rt, TCGArg sa) | |
448 | { | |
449 | int32_t inst; | |
450 | ||
451 | inst = (sa & 32 ? opc2 : opc1); | |
452 | inst |= (rt & 0x1F) << 16; | |
453 | inst |= (rd & 0x1F) << 11; | |
454 | inst |= (sa & 0x1F) << 6; | |
455 | tcg_out32(s, inst); | |
456 | } | |
457 | ||
f8c9eddb RH |
458 | /* |
459 | * Type jump. | |
460 | * Returns true if the branch was in range and the insn was emitted. | |
461 | */ | |
2be7d76b | 462 | static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) |
f8c9eddb RH |
463 | { |
464 | uintptr_t dest = (uintptr_t)target; | |
df5af130 | 465 | uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; |
f8c9eddb RH |
466 | int32_t inst; |
467 | ||
468 | /* The pc-region branch happens within the 256MB region of | |
469 | the delay slot (thus the +4). */ | |
470 | if ((from ^ dest) & -(1 << 28)) { | |
471 | return false; | |
472 | } | |
eabb7b91 | 473 | tcg_debug_assert((dest & 3) == 0); |
f8c9eddb RH |
474 | |
475 | inst = opc; | |
476 | inst |= (dest >> 2) & 0x3ffffff; | |
477 | tcg_out32(s, inst); | |
478 | return true; | |
479 | } | |
480 | ||
10d4af58 | 481 | static void tcg_out_nop(TCGContext *s) |
afa05235 AJ |
482 | { |
483 | tcg_out32(s, 0); | |
484 | } | |
485 | ||
10d4af58 | 486 | static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) |
0119b192 JG |
487 | { |
488 | tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); | |
489 | } | |
490 | ||
10d4af58 | 491 | static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) |
0119b192 JG |
492 | { |
493 | tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); | |
494 | } | |
495 | ||
10d4af58 | 496 | static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) |
0119b192 JG |
497 | { |
498 | tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); | |
499 | } | |
500 | ||
10d4af58 | 501 | static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) |
afa05235 | 502 | { |
18fec301 AJ |
503 | /* Simple reg-reg move, optimising out the 'do nothing' case */ |
504 | if (ret != arg) { | |
2294d05d | 505 | tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); |
18fec301 | 506 | } |
78113e83 | 507 | return true; |
afa05235 AJ |
508 | } |
509 | ||
2294d05d JG |
510 | static void tcg_out_movi(TCGContext *s, TCGType type, |
511 | TCGReg ret, tcg_target_long arg) | |
afa05235 | 512 | { |
2294d05d JG |
513 | if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { |
514 | arg = (int32_t)arg; | |
515 | } | |
afa05235 | 516 | if (arg == (int16_t)arg) { |
2294d05d JG |
517 | tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); |
518 | return; | |
519 | } | |
520 | if (arg == (uint16_t)arg) { | |
521 | tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); | |
522 | return; | |
523 | } | |
524 | if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { | |
525 | tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); | |
afa05235 | 526 | } else { |
2294d05d JG |
527 | tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); |
528 | if (arg & 0xffff0000ull) { | |
529 | tcg_out_dsll(s, ret, ret, 16); | |
530 | tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); | |
531 | tcg_out_dsll(s, ret, ret, 16); | |
532 | } else { | |
533 | tcg_out_dsll(s, ret, ret, 32); | |
7dae901d | 534 | } |
afa05235 | 535 | } |
2294d05d JG |
536 | if (arg & 0xffff) { |
537 | tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); | |
538 | } | |
afa05235 AJ |
539 | } |
540 | ||
27362b7b | 541 | static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) |
afa05235 | 542 | { |
27362b7b RH |
543 | /* ret and arg can't be register tmp0 */ |
544 | tcg_debug_assert(ret != TCG_TMP0); | |
545 | tcg_debug_assert(arg != TCG_TMP0); | |
546 | ||
547 | /* With arg = abcd: */ | |
988902fc | 548 | if (use_mips32r2_instructions) { |
27362b7b RH |
549 | tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ |
550 | if (flags & TCG_BSWAP_OS) { | |
551 | tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ | |
552 | } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { | |
553 | tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ | |
988902fc | 554 | } |
27362b7b | 555 | return; |
988902fc | 556 | } |
afa05235 | 557 | |
27362b7b RH |
558 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ |
559 | if (!(flags & TCG_BSWAP_IZ)) { | |
560 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ | |
561 | } | |
562 | if (flags & TCG_BSWAP_OS) { | |
563 | tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ | |
564 | tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ | |
988902fc | 565 | } else { |
27362b7b RH |
566 | tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ |
567 | if (flags & TCG_BSWAP_OZ) { | |
568 | tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ | |
988902fc | 569 | } |
988902fc | 570 | } |
27362b7b | 571 | tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ |
afa05235 AJ |
572 | } |
573 | ||
df5af130 | 574 | static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) |
bb08afe9 | 575 | { |
d7fc9f48 RH |
576 | if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { |
577 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); | |
578 | tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); | |
579 | } | |
bb08afe9 JG |
580 | } |
581 | ||
1fce6534 | 582 | static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) |
afa05235 | 583 | { |
988902fc AJ |
584 | if (use_mips32r2_instructions) { |
585 | tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); | |
586 | tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); | |
1fce6534 RH |
587 | if (flags & TCG_BSWAP_OZ) { |
588 | tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); | |
589 | } | |
988902fc | 590 | } else { |
1fce6534 RH |
591 | if (flags & TCG_BSWAP_OZ) { |
592 | tcg_out_bswap_subr(s, bswap32u_addr); | |
593 | } else { | |
594 | tcg_out_bswap_subr(s, bswap32_addr); | |
595 | } | |
7f54eaa3 JG |
596 | /* delay slot -- never omit the insn, like tcg_out_mov might. */ |
597 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); | |
598 | tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); | |
0119b192 JG |
599 | } |
600 | } | |
601 | ||
602 | static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) | |
603 | { | |
604 | if (use_mips32r2_instructions) { | |
605 | tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); | |
606 | tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); | |
607 | } else { | |
7f54eaa3 JG |
608 | tcg_out_bswap_subr(s, bswap64_addr); |
609 | /* delay slot -- never omit the insn, like tcg_out_mov might. */ | |
610 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); | |
611 | tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); | |
0119b192 JG |
612 | } |
613 | } | |
614 | ||
10d4af58 | 615 | static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) |
0119b192 JG |
616 | { |
617 | if (use_mips32r2_instructions) { | |
618 | tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); | |
619 | } else { | |
620 | tcg_out_dsll(s, ret, arg, 32); | |
621 | tcg_out_dsrl(s, ret, ret, 32); | |
622 | } | |
623 | } | |
624 | ||
ac0f3b12 | 625 | static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, |
f9a71632 | 626 | TCGReg addr, intptr_t ofs) |
afa05235 | 627 | { |
f9a71632 RH |
628 | int16_t lo = ofs; |
629 | if (ofs != lo) { | |
6c530e32 | 630 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); |
f9a71632 | 631 | if (addr != TCG_REG_ZERO) { |
32b69707 | 632 | tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); |
f9a71632 | 633 | } |
6c530e32 | 634 | addr = TCG_TMP0; |
afa05235 | 635 | } |
f9a71632 | 636 | tcg_out_opc_imm(s, opc, data, addr, lo); |
afa05235 AJ |
637 | } |
638 | ||
10d4af58 RH |
639 | static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, |
640 | TCGReg arg1, intptr_t arg2) | |
afa05235 | 641 | { |
32b69707 JG |
642 | MIPSInsn opc = OPC_LD; |
643 | if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { | |
644 | opc = OPC_LW; | |
645 | } | |
646 | tcg_out_ldst(s, opc, arg, arg1, arg2); | |
afa05235 AJ |
647 | } |
648 | ||
10d4af58 RH |
649 | static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
650 | TCGReg arg1, intptr_t arg2) | |
afa05235 | 651 | { |
32b69707 JG |
652 | MIPSInsn opc = OPC_SD; |
653 | if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { | |
654 | opc = OPC_SW; | |
655 | } | |
656 | tcg_out_ldst(s, opc, arg, arg1, arg2); | |
afa05235 AJ |
657 | } |
658 | ||
10d4af58 RH |
659 | static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, |
660 | TCGReg base, intptr_t ofs) | |
59d7c14e RH |
661 | { |
662 | if (val == 0) { | |
663 | tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); | |
664 | return true; | |
665 | } | |
666 | return false; | |
667 | } | |
668 | ||
d9f26847 AJ |
669 | static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, |
670 | TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, | |
671 | bool cbh, bool is_sub) | |
672 | { | |
673 | TCGReg th = TCG_TMP1; | |
674 | ||
675 | /* If we have a negative constant such that negating it would | |
676 | make the high part zero, we can (usually) eliminate one insn. */ | |
677 | if (cbl && cbh && bh == -1 && bl != 0) { | |
678 | bl = -bl; | |
679 | bh = 0; | |
680 | is_sub = !is_sub; | |
681 | } | |
682 | ||
683 | /* By operating on the high part first, we get to use the final | |
684 | carry operation to move back from the temporary. */ | |
685 | if (!cbh) { | |
686 | tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); | |
687 | } else if (bh != 0 || ah == rl) { | |
688 | tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); | |
689 | } else { | |
690 | th = ah; | |
691 | } | |
692 | ||
693 | /* Note that tcg optimization should eliminate the bl == 0 case. */ | |
694 | if (is_sub) { | |
695 | if (cbl) { | |
696 | tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); | |
697 | tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); | |
698 | } else { | |
699 | tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); | |
700 | tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); | |
701 | } | |
702 | tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); | |
703 | } else { | |
704 | if (cbl) { | |
705 | tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); | |
706 | tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); | |
707 | } else if (rl == al && rl == bl) { | |
161dec9d | 708 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); |
d9f26847 AJ |
709 | tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); |
710 | } else { | |
711 | tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); | |
712 | tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); | |
713 | } | |
714 | tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); | |
715 | } | |
716 | } | |
717 | ||
fd1cf666 RH |
718 | /* Bit 0 set if inversion required; bit 1 set if swapping required. */ |
719 | #define MIPS_CMP_INV 1 | |
720 | #define MIPS_CMP_SWAP 2 | |
721 | ||
722 | static const uint8_t mips_cmp_map[16] = { | |
723 | [TCG_COND_LT] = 0, | |
724 | [TCG_COND_LTU] = 0, | |
725 | [TCG_COND_GE] = MIPS_CMP_INV, | |
726 | [TCG_COND_GEU] = MIPS_CMP_INV, | |
727 | [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, | |
728 | [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, | |
729 | [TCG_COND_GT] = MIPS_CMP_SWAP, | |
730 | [TCG_COND_GTU] = MIPS_CMP_SWAP, | |
731 | }; | |
732 | ||
733 | static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, | |
734 | TCGReg arg1, TCGReg arg2) | |
735 | { | |
736 | MIPSInsn s_opc = OPC_SLTU; | |
737 | int cmp_map; | |
738 | ||
739 | switch (cond) { | |
740 | case TCG_COND_EQ: | |
741 | if (arg2 != 0) { | |
742 | tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); | |
743 | arg1 = ret; | |
744 | } | |
745 | tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); | |
746 | break; | |
747 | ||
748 | case TCG_COND_NE: | |
749 | if (arg2 != 0) { | |
750 | tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); | |
751 | arg1 = ret; | |
752 | } | |
753 | tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); | |
754 | break; | |
755 | ||
756 | case TCG_COND_LT: | |
757 | case TCG_COND_GE: | |
758 | case TCG_COND_LE: | |
759 | case TCG_COND_GT: | |
760 | s_opc = OPC_SLT; | |
761 | /* FALLTHRU */ | |
762 | ||
763 | case TCG_COND_LTU: | |
764 | case TCG_COND_GEU: | |
765 | case TCG_COND_LEU: | |
766 | case TCG_COND_GTU: | |
767 | cmp_map = mips_cmp_map[cond]; | |
768 | if (cmp_map & MIPS_CMP_SWAP) { | |
769 | TCGReg t = arg1; | |
770 | arg1 = arg2; | |
771 | arg2 = t; | |
772 | } | |
773 | tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); | |
774 | if (cmp_map & MIPS_CMP_INV) { | |
775 | tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); | |
776 | } | |
777 | break; | |
778 | ||
779 | default: | |
780 | tcg_abort(); | |
781 | break; | |
782 | } | |
783 | } | |
784 | ||
c068896f | 785 | static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 786 | TCGReg arg2, TCGLabel *l) |
afa05235 | 787 | { |
c068896f RH |
788 | static const MIPSInsn b_zero[16] = { |
789 | [TCG_COND_LT] = OPC_BLTZ, | |
790 | [TCG_COND_GT] = OPC_BGTZ, | |
791 | [TCG_COND_LE] = OPC_BLEZ, | |
792 | [TCG_COND_GE] = OPC_BGEZ, | |
793 | }; | |
794 | ||
c068896f RH |
795 | MIPSInsn s_opc = OPC_SLTU; |
796 | MIPSInsn b_opc; | |
797 | int cmp_map; | |
afa05235 AJ |
798 | |
799 | switch (cond) { | |
800 | case TCG_COND_EQ: | |
c068896f | 801 | b_opc = OPC_BEQ; |
afa05235 AJ |
802 | break; |
803 | case TCG_COND_NE: | |
c068896f | 804 | b_opc = OPC_BNE; |
afa05235 | 805 | break; |
c068896f | 806 | |
afa05235 | 807 | case TCG_COND_LT: |
c068896f | 808 | case TCG_COND_GT: |
afa05235 | 809 | case TCG_COND_LE: |
c068896f | 810 | case TCG_COND_GE: |
0f46c064 | 811 | if (arg2 == 0) { |
c068896f RH |
812 | b_opc = b_zero[cond]; |
813 | arg2 = arg1; | |
814 | arg1 = 0; | |
815 | break; | |
0f46c064 | 816 | } |
c068896f RH |
817 | s_opc = OPC_SLT; |
818 | /* FALLTHRU */ | |
819 | ||
820 | case TCG_COND_LTU: | |
821 | case TCG_COND_GTU: | |
afa05235 | 822 | case TCG_COND_LEU: |
c068896f RH |
823 | case TCG_COND_GEU: |
824 | cmp_map = mips_cmp_map[cond]; | |
825 | if (cmp_map & MIPS_CMP_SWAP) { | |
826 | TCGReg t = arg1; | |
827 | arg1 = arg2; | |
828 | arg2 = t; | |
0f46c064 | 829 | } |
c068896f RH |
830 | tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); |
831 | b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); | |
832 | arg1 = TCG_TMP0; | |
833 | arg2 = TCG_REG_ZERO; | |
afa05235 | 834 | break; |
c068896f | 835 | |
afa05235 AJ |
836 | default: |
837 | tcg_abort(); | |
838 | break; | |
839 | } | |
c068896f RH |
840 | |
841 | tcg_out_opc_br(s, b_opc, arg1, arg2); | |
91a7fd1f | 842 | tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); |
afa05235 AJ |
843 | tcg_out_nop(s); |
844 | } | |
845 | ||
1db1c4d7 RH |
846 | static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, |
847 | TCGReg al, TCGReg ah, | |
848 | TCGReg bl, TCGReg bh) | |
849 | { | |
850 | /* Merge highpart comparison into AH. */ | |
851 | if (bh != 0) { | |
852 | if (ah != 0) { | |
853 | tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); | |
854 | ah = tmp0; | |
855 | } else { | |
856 | ah = bh; | |
857 | } | |
858 | } | |
859 | /* Merge lowpart comparison into AL. */ | |
860 | if (bl != 0) { | |
861 | if (al != 0) { | |
862 | tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); | |
863 | al = tmp1; | |
864 | } else { | |
865 | al = bl; | |
866 | } | |
867 | } | |
868 | /* Merge high and low part comparisons into AL. */ | |
869 | if (ah != 0) { | |
870 | if (al != 0) { | |
871 | tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); | |
872 | al = tmp0; | |
873 | } else { | |
874 | al = ah; | |
875 | } | |
876 | } | |
877 | return al; | |
878 | } | |
879 | ||
9a2f0bfe RH |
880 | static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, |
881 | TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) | |
882 | { | |
883 | TCGReg tmp0 = TCG_TMP0; | |
884 | TCGReg tmp1 = ret; | |
885 | ||
eabb7b91 | 886 | tcg_debug_assert(ret != TCG_TMP0); |
9a2f0bfe | 887 | if (ret == ah || ret == bh) { |
eabb7b91 | 888 | tcg_debug_assert(ret != TCG_TMP1); |
9a2f0bfe RH |
889 | tmp1 = TCG_TMP1; |
890 | } | |
891 | ||
892 | switch (cond) { | |
893 | case TCG_COND_EQ: | |
894 | case TCG_COND_NE: | |
1db1c4d7 RH |
895 | tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); |
896 | tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); | |
9a2f0bfe RH |
897 | break; |
898 | ||
899 | default: | |
900 | tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); | |
901 | tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); | |
902 | tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); | |
903 | tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); | |
904 | tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); | |
905 | break; | |
906 | } | |
907 | } | |
908 | ||
3401fd25 | 909 | static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, |
bec16311 | 910 | TCGReg bl, TCGReg bh, TCGLabel *l) |
3401fd25 RH |
911 | { |
912 | TCGCond b_cond = TCG_COND_NE; | |
913 | TCGReg tmp = TCG_TMP1; | |
914 | ||
915 | /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. | |
916 | With setcond, we emit between 3 and 10 insns and only 1 branch, | |
917 | which ought to get better branch prediction. */ | |
918 | switch (cond) { | |
919 | case TCG_COND_EQ: | |
920 | case TCG_COND_NE: | |
921 | b_cond = cond; | |
922 | tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); | |
afa05235 | 923 | break; |
afa05235 | 924 | |
afa05235 | 925 | default: |
5d831be2 | 926 | /* Minimize code size by preferring a compare not requiring INV. */ |
3401fd25 RH |
927 | if (mips_cmp_map[cond] & MIPS_CMP_INV) { |
928 | cond = tcg_invert_cond(cond); | |
929 | b_cond = TCG_COND_EQ; | |
930 | } | |
931 | tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); | |
932 | break; | |
afa05235 AJ |
933 | } |
934 | ||
bec16311 | 935 | tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); |
afa05235 AJ |
936 | } |
937 | ||
7d7c4930 | 938 | static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, |
137d6390 | 939 | TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) |
7d7c4930 | 940 | { |
137d6390 JH |
941 | bool eqz = false; |
942 | ||
943 | /* If one of the values is zero, put it last to match SEL*Z instructions */ | |
944 | if (use_mips32r6_instructions && v1 == 0) { | |
945 | v1 = v2; | |
946 | v2 = 0; | |
947 | cond = tcg_invert_cond(cond); | |
948 | } | |
33fac20b | 949 | |
7d7c4930 AJ |
950 | switch (cond) { |
951 | case TCG_COND_EQ: | |
137d6390 | 952 | eqz = true; |
33fac20b | 953 | /* FALLTHRU */ |
7d7c4930 | 954 | case TCG_COND_NE: |
33fac20b | 955 | if (c2 != 0) { |
6c530e32 | 956 | tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); |
33fac20b | 957 | c1 = TCG_TMP0; |
7d7c4930 AJ |
958 | } |
959 | break; | |
33fac20b | 960 | |
7d7c4930 | 961 | default: |
5d831be2 | 962 | /* Minimize code size by preferring a compare not requiring INV. */ |
33fac20b RH |
963 | if (mips_cmp_map[cond] & MIPS_CMP_INV) { |
964 | cond = tcg_invert_cond(cond); | |
137d6390 | 965 | eqz = true; |
33fac20b RH |
966 | } |
967 | tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); | |
968 | c1 = TCG_TMP0; | |
7d7c4930 AJ |
969 | break; |
970 | } | |
33fac20b | 971 | |
137d6390 JH |
972 | if (use_mips32r6_instructions) { |
973 | MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; | |
974 | MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; | |
975 | ||
976 | if (v2 != 0) { | |
977 | tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); | |
978 | } | |
979 | tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); | |
980 | if (v2 != 0) { | |
981 | tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); | |
982 | } | |
983 | } else { | |
984 | MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; | |
985 | ||
986 | tcg_out_opc_reg(s, m_opc, ret, v1, c1); | |
987 | ||
988 | /* This should be guaranteed via constraints */ | |
989 | tcg_debug_assert(v2 == ret); | |
990 | } | |
7d7c4930 AJ |
991 | } |
992 | ||
2be7d76b | 993 | static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) |
9d8bf2d1 RH |
994 | { |
995 | /* Note that the ABI requires the called function's address to be | |
996 | loaded into T9, even if a direct branch is in range. */ | |
997 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); | |
998 | ||
999 | /* But do try a direct branch, allowing the cpu better insn prefetch. */ | |
ce0236cf RH |
1000 | if (tail) { |
1001 | if (!tcg_out_opc_jmp(s, OPC_J, arg)) { | |
1002 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); | |
1003 | } | |
1004 | } else { | |
1005 | if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { | |
1006 | tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); | |
1007 | } | |
9d8bf2d1 | 1008 | } |
ce0236cf | 1009 | } |
9d8bf2d1 | 1010 | |
2be7d76b | 1011 | static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) |
ce0236cf RH |
1012 | { |
1013 | tcg_out_call_int(s, arg, false); | |
9d8bf2d1 RH |
1014 | tcg_out_nop(s); |
1015 | } | |
1016 | ||
afa05235 | 1017 | #if defined(CONFIG_SOFTMMU) |
139c1837 | 1018 | #include "../tcg-ldst.c.inc" |
659ef5cb | 1019 | |
ce0236cf RH |
1020 | static void * const qemu_ld_helpers[16] = { |
1021 | [MO_UB] = helper_ret_ldub_mmu, | |
1022 | [MO_SB] = helper_ret_ldsb_mmu, | |
1023 | [MO_LEUW] = helper_le_lduw_mmu, | |
1024 | [MO_LESW] = helper_le_ldsw_mmu, | |
1025 | [MO_LEUL] = helper_le_ldul_mmu, | |
1026 | [MO_LEQ] = helper_le_ldq_mmu, | |
1027 | [MO_BEUW] = helper_be_lduw_mmu, | |
1028 | [MO_BESW] = helper_be_ldsw_mmu, | |
1029 | [MO_BEUL] = helper_be_ldul_mmu, | |
1030 | [MO_BEQ] = helper_be_ldq_mmu, | |
f0d70331 JG |
1031 | #if TCG_TARGET_REG_BITS == 64 |
1032 | [MO_LESL] = helper_le_ldsl_mmu, | |
1033 | [MO_BESL] = helper_be_ldsl_mmu, | |
1034 | #endif | |
e141ab52 BS |
1035 | }; |
1036 | ||
ce0236cf RH |
1037 | static void * const qemu_st_helpers[16] = { |
1038 | [MO_UB] = helper_ret_stb_mmu, | |
1039 | [MO_LEUW] = helper_le_stw_mmu, | |
1040 | [MO_LEUL] = helper_le_stl_mmu, | |
1041 | [MO_LEQ] = helper_le_stq_mmu, | |
1042 | [MO_BEUW] = helper_be_stw_mmu, | |
1043 | [MO_BEUL] = helper_be_stl_mmu, | |
1044 | [MO_BEQ] = helper_be_stq_mmu, | |
e141ab52 | 1045 | }; |
afa05235 | 1046 | |
9d8bf2d1 RH |
1047 | /* Helper routines for marshalling helper function arguments into |
1048 | * the correct registers and stack. | |
1049 | * I is where we want to put this argument, and is updated and returned | |
1050 | * for the next call. ARG is the argument itself. | |
1051 | * | |
1052 | * We provide routines for arguments which are: immediate, 32 bit | |
1053 | * value in register, 16 and 8 bit values in register (which must be zero | |
1054 | * extended before use) and 64 bit value in a lo:hi register pair. | |
1055 | */ | |
1056 | ||
1057 | static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) | |
afa05235 | 1058 | { |
9d8bf2d1 RH |
1059 | if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { |
1060 | tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); | |
1061 | } else { | |
f0d70331 JG |
1062 | /* For N32 and N64, the initial offset is different. But there |
1063 | we also have 8 argument register so we don't run out here. */ | |
1064 | tcg_debug_assert(TCG_TARGET_REG_BITS == 32); | |
9d8bf2d1 RH |
1065 | tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); |
1066 | } | |
1067 | return i + 1; | |
1068 | } | |
afa05235 | 1069 | |
9d8bf2d1 RH |
1070 | static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) |
1071 | { | |
6c530e32 | 1072 | TCGReg tmp = TCG_TMP0; |
9d8bf2d1 RH |
1073 | if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { |
1074 | tmp = tcg_target_call_iarg_regs[i]; | |
1075 | } | |
1076 | tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); | |
1077 | return tcg_out_call_iarg_reg(s, i, tmp); | |
1078 | } | |
1079 | ||
1080 | static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) | |
1081 | { | |
6c530e32 | 1082 | TCGReg tmp = TCG_TMP0; |
9d8bf2d1 RH |
1083 | if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { |
1084 | tmp = tcg_target_call_iarg_regs[i]; | |
1085 | } | |
1086 | tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); | |
1087 | return tcg_out_call_iarg_reg(s, i, tmp); | |
1088 | } | |
1089 | ||
1090 | static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) | |
1091 | { | |
6c530e32 | 1092 | TCGReg tmp = TCG_TMP0; |
9d8bf2d1 RH |
1093 | if (arg == 0) { |
1094 | tmp = TCG_REG_ZERO; | |
afa05235 | 1095 | } else { |
9d8bf2d1 RH |
1096 | if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { |
1097 | tmp = tcg_target_call_iarg_regs[i]; | |
1098 | } | |
1099 | tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); | |
afa05235 | 1100 | } |
9d8bf2d1 RH |
1101 | return tcg_out_call_iarg_reg(s, i, tmp); |
1102 | } | |
1103 | ||
1104 | static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) | |
1105 | { | |
f0d70331 | 1106 | tcg_debug_assert(TCG_TARGET_REG_BITS == 32); |
9d8bf2d1 RH |
1107 | i = (i + 1) & ~1; |
1108 | i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); | |
1109 | i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); | |
1110 | return i; | |
1111 | } | |
1112 | ||
269bd5d8 RH |
1113 | /* We expect to use a 16-bit negative offset from ENV. */ |
1114 | QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); | |
1115 | QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); | |
1116 | ||
ac33373e RH |
1117 | /* |
1118 | * Perform the tlb comparison operation. | |
1119 | * The complete host address is placed in BASE. | |
1120 | * Clobbers TMP0, TMP1, TMP2, TMP3. | |
1121 | */ | |
9d8bf2d1 | 1122 | static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, |
81dfaf1a | 1123 | TCGReg addrh, TCGMemOpIdx oi, |
9d8bf2d1 RH |
1124 | tcg_insn_unit *label_ptr[2], bool is_load) |
1125 | { | |
14776ab5 | 1126 | MemOp opc = get_memop(oi); |
85aa8081 RH |
1127 | unsigned s_bits = opc & MO_SIZE; |
1128 | unsigned a_bits = get_alignment_bits(opc); | |
81dfaf1a | 1129 | int mem_index = get_mmuidx(oi); |
269bd5d8 RH |
1130 | int fast_off = TLB_MASK_TABLE_OFS(mem_index); |
1131 | int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); | |
1132 | int table_off = fast_off + offsetof(CPUTLBDescFast, table); | |
ac33373e RH |
1133 | int add_off = offsetof(CPUTLBEntry, addend); |
1134 | int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) | |
1135 | : offsetof(CPUTLBEntry, addr_write)); | |
ac33373e | 1136 | target_ulong mask; |
9d8bf2d1 | 1137 | |
ac33373e | 1138 | /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ |
269bd5d8 RH |
1139 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); |
1140 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); | |
ac33373e RH |
1141 | |
1142 | /* Extract the TLB index from the address into TMP3. */ | |
1143 | tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, | |
1144 | TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); | |
1145 | tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); | |
1146 | ||
1147 | /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ | |
1148 | tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
1149 | ||
85aa8081 RH |
1150 | /* We don't currently support unaligned accesses. |
1151 | We could do so with mips32r6. */ | |
1152 | if (a_bits < s_bits) { | |
1153 | a_bits = s_bits; | |
1154 | } | |
f0d70331 | 1155 | |
ac33373e | 1156 | /* Mask the page bits, keeping the alignment bits to compare against. */ |
f0d70331 JG |
1157 | mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); |
1158 | ||
ac33373e | 1159 | /* Load the (low-half) tlb comparator. */ |
f0d70331 | 1160 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
ac33373e | 1161 | tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); |
f0d70331 JG |
1162 | tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); |
1163 | } else { | |
ac33373e RH |
1164 | tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD |
1165 | : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), | |
1166 | TCG_TMP0, TCG_TMP3, cmp_off); | |
f0d70331 JG |
1167 | tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); |
1168 | /* No second compare is required here; | |
1169 | load the tlb addend for the fast path. */ | |
ac33373e | 1170 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); |
5eb4f645 | 1171 | } |
9d8bf2d1 | 1172 | |
f0d70331 JG |
1173 | /* Zero extend a 32-bit guest address for a 64-bit host. */ |
1174 | if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { | |
1175 | tcg_out_ext32u(s, base, addrl); | |
1176 | addrl = base; | |
1177 | } | |
4e655e3c | 1178 | tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); |
f0d70331 | 1179 | |
9d8bf2d1 | 1180 | label_ptr[0] = s->code_ptr; |
6c530e32 | 1181 | tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); |
afa05235 | 1182 | |
5eb4f645 | 1183 | /* Load and test the high half tlb comparator. */ |
f0d70331 | 1184 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 | 1185 | /* delay slot */ |
ac33373e | 1186 | tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); |
5eb4f645 | 1187 | |
f0d70331 | 1188 | /* Load the tlb addend for the fast path. */ |
ac33373e | 1189 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); |
afa05235 | 1190 | |
9d8bf2d1 | 1191 | label_ptr[1] = s->code_ptr; |
5eb4f645 | 1192 | tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); |
9d8bf2d1 | 1193 | } |
afa05235 | 1194 | |
9d8bf2d1 | 1195 | /* delay slot */ |
f0d70331 | 1196 | tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); |
9d8bf2d1 | 1197 | } |
afa05235 | 1198 | |
3972ef6f | 1199 | static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, |
f0d70331 | 1200 | TCGType ext, |
9d8bf2d1 RH |
1201 | TCGReg datalo, TCGReg datahi, |
1202 | TCGReg addrlo, TCGReg addrhi, | |
3972ef6f | 1203 | void *raddr, tcg_insn_unit *label_ptr[2]) |
9d8bf2d1 RH |
1204 | { |
1205 | TCGLabelQemuLdst *label = new_ldst_label(s); | |
1206 | ||
1207 | label->is_ld = is_ld; | |
3972ef6f | 1208 | label->oi = oi; |
f0d70331 | 1209 | label->type = ext; |
9d8bf2d1 RH |
1210 | label->datalo_reg = datalo; |
1211 | label->datahi_reg = datahi; | |
1212 | label->addrlo_reg = addrlo; | |
1213 | label->addrhi_reg = addrhi; | |
e5e2e4c7 | 1214 | label->raddr = tcg_splitwx_to_rx(raddr); |
9d8bf2d1 | 1215 | label->label_ptr[0] = label_ptr[0]; |
f0d70331 | 1216 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 RH |
1217 | label->label_ptr[1] = label_ptr[1]; |
1218 | } | |
1219 | } | |
1220 | ||
aeee05f5 | 1221 | static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) |
9d8bf2d1 | 1222 | { |
df5af130 | 1223 | const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); |
a8f13961 | 1224 | TCGMemOpIdx oi = l->oi; |
14776ab5 | 1225 | MemOp opc = get_memop(oi); |
ce0236cf | 1226 | TCGReg v0; |
9d8bf2d1 RH |
1227 | int i; |
1228 | ||
1229 | /* resolve label address */ | |
df5af130 | 1230 | if (!reloc_pc16(l->label_ptr[0], tgt_rx) |
91a7fd1f | 1231 | || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS |
df5af130 | 1232 | && !reloc_pc16(l->label_ptr[1], tgt_rx))) { |
91a7fd1f | 1233 | return false; |
9d8bf2d1 RH |
1234 | } |
1235 | ||
ce0236cf | 1236 | i = 1; |
f0d70331 | 1237 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 RH |
1238 | i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); |
1239 | } else { | |
1240 | i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); | |
1241 | } | |
3972ef6f | 1242 | i = tcg_out_call_iarg_imm(s, i, oi); |
ce0236cf | 1243 | i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); |
2b7ec66f | 1244 | tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); |
ce0236cf RH |
1245 | /* delay slot */ |
1246 | tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); | |
9d8bf2d1 | 1247 | |
ce0236cf | 1248 | v0 = l->datalo_reg; |
f0d70331 | 1249 | if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { |
9d8bf2d1 RH |
1250 | /* We eliminated V0 from the possible output registers, so it |
1251 | cannot be clobbered here. So we must move V1 first. */ | |
ce0236cf RH |
1252 | if (MIPS_BE) { |
1253 | tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); | |
1254 | v0 = l->datahi_reg; | |
1255 | } else { | |
1256 | tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); | |
1257 | } | |
afa05235 AJ |
1258 | } |
1259 | ||
6d8ff4d8 | 1260 | tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); |
91a7fd1f RH |
1261 | if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { |
1262 | return false; | |
1263 | } | |
a31aa4ce | 1264 | |
ce0236cf | 1265 | /* delay slot */ |
f0d70331 JG |
1266 | if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { |
1267 | /* we always sign-extend 32-bit loads */ | |
1268 | tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); | |
1269 | } else { | |
1270 | tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); | |
1271 | } | |
aeee05f5 | 1272 | return true; |
9d8bf2d1 | 1273 | } |
afa05235 | 1274 | |
aeee05f5 | 1275 | static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) |
9d8bf2d1 | 1276 | { |
df5af130 | 1277 | const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); |
a8f13961 | 1278 | TCGMemOpIdx oi = l->oi; |
14776ab5 TN |
1279 | MemOp opc = get_memop(oi); |
1280 | MemOp s_bits = opc & MO_SIZE; | |
9d8bf2d1 RH |
1281 | int i; |
1282 | ||
1283 | /* resolve label address */ | |
df5af130 | 1284 | if (!reloc_pc16(l->label_ptr[0], tgt_rx) |
91a7fd1f | 1285 | || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS |
df5af130 | 1286 | && !reloc_pc16(l->label_ptr[1], tgt_rx))) { |
91a7fd1f | 1287 | return false; |
9d8bf2d1 | 1288 | } |
afa05235 | 1289 | |
ce0236cf | 1290 | i = 1; |
f0d70331 | 1291 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 | 1292 | i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); |
cc01cc8e | 1293 | } else { |
9d8bf2d1 RH |
1294 | i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); |
1295 | } | |
1296 | switch (s_bits) { | |
1297 | case MO_8: | |
1298 | i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); | |
1299 | break; | |
1300 | case MO_16: | |
1301 | i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); | |
1302 | break; | |
1303 | case MO_32: | |
1304 | i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); | |
1305 | break; | |
1306 | case MO_64: | |
f0d70331 JG |
1307 | if (TCG_TARGET_REG_BITS == 32) { |
1308 | i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); | |
1309 | } else { | |
1310 | i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); | |
1311 | } | |
9d8bf2d1 RH |
1312 | break; |
1313 | default: | |
1314 | tcg_abort(); | |
cc01cc8e | 1315 | } |
3972ef6f | 1316 | i = tcg_out_call_iarg_imm(s, i, oi); |
9d8bf2d1 | 1317 | |
ce0236cf RH |
1318 | /* Tail call to the store helper. Thus force the return address |
1319 | computation to take place in the return address register. */ | |
1320 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); | |
1321 | i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); | |
2b7ec66f | 1322 | tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); |
ce0236cf RH |
1323 | /* delay slot */ |
1324 | tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); | |
aeee05f5 | 1325 | return true; |
9d8bf2d1 | 1326 | } |
afa05235 AJ |
1327 | #endif |
1328 | ||
bb08afe9 | 1329 | static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, |
14776ab5 | 1330 | TCGReg base, MemOp opc, bool is_64) |
9d8bf2d1 | 1331 | { |
4214a8cb | 1332 | switch (opc & (MO_SSIZE | MO_BSWAP)) { |
9d8bf2d1 | 1333 | case MO_UB: |
bb08afe9 | 1334 | tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); |
afa05235 | 1335 | break; |
9d8bf2d1 | 1336 | case MO_SB: |
bb08afe9 | 1337 | tcg_out_opc_imm(s, OPC_LB, lo, base, 0); |
afa05235 | 1338 | break; |
9d8bf2d1 | 1339 | case MO_UW | MO_BSWAP: |
6c530e32 | 1340 | tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); |
27362b7b | 1341 | tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ); |
afa05235 | 1342 | break; |
9d8bf2d1 | 1343 | case MO_UW: |
bb08afe9 | 1344 | tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); |
afa05235 | 1345 | break; |
9d8bf2d1 | 1346 | case MO_SW | MO_BSWAP: |
6c530e32 | 1347 | tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); |
27362b7b | 1348 | tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS); |
afa05235 | 1349 | break; |
9d8bf2d1 | 1350 | case MO_SW: |
bb08afe9 | 1351 | tcg_out_opc_imm(s, OPC_LH, lo, base, 0); |
9d8bf2d1 RH |
1352 | break; |
1353 | case MO_UL | MO_BSWAP: | |
f0d70331 JG |
1354 | if (TCG_TARGET_REG_BITS == 64 && is_64) { |
1355 | if (use_mips32r2_instructions) { | |
1356 | tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); | |
1fce6534 | 1357 | tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); |
f0d70331 JG |
1358 | } else { |
1359 | tcg_out_bswap_subr(s, bswap32u_addr); | |
1360 | /* delay slot */ | |
1361 | tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); | |
1362 | tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); | |
1363 | } | |
1364 | break; | |
1365 | } | |
1366 | /* FALLTHRU */ | |
1367 | case MO_SL | MO_BSWAP: | |
bb08afe9 JG |
1368 | if (use_mips32r2_instructions) { |
1369 | tcg_out_opc_imm(s, OPC_LW, lo, base, 0); | |
1fce6534 | 1370 | tcg_out_bswap32(s, lo, lo, 0); |
bb08afe9 JG |
1371 | } else { |
1372 | tcg_out_bswap_subr(s, bswap32_addr); | |
1373 | /* delay slot */ | |
1374 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); | |
1375 | tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); | |
1376 | } | |
9d8bf2d1 RH |
1377 | break; |
1378 | case MO_UL: | |
f0d70331 JG |
1379 | if (TCG_TARGET_REG_BITS == 64 && is_64) { |
1380 | tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); | |
1381 | break; | |
1382 | } | |
1383 | /* FALLTHRU */ | |
1384 | case MO_SL: | |
bb08afe9 | 1385 | tcg_out_opc_imm(s, OPC_LW, lo, base, 0); |
9d8bf2d1 RH |
1386 | break; |
1387 | case MO_Q | MO_BSWAP: | |
f0d70331 JG |
1388 | if (TCG_TARGET_REG_BITS == 64) { |
1389 | if (use_mips32r2_instructions) { | |
1390 | tcg_out_opc_imm(s, OPC_LD, lo, base, 0); | |
1391 | tcg_out_bswap64(s, lo, lo); | |
1392 | } else { | |
1393 | tcg_out_bswap_subr(s, bswap64_addr); | |
1394 | /* delay slot */ | |
1395 | tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); | |
1396 | tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); | |
1397 | } | |
1398 | } else if (use_mips32r2_instructions) { | |
bb08afe9 JG |
1399 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); |
1400 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); | |
1401 | tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); | |
1402 | tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); | |
1403 | tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); | |
1404 | tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); | |
1405 | } else { | |
1406 | tcg_out_bswap_subr(s, bswap32_addr); | |
1407 | /* delay slot */ | |
1408 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); | |
1409 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); | |
1410 | tcg_out_bswap_subr(s, bswap32_addr); | |
1411 | /* delay slot */ | |
1412 | tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); | |
1413 | tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); | |
1414 | } | |
9d8bf2d1 RH |
1415 | break; |
1416 | case MO_Q: | |
bb08afe9 | 1417 | /* Prefer to load from offset 0 first, but allow for overlap. */ |
f0d70331 JG |
1418 | if (TCG_TARGET_REG_BITS == 64) { |
1419 | tcg_out_opc_imm(s, OPC_LD, lo, base, 0); | |
1420 | } else if (MIPS_BE ? hi != base : lo == base) { | |
bb08afe9 JG |
1421 | tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); |
1422 | tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); | |
1423 | } else { | |
1424 | tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); | |
1425 | tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); | |
1426 | } | |
afa05235 AJ |
1427 | break; |
1428 | default: | |
1429 | tcg_abort(); | |
1430 | } | |
afa05235 AJ |
1431 | } |
1432 | ||
fbef2cc8 | 1433 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) |
afa05235 | 1434 | { |
9d8bf2d1 RH |
1435 | TCGReg addr_regl, addr_regh __attribute__((unused)); |
1436 | TCGReg data_regl, data_regh; | |
59227d5d | 1437 | TCGMemOpIdx oi; |
14776ab5 | 1438 | MemOp opc; |
afa05235 | 1439 | #if defined(CONFIG_SOFTMMU) |
9d8bf2d1 | 1440 | tcg_insn_unit *label_ptr[2]; |
afa05235 | 1441 | #endif |
bb08afe9 | 1442 | TCGReg base = TCG_REG_A0; |
9d8bf2d1 | 1443 | |
afa05235 | 1444 | data_regl = *args++; |
f0d70331 | 1445 | data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); |
afa05235 | 1446 | addr_regl = *args++; |
f0d70331 | 1447 | addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); |
59227d5d RH |
1448 | oi = *args++; |
1449 | opc = get_memop(oi); | |
9d8bf2d1 | 1450 | |
0834c9ea | 1451 | #if defined(CONFIG_SOFTMMU) |
81dfaf1a | 1452 | tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); |
f0d70331 JG |
1453 | tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); |
1454 | add_qemu_ldst_label(s, 1, oi, | |
1455 | (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), | |
1456 | data_regl, data_regh, addr_regl, addr_regh, | |
3972ef6f | 1457 | s->code_ptr, label_ptr); |
0834c9ea | 1458 | #else |
f0d70331 JG |
1459 | if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { |
1460 | tcg_out_ext32u(s, base, addr_regl); | |
1461 | addr_regl = base; | |
1462 | } | |
b76f21a7 | 1463 | if (guest_base == 0 && data_regl != addr_regl) { |
9d8bf2d1 | 1464 | base = addr_regl; |
b76f21a7 | 1465 | } else if (guest_base == (int16_t)guest_base) { |
f0d70331 | 1466 | tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); |
0834c9ea | 1467 | } else { |
4df9cac5 | 1468 | tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); |
0834c9ea | 1469 | } |
f0d70331 | 1470 | tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); |
9d8bf2d1 RH |
1471 | #endif |
1472 | } | |
afa05235 | 1473 | |
bb08afe9 | 1474 | static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, |
14776ab5 | 1475 | TCGReg base, MemOp opc) |
9d8bf2d1 | 1476 | { |
bb08afe9 JG |
1477 | /* Don't clutter the code below with checks to avoid bswapping ZERO. */ |
1478 | if ((lo | hi) == 0) { | |
1479 | opc &= ~MO_BSWAP; | |
1480 | } | |
1481 | ||
4214a8cb | 1482 | switch (opc & (MO_SIZE | MO_BSWAP)) { |
9d8bf2d1 | 1483 | case MO_8: |
bb08afe9 | 1484 | tcg_out_opc_imm(s, OPC_SB, lo, base, 0); |
9d8bf2d1 | 1485 | break; |
afa05235 | 1486 | |
9d8bf2d1 | 1487 | case MO_16 | MO_BSWAP: |
27362b7b | 1488 | tcg_out_bswap16(s, TCG_TMP1, lo, 0); |
bb08afe9 | 1489 | lo = TCG_TMP1; |
9d8bf2d1 RH |
1490 | /* FALLTHRU */ |
1491 | case MO_16: | |
bb08afe9 | 1492 | tcg_out_opc_imm(s, OPC_SH, lo, base, 0); |
afa05235 | 1493 | break; |
9d8bf2d1 RH |
1494 | |
1495 | case MO_32 | MO_BSWAP: | |
1fce6534 | 1496 | tcg_out_bswap32(s, TCG_TMP3, lo, 0); |
bb08afe9 | 1497 | lo = TCG_TMP3; |
9d8bf2d1 RH |
1498 | /* FALLTHRU */ |
1499 | case MO_32: | |
bb08afe9 | 1500 | tcg_out_opc_imm(s, OPC_SW, lo, base, 0); |
afa05235 | 1501 | break; |
9d8bf2d1 RH |
1502 | |
1503 | case MO_64 | MO_BSWAP: | |
f0d70331 JG |
1504 | if (TCG_TARGET_REG_BITS == 64) { |
1505 | tcg_out_bswap64(s, TCG_TMP3, lo); | |
1506 | tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); | |
1507 | } else if (use_mips32r2_instructions) { | |
bb08afe9 JG |
1508 | tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); |
1509 | tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); | |
1510 | tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); | |
1511 | tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); | |
1512 | tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); | |
1513 | tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); | |
1514 | } else { | |
1fce6534 | 1515 | tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); |
bb08afe9 | 1516 | tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); |
1fce6534 | 1517 | tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); |
bb08afe9 JG |
1518 | tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); |
1519 | } | |
afa05235 | 1520 | break; |
9d8bf2d1 | 1521 | case MO_64: |
f0d70331 JG |
1522 | if (TCG_TARGET_REG_BITS == 64) { |
1523 | tcg_out_opc_imm(s, OPC_SD, lo, base, 0); | |
1524 | } else { | |
1525 | tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); | |
1526 | tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); | |
1527 | } | |
afa05235 | 1528 | break; |
9d8bf2d1 | 1529 | |
afa05235 AJ |
1530 | default: |
1531 | tcg_abort(); | |
1532 | } | |
9d8bf2d1 | 1533 | } |
afa05235 | 1534 | |
fbef2cc8 | 1535 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) |
9d8bf2d1 RH |
1536 | { |
1537 | TCGReg addr_regl, addr_regh __attribute__((unused)); | |
bb08afe9 | 1538 | TCGReg data_regl, data_regh; |
59227d5d | 1539 | TCGMemOpIdx oi; |
14776ab5 | 1540 | MemOp opc; |
9d8bf2d1 RH |
1541 | #if defined(CONFIG_SOFTMMU) |
1542 | tcg_insn_unit *label_ptr[2]; | |
9d8bf2d1 | 1543 | #endif |
bb08afe9 | 1544 | TCGReg base = TCG_REG_A0; |
9d8bf2d1 RH |
1545 | |
1546 | data_regl = *args++; | |
f0d70331 | 1547 | data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); |
9d8bf2d1 | 1548 | addr_regl = *args++; |
f0d70331 | 1549 | addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); |
59227d5d RH |
1550 | oi = *args++; |
1551 | opc = get_memop(oi); | |
afa05235 | 1552 | |
9d8bf2d1 | 1553 | #if defined(CONFIG_SOFTMMU) |
81dfaf1a | 1554 | tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); |
9d8bf2d1 | 1555 | tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); |
f0d70331 JG |
1556 | add_qemu_ldst_label(s, 0, oi, |
1557 | (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), | |
1558 | data_regl, data_regh, addr_regl, addr_regh, | |
3972ef6f | 1559 | s->code_ptr, label_ptr); |
cc01cc8e | 1560 | #else |
f0d70331 JG |
1561 | base = TCG_REG_A0; |
1562 | if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { | |
1563 | tcg_out_ext32u(s, base, addr_regl); | |
1564 | addr_regl = base; | |
1565 | } | |
b76f21a7 | 1566 | if (guest_base == 0) { |
9d8bf2d1 | 1567 | base = addr_regl; |
f0d70331 JG |
1568 | } else if (guest_base == (int16_t)guest_base) { |
1569 | tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); | |
cc01cc8e | 1570 | } else { |
4df9cac5 | 1571 | tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); |
afa05235 | 1572 | } |
9d8bf2d1 | 1573 | tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); |
afa05235 AJ |
1574 | #endif |
1575 | } | |
1576 | ||
6f0b9910 PK |
1577 | static void tcg_out_mb(TCGContext *s, TCGArg a0) |
1578 | { | |
1579 | static const MIPSInsn sync[] = { | |
1580 | /* Note that SYNC_MB is a slightly weaker than SYNC 0, | |
1581 | as the former is an ordering barrier and the latter | |
1582 | is a completion barrier. */ | |
1583 | [0 ... TCG_MO_ALL] = OPC_SYNC_MB, | |
1584 | [TCG_MO_LD_LD] = OPC_SYNC_RMB, | |
1585 | [TCG_MO_ST_ST] = OPC_SYNC_WMB, | |
1586 | [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, | |
1587 | [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, | |
1588 | [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, | |
1589 | }; | |
1590 | tcg_out32(s, sync[a0 & TCG_MO_ALL]); | |
1591 | } | |
1592 | ||
2a1d9d41 RH |
1593 | static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, |
1594 | int width, TCGReg a0, TCGReg a1, TCGArg a2) | |
1595 | { | |
1596 | if (use_mips32r6_instructions) { | |
1597 | if (a2 == width) { | |
1598 | tcg_out_opc_reg(s, opcv6, a0, a1, 0); | |
1599 | } else { | |
1600 | tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); | |
1601 | tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); | |
1602 | } | |
1603 | } else { | |
1604 | if (a2 == width) { | |
1605 | tcg_out_opc_reg(s, opcv2, a0, a1, a1); | |
1606 | } else if (a0 == a2) { | |
1607 | tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); | |
1608 | tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); | |
1609 | } else if (a0 != a1) { | |
1610 | tcg_out_opc_reg(s, opcv2, a0, a1, a1); | |
1611 | tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); | |
1612 | } else { | |
1613 | tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); | |
1614 | tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); | |
1615 | tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); | |
1616 | } | |
1617 | } | |
1618 | } | |
1619 | ||
10d4af58 RH |
1620 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, |
1621 | const TCGArg args[TCG_MAX_OP_ARGS], | |
1622 | const int const_args[TCG_MAX_OP_ARGS]) | |
afa05235 | 1623 | { |
4f048535 | 1624 | MIPSInsn i1, i2; |
22ee3a98 RH |
1625 | TCGArg a0, a1, a2; |
1626 | int c2; | |
1627 | ||
51800e43 RH |
1628 | /* |
1629 | * Note that many operands use the constraint set "rZ". | |
1630 | * We make use of the fact that 0 is the ZERO register, | |
1631 | * and hence such cases need not check for const_args. | |
1632 | */ | |
22ee3a98 RH |
1633 | a0 = args[0]; |
1634 | a1 = args[1]; | |
1635 | a2 = args[2]; | |
1636 | c2 = const_args[2]; | |
1637 | ||
1638 | switch (opc) { | |
afa05235 | 1639 | case INDEX_op_exit_tb: |
7dae901d | 1640 | { |
7dae901d RH |
1641 | TCGReg b0 = TCG_REG_ZERO; |
1642 | ||
0119b192 | 1643 | a0 = (intptr_t)a0; |
7dae901d RH |
1644 | if (a0 & ~0xffff) { |
1645 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); | |
1646 | b0 = TCG_REG_V0; | |
1647 | } | |
1648 | if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { | |
6c530e32 | 1649 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, |
7dae901d | 1650 | (uintptr_t)tb_ret_addr); |
6c530e32 | 1651 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); |
7dae901d RH |
1652 | } |
1653 | tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); | |
f8c9eddb | 1654 | } |
afa05235 AJ |
1655 | break; |
1656 | case INDEX_op_goto_tb: | |
f309101c | 1657 | if (s->tb_jmp_insn_offset) { |
afa05235 | 1658 | /* direct jump method */ |
f309101c | 1659 | s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); |
b6bfeea9 RH |
1660 | /* Avoid clobbering the address during retranslation. */ |
1661 | tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); | |
afa05235 AJ |
1662 | } else { |
1663 | /* indirect jump method */ | |
6c530e32 | 1664 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, |
f309101c | 1665 | (uintptr_t)(s->tb_jmp_target_addr + a0)); |
6c530e32 | 1666 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); |
afa05235 AJ |
1667 | } |
1668 | tcg_out_nop(s); | |
9f754620 | 1669 | set_jmp_reset_offset(s, a0); |
afa05235 | 1670 | break; |
5786e068 AJ |
1671 | case INDEX_op_goto_ptr: |
1672 | /* jmp to the given host address (could be epilogue) */ | |
1673 | tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); | |
1674 | tcg_out_nop(s); | |
1675 | break; | |
afa05235 | 1676 | case INDEX_op_br: |
bec16311 RH |
1677 | tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, |
1678 | arg_label(a0)); | |
afa05235 AJ |
1679 | break; |
1680 | ||
afa05235 | 1681 | case INDEX_op_ld8u_i32: |
0119b192 | 1682 | case INDEX_op_ld8u_i64: |
4f048535 RH |
1683 | i1 = OPC_LBU; |
1684 | goto do_ldst; | |
afa05235 | 1685 | case INDEX_op_ld8s_i32: |
0119b192 | 1686 | case INDEX_op_ld8s_i64: |
4f048535 RH |
1687 | i1 = OPC_LB; |
1688 | goto do_ldst; | |
afa05235 | 1689 | case INDEX_op_ld16u_i32: |
0119b192 | 1690 | case INDEX_op_ld16u_i64: |
4f048535 RH |
1691 | i1 = OPC_LHU; |
1692 | goto do_ldst; | |
afa05235 | 1693 | case INDEX_op_ld16s_i32: |
0119b192 | 1694 | case INDEX_op_ld16s_i64: |
4f048535 RH |
1695 | i1 = OPC_LH; |
1696 | goto do_ldst; | |
afa05235 | 1697 | case INDEX_op_ld_i32: |
0119b192 | 1698 | case INDEX_op_ld32s_i64: |
4f048535 RH |
1699 | i1 = OPC_LW; |
1700 | goto do_ldst; | |
0119b192 JG |
1701 | case INDEX_op_ld32u_i64: |
1702 | i1 = OPC_LWU; | |
1703 | goto do_ldst; | |
1704 | case INDEX_op_ld_i64: | |
1705 | i1 = OPC_LD; | |
1706 | goto do_ldst; | |
afa05235 | 1707 | case INDEX_op_st8_i32: |
0119b192 | 1708 | case INDEX_op_st8_i64: |
4f048535 RH |
1709 | i1 = OPC_SB; |
1710 | goto do_ldst; | |
afa05235 | 1711 | case INDEX_op_st16_i32: |
0119b192 | 1712 | case INDEX_op_st16_i64: |
4f048535 RH |
1713 | i1 = OPC_SH; |
1714 | goto do_ldst; | |
afa05235 | 1715 | case INDEX_op_st_i32: |
0119b192 | 1716 | case INDEX_op_st32_i64: |
4f048535 | 1717 | i1 = OPC_SW; |
0119b192 JG |
1718 | goto do_ldst; |
1719 | case INDEX_op_st_i64: | |
1720 | i1 = OPC_SD; | |
4f048535 RH |
1721 | do_ldst: |
1722 | tcg_out_ldst(s, i1, a0, a1, a2); | |
afa05235 AJ |
1723 | break; |
1724 | ||
1725 | case INDEX_op_add_i32: | |
4f048535 RH |
1726 | i1 = OPC_ADDU, i2 = OPC_ADDIU; |
1727 | goto do_binary; | |
0119b192 JG |
1728 | case INDEX_op_add_i64: |
1729 | i1 = OPC_DADDU, i2 = OPC_DADDIU; | |
1730 | goto do_binary; | |
4f048535 | 1731 | case INDEX_op_or_i32: |
0119b192 | 1732 | case INDEX_op_or_i64: |
4f048535 RH |
1733 | i1 = OPC_OR, i2 = OPC_ORI; |
1734 | goto do_binary; | |
1735 | case INDEX_op_xor_i32: | |
0119b192 | 1736 | case INDEX_op_xor_i64: |
4f048535 RH |
1737 | i1 = OPC_XOR, i2 = OPC_XORI; |
1738 | do_binary: | |
22ee3a98 | 1739 | if (c2) { |
4f048535 RH |
1740 | tcg_out_opc_imm(s, i2, a0, a1, a2); |
1741 | break; | |
afa05235 | 1742 | } |
4f048535 RH |
1743 | do_binaryv: |
1744 | tcg_out_opc_reg(s, i1, a0, a1, a2); | |
afa05235 | 1745 | break; |
4f048535 | 1746 | |
afa05235 | 1747 | case INDEX_op_sub_i32: |
0119b192 JG |
1748 | i1 = OPC_SUBU, i2 = OPC_ADDIU; |
1749 | goto do_subtract; | |
1750 | case INDEX_op_sub_i64: | |
1751 | i1 = OPC_DSUBU, i2 = OPC_DADDIU; | |
1752 | do_subtract: | |
22ee3a98 | 1753 | if (c2) { |
0119b192 | 1754 | tcg_out_opc_imm(s, i2, a0, a1, -a2); |
4f048535 | 1755 | break; |
afa05235 | 1756 | } |
0119b192 | 1757 | goto do_binaryv; |
4f048535 RH |
1758 | case INDEX_op_and_i32: |
1759 | if (c2 && a2 != (uint16_t)a2) { | |
1760 | int msb = ctz32(~a2) - 1; | |
eabb7b91 AJ |
1761 | tcg_debug_assert(use_mips32r2_instructions); |
1762 | tcg_debug_assert(is_p2m1(a2)); | |
4f048535 RH |
1763 | tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); |
1764 | break; | |
1765 | } | |
1766 | i1 = OPC_AND, i2 = OPC_ANDI; | |
1767 | goto do_binary; | |
0119b192 JG |
1768 | case INDEX_op_and_i64: |
1769 | if (c2 && a2 != (uint16_t)a2) { | |
1770 | int msb = ctz64(~a2) - 1; | |
1771 | tcg_debug_assert(use_mips32r2_instructions); | |
1772 | tcg_debug_assert(is_p2m1(a2)); | |
1773 | tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); | |
1774 | break; | |
1775 | } | |
1776 | i1 = OPC_AND, i2 = OPC_ANDI; | |
1777 | goto do_binary; | |
4f048535 | 1778 | case INDEX_op_nor_i32: |
0119b192 | 1779 | case INDEX_op_nor_i64: |
4f048535 RH |
1780 | i1 = OPC_NOR; |
1781 | goto do_binaryv; | |
1782 | ||
afa05235 | 1783 | case INDEX_op_mul_i32: |
988902fc | 1784 | if (use_mips32_instructions) { |
22ee3a98 | 1785 | tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); |
4f048535 | 1786 | break; |
988902fc | 1787 | } |
4f048535 RH |
1788 | i1 = OPC_MULT, i2 = OPC_MFLO; |
1789 | goto do_hilo1; | |
3c9a8f17 | 1790 | case INDEX_op_mulsh_i32: |
bc6d0c22 JH |
1791 | if (use_mips32r6_instructions) { |
1792 | tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); | |
1793 | break; | |
1794 | } | |
4f048535 RH |
1795 | i1 = OPC_MULT, i2 = OPC_MFHI; |
1796 | goto do_hilo1; | |
3c9a8f17 | 1797 | case INDEX_op_muluh_i32: |
bc6d0c22 JH |
1798 | if (use_mips32r6_instructions) { |
1799 | tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); | |
1800 | break; | |
1801 | } | |
4f048535 RH |
1802 | i1 = OPC_MULTU, i2 = OPC_MFHI; |
1803 | goto do_hilo1; | |
afa05235 | 1804 | case INDEX_op_div_i32: |
bc6d0c22 JH |
1805 | if (use_mips32r6_instructions) { |
1806 | tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); | |
1807 | break; | |
1808 | } | |
4f048535 RH |
1809 | i1 = OPC_DIV, i2 = OPC_MFLO; |
1810 | goto do_hilo1; | |
afa05235 | 1811 | case INDEX_op_divu_i32: |
bc6d0c22 JH |
1812 | if (use_mips32r6_instructions) { |
1813 | tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); | |
1814 | break; | |
1815 | } | |
4f048535 RH |
1816 | i1 = OPC_DIVU, i2 = OPC_MFLO; |
1817 | goto do_hilo1; | |
afa05235 | 1818 | case INDEX_op_rem_i32: |
bc6d0c22 JH |
1819 | if (use_mips32r6_instructions) { |
1820 | tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); | |
1821 | break; | |
1822 | } | |
4f048535 RH |
1823 | i1 = OPC_DIV, i2 = OPC_MFHI; |
1824 | goto do_hilo1; | |
afa05235 | 1825 | case INDEX_op_remu_i32: |
bc6d0c22 JH |
1826 | if (use_mips32r6_instructions) { |
1827 | tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); | |
1828 | break; | |
1829 | } | |
4f048535 | 1830 | i1 = OPC_DIVU, i2 = OPC_MFHI; |
0119b192 JG |
1831 | goto do_hilo1; |
1832 | case INDEX_op_mul_i64: | |
1833 | if (use_mips32r6_instructions) { | |
1834 | tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); | |
1835 | break; | |
1836 | } | |
1837 | i1 = OPC_DMULT, i2 = OPC_MFLO; | |
1838 | goto do_hilo1; | |
1839 | case INDEX_op_mulsh_i64: | |
1840 | if (use_mips32r6_instructions) { | |
1841 | tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); | |
1842 | break; | |
1843 | } | |
1844 | i1 = OPC_DMULT, i2 = OPC_MFHI; | |
1845 | goto do_hilo1; | |
1846 | case INDEX_op_muluh_i64: | |
1847 | if (use_mips32r6_instructions) { | |
1848 | tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); | |
1849 | break; | |
1850 | } | |
1851 | i1 = OPC_DMULTU, i2 = OPC_MFHI; | |
1852 | goto do_hilo1; | |
1853 | case INDEX_op_div_i64: | |
1854 | if (use_mips32r6_instructions) { | |
1855 | tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); | |
1856 | break; | |
1857 | } | |
1858 | i1 = OPC_DDIV, i2 = OPC_MFLO; | |
1859 | goto do_hilo1; | |
1860 | case INDEX_op_divu_i64: | |
1861 | if (use_mips32r6_instructions) { | |
1862 | tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); | |
1863 | break; | |
1864 | } | |
1865 | i1 = OPC_DDIVU, i2 = OPC_MFLO; | |
1866 | goto do_hilo1; | |
1867 | case INDEX_op_rem_i64: | |
1868 | if (use_mips32r6_instructions) { | |
1869 | tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); | |
1870 | break; | |
1871 | } | |
1872 | i1 = OPC_DDIV, i2 = OPC_MFHI; | |
1873 | goto do_hilo1; | |
1874 | case INDEX_op_remu_i64: | |
1875 | if (use_mips32r6_instructions) { | |
1876 | tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); | |
1877 | break; | |
1878 | } | |
1879 | i1 = OPC_DDIVU, i2 = OPC_MFHI; | |
4f048535 RH |
1880 | do_hilo1: |
1881 | tcg_out_opc_reg(s, i1, 0, a1, a2); | |
1882 | tcg_out_opc_reg(s, i2, a0, 0, 0); | |
afa05235 AJ |
1883 | break; |
1884 | ||
4f048535 RH |
1885 | case INDEX_op_muls2_i32: |
1886 | i1 = OPC_MULT; | |
1887 | goto do_hilo2; | |
1888 | case INDEX_op_mulu2_i32: | |
1889 | i1 = OPC_MULTU; | |
0119b192 JG |
1890 | goto do_hilo2; |
1891 | case INDEX_op_muls2_i64: | |
1892 | i1 = OPC_DMULT; | |
1893 | goto do_hilo2; | |
1894 | case INDEX_op_mulu2_i64: | |
1895 | i1 = OPC_DMULTU; | |
4f048535 RH |
1896 | do_hilo2: |
1897 | tcg_out_opc_reg(s, i1, 0, a2, args[3]); | |
1898 | tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); | |
1899 | tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); | |
2b79487a | 1900 | break; |
4f048535 | 1901 | |
afa05235 | 1902 | case INDEX_op_not_i32: |
0119b192 | 1903 | case INDEX_op_not_i64: |
4f048535 RH |
1904 | i1 = OPC_NOR; |
1905 | goto do_unary; | |
4f048535 | 1906 | case INDEX_op_ext8s_i32: |
0119b192 | 1907 | case INDEX_op_ext8s_i64: |
4f048535 RH |
1908 | i1 = OPC_SEB; |
1909 | goto do_unary; | |
1910 | case INDEX_op_ext16s_i32: | |
0119b192 | 1911 | case INDEX_op_ext16s_i64: |
4f048535 RH |
1912 | i1 = OPC_SEH; |
1913 | do_unary: | |
1914 | tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); | |
afa05235 AJ |
1915 | break; |
1916 | ||
27362b7b RH |
1917 | case INDEX_op_bswap16_i32: |
1918 | case INDEX_op_bswap16_i64: | |
1919 | tcg_out_bswap16(s, a0, a1, a2); | |
1920 | break; | |
0119b192 | 1921 | case INDEX_op_bswap32_i32: |
1fce6534 | 1922 | tcg_out_bswap32(s, a0, a1, 0); |
0119b192 JG |
1923 | break; |
1924 | case INDEX_op_bswap32_i64: | |
1fce6534 | 1925 | tcg_out_bswap32(s, a0, a1, a2); |
0119b192 JG |
1926 | break; |
1927 | case INDEX_op_bswap64_i64: | |
1928 | tcg_out_bswap64(s, a0, a1); | |
1929 | break; | |
1930 | case INDEX_op_extrh_i64_i32: | |
1931 | tcg_out_dsra(s, a0, a1, 32); | |
1932 | break; | |
1933 | case INDEX_op_ext32s_i64: | |
1934 | case INDEX_op_ext_i32_i64: | |
1935 | case INDEX_op_extrl_i64_i32: | |
1936 | tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); | |
1937 | break; | |
1938 | case INDEX_op_ext32u_i64: | |
1939 | case INDEX_op_extu_i32_i64: | |
1940 | tcg_out_ext32u(s, a0, a1); | |
1941 | break; | |
1942 | ||
afa05235 | 1943 | case INDEX_op_sar_i32: |
4f048535 RH |
1944 | i1 = OPC_SRAV, i2 = OPC_SRA; |
1945 | goto do_shift; | |
afa05235 | 1946 | case INDEX_op_shl_i32: |
4f048535 RH |
1947 | i1 = OPC_SLLV, i2 = OPC_SLL; |
1948 | goto do_shift; | |
afa05235 | 1949 | case INDEX_op_shr_i32: |
4f048535 RH |
1950 | i1 = OPC_SRLV, i2 = OPC_SRL; |
1951 | goto do_shift; | |
1952 | case INDEX_op_rotr_i32: | |
1953 | i1 = OPC_ROTRV, i2 = OPC_ROTR; | |
1954 | do_shift: | |
22ee3a98 | 1955 | if (c2) { |
4f048535 | 1956 | tcg_out_opc_sa(s, i2, a0, a1, a2); |
0119b192 | 1957 | break; |
afa05235 | 1958 | } |
0119b192 JG |
1959 | do_shiftv: |
1960 | tcg_out_opc_reg(s, i1, a0, a2, a1); | |
afa05235 | 1961 | break; |
9a152519 | 1962 | case INDEX_op_rotl_i32: |
22ee3a98 RH |
1963 | if (c2) { |
1964 | tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); | |
9a152519 | 1965 | } else { |
22ee3a98 RH |
1966 | tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); |
1967 | tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); | |
9a152519 AJ |
1968 | } |
1969 | break; | |
0119b192 JG |
1970 | case INDEX_op_sar_i64: |
1971 | if (c2) { | |
1972 | tcg_out_dsra(s, a0, a1, a2); | |
1973 | break; | |
1974 | } | |
1975 | i1 = OPC_DSRAV; | |
1976 | goto do_shiftv; | |
1977 | case INDEX_op_shl_i64: | |
1978 | if (c2) { | |
1979 | tcg_out_dsll(s, a0, a1, a2); | |
1980 | break; | |
1981 | } | |
1982 | i1 = OPC_DSLLV; | |
1983 | goto do_shiftv; | |
1984 | case INDEX_op_shr_i64: | |
1985 | if (c2) { | |
1986 | tcg_out_dsrl(s, a0, a1, a2); | |
1987 | break; | |
1988 | } | |
1989 | i1 = OPC_DSRLV; | |
1990 | goto do_shiftv; | |
1991 | case INDEX_op_rotr_i64: | |
1992 | if (c2) { | |
1993 | tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); | |
1994 | break; | |
1995 | } | |
1996 | i1 = OPC_DROTRV; | |
1997 | goto do_shiftv; | |
1998 | case INDEX_op_rotl_i64: | |
1999 | if (c2) { | |
2000 | tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); | |
2001 | } else { | |
2002 | tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); | |
2003 | tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); | |
2004 | } | |
c1cf85c9 AJ |
2005 | break; |
2006 | ||
2a1d9d41 RH |
2007 | case INDEX_op_clz_i32: |
2008 | tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); | |
2009 | break; | |
2010 | case INDEX_op_clz_i64: | |
2011 | tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); | |
2012 | break; | |
2013 | ||
04f71aa3 | 2014 | case INDEX_op_deposit_i32: |
22ee3a98 | 2015 | tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); |
04f71aa3 | 2016 | break; |
0119b192 JG |
2017 | case INDEX_op_deposit_i64: |
2018 | tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, | |
2019 | args[3] + args[4] - 1, args[3]); | |
2020 | break; | |
befbb3ce | 2021 | case INDEX_op_extract_i32: |
2f5a5f57 | 2022 | tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); |
befbb3ce RH |
2023 | break; |
2024 | case INDEX_op_extract_i64: | |
2025 | tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, | |
2f5a5f57 | 2026 | args[3] - 1, a2); |
befbb3ce | 2027 | break; |
04f71aa3 | 2028 | |
afa05235 | 2029 | case INDEX_op_brcond_i32: |
0119b192 | 2030 | case INDEX_op_brcond_i64: |
bec16311 | 2031 | tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); |
afa05235 AJ |
2032 | break; |
2033 | case INDEX_op_brcond2_i32: | |
bec16311 | 2034 | tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); |
afa05235 AJ |
2035 | break; |
2036 | ||
7d7c4930 | 2037 | case INDEX_op_movcond_i32: |
0119b192 | 2038 | case INDEX_op_movcond_i64: |
137d6390 | 2039 | tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); |
7d7c4930 AJ |
2040 | break; |
2041 | ||
4cb26382 | 2042 | case INDEX_op_setcond_i32: |
0119b192 | 2043 | case INDEX_op_setcond_i64: |
22ee3a98 | 2044 | tcg_out_setcond(s, args[3], a0, a1, a2); |
4cb26382 | 2045 | break; |
434254aa | 2046 | case INDEX_op_setcond2_i32: |
22ee3a98 | 2047 | tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); |
434254aa | 2048 | break; |
4cb26382 | 2049 | |
fbef2cc8 RH |
2050 | case INDEX_op_qemu_ld_i32: |
2051 | tcg_out_qemu_ld(s, args, false); | |
afa05235 | 2052 | break; |
fbef2cc8 RH |
2053 | case INDEX_op_qemu_ld_i64: |
2054 | tcg_out_qemu_ld(s, args, true); | |
afa05235 | 2055 | break; |
fbef2cc8 RH |
2056 | case INDEX_op_qemu_st_i32: |
2057 | tcg_out_qemu_st(s, args, false); | |
afa05235 | 2058 | break; |
fbef2cc8 RH |
2059 | case INDEX_op_qemu_st_i64: |
2060 | tcg_out_qemu_st(s, args, true); | |
afa05235 AJ |
2061 | break; |
2062 | ||
741f117d RH |
2063 | case INDEX_op_add2_i32: |
2064 | tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], | |
2065 | const_args[4], const_args[5], false); | |
2066 | break; | |
2067 | case INDEX_op_sub2_i32: | |
2068 | tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], | |
2069 | const_args[4], const_args[5], true); | |
2070 | break; | |
2071 | ||
6f0b9910 PK |
2072 | case INDEX_op_mb: |
2073 | tcg_out_mb(s, a0); | |
2074 | break; | |
96d0ee7f | 2075 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ |
0119b192 | 2076 | case INDEX_op_mov_i64: |
96d0ee7f | 2077 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ |
afa05235 AJ |
2078 | default: |
2079 | tcg_abort(); | |
2080 | } | |
2081 | } | |
2082 | ||
0263330b | 2083 | static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) |
89b2e37e | 2084 | { |
89b2e37e RH |
2085 | switch (op) { |
2086 | case INDEX_op_goto_ptr: | |
0263330b | 2087 | return C_O0_I1(r); |
afa05235 | 2088 | |
89b2e37e RH |
2089 | case INDEX_op_ld8u_i32: |
2090 | case INDEX_op_ld8s_i32: | |
2091 | case INDEX_op_ld16u_i32: | |
2092 | case INDEX_op_ld16s_i32: | |
2093 | case INDEX_op_ld_i32: | |
2094 | case INDEX_op_not_i32: | |
2095 | case INDEX_op_bswap16_i32: | |
2096 | case INDEX_op_bswap32_i32: | |
2097 | case INDEX_op_ext8s_i32: | |
2098 | case INDEX_op_ext16s_i32: | |
2099 | case INDEX_op_extract_i32: | |
2100 | case INDEX_op_ld8u_i64: | |
2101 | case INDEX_op_ld8s_i64: | |
2102 | case INDEX_op_ld16u_i64: | |
2103 | case INDEX_op_ld16s_i64: | |
2104 | case INDEX_op_ld32s_i64: | |
2105 | case INDEX_op_ld32u_i64: | |
2106 | case INDEX_op_ld_i64: | |
2107 | case INDEX_op_not_i64: | |
2108 | case INDEX_op_bswap16_i64: | |
2109 | case INDEX_op_bswap32_i64: | |
2110 | case INDEX_op_bswap64_i64: | |
2111 | case INDEX_op_ext8s_i64: | |
2112 | case INDEX_op_ext16s_i64: | |
2113 | case INDEX_op_ext32s_i64: | |
2114 | case INDEX_op_ext32u_i64: | |
2115 | case INDEX_op_ext_i32_i64: | |
2116 | case INDEX_op_extu_i32_i64: | |
2117 | case INDEX_op_extrl_i64_i32: | |
2118 | case INDEX_op_extrh_i64_i32: | |
2119 | case INDEX_op_extract_i64: | |
0263330b | 2120 | return C_O1_I1(r, r); |
afa05235 | 2121 | |
89b2e37e RH |
2122 | case INDEX_op_st8_i32: |
2123 | case INDEX_op_st16_i32: | |
2124 | case INDEX_op_st_i32: | |
2125 | case INDEX_op_st8_i64: | |
2126 | case INDEX_op_st16_i64: | |
2127 | case INDEX_op_st32_i64: | |
2128 | case INDEX_op_st_i64: | |
0263330b | 2129 | return C_O0_I2(rZ, r); |
6f0b9910 | 2130 | |
89b2e37e RH |
2131 | case INDEX_op_add_i32: |
2132 | case INDEX_op_add_i64: | |
0263330b | 2133 | return C_O1_I2(r, r, rJ); |
89b2e37e RH |
2134 | case INDEX_op_sub_i32: |
2135 | case INDEX_op_sub_i64: | |
0263330b | 2136 | return C_O1_I2(r, rZ, rN); |
89b2e37e RH |
2137 | case INDEX_op_mul_i32: |
2138 | case INDEX_op_mulsh_i32: | |
2139 | case INDEX_op_muluh_i32: | |
2140 | case INDEX_op_div_i32: | |
2141 | case INDEX_op_divu_i32: | |
2142 | case INDEX_op_rem_i32: | |
2143 | case INDEX_op_remu_i32: | |
2144 | case INDEX_op_nor_i32: | |
2145 | case INDEX_op_setcond_i32: | |
2146 | case INDEX_op_mul_i64: | |
2147 | case INDEX_op_mulsh_i64: | |
2148 | case INDEX_op_muluh_i64: | |
2149 | case INDEX_op_div_i64: | |
2150 | case INDEX_op_divu_i64: | |
2151 | case INDEX_op_rem_i64: | |
2152 | case INDEX_op_remu_i64: | |
2153 | case INDEX_op_nor_i64: | |
2154 | case INDEX_op_setcond_i64: | |
0263330b | 2155 | return C_O1_I2(r, rZ, rZ); |
89b2e37e RH |
2156 | case INDEX_op_muls2_i32: |
2157 | case INDEX_op_mulu2_i32: | |
2158 | case INDEX_op_muls2_i64: | |
2159 | case INDEX_op_mulu2_i64: | |
0263330b | 2160 | return C_O2_I2(r, r, r, r); |
89b2e37e RH |
2161 | case INDEX_op_and_i32: |
2162 | case INDEX_op_and_i64: | |
0263330b | 2163 | return C_O1_I2(r, r, rIK); |
89b2e37e RH |
2164 | case INDEX_op_or_i32: |
2165 | case INDEX_op_xor_i32: | |
2166 | case INDEX_op_or_i64: | |
2167 | case INDEX_op_xor_i64: | |
0263330b | 2168 | return C_O1_I2(r, r, rI); |
89b2e37e RH |
2169 | case INDEX_op_shl_i32: |
2170 | case INDEX_op_shr_i32: | |
2171 | case INDEX_op_sar_i32: | |
2172 | case INDEX_op_rotr_i32: | |
2173 | case INDEX_op_rotl_i32: | |
2174 | case INDEX_op_shl_i64: | |
2175 | case INDEX_op_shr_i64: | |
2176 | case INDEX_op_sar_i64: | |
2177 | case INDEX_op_rotr_i64: | |
2178 | case INDEX_op_rotl_i64: | |
0263330b | 2179 | return C_O1_I2(r, r, ri); |
89b2e37e RH |
2180 | case INDEX_op_clz_i32: |
2181 | case INDEX_op_clz_i64: | |
0263330b | 2182 | return C_O1_I2(r, r, rWZ); |
afa05235 | 2183 | |
89b2e37e RH |
2184 | case INDEX_op_deposit_i32: |
2185 | case INDEX_op_deposit_i64: | |
0263330b | 2186 | return C_O1_I2(r, 0, rZ); |
89b2e37e RH |
2187 | case INDEX_op_brcond_i32: |
2188 | case INDEX_op_brcond_i64: | |
0263330b | 2189 | return C_O0_I2(rZ, rZ); |
89b2e37e RH |
2190 | case INDEX_op_movcond_i32: |
2191 | case INDEX_op_movcond_i64: | |
0263330b RH |
2192 | return (use_mips32r6_instructions |
2193 | ? C_O1_I4(r, rZ, rZ, rZ, rZ) | |
2194 | : C_O1_I4(r, rZ, rZ, rZ, 0)); | |
89b2e37e RH |
2195 | case INDEX_op_add2_i32: |
2196 | case INDEX_op_sub2_i32: | |
0263330b | 2197 | return C_O2_I4(r, r, rZ, rZ, rN, rN); |
89b2e37e | 2198 | case INDEX_op_setcond2_i32: |
0263330b | 2199 | return C_O1_I4(r, rZ, rZ, rZ, rZ); |
89b2e37e | 2200 | case INDEX_op_brcond2_i32: |
0263330b | 2201 | return C_O0_I4(rZ, rZ, rZ, rZ); |
89b2e37e RH |
2202 | |
2203 | case INDEX_op_qemu_ld_i32: | |
2204 | return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 | |
0263330b | 2205 | ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); |
89b2e37e RH |
2206 | case INDEX_op_qemu_st_i32: |
2207 | return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 | |
0263330b | 2208 | ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); |
89b2e37e | 2209 | case INDEX_op_qemu_ld_i64: |
0263330b RH |
2210 | return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) |
2211 | : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L) | |
2212 | : C_O2_I2(r, r, L, L)); | |
89b2e37e | 2213 | case INDEX_op_qemu_st_i64: |
0263330b RH |
2214 | return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S) |
2215 | : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S) | |
2216 | : C_O0_I4(SZ, SZ, S, S)); | |
89b2e37e RH |
2217 | |
2218 | default: | |
0263330b | 2219 | g_assert_not_reached(); |
f69d277e | 2220 | } |
f69d277e RH |
2221 | } |
2222 | ||
d453ec78 | 2223 | static const int tcg_target_callee_save_regs[] = { |
cea5f9a2 | 2224 | TCG_REG_S0, /* used for the global env (TCG_AREG0) */ |
afa05235 AJ |
2225 | TCG_REG_S1, |
2226 | TCG_REG_S2, | |
2227 | TCG_REG_S3, | |
2228 | TCG_REG_S4, | |
2229 | TCG_REG_S5, | |
2230 | TCG_REG_S6, | |
2231 | TCG_REG_S7, | |
41883904 | 2232 | TCG_REG_S8, |
afa05235 AJ |
2233 | TCG_REG_RA, /* should be last for ABI compliance */ |
2234 | }; | |
2235 | ||
988902fc AJ |
2236 | /* The Linux kernel doesn't provide any information about the available |
2237 | instruction set. Probe it using a signal handler. */ | |
2238 | ||
988902fc AJ |
2239 | |
2240 | #ifndef use_movnz_instructions | |
2241 | bool use_movnz_instructions = false; | |
2242 | #endif | |
2243 | ||
2244 | #ifndef use_mips32_instructions | |
2245 | bool use_mips32_instructions = false; | |
2246 | #endif | |
2247 | ||
2248 | #ifndef use_mips32r2_instructions | |
2249 | bool use_mips32r2_instructions = false; | |
2250 | #endif | |
2251 | ||
2252 | static volatile sig_atomic_t got_sigill; | |
2253 | ||
2254 | static void sigill_handler(int signo, siginfo_t *si, void *data) | |
2255 | { | |
2256 | /* Skip the faulty instruction */ | |
2257 | ucontext_t *uc = (ucontext_t *)data; | |
2258 | uc->uc_mcontext.pc += 4; | |
2259 | ||
2260 | got_sigill = 1; | |
2261 | } | |
2262 | ||
2263 | static void tcg_target_detect_isa(void) | |
2264 | { | |
2265 | struct sigaction sa_old, sa_new; | |
2266 | ||
2267 | memset(&sa_new, 0, sizeof(sa_new)); | |
2268 | sa_new.sa_flags = SA_SIGINFO; | |
2269 | sa_new.sa_sigaction = sigill_handler; | |
2270 | sigaction(SIGILL, &sa_new, &sa_old); | |
2271 | ||
2272 | /* Probe for movn/movz, necessary to implement movcond. */ | |
2273 | #ifndef use_movnz_instructions | |
2274 | got_sigill = 0; | |
2275 | asm volatile(".set push\n" | |
2276 | ".set mips32\n" | |
2277 | "movn $zero, $zero, $zero\n" | |
2278 | "movz $zero, $zero, $zero\n" | |
2279 | ".set pop\n" | |
2280 | : : : ); | |
2281 | use_movnz_instructions = !got_sigill; | |
2282 | #endif | |
2283 | ||
2284 | /* Probe for MIPS32 instructions. As no subsetting is allowed | |
2285 | by the specification, it is only necessary to probe for one | |
2286 | of the instructions. */ | |
2287 | #ifndef use_mips32_instructions | |
2288 | got_sigill = 0; | |
2289 | asm volatile(".set push\n" | |
2290 | ".set mips32\n" | |
2291 | "mul $zero, $zero\n" | |
2292 | ".set pop\n" | |
2293 | : : : ); | |
2294 | use_mips32_instructions = !got_sigill; | |
2295 | #endif | |
2296 | ||
2297 | /* Probe for MIPS32r2 instructions if MIPS32 instructions are | |
2298 | available. As no subsetting is allowed by the specification, | |
2299 | it is only necessary to probe for one of the instructions. */ | |
2300 | #ifndef use_mips32r2_instructions | |
2301 | if (use_mips32_instructions) { | |
2302 | got_sigill = 0; | |
2303 | asm volatile(".set push\n" | |
2304 | ".set mips32r2\n" | |
2305 | "seb $zero, $zero\n" | |
2306 | ".set pop\n" | |
2307 | : : : ); | |
2308 | use_mips32r2_instructions = !got_sigill; | |
2309 | } | |
2310 | #endif | |
2311 | ||
2312 | sigaction(SIGILL, &sa_old, NULL); | |
2313 | } | |
2314 | ||
bb08afe9 JG |
2315 | static tcg_insn_unit *align_code_ptr(TCGContext *s) |
2316 | { | |
2317 | uintptr_t p = (uintptr_t)s->code_ptr; | |
2318 | if (p & 15) { | |
2319 | p = (p + 15) & -16; | |
2320 | s->code_ptr = (void *)p; | |
2321 | } | |
2322 | return s->code_ptr; | |
2323 | } | |
2324 | ||
0973b1cf JG |
2325 | /* Stack frame parameters. */ |
2326 | #define REG_SIZE (TCG_TARGET_REG_BITS / 8) | |
2327 | #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) | |
2328 | #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) | |
2329 | ||
2330 | #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ | |
2331 | + TCG_TARGET_STACK_ALIGN - 1) \ | |
2332 | & -TCG_TARGET_STACK_ALIGN) | |
2333 | #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) | |
2334 | ||
2335 | /* We're expecting to be able to use an immediate for frame allocation. */ | |
2336 | QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); | |
2337 | ||
afa05235 | 2338 | /* Generate global QEMU prologue and epilogue code */ |
e4d58b41 | 2339 | static void tcg_target_qemu_prologue(TCGContext *s) |
afa05235 | 2340 | { |
0973b1cf JG |
2341 | int i; |
2342 | ||
2343 | tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); | |
afa05235 AJ |
2344 | |
2345 | /* TB prologue */ | |
0973b1cf JG |
2346 | tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); |
2347 | for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { | |
2348 | tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], | |
2349 | TCG_REG_SP, SAVE_OFS + i * REG_SIZE); | |
afa05235 AJ |
2350 | } |
2351 | ||
4df9cac5 JB |
2352 | #ifndef CONFIG_SOFTMMU |
2353 | if (guest_base) { | |
2354 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); | |
2355 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); | |
2356 | } | |
2357 | #endif | |
2358 | ||
afa05235 | 2359 | /* Call generated code */ |
ea15fb06 | 2360 | tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); |
0973b1cf | 2361 | /* delay slot */ |
cea5f9a2 | 2362 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); |
afa05235 | 2363 | |
5786e068 AJ |
2364 | /* |
2365 | * Return path for goto_ptr. Set return value to 0, a-la exit_tb, | |
2366 | * and fall through to the rest of the epilogue. | |
2367 | */ | |
c8bc1168 | 2368 | tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); |
5786e068 AJ |
2369 | tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); |
2370 | ||
afa05235 | 2371 | /* TB epilogue */ |
df5af130 | 2372 | tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); |
0973b1cf JG |
2373 | for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { |
2374 | tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], | |
2375 | TCG_REG_SP, SAVE_OFS + i * REG_SIZE); | |
afa05235 AJ |
2376 | } |
2377 | ||
2378 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); | |
bb08afe9 | 2379 | /* delay slot */ |
0973b1cf | 2380 | tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); |
bb08afe9 JG |
2381 | |
2382 | if (use_mips32r2_instructions) { | |
2383 | return; | |
2384 | } | |
2385 | ||
7f54eaa3 | 2386 | /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; |
bb08afe9 JG |
2387 | clobbers TCG_TMP1, TCG_TMP2. */ |
2388 | ||
2389 | /* | |
2390 | * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. | |
2391 | */ | |
df5af130 | 2392 | bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); |
bb08afe9 JG |
2393 | /* t3 = (ssss)d000 */ |
2394 | tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); | |
2395 | /* t1 = 000a */ | |
2396 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); | |
2397 | /* t2 = 00c0 */ | |
2398 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); | |
2399 | /* t3 = d00a */ | |
2400 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2401 | /* t1 = 0abc */ | |
2402 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); | |
2403 | /* t2 = 0c00 */ | |
2404 | tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); | |
2405 | /* t1 = 00b0 */ | |
2406 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); | |
2407 | /* t3 = dc0a */ | |
2408 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2409 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); | |
2410 | /* t3 = dcba -- delay slot */ | |
2411 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
7f54eaa3 JG |
2412 | |
2413 | if (TCG_TARGET_REG_BITS == 32) { | |
2414 | return; | |
2415 | } | |
2416 | ||
2417 | /* | |
2418 | * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. | |
2419 | */ | |
df5af130 | 2420 | bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); |
7f54eaa3 JG |
2421 | /* t1 = (0000)000d */ |
2422 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); | |
2423 | /* t3 = 000a */ | |
2424 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); | |
2425 | /* t1 = (0000)d000 */ | |
2426 | tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); | |
2427 | /* t2 = 00c0 */ | |
2428 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); | |
2429 | /* t3 = d00a */ | |
2430 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2431 | /* t1 = 0abc */ | |
2432 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); | |
2433 | /* t2 = 0c00 */ | |
2434 | tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); | |
2435 | /* t1 = 00b0 */ | |
2436 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); | |
2437 | /* t3 = dc0a */ | |
2438 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2439 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); | |
2440 | /* t3 = dcba -- delay slot */ | |
2441 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2442 | ||
2443 | /* | |
2444 | * bswap64 -- 64-bit swap. a0 = abcdefgh | |
2445 | */ | |
df5af130 | 2446 | bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); |
7f54eaa3 JG |
2447 | /* t3 = h0000000 */ |
2448 | tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); | |
2449 | /* t1 = 0000000a */ | |
2450 | tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); | |
2451 | ||
2452 | /* t2 = 000000g0 */ | |
2453 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); | |
2454 | /* t3 = h000000a */ | |
2455 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2456 | /* t1 = 00000abc */ | |
2457 | tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); | |
2458 | /* t2 = 0g000000 */ | |
2459 | tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); | |
2460 | /* t1 = 000000b0 */ | |
2461 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); | |
2462 | ||
2463 | /* t3 = hg00000a */ | |
2464 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2465 | /* t2 = 0000abcd */ | |
2466 | tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); | |
2467 | /* t3 = hg0000ba */ | |
2468 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2469 | ||
2470 | /* t1 = 000000c0 */ | |
2471 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); | |
2472 | /* t2 = 0000000d */ | |
2473 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); | |
2474 | /* t1 = 00000c00 */ | |
2475 | tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); | |
2476 | /* t2 = 0000d000 */ | |
2477 | tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); | |
2478 | ||
2479 | /* t3 = hg000cba */ | |
2480 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2481 | /* t1 = 00abcdef */ | |
2482 | tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); | |
2483 | /* t3 = hg00dcba */ | |
2484 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2485 | ||
2486 | /* t2 = 0000000f */ | |
2487 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); | |
2488 | /* t1 = 000000e0 */ | |
2489 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); | |
2490 | /* t2 = 00f00000 */ | |
2491 | tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); | |
2492 | /* t1 = 000e0000 */ | |
2493 | tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); | |
2494 | ||
2495 | /* t3 = hgf0dcba */ | |
2496 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2497 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); | |
2498 | /* t3 = hgfedcba -- delay slot */ | |
2499 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
afa05235 AJ |
2500 | } |
2501 | ||
e4d58b41 | 2502 | static void tcg_target_init(TCGContext *s) |
afa05235 | 2503 | { |
988902fc | 2504 | tcg_target_detect_isa(); |
d21369f5 | 2505 | tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; |
999b9416 | 2506 | if (TCG_TARGET_REG_BITS == 64) { |
d21369f5 RH |
2507 | tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; |
2508 | } | |
2509 | ||
2510 | tcg_target_call_clobber_regs = 0; | |
2511 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); | |
2512 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); | |
2513 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); | |
2514 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); | |
2515 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); | |
2516 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); | |
2517 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); | |
2518 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); | |
2519 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); | |
2520 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); | |
2521 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); | |
2522 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); | |
2523 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); | |
2524 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); | |
2525 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); | |
2526 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); | |
afa05235 | 2527 | |
ccb1bb66 | 2528 | s->reserved_regs = 0; |
afa05235 AJ |
2529 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ |
2530 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ | |
2531 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ | |
6c530e32 RH |
2532 | tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ |
2533 | tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ | |
bb08afe9 JG |
2534 | tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ |
2535 | tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ | |
afa05235 AJ |
2536 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ |
2537 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ | |
3314e008 | 2538 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ |
afa05235 | 2539 | } |
b6bfeea9 | 2540 | |
1acbad0f RH |
2541 | void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, |
2542 | uintptr_t jmp_rw, uintptr_t addr) | |
b6bfeea9 | 2543 | { |
1acbad0f RH |
2544 | qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); |
2545 | flush_idcache_range(jmp_rx, jmp_rw, 4); | |
b6bfeea9 | 2546 | } |
98d69076 JG |
2547 | |
2548 | typedef struct { | |
2549 | DebugFrameHeader h; | |
2550 | uint8_t fde_def_cfa[4]; | |
2551 | uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; | |
2552 | } DebugFrame; | |
2553 | ||
2554 | #define ELF_HOST_MACHINE EM_MIPS | |
2555 | /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, | |
2556 | which is good because they're really quite complicated for MIPS. */ | |
2557 | ||
2558 | static const DebugFrame debug_frame = { | |
2559 | .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ | |
2560 | .h.cie.id = -1, | |
2561 | .h.cie.version = 1, | |
2562 | .h.cie.code_align = 1, | |
2563 | .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ | |
2564 | .h.cie.return_column = TCG_REG_RA, | |
2565 | ||
2566 | /* Total FDE size does not include the "len" member. */ | |
2567 | .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), | |
2568 | ||
2569 | .fde_def_cfa = { | |
2570 | 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ | |
2571 | (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ | |
2572 | (FRAME_SIZE >> 7) | |
2573 | }, | |
2574 | .fde_reg_ofs = { | |
2575 | 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ | |
2576 | 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ | |
2577 | 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ | |
2578 | 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ | |
2579 | 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ | |
2580 | 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ | |
2581 | 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ | |
2582 | 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ | |
2583 | 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ | |
2584 | } | |
2585 | }; | |
2586 | ||
755bf9e5 | 2587 | void tcg_register_jit(const void *buf, size_t buf_size) |
98d69076 JG |
2588 | { |
2589 | tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); | |
2590 | } |