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tcg: Remove TCG_TARGET_SUPPORT_MIRROR
[mirror_qemu.git] / tcg / mips / tcg-target.c.inc
CommitLineData
afa05235
AJ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
9d8bf2d1
RH		 27#ifdef HOST_WORDS_BIGENDIAN
28# define MIPS_BE 1
afa05235 29#else
9d8bf2d1 30# define MIPS_BE 0
afa05235
AJ		 31#endif
32
f0d70331
JG		 33#if TCG_TARGET_REG_BITS == 32
34# define LO_OFF (MIPS_BE * 4)
35# define HI_OFF (4 - LO_OFF)
36#else
37/* To assert at compile-time that these values are never used
38 for TCG_TARGET_REG_BITS == 64. */
8df8d529 39int link_error(void);
f0d70331
JG		 40# define LO_OFF link_error()
41# define HI_OFF link_error()
42#endif
9d8bf2d1 43
8d8fdbae 44#ifdef CONFIG_DEBUG_TCG
afa05235
AJ		 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 "zero",
47 "at",
48 "v0",
49 "v1",
50 "a0",
51 "a1",
52 "a2",
53 "a3",
54 "t0",
55 "t1",
56 "t2",
57 "t3",
58 "t4",
59 "t5",
60 "t6",
61 "t7",
62 "s0",
63 "s1",
64 "s2",
65 "s3",
66 "s4",
67 "s5",
68 "s6",
69 "s7",
70 "t8",
71 "t9",
72 "k0",
73 "k1",
74 "gp",
75 "sp",
41883904 76 "s8",
afa05235
AJ		 77 "ra",
78};
79#endif
80
6c530e32 81#define TCG_TMP0 TCG_REG_AT
f216a35f 82#define TCG_TMP1 TCG_REG_T9
bb08afe9
JG		 83#define TCG_TMP2 TCG_REG_T8
84#define TCG_TMP3 TCG_REG_T7
6c530e32 85
4df9cac5
JB		 86#ifndef CONFIG_SOFTMMU
87#define TCG_GUEST_BASE_REG TCG_REG_S1
88#endif
89
afa05235 90/* check if we really need so many registers :P */
2dc7553d 91static const int tcg_target_reg_alloc_order[] = {
41883904 92 /* Call saved registers. */
afa05235
AJ		 93 TCG_REG_S0,
94 TCG_REG_S1,
95 TCG_REG_S2,
96 TCG_REG_S3,
97 TCG_REG_S4,
98 TCG_REG_S5,
99 TCG_REG_S6,
100 TCG_REG_S7,
41883904
RH		 101 TCG_REG_S8,
102
103 /* Call clobbered registers. */
afa05235
AJ		 104 TCG_REG_T4,
105 TCG_REG_T5,
106 TCG_REG_T6,
107 TCG_REG_T7,
108 TCG_REG_T8,
109 TCG_REG_T9,
41883904 110 TCG_REG_V1,
afa05235 111 TCG_REG_V0,
41883904
RH		 112
113 /* Argument registers, opposite order of allocation. */
999b9416
JG		 114 TCG_REG_T3,
115 TCG_REG_T2,
116 TCG_REG_T1,
117 TCG_REG_T0,
41883904
RH		 118 TCG_REG_A3,
119 TCG_REG_A2,
120 TCG_REG_A1,
121 TCG_REG_A0,
afa05235
AJ		 122};
123
999b9416 124static const TCGReg tcg_target_call_iarg_regs[] = {
afa05235
AJ		 125 TCG_REG_A0,
126 TCG_REG_A1,
127 TCG_REG_A2,
999b9416
JG		 128 TCG_REG_A3,
129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
130 TCG_REG_T0,
131 TCG_REG_T1,
132 TCG_REG_T2,
133 TCG_REG_T3,
134#endif
afa05235
AJ		 135};
136
5a0eed37 137static const TCGReg tcg_target_call_oarg_regs[2] = {
afa05235
AJ		 138 TCG_REG_V0,
139 TCG_REG_V1
140};
141
df5af130
RH		 142static const tcg_insn_unit *tb_ret_addr;
143static const tcg_insn_unit *bswap32_addr;
144static const tcg_insn_unit *bswap32u_addr;
145static const tcg_insn_unit *bswap64_addr;
afa05235 146
df5af130 147static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
afa05235 148{
ae0218e3 149 /* Let the compiler perform the right-shift as part of the arithmetic. */
df5af130
RH		 150 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
151 ptrdiff_t disp = target - (src_rx + 1);
91a7fd1f 152 if (disp == (int16_t)disp) {
df5af130 153 *src_rw = deposit32(*src_rw, 0, 16, disp);
91a7fd1f
RH		 154 return true;
155 }
156 return false;
afa05235
AJ		 157}
158
6ac17786 159static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
2ba7fae2 160 intptr_t value, intptr_t addend)
afa05235 161{
eabb7b91
AJ		 162 tcg_debug_assert(type == R_MIPS_PC16);
163 tcg_debug_assert(addend == 0);
91a7fd1f 164 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
afa05235
AJ		 165}
166
1c418268 167#define TCG_CT_CONST_ZERO 0x100
070603f6
RH		 168#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
169#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
170#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
171#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
2a1d9d41 172#define TCG_CT_CONST_WSZ 0x2000 /* word size */
1c418268
RH		 173
174static inline bool is_p2m1(tcg_target_long val)
175{
176 return val && ((val + 1) & val) == 0;
177}
178
afa05235 179/* parse target specific constraints */
069ea736
RH		 180static const char *target_parse_constraint(TCGArgConstraint *ct,
181 const char *ct_str, TCGType type)
afa05235 182{
069ea736 183 switch(*ct_str++) {
afa05235 184 case 'r':
9be0d080 185 ct->regs = 0xffffffff;
afa05235 186 break;
bb08afe9 187 case 'L': /* qemu_ld input arg constraint */
9be0d080
RH		 188 ct->regs = 0xffffffff;
189 tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
9d8bf2d1 190#if defined(CONFIG_SOFTMMU)
f0d70331 191 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9be0d080 192 tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
9d8bf2d1 193 }
afa05235
AJ		 194#endif
195 break;
196 case 'S': /* qemu_st constraint */
9be0d080
RH		 197 ct->regs = 0xffffffff;
198 tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
cc01cc8e 199#if defined(CONFIG_SOFTMMU)
f0d70331 200 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9be0d080
RH		 201 tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
202 tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
f0d70331 203 } else {
9be0d080 204 tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
9d8bf2d1 205 }
afa05235
AJ		 206#endif
207 break;
208 case 'I':
209 ct->ct |= TCG_CT_CONST_U16;
210 break;
211 case 'J':
212 ct->ct |= TCG_CT_CONST_S16;
213 break;
1c418268
RH		 214 case 'K':
215 ct->ct |= TCG_CT_CONST_P2M1;
216 break;
070603f6
RH		 217 case 'N':
218 ct->ct |= TCG_CT_CONST_N16;
219 break;
2a1d9d41
RH		 220 case 'W':
221 ct->ct |= TCG_CT_CONST_WSZ;
222 break;
afa05235
AJ		 223 case 'Z':
224 /* We are cheating a bit here, using the fact that the register
225 ZERO is also the register number 0. Hence there is no need
226 to check for const_args in each instruction. */
227 ct->ct |= TCG_CT_CONST_ZERO;
228 break;
229 default:
069ea736 230 return NULL;
afa05235 231 }
069ea736 232 return ct_str;
afa05235
AJ		 233}
234
235/* test if a constant matches the constraint */
f6c6afc1 236static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
afa05235
AJ		 237 const TCGArgConstraint *arg_ct)
238{
239 int ct;
240 ct = arg_ct->ct;
1c418268 241 if (ct & TCG_CT_CONST) {
afa05235 242 return 1;
1c418268 243 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
afa05235 244 return 1;
1c418268 245 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
afa05235 246 return 1;
1c418268 247 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
afa05235 248 return 1;
070603f6
RH		 249 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
250 return 1;
1c418268
RH		 251 } else if ((ct & TCG_CT_CONST_P2M1)
252 && use_mips32r2_instructions && is_p2m1(val)) {
253 return 1;
2a1d9d41
RH		 254 } else if ((ct & TCG_CT_CONST_WSZ)
255 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
256 return 1;
1c418268
RH		 257 }
258 return 0;
afa05235
AJ		 259}
260
261/* instruction opcodes */
ac0f3b12 262typedef enum {
57a701fc
JG		 263 OPC_J = 002 << 26,
264 OPC_JAL = 003 << 26,
265 OPC_BEQ = 004 << 26,
266 OPC_BNE = 005 << 26,
267 OPC_BLEZ = 006 << 26,
268 OPC_BGTZ = 007 << 26,
269 OPC_ADDIU = 011 << 26,
270 OPC_SLTI = 012 << 26,
271 OPC_SLTIU = 013 << 26,
272 OPC_ANDI = 014 << 26,
273 OPC_ORI = 015 << 26,
274 OPC_XORI = 016 << 26,
275 OPC_LUI = 017 << 26,
276 OPC_DADDIU = 031 << 26,
277 OPC_LB = 040 << 26,
278 OPC_LH = 041 << 26,
279 OPC_LW = 043 << 26,
280 OPC_LBU = 044 << 26,
281 OPC_LHU = 045 << 26,
282 OPC_LWU = 047 << 26,
283 OPC_SB = 050 << 26,
284 OPC_SH = 051 << 26,
285 OPC_SW = 053 << 26,
286 OPC_LD = 067 << 26,
287 OPC_SD = 077 << 26,
288
289 OPC_SPECIAL = 000 << 26,
290 OPC_SLL = OPC_SPECIAL | 000,
291 OPC_SRL = OPC_SPECIAL | 002,
292 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
293 OPC_SRA = OPC_SPECIAL | 003,
294 OPC_SLLV = OPC_SPECIAL | 004,
295 OPC_SRLV = OPC_SPECIAL | 006,
296 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
297 OPC_SRAV = OPC_SPECIAL | 007,
298 OPC_JR_R5 = OPC_SPECIAL | 010,
299 OPC_JALR = OPC_SPECIAL | 011,
300 OPC_MOVZ = OPC_SPECIAL | 012,
301 OPC_MOVN = OPC_SPECIAL | 013,
302 OPC_SYNC = OPC_SPECIAL | 017,
303 OPC_MFHI = OPC_SPECIAL | 020,
304 OPC_MFLO = OPC_SPECIAL | 022,
305 OPC_DSLLV = OPC_SPECIAL | 024,
306 OPC_DSRLV = OPC_SPECIAL | 026,
307 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
308 OPC_DSRAV = OPC_SPECIAL | 027,
309 OPC_MULT = OPC_SPECIAL | 030,
310 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
311 OPC_MUH = OPC_SPECIAL | 030 | 0300,
312 OPC_MULTU = OPC_SPECIAL | 031,
313 OPC_MULU = OPC_SPECIAL | 031 | 0200,
314 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
315 OPC_DIV = OPC_SPECIAL | 032,
316 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
317 OPC_MOD = OPC_SPECIAL | 032 | 0300,
318 OPC_DIVU = OPC_SPECIAL | 033,
319 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
320 OPC_MODU = OPC_SPECIAL | 033 | 0300,
321 OPC_DMULT = OPC_SPECIAL | 034,
322 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
323 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
324 OPC_DMULTU = OPC_SPECIAL | 035,
325 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
326 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
327 OPC_DDIV = OPC_SPECIAL | 036,
328 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
329 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
330 OPC_DDIVU = OPC_SPECIAL | 037,
331 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
332 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
333 OPC_ADDU = OPC_SPECIAL | 041,
334 OPC_SUBU = OPC_SPECIAL | 043,
335 OPC_AND = OPC_SPECIAL | 044,
336 OPC_OR = OPC_SPECIAL | 045,
337 OPC_XOR = OPC_SPECIAL | 046,
338 OPC_NOR = OPC_SPECIAL | 047,
339 OPC_SLT = OPC_SPECIAL | 052,
340 OPC_SLTU = OPC_SPECIAL | 053,
341 OPC_DADDU = OPC_SPECIAL | 055,
342 OPC_DSUBU = OPC_SPECIAL | 057,
343 OPC_SELEQZ = OPC_SPECIAL | 065,
344 OPC_SELNEZ = OPC_SPECIAL | 067,
345 OPC_DSLL = OPC_SPECIAL | 070,
346 OPC_DSRL = OPC_SPECIAL | 072,
347 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
348 OPC_DSRA = OPC_SPECIAL | 073,
349 OPC_DSLL32 = OPC_SPECIAL | 074,
350 OPC_DSRL32 = OPC_SPECIAL | 076,
351 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
352 OPC_DSRA32 = OPC_SPECIAL | 077,
2a1d9d41
RH		 353 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
354 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
57a701fc
JG		 355
356 OPC_REGIMM = 001 << 26,
357 OPC_BLTZ = OPC_REGIMM | (000 << 16),
358 OPC_BGEZ = OPC_REGIMM | (001 << 16),
359
360 OPC_SPECIAL2 = 034 << 26,
361 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
2a1d9d41
RH		 362 OPC_CLZ = OPC_SPECIAL2 | 040,
363 OPC_DCLZ = OPC_SPECIAL2 | 044,
57a701fc
JG		 364
365 OPC_SPECIAL3 = 037 << 26,
366 OPC_EXT = OPC_SPECIAL3 | 000,
367 OPC_DEXTM = OPC_SPECIAL3 | 001,
368 OPC_DEXTU = OPC_SPECIAL3 | 002,
369 OPC_DEXT = OPC_SPECIAL3 | 003,
370 OPC_INS = OPC_SPECIAL3 | 004,
371 OPC_DINSM = OPC_SPECIAL3 | 005,
372 OPC_DINSU = OPC_SPECIAL3 | 006,
373 OPC_DINS = OPC_SPECIAL3 | 007,
374 OPC_WSBH = OPC_SPECIAL3 | 00240,
375 OPC_DSBH = OPC_SPECIAL3 | 00244,
376 OPC_DSHD = OPC_SPECIAL3 | 00544,
377 OPC_SEB = OPC_SPECIAL3 | 02040,
378 OPC_SEH = OPC_SPECIAL3 | 03040,
6e0d0969
JH		 379
380 /* MIPS r6 doesn't have JR, JALR should be used instead */
381 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
bc6d0c22
JH		 382
383 /*
384 * MIPS r6 replaces MUL with an alternative encoding which is
385 * backwards-compatible at the assembly level.
386 */
387 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
6f0b9910
PK		 388
389 /* MIPS r6 introduced names for weaker variants of SYNC. These are
390 backward compatible to previous architecture revisions. */
a4e57084 391 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
392 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
393 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
394 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
395 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
57a701fc
JG		 396
397 /* Aliases for convenience. */
398 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
399 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
400 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
401 ? OPC_SRL : OPC_DSRL,
ac0f3b12 402} MIPSInsn;
afa05235
AJ		 403
404/*
405 * Type reg
406 */
ac0f3b12 407static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
5a0eed37 408 TCGReg rd, TCGReg rs, TCGReg rt)
afa05235
AJ		 409{
410 int32_t inst;
411
412 inst = opc;
413 inst |= (rs & 0x1F) << 21;
414 inst |= (rt & 0x1F) << 16;
415 inst |= (rd & 0x1F) << 11;
416 tcg_out32(s, inst);
417}
418
419/*
420 * Type immediate
421 */
ac0f3b12 422static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
5a0eed37 423 TCGReg rt, TCGReg rs, TCGArg imm)
afa05235
AJ		 424{
425 int32_t inst;
426
427 inst = opc;
428 inst |= (rs & 0x1F) << 21;
429 inst |= (rt & 0x1F) << 16;
430 inst |= (imm & 0xffff);
431 tcg_out32(s, inst);
432}
433
1c418268
RH		 434/*
435 * Type bitfield
436 */
ac0f3b12 437static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
1c418268
RH		 438 TCGReg rs, int msb, int lsb)
439{
440 int32_t inst;
441
442 inst = opc;
443 inst |= (rs & 0x1F) << 21;
444 inst |= (rt & 0x1F) << 16;
445 inst |= (msb & 0x1F) << 11;
446 inst |= (lsb & 0x1F) << 6;
447 tcg_out32(s, inst);
448}
449
0119b192
JG		 450static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
451 MIPSInsn oph, TCGReg rt, TCGReg rs,
452 int msb, int lsb)
453{
454 if (lsb >= 32) {
455 opc = oph;
456 msb -= 32;
457 lsb -= 32;
458 } else if (msb >= 32) {
459 opc = opm;
460 msb -= 32;
461 }
462 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
463}
464
6d8ff4d8
AJ		 465/*
466 * Type branch
467 */
ac0f3b12 468static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
5a0eed37 469 TCGReg rt, TCGReg rs)
6d8ff4d8 470{
8c1b0792 471 tcg_out_opc_imm(s, opc, rt, rs, 0);
6d8ff4d8
AJ		 472}
473
afa05235
AJ		 474/*
475 * Type sa
476 */
ac0f3b12 477static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
5a0eed37 478 TCGReg rd, TCGReg rt, TCGArg sa)
afa05235
AJ		 479{
480 int32_t inst;
481
482 inst = opc;
483 inst |= (rt & 0x1F) << 16;
484 inst |= (rd & 0x1F) << 11;
485 inst |= (sa & 0x1F) << 6;
486 tcg_out32(s, inst);
487
488}
489
0119b192
JG		 490static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
491 TCGReg rd, TCGReg rt, TCGArg sa)
492{
493 int32_t inst;
494
495 inst = (sa & 32 ? opc2 : opc1);
496 inst |= (rt & 0x1F) << 16;
497 inst |= (rd & 0x1F) << 11;
498 inst |= (sa & 0x1F) << 6;
499 tcg_out32(s, inst);
500}
501
f8c9eddb
RH		 502/*
503 * Type jump.
504 * Returns true if the branch was in range and the insn was emitted.
505 */
2be7d76b 506static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
f8c9eddb
RH		 507{
508 uintptr_t dest = (uintptr_t)target;
df5af130 509 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4;
f8c9eddb
RH		 510 int32_t inst;
511
512 /* The pc-region branch happens within the 256MB region of
513 the delay slot (thus the +4). */
514 if ((from ^ dest) & -(1 << 28)) {
515 return false;
516 }
eabb7b91 517 tcg_debug_assert((dest & 3) == 0);
f8c9eddb
RH		 518
519 inst = opc;
520 inst |= (dest >> 2) & 0x3ffffff;
521 tcg_out32(s, inst);
522 return true;
523}
524
afa05235
AJ		 525static inline void tcg_out_nop(TCGContext *s)
526{
527 tcg_out32(s, 0);
528}
529
0119b192
JG		 530static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
531{
532 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
533}
534
535static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
536{
537 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
538}
539
540static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
541{
542 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
543}
544
78113e83 545static inline bool tcg_out_mov(TCGContext *s, TCGType type,
2a534aff 546 TCGReg ret, TCGReg arg)
afa05235 547{
18fec301
AJ		 548 /* Simple reg-reg move, optimising out the 'do nothing' case */
549 if (ret != arg) {
2294d05d 550 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
18fec301 551 }
78113e83 552 return true;
afa05235
AJ		 553}
554
2294d05d
JG		 555static void tcg_out_movi(TCGContext *s, TCGType type,
556 TCGReg ret, tcg_target_long arg)
afa05235 557{
2294d05d
JG		 558 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
559 arg = (int32_t)arg;
560 }
afa05235 561 if (arg == (int16_t)arg) {
2294d05d
JG		 562 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
563 return;
564 }
565 if (arg == (uint16_t)arg) {
566 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
567 return;
568 }
569 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
570 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
afa05235 571 } else {
2294d05d
JG		 572 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
573 if (arg & 0xffff0000ull) {
574 tcg_out_dsll(s, ret, ret, 16);
575 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
576 tcg_out_dsll(s, ret, ret, 16);
577 } else {
578 tcg_out_dsll(s, ret, ret, 32);
7dae901d 579 }
afa05235 580 }
2294d05d
JG		 581 if (arg & 0xffff) {
582 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
583 }
afa05235
AJ		 584}
585
5a0eed37 586static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
afa05235 587{
988902fc
AJ		 588 if (use_mips32r2_instructions) {
589 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
590 } else {
591 /* ret and arg can't be register at */
6c530e32 592 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
988902fc
AJ		 593 tcg_abort();
594 }
afa05235 595
6c530e32 596 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
988902fc
AJ		 597 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
598 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
6c530e32 599 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
988902fc 600 }
afa05235
AJ		 601}
602
5a0eed37 603static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
afa05235 604{
988902fc
AJ		 605 if (use_mips32r2_instructions) {
606 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
607 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
608 } else {
609 /* ret and arg can't be register at */
6c530e32 610 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
988902fc
AJ		 611 tcg_abort();
612 }
afa05235 613
6c530e32 614 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
988902fc
AJ		 615 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
616 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
6c530e32 617 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
988902fc 618 }
afa05235
AJ		 619}
620
df5af130 621static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
bb08afe9
JG		 622{
623 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub);
624 tcg_debug_assert(ok);
625}
626
627static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
afa05235 628{
988902fc
AJ		 629 if (use_mips32r2_instructions) {
630 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
631 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
632 } else {
bb08afe9
JG		 633 tcg_out_bswap_subr(s, bswap32_addr);
634 /* delay slot -- never omit the insn, like tcg_out_mov might. */
635 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
636 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
988902fc 637 }
afa05235
AJ		 638}
639
0119b192
JG		 640static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
641{
642 if (use_mips32r2_instructions) {
643 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
644 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
645 tcg_out_dsrl(s, ret, ret, 32);
646 } else {
7f54eaa3
JG		 647 tcg_out_bswap_subr(s, bswap32u_addr);
648 /* delay slot -- never omit the insn, like tcg_out_mov might. */
649 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
650 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
0119b192
JG		 651 }
652}
653
654static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
655{
656 if (use_mips32r2_instructions) {
657 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
658 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
659 } else {
7f54eaa3
JG		 660 tcg_out_bswap_subr(s, bswap64_addr);
661 /* delay slot -- never omit the insn, like tcg_out_mov might. */
662 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
663 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
0119b192
JG		 664 }
665}
666
5a0eed37 667static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
116348de 668{
988902fc
AJ		 669 if (use_mips32r2_instructions) {
670 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
671 } else {
672 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
673 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
674 }
116348de
AJ		 675}
676
5a0eed37 677static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
116348de 678{
988902fc
AJ		 679 if (use_mips32r2_instructions) {
680 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
681 } else {
682 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
683 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
684 }
116348de
AJ		 685}
686
0119b192
JG		 687static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
688{
689 if (use_mips32r2_instructions) {
690 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
691 } else {
692 tcg_out_dsll(s, ret, arg, 32);
693 tcg_out_dsrl(s, ret, ret, 32);
694 }
695}
696
ac0f3b12 697static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
f9a71632 698 TCGReg addr, intptr_t ofs)
afa05235 699{
f9a71632
RH		 700 int16_t lo = ofs;
701 if (ofs != lo) {
6c530e32 702 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
f9a71632 703 if (addr != TCG_REG_ZERO) {
32b69707 704 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
f9a71632 705 }
6c530e32 706 addr = TCG_TMP0;
afa05235 707 }
f9a71632 708 tcg_out_opc_imm(s, opc, data, addr, lo);
afa05235
AJ		 709}
710
2a534aff 711static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
a05b5b9b 712 TCGReg arg1, intptr_t arg2)
afa05235 713{
32b69707
JG		 714 MIPSInsn opc = OPC_LD;
715 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
716 opc = OPC_LW;
717 }
718 tcg_out_ldst(s, opc, arg, arg1, arg2);
afa05235
AJ		 719}
720
2a534aff 721static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
a05b5b9b 722 TCGReg arg1, intptr_t arg2)
afa05235 723{
32b69707
JG		 724 MIPSInsn opc = OPC_SD;
725 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
726 opc = OPC_SW;
727 }
728 tcg_out_ldst(s, opc, arg, arg1, arg2);
afa05235
AJ		 729}
730
59d7c14e
RH		 731static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
732 TCGReg base, intptr_t ofs)
733{
734 if (val == 0) {
735 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
736 return true;
737 }
738 return false;
739}
740
d9f26847
AJ		 741static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
742 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
743 bool cbh, bool is_sub)
744{
745 TCGReg th = TCG_TMP1;
746
747 /* If we have a negative constant such that negating it would
748 make the high part zero, we can (usually) eliminate one insn. */
749 if (cbl && cbh && bh == -1 && bl != 0) {
750 bl = -bl;
751 bh = 0;
752 is_sub = !is_sub;
753 }
754
755 /* By operating on the high part first, we get to use the final
756 carry operation to move back from the temporary. */
757 if (!cbh) {
758 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
759 } else if (bh != 0 || ah == rl) {
760 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
761 } else {
762 th = ah;
763 }
764
765 /* Note that tcg optimization should eliminate the bl == 0 case. */
766 if (is_sub) {
767 if (cbl) {
768 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
769 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
770 } else {
771 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
772 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
773 }
774 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
775 } else {
776 if (cbl) {
777 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
778 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
779 } else if (rl == al && rl == bl) {
161dec9d 780 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
d9f26847
AJ		 781 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
782 } else {
783 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
784 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
785 }
786 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
787 }
788}
789
fd1cf666
RH		 790/* Bit 0 set if inversion required; bit 1 set if swapping required. */
791#define MIPS_CMP_INV 1
792#define MIPS_CMP_SWAP 2
793
794static const uint8_t mips_cmp_map[16] = {
795 [TCG_COND_LT] = 0,
796 [TCG_COND_LTU] = 0,
797 [TCG_COND_GE] = MIPS_CMP_INV,
798 [TCG_COND_GEU] = MIPS_CMP_INV,
799 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
800 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
801 [TCG_COND_GT] = MIPS_CMP_SWAP,
802 [TCG_COND_GTU] = MIPS_CMP_SWAP,
803};
804
805static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
806 TCGReg arg1, TCGReg arg2)
807{
808 MIPSInsn s_opc = OPC_SLTU;
809 int cmp_map;
810
811 switch (cond) {
812 case TCG_COND_EQ:
813 if (arg2 != 0) {
814 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
815 arg1 = ret;
816 }
817 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
818 break;
819
820 case TCG_COND_NE:
821 if (arg2 != 0) {
822 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
823 arg1 = ret;
824 }
825 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
826 break;
827
828 case TCG_COND_LT:
829 case TCG_COND_GE:
830 case TCG_COND_LE:
831 case TCG_COND_GT:
832 s_opc = OPC_SLT;
833 /* FALLTHRU */
834
835 case TCG_COND_LTU:
836 case TCG_COND_GEU:
837 case TCG_COND_LEU:
838 case TCG_COND_GTU:
839 cmp_map = mips_cmp_map[cond];
840 if (cmp_map & MIPS_CMP_SWAP) {
841 TCGReg t = arg1;
842 arg1 = arg2;
843 arg2 = t;
844 }
845 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
846 if (cmp_map & MIPS_CMP_INV) {
847 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
848 }
849 break;
850
851 default:
852 tcg_abort();
853 break;
854 }
855}
856
c068896f 857static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
bec16311 858 TCGReg arg2, TCGLabel *l)
afa05235 859{
c068896f
RH		 860 static const MIPSInsn b_zero[16] = {
861 [TCG_COND_LT] = OPC_BLTZ,
862 [TCG_COND_GT] = OPC_BGTZ,
863 [TCG_COND_LE] = OPC_BLEZ,
864 [TCG_COND_GE] = OPC_BGEZ,
865 };
866
c068896f
RH		 867 MIPSInsn s_opc = OPC_SLTU;
868 MIPSInsn b_opc;
869 int cmp_map;
afa05235
AJ		 870
871 switch (cond) {
872 case TCG_COND_EQ:
c068896f 873 b_opc = OPC_BEQ;
afa05235
AJ		 874 break;
875 case TCG_COND_NE:
c068896f 876 b_opc = OPC_BNE;
afa05235 877 break;
c068896f 878
afa05235 879 case TCG_COND_LT:
c068896f 880 case TCG_COND_GT:
afa05235 881 case TCG_COND_LE:
c068896f 882 case TCG_COND_GE:
0f46c064 883 if (arg2 == 0) {
c068896f
RH		 884 b_opc = b_zero[cond];
885 arg2 = arg1;
886 arg1 = 0;
887 break;
0f46c064 888 }
c068896f
RH		 889 s_opc = OPC_SLT;
890 /* FALLTHRU */
891
892 case TCG_COND_LTU:
893 case TCG_COND_GTU:
afa05235 894 case TCG_COND_LEU:
c068896f
RH		 895 case TCG_COND_GEU:
896 cmp_map = mips_cmp_map[cond];
897 if (cmp_map & MIPS_CMP_SWAP) {
898 TCGReg t = arg1;
899 arg1 = arg2;
900 arg2 = t;
0f46c064 901 }
c068896f
RH		 902 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
903 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
904 arg1 = TCG_TMP0;
905 arg2 = TCG_REG_ZERO;
afa05235 906 break;
c068896f 907
afa05235
AJ		 908 default:
909 tcg_abort();
910 break;
911 }
c068896f
RH		 912
913 tcg_out_opc_br(s, b_opc, arg1, arg2);
91a7fd1f 914 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
afa05235
AJ		 915 tcg_out_nop(s);
916}
917
1db1c4d7
RH		 918static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
919 TCGReg al, TCGReg ah,
920 TCGReg bl, TCGReg bh)
921{
922 /* Merge highpart comparison into AH. */
923 if (bh != 0) {
924 if (ah != 0) {
925 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
926 ah = tmp0;
927 } else {
928 ah = bh;
929 }
930 }
931 /* Merge lowpart comparison into AL. */
932 if (bl != 0) {
933 if (al != 0) {
934 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
935 al = tmp1;
936 } else {
937 al = bl;
938 }
939 }
940 /* Merge high and low part comparisons into AL. */
941 if (ah != 0) {
942 if (al != 0) {
943 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
944 al = tmp0;
945 } else {
946 al = ah;
947 }
948 }
949 return al;
950}
951
9a2f0bfe
RH		 952static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
953 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
954{
955 TCGReg tmp0 = TCG_TMP0;
956 TCGReg tmp1 = ret;
957
eabb7b91 958 tcg_debug_assert(ret != TCG_TMP0);
9a2f0bfe 959 if (ret == ah || ret == bh) {
eabb7b91 960 tcg_debug_assert(ret != TCG_TMP1);
9a2f0bfe
RH		 961 tmp1 = TCG_TMP1;
962 }
963
964 switch (cond) {
965 case TCG_COND_EQ:
966 case TCG_COND_NE:
1db1c4d7
RH		 967 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
968 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
9a2f0bfe
RH		 969 break;
970
971 default:
972 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
973 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
974 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
975 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
976 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
977 break;
978 }
979}
980
3401fd25 981static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
bec16311 982 TCGReg bl, TCGReg bh, TCGLabel *l)
3401fd25
RH		 983{
984 TCGCond b_cond = TCG_COND_NE;
985 TCGReg tmp = TCG_TMP1;
986
987 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
988 With setcond, we emit between 3 and 10 insns and only 1 branch,
989 which ought to get better branch prediction. */
990 switch (cond) {
991 case TCG_COND_EQ:
992 case TCG_COND_NE:
993 b_cond = cond;
994 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
afa05235 995 break;
afa05235 996
afa05235 997 default:
5d831be2 998 /* Minimize code size by preferring a compare not requiring INV. */
3401fd25
RH		 999 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1000 cond = tcg_invert_cond(cond);
1001 b_cond = TCG_COND_EQ;
1002 }
1003 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
1004 break;
afa05235
AJ		 1005 }
1006
bec16311 1007 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
afa05235
AJ		 1008}
1009
7d7c4930 1010static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
137d6390 1011 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
7d7c4930 1012{
137d6390
JH		 1013 bool eqz = false;
1014
1015 /* If one of the values is zero, put it last to match SEL*Z instructions */
1016 if (use_mips32r6_instructions && v1 == 0) {
1017 v1 = v2;
1018 v2 = 0;
1019 cond = tcg_invert_cond(cond);
1020 }
33fac20b 1021
7d7c4930
AJ		 1022 switch (cond) {
1023 case TCG_COND_EQ:
137d6390 1024 eqz = true;
33fac20b 1025 /* FALLTHRU */
7d7c4930 1026 case TCG_COND_NE:
33fac20b 1027 if (c2 != 0) {
6c530e32 1028 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
33fac20b 1029 c1 = TCG_TMP0;
7d7c4930
AJ		 1030 }
1031 break;
33fac20b 1032
7d7c4930 1033 default:
5d831be2 1034 /* Minimize code size by preferring a compare not requiring INV. */
33fac20b
RH		 1035 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1036 cond = tcg_invert_cond(cond);
137d6390 1037 eqz = true;
33fac20b
RH		 1038 }
1039 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1040 c1 = TCG_TMP0;
7d7c4930
AJ		 1041 break;
1042 }
33fac20b 1043
137d6390
JH		 1044 if (use_mips32r6_instructions) {
1045 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1046 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1047
1048 if (v2 != 0) {
1049 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1050 }
1051 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1052 if (v2 != 0) {
1053 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1054 }
1055 } else {
1056 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1057
1058 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1059
1060 /* This should be guaranteed via constraints */
1061 tcg_debug_assert(v2 == ret);
1062 }
7d7c4930
AJ		 1063}
1064
2be7d76b 1065static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
9d8bf2d1
RH		 1066{
1067 /* Note that the ABI requires the called function's address to be
1068 loaded into T9, even if a direct branch is in range. */
1069 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1070
1071 /* But do try a direct branch, allowing the cpu better insn prefetch. */
ce0236cf
RH		 1072 if (tail) {
1073 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1074 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1075 }
1076 } else {
1077 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1078 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1079 }
9d8bf2d1 1080 }
ce0236cf 1081}
9d8bf2d1 1082
2be7d76b 1083static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
ce0236cf
RH		 1084{
1085 tcg_out_call_int(s, arg, false);
9d8bf2d1
RH		 1086 tcg_out_nop(s);
1087}
1088
afa05235 1089#if defined(CONFIG_SOFTMMU)
139c1837 1090#include "../tcg-ldst.c.inc"
659ef5cb 1091
ce0236cf
RH		 1092static void * const qemu_ld_helpers[16] = {
1093 [MO_UB] = helper_ret_ldub_mmu,
1094 [MO_SB] = helper_ret_ldsb_mmu,
1095 [MO_LEUW] = helper_le_lduw_mmu,
1096 [MO_LESW] = helper_le_ldsw_mmu,
1097 [MO_LEUL] = helper_le_ldul_mmu,
1098 [MO_LEQ] = helper_le_ldq_mmu,
1099 [MO_BEUW] = helper_be_lduw_mmu,
1100 [MO_BESW] = helper_be_ldsw_mmu,
1101 [MO_BEUL] = helper_be_ldul_mmu,
1102 [MO_BEQ] = helper_be_ldq_mmu,
f0d70331
JG		 1103#if TCG_TARGET_REG_BITS == 64
1104 [MO_LESL] = helper_le_ldsl_mmu,
1105 [MO_BESL] = helper_be_ldsl_mmu,
1106#endif
e141ab52
BS		 1107};
1108
ce0236cf
RH		 1109static void * const qemu_st_helpers[16] = {
1110 [MO_UB] = helper_ret_stb_mmu,
1111 [MO_LEUW] = helper_le_stw_mmu,
1112 [MO_LEUL] = helper_le_stl_mmu,
1113 [MO_LEQ] = helper_le_stq_mmu,
1114 [MO_BEUW] = helper_be_stw_mmu,
1115 [MO_BEUL] = helper_be_stl_mmu,
1116 [MO_BEQ] = helper_be_stq_mmu,
e141ab52 1117};
afa05235 1118
9d8bf2d1
RH		 1119/* Helper routines for marshalling helper function arguments into
1120 * the correct registers and stack.
1121 * I is where we want to put this argument, and is updated and returned
1122 * for the next call. ARG is the argument itself.
1123 *
1124 * We provide routines for arguments which are: immediate, 32 bit
1125 * value in register, 16 and 8 bit values in register (which must be zero
1126 * extended before use) and 64 bit value in a lo:hi register pair.
1127 */
1128
1129static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
afa05235 1130{
9d8bf2d1
RH		 1131 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1132 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1133 } else {
f0d70331
JG		 1134 /* For N32 and N64, the initial offset is different. But there
1135 we also have 8 argument register so we don't run out here. */
1136 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
9d8bf2d1
RH		 1137 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1138 }
1139 return i + 1;
1140}
afa05235 1141
9d8bf2d1
RH		 1142static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1143{
6c530e32 1144 TCGReg tmp = TCG_TMP0;
9d8bf2d1
RH		 1145 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1146 tmp = tcg_target_call_iarg_regs[i];
1147 }
1148 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
1149 return tcg_out_call_iarg_reg(s, i, tmp);
1150}
1151
1152static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1153{
6c530e32 1154 TCGReg tmp = TCG_TMP0;
9d8bf2d1
RH		 1155 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1156 tmp = tcg_target_call_iarg_regs[i];
1157 }
1158 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1159 return tcg_out_call_iarg_reg(s, i, tmp);
1160}
1161
1162static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1163{
6c530e32 1164 TCGReg tmp = TCG_TMP0;
9d8bf2d1
RH		 1165 if (arg == 0) {
1166 tmp = TCG_REG_ZERO;
afa05235 1167 } else {
9d8bf2d1
RH		 1168 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1169 tmp = tcg_target_call_iarg_regs[i];
1170 }
1171 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
afa05235 1172 }
9d8bf2d1
RH		 1173 return tcg_out_call_iarg_reg(s, i, tmp);
1174}
1175
1176static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1177{
f0d70331 1178 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
9d8bf2d1
RH		 1179 i = (i + 1) & ~1;
1180 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1181 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1182 return i;
1183}
1184
269bd5d8
RH		 1185/* We expect to use a 16-bit negative offset from ENV. */
1186QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1187QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1188
ac33373e
RH		 1189/*
1190 * Perform the tlb comparison operation.
1191 * The complete host address is placed in BASE.
1192 * Clobbers TMP0, TMP1, TMP2, TMP3.
1193 */
9d8bf2d1 1194static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
81dfaf1a 1195 TCGReg addrh, TCGMemOpIdx oi,
9d8bf2d1
RH		 1196 tcg_insn_unit *label_ptr[2], bool is_load)
1197{
14776ab5 1198 MemOp opc = get_memop(oi);
85aa8081
RH		 1199 unsigned s_bits = opc & MO_SIZE;
1200 unsigned a_bits = get_alignment_bits(opc);
81dfaf1a 1201 int mem_index = get_mmuidx(oi);
269bd5d8
RH		 1202 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1203 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1204 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
ac33373e
RH		 1205 int add_off = offsetof(CPUTLBEntry, addend);
1206 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
1207 : offsetof(CPUTLBEntry, addr_write));
ac33373e 1208 target_ulong mask;
9d8bf2d1 1209
ac33373e 1210 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
269bd5d8
RH		 1211 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1212 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
ac33373e
RH		 1213
1214 /* Extract the TLB index from the address into TMP3. */
1215 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
1216 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1217 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1218
1219 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1220 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1221
85aa8081
RH		 1222 /* We don't currently support unaligned accesses.
1223 We could do so with mips32r6. */
1224 if (a_bits < s_bits) {
1225 a_bits = s_bits;
1226 }
f0d70331 1227
ac33373e 1228 /* Mask the page bits, keeping the alignment bits to compare against. */
f0d70331
JG		 1229 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
1230
ac33373e 1231 /* Load the (low-half) tlb comparator. */
f0d70331 1232 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
ac33373e 1233 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
f0d70331
JG		 1234 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
1235 } else {
ac33373e
RH		 1236 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
1237 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1238 TCG_TMP0, TCG_TMP3, cmp_off);
f0d70331
JG		 1239 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
1240 /* No second compare is required here;
1241 load the tlb addend for the fast path. */
ac33373e 1242 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
5eb4f645 1243 }
6c530e32 1244 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
9d8bf2d1 1245
f0d70331
JG		 1246 /* Zero extend a 32-bit guest address for a 64-bit host. */
1247 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1248 tcg_out_ext32u(s, base, addrl);
1249 addrl = base;
1250 }
1251
9d8bf2d1 1252 label_ptr[0] = s->code_ptr;
6c530e32 1253 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
afa05235 1254
5eb4f645 1255 /* Load and test the high half tlb comparator. */
f0d70331 1256 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1 1257 /* delay slot */
ac33373e 1258 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
5eb4f645 1259
f0d70331 1260 /* Load the tlb addend for the fast path. */
ac33373e 1261 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
afa05235 1262
9d8bf2d1 1263 label_ptr[1] = s->code_ptr;
5eb4f645 1264 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
9d8bf2d1 1265 }
afa05235 1266
9d8bf2d1 1267 /* delay slot */
f0d70331 1268 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
9d8bf2d1 1269}
afa05235 1270
3972ef6f 1271static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
f0d70331 1272 TCGType ext,
9d8bf2d1
RH		 1273 TCGReg datalo, TCGReg datahi,
1274 TCGReg addrlo, TCGReg addrhi,
3972ef6f 1275 void *raddr, tcg_insn_unit *label_ptr[2])
9d8bf2d1
RH		 1276{
1277 TCGLabelQemuLdst *label = new_ldst_label(s);
1278
1279 label->is_ld = is_ld;
3972ef6f 1280 label->oi = oi;
f0d70331 1281 label->type = ext;
9d8bf2d1
RH		 1282 label->datalo_reg = datalo;
1283 label->datahi_reg = datahi;
1284 label->addrlo_reg = addrlo;
1285 label->addrhi_reg = addrhi;
df5af130
RH		 1286 /* TODO: Cast goes away when all hosts converted */
1287 label->raddr = (void *)tcg_splitwx_to_rx(raddr);
9d8bf2d1 1288 label->label_ptr[0] = label_ptr[0];
f0d70331 1289 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1
RH		 1290 label->label_ptr[1] = label_ptr[1];
1291 }
1292}
1293
aeee05f5 1294static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
9d8bf2d1 1295{
df5af130 1296 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
a8f13961 1297 TCGMemOpIdx oi = l->oi;
14776ab5 1298 MemOp opc = get_memop(oi);
ce0236cf 1299 TCGReg v0;
9d8bf2d1
RH		 1300 int i;
1301
1302 /* resolve label address */
df5af130 1303 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
91a7fd1f 1304 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
df5af130 1305 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
91a7fd1f 1306 return false;
9d8bf2d1
RH		 1307 }
1308
ce0236cf 1309 i = 1;
f0d70331 1310 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1
RH		 1311 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1312 } else {
1313 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1314 }
3972ef6f 1315 i = tcg_out_call_iarg_imm(s, i, oi);
ce0236cf 1316 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
2b7ec66f 1317 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
ce0236cf
RH		 1318 /* delay slot */
1319 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
9d8bf2d1 1320
ce0236cf 1321 v0 = l->datalo_reg;
f0d70331 1322 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
9d8bf2d1
RH		 1323 /* We eliminated V0 from the possible output registers, so it
1324 cannot be clobbered here. So we must move V1 first. */
ce0236cf
RH		 1325 if (MIPS_BE) {
1326 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1327 v0 = l->datahi_reg;
1328 } else {
1329 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1330 }
afa05235
AJ		 1331 }
1332
6d8ff4d8 1333 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
91a7fd1f
RH		 1334 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1335 return false;
1336 }
a31aa4ce 1337
ce0236cf 1338 /* delay slot */
f0d70331
JG		 1339 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1340 /* we always sign-extend 32-bit loads */
1341 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
1342 } else {
1343 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1344 }
aeee05f5 1345 return true;
9d8bf2d1 1346}
afa05235 1347
aeee05f5 1348static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
9d8bf2d1 1349{
df5af130 1350 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
a8f13961 1351 TCGMemOpIdx oi = l->oi;
14776ab5
TN		 1352 MemOp opc = get_memop(oi);
1353 MemOp s_bits = opc & MO_SIZE;
9d8bf2d1
RH		 1354 int i;
1355
1356 /* resolve label address */
df5af130 1357 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
91a7fd1f 1358 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
df5af130 1359 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
91a7fd1f 1360 return false;
9d8bf2d1 1361 }
afa05235 1362
ce0236cf 1363 i = 1;
f0d70331 1364 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1 1365 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
cc01cc8e 1366 } else {
9d8bf2d1
RH		 1367 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1368 }
1369 switch (s_bits) {
1370 case MO_8:
1371 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1372 break;
1373 case MO_16:
1374 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1375 break;
1376 case MO_32:
1377 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1378 break;
1379 case MO_64:
f0d70331
JG		 1380 if (TCG_TARGET_REG_BITS == 32) {
1381 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1382 } else {
1383 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1384 }
9d8bf2d1
RH		 1385 break;
1386 default:
1387 tcg_abort();
cc01cc8e 1388 }
3972ef6f 1389 i = tcg_out_call_iarg_imm(s, i, oi);
9d8bf2d1 1390
ce0236cf
RH		 1391 /* Tail call to the store helper. Thus force the return address
1392 computation to take place in the return address register. */
1393 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1394 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
2b7ec66f 1395 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
ce0236cf
RH		 1396 /* delay slot */
1397 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
aeee05f5 1398 return true;
9d8bf2d1 1399}
afa05235
AJ		 1400#endif
1401
bb08afe9 1402static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
14776ab5 1403 TCGReg base, MemOp opc, bool is_64)
9d8bf2d1 1404{
4214a8cb 1405 switch (opc & (MO_SSIZE | MO_BSWAP)) {
9d8bf2d1 1406 case MO_UB:
bb08afe9 1407 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
afa05235 1408 break;
9d8bf2d1 1409 case MO_SB:
bb08afe9 1410 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
afa05235 1411 break;
9d8bf2d1 1412 case MO_UW | MO_BSWAP:
6c530e32 1413 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
bb08afe9 1414 tcg_out_bswap16(s, lo, TCG_TMP1);
afa05235 1415 break;
9d8bf2d1 1416 case MO_UW:
bb08afe9 1417 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
afa05235 1418 break;
9d8bf2d1 1419 case MO_SW | MO_BSWAP:
6c530e32 1420 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
bb08afe9 1421 tcg_out_bswap16s(s, lo, TCG_TMP1);
afa05235 1422 break;
9d8bf2d1 1423 case MO_SW:
bb08afe9 1424 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
9d8bf2d1
RH		 1425 break;
1426 case MO_UL | MO_BSWAP:
f0d70331
JG		 1427 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1428 if (use_mips32r2_instructions) {
1429 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1430 tcg_out_bswap32u(s, lo, lo);
1431 } else {
1432 tcg_out_bswap_subr(s, bswap32u_addr);
1433 /* delay slot */
1434 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1435 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1436 }
1437 break;
1438 }
1439 /* FALLTHRU */
1440 case MO_SL | MO_BSWAP:
bb08afe9
JG		 1441 if (use_mips32r2_instructions) {
1442 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1443 tcg_out_bswap32(s, lo, lo);
1444 } else {
1445 tcg_out_bswap_subr(s, bswap32_addr);
1446 /* delay slot */
1447 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1448 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1449 }
9d8bf2d1
RH		 1450 break;
1451 case MO_UL:
f0d70331
JG		 1452 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1453 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1454 break;
1455 }
1456 /* FALLTHRU */
1457 case MO_SL:
bb08afe9 1458 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
9d8bf2d1
RH		 1459 break;
1460 case MO_Q | MO_BSWAP:
f0d70331
JG		 1461 if (TCG_TARGET_REG_BITS == 64) {
1462 if (use_mips32r2_instructions) {
1463 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1464 tcg_out_bswap64(s, lo, lo);
1465 } else {
1466 tcg_out_bswap_subr(s, bswap64_addr);
1467 /* delay slot */
1468 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1469 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1470 }
1471 } else if (use_mips32r2_instructions) {
bb08afe9
JG		 1472 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1473 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1474 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1475 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1476 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1477 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1478 } else {
1479 tcg_out_bswap_subr(s, bswap32_addr);
1480 /* delay slot */
1481 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1482 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1483 tcg_out_bswap_subr(s, bswap32_addr);
1484 /* delay slot */
1485 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1486 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1487 }
9d8bf2d1
RH		 1488 break;
1489 case MO_Q:
bb08afe9 1490 /* Prefer to load from offset 0 first, but allow for overlap. */
f0d70331
JG		 1491 if (TCG_TARGET_REG_BITS == 64) {
1492 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1493 } else if (MIPS_BE ? hi != base : lo == base) {
bb08afe9
JG		 1494 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1495 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1496 } else {
1497 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1498 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1499 }
afa05235
AJ		 1500 break;
1501 default:
1502 tcg_abort();
1503 }
afa05235
AJ		 1504}
1505
fbef2cc8 1506static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
afa05235 1507{
9d8bf2d1
RH		 1508 TCGReg addr_regl, addr_regh __attribute__((unused));
1509 TCGReg data_regl, data_regh;
59227d5d 1510 TCGMemOpIdx oi;
14776ab5 1511 MemOp opc;
afa05235 1512#if defined(CONFIG_SOFTMMU)
9d8bf2d1 1513 tcg_insn_unit *label_ptr[2];
afa05235 1514#endif
bb08afe9 1515 TCGReg base = TCG_REG_A0;
9d8bf2d1 1516
afa05235 1517 data_regl = *args++;
f0d70331 1518 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
afa05235 1519 addr_regl = *args++;
f0d70331 1520 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1521 oi = *args++;
1522 opc = get_memop(oi);
9d8bf2d1 1523
0834c9ea 1524#if defined(CONFIG_SOFTMMU)
81dfaf1a 1525 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
f0d70331
JG		 1526 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1527 add_qemu_ldst_label(s, 1, oi,
1528 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1529 data_regl, data_regh, addr_regl, addr_regh,
3972ef6f 1530 s->code_ptr, label_ptr);
0834c9ea 1531#else
f0d70331
JG		 1532 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1533 tcg_out_ext32u(s, base, addr_regl);
1534 addr_regl = base;
1535 }
b76f21a7 1536 if (guest_base == 0 && data_regl != addr_regl) {
9d8bf2d1 1537 base = addr_regl;
b76f21a7 1538 } else if (guest_base == (int16_t)guest_base) {
f0d70331 1539 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
0834c9ea 1540 } else {
4df9cac5 1541 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
0834c9ea 1542 }
f0d70331 1543 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
9d8bf2d1
RH		 1544#endif
1545}
afa05235 1546
bb08afe9 1547static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
14776ab5 1548 TCGReg base, MemOp opc)
9d8bf2d1 1549{
bb08afe9
JG		 1550 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1551 if ((lo | hi) == 0) {
1552 opc &= ~MO_BSWAP;
1553 }
1554
4214a8cb 1555 switch (opc & (MO_SIZE | MO_BSWAP)) {
9d8bf2d1 1556 case MO_8:
bb08afe9 1557 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
9d8bf2d1 1558 break;
afa05235 1559
9d8bf2d1 1560 case MO_16 | MO_BSWAP:
bb08afe9 1561 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
6c530e32 1562 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
bb08afe9 1563 lo = TCG_TMP1;
9d8bf2d1
RH		 1564 /* FALLTHRU */
1565 case MO_16:
bb08afe9 1566 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
afa05235 1567 break;
9d8bf2d1
RH		 1568
1569 case MO_32 | MO_BSWAP:
bb08afe9
JG		 1570 tcg_out_bswap32(s, TCG_TMP3, lo);
1571 lo = TCG_TMP3;
9d8bf2d1
RH		 1572 /* FALLTHRU */
1573 case MO_32:
bb08afe9 1574 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
afa05235 1575 break;
9d8bf2d1
RH		 1576
1577 case MO_64 | MO_BSWAP:
f0d70331
JG		 1578 if (TCG_TARGET_REG_BITS == 64) {
1579 tcg_out_bswap64(s, TCG_TMP3, lo);
1580 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1581 } else if (use_mips32r2_instructions) {
bb08afe9
JG		 1582 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1583 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1584 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1585 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1586 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1587 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1588 } else {
1589 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
1590 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1591 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
1592 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1593 }
afa05235 1594 break;
9d8bf2d1 1595 case MO_64:
f0d70331
JG		 1596 if (TCG_TARGET_REG_BITS == 64) {
1597 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1598 } else {
1599 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1600 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1601 }
afa05235 1602 break;
9d8bf2d1 1603
afa05235
AJ		 1604 default:
1605 tcg_abort();
1606 }
9d8bf2d1 1607}
afa05235 1608
fbef2cc8 1609static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
9d8bf2d1
RH		 1610{
1611 TCGReg addr_regl, addr_regh __attribute__((unused));
bb08afe9 1612 TCGReg data_regl, data_regh;
59227d5d 1613 TCGMemOpIdx oi;
14776ab5 1614 MemOp opc;
9d8bf2d1
RH		 1615#if defined(CONFIG_SOFTMMU)
1616 tcg_insn_unit *label_ptr[2];
9d8bf2d1 1617#endif
bb08afe9 1618 TCGReg base = TCG_REG_A0;
9d8bf2d1
RH		 1619
1620 data_regl = *args++;
f0d70331 1621 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
9d8bf2d1 1622 addr_regl = *args++;
f0d70331 1623 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1624 oi = *args++;
1625 opc = get_memop(oi);
afa05235 1626
9d8bf2d1 1627#if defined(CONFIG_SOFTMMU)
81dfaf1a 1628 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
9d8bf2d1 1629 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
f0d70331
JG		 1630 add_qemu_ldst_label(s, 0, oi,
1631 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1632 data_regl, data_regh, addr_regl, addr_regh,
3972ef6f 1633 s->code_ptr, label_ptr);
cc01cc8e 1634#else
f0d70331
JG		 1635 base = TCG_REG_A0;
1636 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1637 tcg_out_ext32u(s, base, addr_regl);
1638 addr_regl = base;
1639 }
b76f21a7 1640 if (guest_base == 0) {
9d8bf2d1 1641 base = addr_regl;
f0d70331
JG		 1642 } else if (guest_base == (int16_t)guest_base) {
1643 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
cc01cc8e 1644 } else {
4df9cac5 1645 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
afa05235 1646 }
9d8bf2d1 1647 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
afa05235
AJ		 1648#endif
1649}
1650
6f0b9910
PK		 1651static void tcg_out_mb(TCGContext *s, TCGArg a0)
1652{
1653 static const MIPSInsn sync[] = {
1654 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1655 as the former is an ordering barrier and the latter
1656 is a completion barrier. */
1657 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1658 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1659 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1660 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1661 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1662 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1663 };
1664 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1665}
1666
2a1d9d41
RH		 1667static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1668 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1669{
1670 if (use_mips32r6_instructions) {
1671 if (a2 == width) {
1672 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1673 } else {
1674 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1675 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1676 }
1677 } else {
1678 if (a2 == width) {
1679 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1680 } else if (a0 == a2) {
1681 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1682 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1683 } else if (a0 != a1) {
1684 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1685 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1686 } else {
1687 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1688 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1689 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1690 }
1691 }
1692}
1693
a9751609 1694static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
afa05235
AJ		 1695 const TCGArg *args, const int *const_args)
1696{
4f048535 1697 MIPSInsn i1, i2;
22ee3a98
RH		 1698 TCGArg a0, a1, a2;
1699 int c2;
1700
1701 a0 = args[0];
1702 a1 = args[1];
1703 a2 = args[2];
1704 c2 = const_args[2];
1705
1706 switch (opc) {
afa05235 1707 case INDEX_op_exit_tb:
7dae901d 1708 {
7dae901d
RH		 1709 TCGReg b0 = TCG_REG_ZERO;
1710
0119b192 1711 a0 = (intptr_t)a0;
7dae901d
RH		 1712 if (a0 & ~0xffff) {
1713 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1714 b0 = TCG_REG_V0;
1715 }
1716 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
6c530e32 1717 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
7dae901d 1718 (uintptr_t)tb_ret_addr);
6c530e32 1719 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
7dae901d
RH		 1720 }
1721 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
f8c9eddb 1722 }
afa05235
AJ		 1723 break;
1724 case INDEX_op_goto_tb:
f309101c 1725 if (s->tb_jmp_insn_offset) {
afa05235 1726 /* direct jump method */
f309101c 1727 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
b6bfeea9
RH		 1728 /* Avoid clobbering the address during retranslation. */
1729 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
afa05235
AJ		 1730 } else {
1731 /* indirect jump method */
6c530e32 1732 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
f309101c 1733 (uintptr_t)(s->tb_jmp_target_addr + a0));
6c530e32 1734 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
afa05235
AJ		 1735 }
1736 tcg_out_nop(s);
9f754620 1737 set_jmp_reset_offset(s, a0);
afa05235 1738 break;
5786e068
AJ		 1739 case INDEX_op_goto_ptr:
1740 /* jmp to the given host address (could be epilogue) */
1741 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1742 tcg_out_nop(s);
1743 break;
afa05235 1744 case INDEX_op_br:
bec16311
RH		 1745 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1746 arg_label(a0));
afa05235
AJ		 1747 break;
1748
afa05235 1749 case INDEX_op_ld8u_i32:
0119b192 1750 case INDEX_op_ld8u_i64:
4f048535
RH		 1751 i1 = OPC_LBU;
1752 goto do_ldst;
afa05235 1753 case INDEX_op_ld8s_i32:
0119b192 1754 case INDEX_op_ld8s_i64:
4f048535
RH		 1755 i1 = OPC_LB;
1756 goto do_ldst;
afa05235 1757 case INDEX_op_ld16u_i32:
0119b192 1758 case INDEX_op_ld16u_i64:
4f048535
RH		 1759 i1 = OPC_LHU;
1760 goto do_ldst;
afa05235 1761 case INDEX_op_ld16s_i32:
0119b192 1762 case INDEX_op_ld16s_i64:
4f048535
RH		 1763 i1 = OPC_LH;
1764 goto do_ldst;
afa05235 1765 case INDEX_op_ld_i32:
0119b192 1766 case INDEX_op_ld32s_i64:
4f048535
RH		 1767 i1 = OPC_LW;
1768 goto do_ldst;
0119b192
JG		 1769 case INDEX_op_ld32u_i64:
1770 i1 = OPC_LWU;
1771 goto do_ldst;
1772 case INDEX_op_ld_i64:
1773 i1 = OPC_LD;
1774 goto do_ldst;
afa05235 1775 case INDEX_op_st8_i32:
0119b192 1776 case INDEX_op_st8_i64:
4f048535
RH		 1777 i1 = OPC_SB;
1778 goto do_ldst;
afa05235 1779 case INDEX_op_st16_i32:
0119b192 1780 case INDEX_op_st16_i64:
4f048535
RH		 1781 i1 = OPC_SH;
1782 goto do_ldst;
afa05235 1783 case INDEX_op_st_i32:
0119b192 1784 case INDEX_op_st32_i64:
4f048535 1785 i1 = OPC_SW;
0119b192
JG		 1786 goto do_ldst;
1787 case INDEX_op_st_i64:
1788 i1 = OPC_SD;
4f048535
RH		 1789 do_ldst:
1790 tcg_out_ldst(s, i1, a0, a1, a2);
afa05235
AJ		 1791 break;
1792
1793 case INDEX_op_add_i32:
4f048535
RH		 1794 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1795 goto do_binary;
0119b192
JG		 1796 case INDEX_op_add_i64:
1797 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1798 goto do_binary;
4f048535 1799 case INDEX_op_or_i32:
0119b192 1800 case INDEX_op_or_i64:
4f048535
RH		 1801 i1 = OPC_OR, i2 = OPC_ORI;
1802 goto do_binary;
1803 case INDEX_op_xor_i32:
0119b192 1804 case INDEX_op_xor_i64:
4f048535
RH		 1805 i1 = OPC_XOR, i2 = OPC_XORI;
1806 do_binary:
22ee3a98 1807 if (c2) {
4f048535
RH		 1808 tcg_out_opc_imm(s, i2, a0, a1, a2);
1809 break;
afa05235 1810 }
4f048535
RH		 1811 do_binaryv:
1812 tcg_out_opc_reg(s, i1, a0, a1, a2);
afa05235 1813 break;
4f048535 1814
afa05235 1815 case INDEX_op_sub_i32:
0119b192
JG		 1816 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1817 goto do_subtract;
1818 case INDEX_op_sub_i64:
1819 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1820 do_subtract:
22ee3a98 1821 if (c2) {
0119b192 1822 tcg_out_opc_imm(s, i2, a0, a1, -a2);
4f048535 1823 break;
afa05235 1824 }
0119b192 1825 goto do_binaryv;
4f048535
RH		 1826 case INDEX_op_and_i32:
1827 if (c2 && a2 != (uint16_t)a2) {
1828 int msb = ctz32(~a2) - 1;
eabb7b91
AJ		 1829 tcg_debug_assert(use_mips32r2_instructions);
1830 tcg_debug_assert(is_p2m1(a2));
4f048535
RH		 1831 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1832 break;
1833 }
1834 i1 = OPC_AND, i2 = OPC_ANDI;
1835 goto do_binary;
0119b192
JG		 1836 case INDEX_op_and_i64:
1837 if (c2 && a2 != (uint16_t)a2) {
1838 int msb = ctz64(~a2) - 1;
1839 tcg_debug_assert(use_mips32r2_instructions);
1840 tcg_debug_assert(is_p2m1(a2));
1841 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1842 break;
1843 }
1844 i1 = OPC_AND, i2 = OPC_ANDI;
1845 goto do_binary;
4f048535 1846 case INDEX_op_nor_i32:
0119b192 1847 case INDEX_op_nor_i64:
4f048535
RH		 1848 i1 = OPC_NOR;
1849 goto do_binaryv;
1850
afa05235 1851 case INDEX_op_mul_i32:
988902fc 1852 if (use_mips32_instructions) {
22ee3a98 1853 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
4f048535 1854 break;
988902fc 1855 }
4f048535
RH		 1856 i1 = OPC_MULT, i2 = OPC_MFLO;
1857 goto do_hilo1;
3c9a8f17 1858 case INDEX_op_mulsh_i32:
bc6d0c22
JH		 1859 if (use_mips32r6_instructions) {
1860 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1861 break;
1862 }
4f048535
RH		 1863 i1 = OPC_MULT, i2 = OPC_MFHI;
1864 goto do_hilo1;
3c9a8f17 1865 case INDEX_op_muluh_i32:
bc6d0c22
JH		 1866 if (use_mips32r6_instructions) {
1867 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1868 break;
1869 }
4f048535
RH		 1870 i1 = OPC_MULTU, i2 = OPC_MFHI;
1871 goto do_hilo1;
afa05235 1872 case INDEX_op_div_i32:
bc6d0c22
JH		 1873 if (use_mips32r6_instructions) {
1874 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1875 break;
1876 }
4f048535
RH		 1877 i1 = OPC_DIV, i2 = OPC_MFLO;
1878 goto do_hilo1;
afa05235 1879 case INDEX_op_divu_i32:
bc6d0c22
JH		 1880 if (use_mips32r6_instructions) {
1881 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1882 break;
1883 }
4f048535
RH		 1884 i1 = OPC_DIVU, i2 = OPC_MFLO;
1885 goto do_hilo1;
afa05235 1886 case INDEX_op_rem_i32:
bc6d0c22
JH		 1887 if (use_mips32r6_instructions) {
1888 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1889 break;
1890 }
4f048535
RH		 1891 i1 = OPC_DIV, i2 = OPC_MFHI;
1892 goto do_hilo1;
afa05235 1893 case INDEX_op_remu_i32:
bc6d0c22
JH		 1894 if (use_mips32r6_instructions) {
1895 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1896 break;
1897 }
4f048535 1898 i1 = OPC_DIVU, i2 = OPC_MFHI;
0119b192
JG		 1899 goto do_hilo1;
1900 case INDEX_op_mul_i64:
1901 if (use_mips32r6_instructions) {
1902 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1903 break;
1904 }
1905 i1 = OPC_DMULT, i2 = OPC_MFLO;
1906 goto do_hilo1;
1907 case INDEX_op_mulsh_i64:
1908 if (use_mips32r6_instructions) {
1909 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1910 break;
1911 }
1912 i1 = OPC_DMULT, i2 = OPC_MFHI;
1913 goto do_hilo1;
1914 case INDEX_op_muluh_i64:
1915 if (use_mips32r6_instructions) {
1916 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1917 break;
1918 }
1919 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1920 goto do_hilo1;
1921 case INDEX_op_div_i64:
1922 if (use_mips32r6_instructions) {
1923 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1924 break;
1925 }
1926 i1 = OPC_DDIV, i2 = OPC_MFLO;
1927 goto do_hilo1;
1928 case INDEX_op_divu_i64:
1929 if (use_mips32r6_instructions) {
1930 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1931 break;
1932 }
1933 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1934 goto do_hilo1;
1935 case INDEX_op_rem_i64:
1936 if (use_mips32r6_instructions) {
1937 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1938 break;
1939 }
1940 i1 = OPC_DDIV, i2 = OPC_MFHI;
1941 goto do_hilo1;
1942 case INDEX_op_remu_i64:
1943 if (use_mips32r6_instructions) {
1944 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1945 break;
1946 }
1947 i1 = OPC_DDIVU, i2 = OPC_MFHI;
4f048535
RH		 1948 do_hilo1:
1949 tcg_out_opc_reg(s, i1, 0, a1, a2);
1950 tcg_out_opc_reg(s, i2, a0, 0, 0);
afa05235
AJ		 1951 break;
1952
4f048535
RH		 1953 case INDEX_op_muls2_i32:
1954 i1 = OPC_MULT;
1955 goto do_hilo2;
1956 case INDEX_op_mulu2_i32:
1957 i1 = OPC_MULTU;
0119b192
JG		 1958 goto do_hilo2;
1959 case INDEX_op_muls2_i64:
1960 i1 = OPC_DMULT;
1961 goto do_hilo2;
1962 case INDEX_op_mulu2_i64:
1963 i1 = OPC_DMULTU;
4f048535
RH		 1964 do_hilo2:
1965 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1966 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1967 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
2b79487a 1968 break;
4f048535 1969
afa05235 1970 case INDEX_op_not_i32:
0119b192 1971 case INDEX_op_not_i64:
4f048535
RH		 1972 i1 = OPC_NOR;
1973 goto do_unary;
1974 case INDEX_op_bswap16_i32:
0119b192 1975 case INDEX_op_bswap16_i64:
4f048535
RH		 1976 i1 = OPC_WSBH;
1977 goto do_unary;
1978 case INDEX_op_ext8s_i32:
0119b192 1979 case INDEX_op_ext8s_i64:
4f048535
RH		 1980 i1 = OPC_SEB;
1981 goto do_unary;
1982 case INDEX_op_ext16s_i32:
0119b192 1983 case INDEX_op_ext16s_i64:
4f048535
RH		 1984 i1 = OPC_SEH;
1985 do_unary:
1986 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
afa05235
AJ		 1987 break;
1988
0119b192
JG		 1989 case INDEX_op_bswap32_i32:
1990 tcg_out_bswap32(s, a0, a1);
1991 break;
1992 case INDEX_op_bswap32_i64:
1993 tcg_out_bswap32u(s, a0, a1);
1994 break;
1995 case INDEX_op_bswap64_i64:
1996 tcg_out_bswap64(s, a0, a1);
1997 break;
1998 case INDEX_op_extrh_i64_i32:
1999 tcg_out_dsra(s, a0, a1, 32);
2000 break;
2001 case INDEX_op_ext32s_i64:
2002 case INDEX_op_ext_i32_i64:
2003 case INDEX_op_extrl_i64_i32:
2004 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
2005 break;
2006 case INDEX_op_ext32u_i64:
2007 case INDEX_op_extu_i32_i64:
2008 tcg_out_ext32u(s, a0, a1);
2009 break;
2010
afa05235 2011 case INDEX_op_sar_i32:
4f048535
RH		 2012 i1 = OPC_SRAV, i2 = OPC_SRA;
2013 goto do_shift;
afa05235 2014 case INDEX_op_shl_i32:
4f048535
RH		 2015 i1 = OPC_SLLV, i2 = OPC_SLL;
2016 goto do_shift;
afa05235 2017 case INDEX_op_shr_i32:
4f048535
RH		 2018 i1 = OPC_SRLV, i2 = OPC_SRL;
2019 goto do_shift;
2020 case INDEX_op_rotr_i32:
2021 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2022 do_shift:
22ee3a98 2023 if (c2) {
4f048535 2024 tcg_out_opc_sa(s, i2, a0, a1, a2);
0119b192 2025 break;
afa05235 2026 }
0119b192
JG		 2027 do_shiftv:
2028 tcg_out_opc_reg(s, i1, a0, a2, a1);
afa05235 2029 break;
9a152519 2030 case INDEX_op_rotl_i32:
22ee3a98
RH		 2031 if (c2) {
2032 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
9a152519 2033 } else {
22ee3a98
RH		 2034 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2035 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
9a152519
AJ		 2036 }
2037 break;
0119b192
JG		 2038 case INDEX_op_sar_i64:
2039 if (c2) {
2040 tcg_out_dsra(s, a0, a1, a2);
2041 break;
2042 }
2043 i1 = OPC_DSRAV;
2044 goto do_shiftv;
2045 case INDEX_op_shl_i64:
2046 if (c2) {
2047 tcg_out_dsll(s, a0, a1, a2);
2048 break;
2049 }
2050 i1 = OPC_DSLLV;
2051 goto do_shiftv;
2052 case INDEX_op_shr_i64:
2053 if (c2) {
2054 tcg_out_dsrl(s, a0, a1, a2);
2055 break;
2056 }
2057 i1 = OPC_DSRLV;
2058 goto do_shiftv;
2059 case INDEX_op_rotr_i64:
2060 if (c2) {
2061 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2062 break;
2063 }
2064 i1 = OPC_DROTRV;
2065 goto do_shiftv;
2066 case INDEX_op_rotl_i64:
2067 if (c2) {
2068 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2069 } else {
2070 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2071 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2072 }
c1cf85c9
AJ		 2073 break;
2074
2a1d9d41
RH		 2075 case INDEX_op_clz_i32:
2076 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2077 break;
2078 case INDEX_op_clz_i64:
2079 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2080 break;
2081
04f71aa3 2082 case INDEX_op_deposit_i32:
22ee3a98 2083 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
04f71aa3 2084 break;
0119b192
JG		 2085 case INDEX_op_deposit_i64:
2086 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2087 args[3] + args[4] - 1, args[3]);
2088 break;
befbb3ce 2089 case INDEX_op_extract_i32:
2f5a5f57 2090 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
befbb3ce
RH		 2091 break;
2092 case INDEX_op_extract_i64:
2093 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2f5a5f57 2094 args[3] - 1, a2);
befbb3ce 2095 break;
04f71aa3 2096
afa05235 2097 case INDEX_op_brcond_i32:
0119b192 2098 case INDEX_op_brcond_i64:
bec16311 2099 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
afa05235
AJ		 2100 break;
2101 case INDEX_op_brcond2_i32:
bec16311 2102 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
afa05235
AJ		 2103 break;
2104
7d7c4930 2105 case INDEX_op_movcond_i32:
0119b192 2106 case INDEX_op_movcond_i64:
137d6390 2107 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
7d7c4930
AJ		 2108 break;
2109
4cb26382 2110 case INDEX_op_setcond_i32:
0119b192 2111 case INDEX_op_setcond_i64:
22ee3a98 2112 tcg_out_setcond(s, args[3], a0, a1, a2);
4cb26382 2113 break;
434254aa 2114 case INDEX_op_setcond2_i32:
22ee3a98 2115 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
434254aa 2116 break;
4cb26382 2117
fbef2cc8
RH		 2118 case INDEX_op_qemu_ld_i32:
2119 tcg_out_qemu_ld(s, args, false);
afa05235 2120 break;
fbef2cc8
RH		 2121 case INDEX_op_qemu_ld_i64:
2122 tcg_out_qemu_ld(s, args, true);
afa05235 2123 break;
fbef2cc8
RH		 2124 case INDEX_op_qemu_st_i32:
2125 tcg_out_qemu_st(s, args, false);
afa05235 2126 break;
fbef2cc8
RH		 2127 case INDEX_op_qemu_st_i64:
2128 tcg_out_qemu_st(s, args, true);
afa05235
AJ		 2129 break;
2130
741f117d
RH		 2131 case INDEX_op_add2_i32:
2132 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2133 const_args[4], const_args[5], false);
2134 break;
2135 case INDEX_op_sub2_i32:
2136 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2137 const_args[4], const_args[5], true);
2138 break;
2139
6f0b9910
PK		 2140 case INDEX_op_mb:
2141 tcg_out_mb(s, a0);
2142 break;
96d0ee7f 2143 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
0119b192 2144 case INDEX_op_mov_i64:
96d0ee7f 2145 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
0119b192 2146 case INDEX_op_movi_i64:
96d0ee7f 2147 case INDEX_op_call: /* Always emitted via tcg_out_call. */
afa05235
AJ		 2148 default:
2149 tcg_abort();
2150 }
2151}
2152
89b2e37e
RH		 2153static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2154{
2155 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2156 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2157 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2158 static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
2159 static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
2160 static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
2161 static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
2162 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
2163 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2164 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2165 static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
2166 static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
2167 static const TCGTargetOpDef SZ_SZ_S
2168 = { .args_ct_str = { "SZ", "SZ", "S" } };
2169 static const TCGTargetOpDef SZ_SZ_S_S
2170 = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
2171 static const TCGTargetOpDef r_rZ_rN
2172 = { .args_ct_str = { "r", "rZ", "rN" } };
2173 static const TCGTargetOpDef r_rZ_rZ
2174 = { .args_ct_str = { "r", "rZ", "rZ" } };
2175 static const TCGTargetOpDef r_r_rIK
2176 = { .args_ct_str = { "r", "r", "rIK" } };
2177 static const TCGTargetOpDef r_r_rWZ
2178 = { .args_ct_str = { "r", "r", "rWZ" } };
2179 static const TCGTargetOpDef r_r_r_r
2180 = { .args_ct_str = { "r", "r", "r", "r" } };
2181 static const TCGTargetOpDef r_r_L_L
2182 = { .args_ct_str = { "r", "r", "L", "L" } };
2183 static const TCGTargetOpDef dep
2184 = { .args_ct_str = { "r", "0", "rZ" } };
2185 static const TCGTargetOpDef movc
2186 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
2187 static const TCGTargetOpDef movc_r6
2188 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2189 static const TCGTargetOpDef add2
2190 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
2191 static const TCGTargetOpDef br2
2192 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
2193 static const TCGTargetOpDef setc2
2194 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2195
2196 switch (op) {
2197 case INDEX_op_goto_ptr:
2198 return &r;
afa05235 2199
89b2e37e
RH		 2200 case INDEX_op_ld8u_i32:
2201 case INDEX_op_ld8s_i32:
2202 case INDEX_op_ld16u_i32:
2203 case INDEX_op_ld16s_i32:
2204 case INDEX_op_ld_i32:
2205 case INDEX_op_not_i32:
2206 case INDEX_op_bswap16_i32:
2207 case INDEX_op_bswap32_i32:
2208 case INDEX_op_ext8s_i32:
2209 case INDEX_op_ext16s_i32:
2210 case INDEX_op_extract_i32:
2211 case INDEX_op_ld8u_i64:
2212 case INDEX_op_ld8s_i64:
2213 case INDEX_op_ld16u_i64:
2214 case INDEX_op_ld16s_i64:
2215 case INDEX_op_ld32s_i64:
2216 case INDEX_op_ld32u_i64:
2217 case INDEX_op_ld_i64:
2218 case INDEX_op_not_i64:
2219 case INDEX_op_bswap16_i64:
2220 case INDEX_op_bswap32_i64:
2221 case INDEX_op_bswap64_i64:
2222 case INDEX_op_ext8s_i64:
2223 case INDEX_op_ext16s_i64:
2224 case INDEX_op_ext32s_i64:
2225 case INDEX_op_ext32u_i64:
2226 case INDEX_op_ext_i32_i64:
2227 case INDEX_op_extu_i32_i64:
2228 case INDEX_op_extrl_i64_i32:
2229 case INDEX_op_extrh_i64_i32:
2230 case INDEX_op_extract_i64:
2231 return &r_r;
afa05235 2232
89b2e37e
RH		 2233 case INDEX_op_st8_i32:
2234 case INDEX_op_st16_i32:
2235 case INDEX_op_st_i32:
2236 case INDEX_op_st8_i64:
2237 case INDEX_op_st16_i64:
2238 case INDEX_op_st32_i64:
2239 case INDEX_op_st_i64:
2240 return &rZ_r;
6f0b9910 2241
89b2e37e
RH		 2242 case INDEX_op_add_i32:
2243 case INDEX_op_add_i64:
2244 return &r_r_rJ;
2245 case INDEX_op_sub_i32:
2246 case INDEX_op_sub_i64:
2247 return &r_rZ_rN;
2248 case INDEX_op_mul_i32:
2249 case INDEX_op_mulsh_i32:
2250 case INDEX_op_muluh_i32:
2251 case INDEX_op_div_i32:
2252 case INDEX_op_divu_i32:
2253 case INDEX_op_rem_i32:
2254 case INDEX_op_remu_i32:
2255 case INDEX_op_nor_i32:
2256 case INDEX_op_setcond_i32:
2257 case INDEX_op_mul_i64:
2258 case INDEX_op_mulsh_i64:
2259 case INDEX_op_muluh_i64:
2260 case INDEX_op_div_i64:
2261 case INDEX_op_divu_i64:
2262 case INDEX_op_rem_i64:
2263 case INDEX_op_remu_i64:
2264 case INDEX_op_nor_i64:
2265 case INDEX_op_setcond_i64:
2266 return &r_rZ_rZ;
2267 case INDEX_op_muls2_i32:
2268 case INDEX_op_mulu2_i32:
2269 case INDEX_op_muls2_i64:
2270 case INDEX_op_mulu2_i64:
2271 return &r_r_r_r;
2272 case INDEX_op_and_i32:
2273 case INDEX_op_and_i64:
2274 return &r_r_rIK;
2275 case INDEX_op_or_i32:
2276 case INDEX_op_xor_i32:
2277 case INDEX_op_or_i64:
2278 case INDEX_op_xor_i64:
2279 return &r_r_rI;
2280 case INDEX_op_shl_i32:
2281 case INDEX_op_shr_i32:
2282 case INDEX_op_sar_i32:
2283 case INDEX_op_rotr_i32:
2284 case INDEX_op_rotl_i32:
2285 case INDEX_op_shl_i64:
2286 case INDEX_op_shr_i64:
2287 case INDEX_op_sar_i64:
2288 case INDEX_op_rotr_i64:
2289 case INDEX_op_rotl_i64:
2290 return &r_r_ri;
2291 case INDEX_op_clz_i32:
2292 case INDEX_op_clz_i64:
2293 return &r_r_rWZ;
afa05235 2294
89b2e37e
RH		 2295 case INDEX_op_deposit_i32:
2296 case INDEX_op_deposit_i64:
2297 return &dep;
2298 case INDEX_op_brcond_i32:
2299 case INDEX_op_brcond_i64:
2300 return &rZ_rZ;
2301 case INDEX_op_movcond_i32:
2302 case INDEX_op_movcond_i64:
2303 return use_mips32r6_instructions ? &movc_r6 : &movc;
f69d277e 2304
89b2e37e
RH		 2305 case INDEX_op_add2_i32:
2306 case INDEX_op_sub2_i32:
2307 return &add2;
2308 case INDEX_op_setcond2_i32:
2309 return &setc2;
2310 case INDEX_op_brcond2_i32:
2311 return &br2;
2312
2313 case INDEX_op_qemu_ld_i32:
2314 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2315 ? &r_L : &r_L_L);
2316 case INDEX_op_qemu_st_i32:
2317 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2318 ? &SZ_S : &SZ_S_S);
2319 case INDEX_op_qemu_ld_i64:
2320 return (TCG_TARGET_REG_BITS == 64 ? &r_L
2321 : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
2322 case INDEX_op_qemu_st_i64:
2323 return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
2324 : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
2325
2326 default:
2327 return NULL;
f69d277e 2328 }
f69d277e
RH		 2329}
2330
d453ec78 2331static const int tcg_target_callee_save_regs[] = {
cea5f9a2 2332 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
afa05235
AJ		 2333 TCG_REG_S1,
2334 TCG_REG_S2,
2335 TCG_REG_S3,
2336 TCG_REG_S4,
2337 TCG_REG_S5,
2338 TCG_REG_S6,
2339 TCG_REG_S7,
41883904 2340 TCG_REG_S8,
afa05235
AJ		 2341 TCG_REG_RA, /* should be last for ABI compliance */
2342};
2343
988902fc
AJ		 2344/* The Linux kernel doesn't provide any information about the available
2345 instruction set. Probe it using a signal handler. */
2346
988902fc
AJ		 2347
2348#ifndef use_movnz_instructions
2349bool use_movnz_instructions = false;
2350#endif
2351
2352#ifndef use_mips32_instructions
2353bool use_mips32_instructions = false;
2354#endif
2355
2356#ifndef use_mips32r2_instructions
2357bool use_mips32r2_instructions = false;
2358#endif
2359
2360static volatile sig_atomic_t got_sigill;
2361
2362static void sigill_handler(int signo, siginfo_t *si, void *data)
2363{
2364 /* Skip the faulty instruction */
2365 ucontext_t *uc = (ucontext_t *)data;
2366 uc->uc_mcontext.pc += 4;
2367
2368 got_sigill = 1;
2369}
2370
2371static void tcg_target_detect_isa(void)
2372{
2373 struct sigaction sa_old, sa_new;
2374
2375 memset(&sa_new, 0, sizeof(sa_new));
2376 sa_new.sa_flags = SA_SIGINFO;
2377 sa_new.sa_sigaction = sigill_handler;
2378 sigaction(SIGILL, &sa_new, &sa_old);
2379
2380 /* Probe for movn/movz, necessary to implement movcond. */
2381#ifndef use_movnz_instructions
2382 got_sigill = 0;
2383 asm volatile(".set push\n"
2384 ".set mips32\n"
2385 "movn $zero, $zero, $zero\n"
2386 "movz $zero, $zero, $zero\n"
2387 ".set pop\n"
2388 : : : );
2389 use_movnz_instructions = !got_sigill;
2390#endif
2391
2392 /* Probe for MIPS32 instructions. As no subsetting is allowed
2393 by the specification, it is only necessary to probe for one
2394 of the instructions. */
2395#ifndef use_mips32_instructions
2396 got_sigill = 0;
2397 asm volatile(".set push\n"
2398 ".set mips32\n"
2399 "mul $zero, $zero\n"
2400 ".set pop\n"
2401 : : : );
2402 use_mips32_instructions = !got_sigill;
2403#endif
2404
2405 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2406 available. As no subsetting is allowed by the specification,
2407 it is only necessary to probe for one of the instructions. */
2408#ifndef use_mips32r2_instructions
2409 if (use_mips32_instructions) {
2410 got_sigill = 0;
2411 asm volatile(".set push\n"
2412 ".set mips32r2\n"
2413 "seb $zero, $zero\n"
2414 ".set pop\n"
2415 : : : );
2416 use_mips32r2_instructions = !got_sigill;
2417 }
2418#endif
2419
2420 sigaction(SIGILL, &sa_old, NULL);
2421}
2422
bb08afe9
JG		 2423static tcg_insn_unit *align_code_ptr(TCGContext *s)
2424{
2425 uintptr_t p = (uintptr_t)s->code_ptr;
2426 if (p & 15) {
2427 p = (p + 15) & -16;
2428 s->code_ptr = (void *)p;
2429 }
2430 return s->code_ptr;
2431}
2432
0973b1cf
JG		 2433/* Stack frame parameters. */
2434#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2435#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2436#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2437
2438#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2439 + TCG_TARGET_STACK_ALIGN - 1) \
2440 & -TCG_TARGET_STACK_ALIGN)
2441#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2442
2443/* We're expecting to be able to use an immediate for frame allocation. */
2444QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2445
afa05235 2446/* Generate global QEMU prologue and epilogue code */
e4d58b41 2447static void tcg_target_qemu_prologue(TCGContext *s)
afa05235 2448{
0973b1cf
JG		 2449 int i;
2450
2451 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
afa05235
AJ		 2452
2453 /* TB prologue */
0973b1cf
JG		 2454 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2455 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2456 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2457 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
afa05235
AJ		 2458 }
2459
4df9cac5
JB		 2460#ifndef CONFIG_SOFTMMU
2461 if (guest_base) {
2462 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2463 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2464 }
2465#endif
2466
afa05235 2467 /* Call generated code */
ea15fb06 2468 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
0973b1cf 2469 /* delay slot */
cea5f9a2 2470 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
afa05235 2471
5786e068
AJ		 2472 /*
2473 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2474 * and fall through to the rest of the epilogue.
2475 */
df5af130
RH		 2476 /* TODO: Cast goes away when all hosts converted */
2477 tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr);
5786e068
AJ		 2478 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2479
afa05235 2480 /* TB epilogue */
df5af130 2481 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
0973b1cf
JG		 2482 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2483 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2484 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
afa05235
AJ		 2485 }
2486
2487 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
bb08afe9 2488 /* delay slot */
0973b1cf 2489 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
bb08afe9
JG		 2490
2491 if (use_mips32r2_instructions) {
2492 return;
2493 }
2494
7f54eaa3 2495 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
bb08afe9
JG		 2496 clobbers TCG_TMP1, TCG_TMP2. */
2497
2498 /*
2499 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2500 */
df5af130 2501 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s));
bb08afe9
JG		 2502 /* t3 = (ssss)d000 */
2503 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2504 /* t1 = 000a */
2505 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2506 /* t2 = 00c0 */
2507 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2508 /* t3 = d00a */
2509 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2510 /* t1 = 0abc */
2511 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2512 /* t2 = 0c00 */
2513 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2514 /* t1 = 00b0 */
2515 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2516 /* t3 = dc0a */
2517 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2518 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2519 /* t3 = dcba -- delay slot */
2520 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
7f54eaa3
JG		 2521
2522 if (TCG_TARGET_REG_BITS == 32) {
2523 return;
2524 }
2525
2526 /*
2527 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2528 */
df5af130 2529 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s));
7f54eaa3
JG		 2530 /* t1 = (0000)000d */
2531 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2532 /* t3 = 000a */
2533 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2534 /* t1 = (0000)d000 */
2535 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2536 /* t2 = 00c0 */
2537 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2538 /* t3 = d00a */
2539 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2540 /* t1 = 0abc */
2541 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2542 /* t2 = 0c00 */
2543 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2544 /* t1 = 00b0 */
2545 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2546 /* t3 = dc0a */
2547 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2548 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2549 /* t3 = dcba -- delay slot */
2550 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2551
2552 /*
2553 * bswap64 -- 64-bit swap. a0 = abcdefgh
2554 */
df5af130 2555 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s));
7f54eaa3
JG		 2556 /* t3 = h0000000 */
2557 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2558 /* t1 = 0000000a */
2559 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2560
2561 /* t2 = 000000g0 */
2562 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2563 /* t3 = h000000a */
2564 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2565 /* t1 = 00000abc */
2566 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2567 /* t2 = 0g000000 */
2568 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2569 /* t1 = 000000b0 */
2570 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2571
2572 /* t3 = hg00000a */
2573 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2574 /* t2 = 0000abcd */
2575 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2576 /* t3 = hg0000ba */
2577 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2578
2579 /* t1 = 000000c0 */
2580 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2581 /* t2 = 0000000d */
2582 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2583 /* t1 = 00000c00 */
2584 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2585 /* t2 = 0000d000 */
2586 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2587
2588 /* t3 = hg000cba */
2589 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2590 /* t1 = 00abcdef */
2591 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2592 /* t3 = hg00dcba */
2593 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2594
2595 /* t2 = 0000000f */
2596 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2597 /* t1 = 000000e0 */
2598 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2599 /* t2 = 00f00000 */
2600 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2601 /* t1 = 000e0000 */
2602 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2603
2604 /* t3 = hgf0dcba */
2605 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2606 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2607 /* t3 = hgfedcba -- delay slot */
2608 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
afa05235
AJ		 2609}
2610
e4d58b41 2611static void tcg_target_init(TCGContext *s)
afa05235 2612{
988902fc 2613 tcg_target_detect_isa();
d21369f5 2614 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
999b9416 2615 if (TCG_TARGET_REG_BITS == 64) {
d21369f5
RH		 2616 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2617 }
2618
2619 tcg_target_call_clobber_regs = 0;
2620 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2621 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2622 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2623 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2624 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2625 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2626 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2627 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2628 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2629 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2630 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2631 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2632 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2633 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2634 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2635 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
afa05235 2636
ccb1bb66 2637 s->reserved_regs = 0;
afa05235
AJ		 2638 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2639 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2640 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
6c530e32
RH		 2641 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2642 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
bb08afe9
JG		 2643 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2644 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
afa05235
AJ		 2645 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2646 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
3314e008 2647 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
afa05235 2648}
b6bfeea9 2649
1acbad0f
RH		 2650void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
2651 uintptr_t jmp_rw, uintptr_t addr)
b6bfeea9 2652{
1acbad0f
RH		 2653 qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2));
2654 flush_idcache_range(jmp_rx, jmp_rw, 4);
b6bfeea9 2655}
98d69076
JG		 2656
2657typedef struct {
2658 DebugFrameHeader h;
2659 uint8_t fde_def_cfa[4];
2660 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2661} DebugFrame;
2662
2663#define ELF_HOST_MACHINE EM_MIPS
2664/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2665 which is good because they're really quite complicated for MIPS. */
2666
2667static const DebugFrame debug_frame = {
2668 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2669 .h.cie.id = -1,
2670 .h.cie.version = 1,
2671 .h.cie.code_align = 1,
2672 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2673 .h.cie.return_column = TCG_REG_RA,
2674
2675 /* Total FDE size does not include the "len" member. */
2676 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2677
2678 .fde_def_cfa = {
2679 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2680 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2681 (FRAME_SIZE >> 7)
2682 },
2683 .fde_reg_ofs = {
2684 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2685 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2686 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2687 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2688 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2689 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2690 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2691 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2692 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2693 }
2694};
2695
755bf9e5 2696void tcg_register_jit(const void *buf, size_t buf_size)
98d69076
JG		 2697{
2698 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2699}
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