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Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190705-pull-request' into...
[mirror_qemu.git] / tcg / mips / tcg-target.inc.c
CommitLineData
afa05235
AJ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
9d8bf2d1
RH		 27#ifdef HOST_WORDS_BIGENDIAN
28# define MIPS_BE 1
afa05235 29#else
9d8bf2d1 30# define MIPS_BE 0
afa05235
AJ		 31#endif
32
f0d70331
JG		 33#if TCG_TARGET_REG_BITS == 32
34# define LO_OFF (MIPS_BE * 4)
35# define HI_OFF (4 - LO_OFF)
36#else
37/* To assert at compile-time that these values are never used
38 for TCG_TARGET_REG_BITS == 64. */
8df8d529 39int link_error(void);
f0d70331
JG		 40# define LO_OFF link_error()
41# define HI_OFF link_error()
42#endif
9d8bf2d1 43
8d8fdbae 44#ifdef CONFIG_DEBUG_TCG
afa05235
AJ		 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 "zero",
47 "at",
48 "v0",
49 "v1",
50 "a0",
51 "a1",
52 "a2",
53 "a3",
54 "t0",
55 "t1",
56 "t2",
57 "t3",
58 "t4",
59 "t5",
60 "t6",
61 "t7",
62 "s0",
63 "s1",
64 "s2",
65 "s3",
66 "s4",
67 "s5",
68 "s6",
69 "s7",
70 "t8",
71 "t9",
72 "k0",
73 "k1",
74 "gp",
75 "sp",
41883904 76 "s8",
afa05235
AJ		 77 "ra",
78};
79#endif
80
6c530e32 81#define TCG_TMP0 TCG_REG_AT
f216a35f 82#define TCG_TMP1 TCG_REG_T9
bb08afe9
JG		 83#define TCG_TMP2 TCG_REG_T8
84#define TCG_TMP3 TCG_REG_T7
6c530e32 85
4df9cac5
JB		 86#ifndef CONFIG_SOFTMMU
87#define TCG_GUEST_BASE_REG TCG_REG_S1
88#endif
89
afa05235 90/* check if we really need so many registers :P */
2dc7553d 91static const int tcg_target_reg_alloc_order[] = {
41883904 92 /* Call saved registers. */
afa05235
AJ		 93 TCG_REG_S0,
94 TCG_REG_S1,
95 TCG_REG_S2,
96 TCG_REG_S3,
97 TCG_REG_S4,
98 TCG_REG_S5,
99 TCG_REG_S6,
100 TCG_REG_S7,
41883904
RH		 101 TCG_REG_S8,
102
103 /* Call clobbered registers. */
afa05235
AJ		 104 TCG_REG_T4,
105 TCG_REG_T5,
106 TCG_REG_T6,
107 TCG_REG_T7,
108 TCG_REG_T8,
109 TCG_REG_T9,
41883904 110 TCG_REG_V1,
afa05235 111 TCG_REG_V0,
41883904
RH		 112
113 /* Argument registers, opposite order of allocation. */
999b9416
JG		 114 TCG_REG_T3,
115 TCG_REG_T2,
116 TCG_REG_T1,
117 TCG_REG_T0,
41883904
RH		 118 TCG_REG_A3,
119 TCG_REG_A2,
120 TCG_REG_A1,
121 TCG_REG_A0,
afa05235
AJ		 122};
123
999b9416 124static const TCGReg tcg_target_call_iarg_regs[] = {
afa05235
AJ		 125 TCG_REG_A0,
126 TCG_REG_A1,
127 TCG_REG_A2,
999b9416
JG		 128 TCG_REG_A3,
129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
130 TCG_REG_T0,
131 TCG_REG_T1,
132 TCG_REG_T2,
133 TCG_REG_T3,
134#endif
afa05235
AJ		 135};
136
5a0eed37 137static const TCGReg tcg_target_call_oarg_regs[2] = {
afa05235
AJ		 138 TCG_REG_V0,
139 TCG_REG_V1
140};
141
ae0218e3 142static tcg_insn_unit *tb_ret_addr;
bb08afe9 143static tcg_insn_unit *bswap32_addr;
7f54eaa3
JG		 144static tcg_insn_unit *bswap32u_addr;
145static tcg_insn_unit *bswap64_addr;
afa05235 146
ae0218e3 147static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
afa05235 148{
ae0218e3
RH		 149 /* Let the compiler perform the right-shift as part of the arithmetic. */
150 ptrdiff_t disp = target - (pc + 1);
eabb7b91 151 tcg_debug_assert(disp == (int16_t)disp);
ae0218e3 152 return disp & 0xffff;
afa05235
AJ		 153}
154
ae0218e3 155static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
afa05235 156{
ae0218e3 157 *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target));
afa05235
AJ		 158}
159
ae0218e3 160static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
afa05235 161{
eabb7b91 162 tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
ae0218e3 163 return ((uintptr_t)target >> 2) & 0x3ffffff;
afa05235
AJ		 164}
165
ae0218e3 166static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
afa05235 167{
ae0218e3 168 *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target));
afa05235
AJ		 169}
170
6ac17786 171static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
2ba7fae2 172 intptr_t value, intptr_t addend)
afa05235 173{
eabb7b91
AJ		 174 tcg_debug_assert(type == R_MIPS_PC16);
175 tcg_debug_assert(addend == 0);
ae0218e3 176 reloc_pc16(code_ptr, (tcg_insn_unit *)value);
6ac17786 177 return true;
afa05235
AJ		 178}
179
1c418268 180#define TCG_CT_CONST_ZERO 0x100
070603f6
RH		 181#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
182#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
183#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
184#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
2a1d9d41 185#define TCG_CT_CONST_WSZ 0x2000 /* word size */
1c418268
RH		 186
187static inline bool is_p2m1(tcg_target_long val)
188{
189 return val && ((val + 1) & val) == 0;
190}
191
afa05235 192/* parse target specific constraints */
069ea736
RH		 193static const char *target_parse_constraint(TCGArgConstraint *ct,
194 const char *ct_str, TCGType type)
afa05235 195{
069ea736 196 switch(*ct_str++) {
afa05235
AJ		 197 case 'r':
198 ct->ct |= TCG_CT_REG;
d21369f5 199 ct->u.regs = 0xffffffff;
afa05235 200 break;
bb08afe9 201 case 'L': /* qemu_ld input arg constraint */
afa05235 202 ct->ct |= TCG_CT_REG;
d21369f5 203 ct->u.regs = 0xffffffff;
afa05235 204 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
9d8bf2d1 205#if defined(CONFIG_SOFTMMU)
f0d70331 206 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1
RH		 207 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
208 }
afa05235
AJ		 209#endif
210 break;
211 case 'S': /* qemu_st constraint */
212 ct->ct |= TCG_CT_REG;
d21369f5 213 ct->u.regs = 0xffffffff;
afa05235 214 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
cc01cc8e 215#if defined(CONFIG_SOFTMMU)
f0d70331 216 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1
RH		 217 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
218 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
f0d70331
JG		 219 } else {
220 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
9d8bf2d1 221 }
afa05235
AJ		 222#endif
223 break;
224 case 'I':
225 ct->ct |= TCG_CT_CONST_U16;
226 break;
227 case 'J':
228 ct->ct |= TCG_CT_CONST_S16;
229 break;
1c418268
RH		 230 case 'K':
231 ct->ct |= TCG_CT_CONST_P2M1;
232 break;
070603f6
RH		 233 case 'N':
234 ct->ct |= TCG_CT_CONST_N16;
235 break;
2a1d9d41
RH		 236 case 'W':
237 ct->ct |= TCG_CT_CONST_WSZ;
238 break;
afa05235
AJ		 239 case 'Z':
240 /* We are cheating a bit here, using the fact that the register
241 ZERO is also the register number 0. Hence there is no need
242 to check for const_args in each instruction. */
243 ct->ct |= TCG_CT_CONST_ZERO;
244 break;
245 default:
069ea736 246 return NULL;
afa05235 247 }
069ea736 248 return ct_str;
afa05235
AJ		 249}
250
251/* test if a constant matches the constraint */
f6c6afc1 252static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
afa05235
AJ		 253 const TCGArgConstraint *arg_ct)
254{
255 int ct;
256 ct = arg_ct->ct;
1c418268 257 if (ct & TCG_CT_CONST) {
afa05235 258 return 1;
1c418268 259 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
afa05235 260 return 1;
1c418268 261 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
afa05235 262 return 1;
1c418268 263 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
afa05235 264 return 1;
070603f6
RH		 265 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
266 return 1;
1c418268
RH		 267 } else if ((ct & TCG_CT_CONST_P2M1)
268 && use_mips32r2_instructions && is_p2m1(val)) {
269 return 1;
2a1d9d41
RH		 270 } else if ((ct & TCG_CT_CONST_WSZ)
271 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
272 return 1;
1c418268
RH		 273 }
274 return 0;
afa05235
AJ		 275}
276
277/* instruction opcodes */
ac0f3b12 278typedef enum {
57a701fc
JG		 279 OPC_J = 002 << 26,
280 OPC_JAL = 003 << 26,
281 OPC_BEQ = 004 << 26,
282 OPC_BNE = 005 << 26,
283 OPC_BLEZ = 006 << 26,
284 OPC_BGTZ = 007 << 26,
285 OPC_ADDIU = 011 << 26,
286 OPC_SLTI = 012 << 26,
287 OPC_SLTIU = 013 << 26,
288 OPC_ANDI = 014 << 26,
289 OPC_ORI = 015 << 26,
290 OPC_XORI = 016 << 26,
291 OPC_LUI = 017 << 26,
292 OPC_DADDIU = 031 << 26,
293 OPC_LB = 040 << 26,
294 OPC_LH = 041 << 26,
295 OPC_LW = 043 << 26,
296 OPC_LBU = 044 << 26,
297 OPC_LHU = 045 << 26,
298 OPC_LWU = 047 << 26,
299 OPC_SB = 050 << 26,
300 OPC_SH = 051 << 26,
301 OPC_SW = 053 << 26,
302 OPC_LD = 067 << 26,
303 OPC_SD = 077 << 26,
304
305 OPC_SPECIAL = 000 << 26,
306 OPC_SLL = OPC_SPECIAL | 000,
307 OPC_SRL = OPC_SPECIAL | 002,
308 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
309 OPC_SRA = OPC_SPECIAL | 003,
310 OPC_SLLV = OPC_SPECIAL | 004,
311 OPC_SRLV = OPC_SPECIAL | 006,
312 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
313 OPC_SRAV = OPC_SPECIAL | 007,
314 OPC_JR_R5 = OPC_SPECIAL | 010,
315 OPC_JALR = OPC_SPECIAL | 011,
316 OPC_MOVZ = OPC_SPECIAL | 012,
317 OPC_MOVN = OPC_SPECIAL | 013,
318 OPC_SYNC = OPC_SPECIAL | 017,
319 OPC_MFHI = OPC_SPECIAL | 020,
320 OPC_MFLO = OPC_SPECIAL | 022,
321 OPC_DSLLV = OPC_SPECIAL | 024,
322 OPC_DSRLV = OPC_SPECIAL | 026,
323 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
324 OPC_DSRAV = OPC_SPECIAL | 027,
325 OPC_MULT = OPC_SPECIAL | 030,
326 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
327 OPC_MUH = OPC_SPECIAL | 030 | 0300,
328 OPC_MULTU = OPC_SPECIAL | 031,
329 OPC_MULU = OPC_SPECIAL | 031 | 0200,
330 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
331 OPC_DIV = OPC_SPECIAL | 032,
332 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
333 OPC_MOD = OPC_SPECIAL | 032 | 0300,
334 OPC_DIVU = OPC_SPECIAL | 033,
335 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
336 OPC_MODU = OPC_SPECIAL | 033 | 0300,
337 OPC_DMULT = OPC_SPECIAL | 034,
338 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
339 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
340 OPC_DMULTU = OPC_SPECIAL | 035,
341 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
342 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
343 OPC_DDIV = OPC_SPECIAL | 036,
344 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
345 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
346 OPC_DDIVU = OPC_SPECIAL | 037,
347 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
348 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
349 OPC_ADDU = OPC_SPECIAL | 041,
350 OPC_SUBU = OPC_SPECIAL | 043,
351 OPC_AND = OPC_SPECIAL | 044,
352 OPC_OR = OPC_SPECIAL | 045,
353 OPC_XOR = OPC_SPECIAL | 046,
354 OPC_NOR = OPC_SPECIAL | 047,
355 OPC_SLT = OPC_SPECIAL | 052,
356 OPC_SLTU = OPC_SPECIAL | 053,
357 OPC_DADDU = OPC_SPECIAL | 055,
358 OPC_DSUBU = OPC_SPECIAL | 057,
359 OPC_SELEQZ = OPC_SPECIAL | 065,
360 OPC_SELNEZ = OPC_SPECIAL | 067,
361 OPC_DSLL = OPC_SPECIAL | 070,
362 OPC_DSRL = OPC_SPECIAL | 072,
363 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
364 OPC_DSRA = OPC_SPECIAL | 073,
365 OPC_DSLL32 = OPC_SPECIAL | 074,
366 OPC_DSRL32 = OPC_SPECIAL | 076,
367 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
368 OPC_DSRA32 = OPC_SPECIAL | 077,
2a1d9d41
RH		 369 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
370 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
57a701fc
JG		 371
372 OPC_REGIMM = 001 << 26,
373 OPC_BLTZ = OPC_REGIMM | (000 << 16),
374 OPC_BGEZ = OPC_REGIMM | (001 << 16),
375
376 OPC_SPECIAL2 = 034 << 26,
377 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
2a1d9d41
RH		 378 OPC_CLZ = OPC_SPECIAL2 | 040,
379 OPC_DCLZ = OPC_SPECIAL2 | 044,
57a701fc
JG		 380
381 OPC_SPECIAL3 = 037 << 26,
382 OPC_EXT = OPC_SPECIAL3 | 000,
383 OPC_DEXTM = OPC_SPECIAL3 | 001,
384 OPC_DEXTU = OPC_SPECIAL3 | 002,
385 OPC_DEXT = OPC_SPECIAL3 | 003,
386 OPC_INS = OPC_SPECIAL3 | 004,
387 OPC_DINSM = OPC_SPECIAL3 | 005,
388 OPC_DINSU = OPC_SPECIAL3 | 006,
389 OPC_DINS = OPC_SPECIAL3 | 007,
390 OPC_WSBH = OPC_SPECIAL3 | 00240,
391 OPC_DSBH = OPC_SPECIAL3 | 00244,
392 OPC_DSHD = OPC_SPECIAL3 | 00544,
393 OPC_SEB = OPC_SPECIAL3 | 02040,
394 OPC_SEH = OPC_SPECIAL3 | 03040,
6e0d0969
JH		 395
396 /* MIPS r6 doesn't have JR, JALR should be used instead */
397 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
bc6d0c22
JH		 398
399 /*
400 * MIPS r6 replaces MUL with an alternative encoding which is
401 * backwards-compatible at the assembly level.
402 */
403 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
6f0b9910
PK		 404
405 /* MIPS r6 introduced names for weaker variants of SYNC. These are
406 backward compatible to previous architecture revisions. */
407 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 5,
408 OPC_SYNC_MB = OPC_SYNC | 0x10 << 5,
409 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 5,
410 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 5,
411 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 5,
57a701fc
JG		 412
413 /* Aliases for convenience. */
414 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
415 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
416 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
417 ? OPC_SRL : OPC_DSRL,
ac0f3b12 418} MIPSInsn;
afa05235
AJ		 419
420/*
421 * Type reg
422 */
ac0f3b12 423static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
5a0eed37 424 TCGReg rd, TCGReg rs, TCGReg rt)
afa05235
AJ		 425{
426 int32_t inst;
427
428 inst = opc;
429 inst |= (rs & 0x1F) << 21;
430 inst |= (rt & 0x1F) << 16;
431 inst |= (rd & 0x1F) << 11;
432 tcg_out32(s, inst);
433}
434
435/*
436 * Type immediate
437 */
ac0f3b12 438static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
5a0eed37 439 TCGReg rt, TCGReg rs, TCGArg imm)
afa05235
AJ		 440{
441 int32_t inst;
442
443 inst = opc;
444 inst |= (rs & 0x1F) << 21;
445 inst |= (rt & 0x1F) << 16;
446 inst |= (imm & 0xffff);
447 tcg_out32(s, inst);
448}
449
1c418268
RH		 450/*
451 * Type bitfield
452 */
ac0f3b12 453static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
1c418268
RH		 454 TCGReg rs, int msb, int lsb)
455{
456 int32_t inst;
457
458 inst = opc;
459 inst |= (rs & 0x1F) << 21;
460 inst |= (rt & 0x1F) << 16;
461 inst |= (msb & 0x1F) << 11;
462 inst |= (lsb & 0x1F) << 6;
463 tcg_out32(s, inst);
464}
465
0119b192
JG		 466static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
467 MIPSInsn oph, TCGReg rt, TCGReg rs,
468 int msb, int lsb)
469{
470 if (lsb >= 32) {
471 opc = oph;
472 msb -= 32;
473 lsb -= 32;
474 } else if (msb >= 32) {
475 opc = opm;
476 msb -= 32;
477 }
478 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
479}
480
6d8ff4d8
AJ		 481/*
482 * Type branch
483 */
ac0f3b12 484static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
5a0eed37 485 TCGReg rt, TCGReg rs)
6d8ff4d8 486{
8c1b0792 487 tcg_out_opc_imm(s, opc, rt, rs, 0);
6d8ff4d8
AJ		 488}
489
afa05235
AJ		 490/*
491 * Type sa
492 */
ac0f3b12 493static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
5a0eed37 494 TCGReg rd, TCGReg rt, TCGArg sa)
afa05235
AJ		 495{
496 int32_t inst;
497
498 inst = opc;
499 inst |= (rt & 0x1F) << 16;
500 inst |= (rd & 0x1F) << 11;
501 inst |= (sa & 0x1F) << 6;
502 tcg_out32(s, inst);
503
504}
505
0119b192
JG		 506static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
507 TCGReg rd, TCGReg rt, TCGArg sa)
508{
509 int32_t inst;
510
511 inst = (sa & 32 ? opc2 : opc1);
512 inst |= (rt & 0x1F) << 16;
513 inst |= (rd & 0x1F) << 11;
514 inst |= (sa & 0x1F) << 6;
515 tcg_out32(s, inst);
516}
517
f8c9eddb
RH		 518/*
519 * Type jump.
520 * Returns true if the branch was in range and the insn was emitted.
521 */
ac0f3b12 522static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
f8c9eddb
RH		 523{
524 uintptr_t dest = (uintptr_t)target;
525 uintptr_t from = (uintptr_t)s->code_ptr + 4;
526 int32_t inst;
527
528 /* The pc-region branch happens within the 256MB region of
529 the delay slot (thus the +4). */
530 if ((from ^ dest) & -(1 << 28)) {
531 return false;
532 }
eabb7b91 533 tcg_debug_assert((dest & 3) == 0);
f8c9eddb
RH		 534
535 inst = opc;
536 inst |= (dest >> 2) & 0x3ffffff;
537 tcg_out32(s, inst);
538 return true;
539}
540
afa05235
AJ		 541static inline void tcg_out_nop(TCGContext *s)
542{
543 tcg_out32(s, 0);
544}
545
0119b192
JG		 546static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
547{
548 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
549}
550
551static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
552{
553 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
554}
555
556static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
557{
558 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
559}
560
78113e83 561static inline bool tcg_out_mov(TCGContext *s, TCGType type,
2a534aff 562 TCGReg ret, TCGReg arg)
afa05235 563{
18fec301
AJ		 564 /* Simple reg-reg move, optimising out the 'do nothing' case */
565 if (ret != arg) {
2294d05d 566 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
18fec301 567 }
78113e83 568 return true;
afa05235
AJ		 569}
570
2294d05d
JG		 571static void tcg_out_movi(TCGContext *s, TCGType type,
572 TCGReg ret, tcg_target_long arg)
afa05235 573{
2294d05d
JG		 574 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
575 arg = (int32_t)arg;
576 }
afa05235 577 if (arg == (int16_t)arg) {
2294d05d
JG		 578 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
579 return;
580 }
581 if (arg == (uint16_t)arg) {
582 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
583 return;
584 }
585 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
586 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
afa05235 587 } else {
2294d05d
JG		 588 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
589 if (arg & 0xffff0000ull) {
590 tcg_out_dsll(s, ret, ret, 16);
591 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
592 tcg_out_dsll(s, ret, ret, 16);
593 } else {
594 tcg_out_dsll(s, ret, ret, 32);
7dae901d 595 }
afa05235 596 }
2294d05d
JG		 597 if (arg & 0xffff) {
598 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
599 }
afa05235
AJ		 600}
601
5a0eed37 602static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
afa05235 603{
988902fc
AJ		 604 if (use_mips32r2_instructions) {
605 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
606 } else {
607 /* ret and arg can't be register at */
6c530e32 608 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
988902fc
AJ		 609 tcg_abort();
610 }
afa05235 611
6c530e32 612 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
988902fc
AJ		 613 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
614 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
6c530e32 615 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
988902fc 616 }
afa05235
AJ		 617}
618
5a0eed37 619static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
afa05235 620{
988902fc
AJ		 621 if (use_mips32r2_instructions) {
622 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
623 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
624 } else {
625 /* ret and arg can't be register at */
6c530e32 626 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
988902fc
AJ		 627 tcg_abort();
628 }
afa05235 629
6c530e32 630 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
988902fc
AJ		 631 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
632 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
6c530e32 633 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
988902fc 634 }
afa05235
AJ		 635}
636
bb08afe9
JG		 637static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub)
638{
639 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub);
640 tcg_debug_assert(ok);
641}
642
643static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
afa05235 644{
988902fc
AJ		 645 if (use_mips32r2_instructions) {
646 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
647 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
648 } else {
bb08afe9
JG		 649 tcg_out_bswap_subr(s, bswap32_addr);
650 /* delay slot -- never omit the insn, like tcg_out_mov might. */
651 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
652 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
988902fc 653 }
afa05235
AJ		 654}
655
0119b192
JG		 656static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
657{
658 if (use_mips32r2_instructions) {
659 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
660 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
661 tcg_out_dsrl(s, ret, ret, 32);
662 } else {
7f54eaa3
JG		 663 tcg_out_bswap_subr(s, bswap32u_addr);
664 /* delay slot -- never omit the insn, like tcg_out_mov might. */
665 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
666 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
0119b192
JG		 667 }
668}
669
670static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
671{
672 if (use_mips32r2_instructions) {
673 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
674 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
675 } else {
7f54eaa3
JG		 676 tcg_out_bswap_subr(s, bswap64_addr);
677 /* delay slot -- never omit the insn, like tcg_out_mov might. */
678 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
679 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
0119b192
JG		 680 }
681}
682
5a0eed37 683static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
116348de 684{
988902fc
AJ		 685 if (use_mips32r2_instructions) {
686 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
687 } else {
688 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
689 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
690 }
116348de
AJ		 691}
692
5a0eed37 693static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
116348de 694{
988902fc
AJ		 695 if (use_mips32r2_instructions) {
696 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
697 } else {
698 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
699 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
700 }
116348de
AJ		 701}
702
0119b192
JG		 703static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
704{
705 if (use_mips32r2_instructions) {
706 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
707 } else {
708 tcg_out_dsll(s, ret, arg, 32);
709 tcg_out_dsrl(s, ret, ret, 32);
710 }
711}
712
ac0f3b12 713static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
f9a71632 714 TCGReg addr, intptr_t ofs)
afa05235 715{
f9a71632
RH		 716 int16_t lo = ofs;
717 if (ofs != lo) {
6c530e32 718 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
f9a71632 719 if (addr != TCG_REG_ZERO) {
32b69707 720 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
f9a71632 721 }
6c530e32 722 addr = TCG_TMP0;
afa05235 723 }
f9a71632 724 tcg_out_opc_imm(s, opc, data, addr, lo);
afa05235
AJ		 725}
726
2a534aff 727static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
a05b5b9b 728 TCGReg arg1, intptr_t arg2)
afa05235 729{
32b69707
JG		 730 MIPSInsn opc = OPC_LD;
731 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
732 opc = OPC_LW;
733 }
734 tcg_out_ldst(s, opc, arg, arg1, arg2);
afa05235
AJ		 735}
736
2a534aff 737static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
a05b5b9b 738 TCGReg arg1, intptr_t arg2)
afa05235 739{
32b69707
JG		 740 MIPSInsn opc = OPC_SD;
741 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
742 opc = OPC_SW;
743 }
744 tcg_out_ldst(s, opc, arg, arg1, arg2);
afa05235
AJ		 745}
746
59d7c14e
RH		 747static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
748 TCGReg base, intptr_t ofs)
749{
750 if (val == 0) {
751 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
752 return true;
753 }
754 return false;
755}
756
d9f26847
AJ		 757static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
758 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
759 bool cbh, bool is_sub)
760{
761 TCGReg th = TCG_TMP1;
762
763 /* If we have a negative constant such that negating it would
764 make the high part zero, we can (usually) eliminate one insn. */
765 if (cbl && cbh && bh == -1 && bl != 0) {
766 bl = -bl;
767 bh = 0;
768 is_sub = !is_sub;
769 }
770
771 /* By operating on the high part first, we get to use the final
772 carry operation to move back from the temporary. */
773 if (!cbh) {
774 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
775 } else if (bh != 0 || ah == rl) {
776 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
777 } else {
778 th = ah;
779 }
780
781 /* Note that tcg optimization should eliminate the bl == 0 case. */
782 if (is_sub) {
783 if (cbl) {
784 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
785 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
786 } else {
787 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
788 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
789 }
790 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
791 } else {
792 if (cbl) {
793 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
794 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
795 } else if (rl == al && rl == bl) {
161dec9d 796 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
d9f26847
AJ		 797 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
798 } else {
799 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
800 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
801 }
802 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
803 }
804}
805
fd1cf666
RH		 806/* Bit 0 set if inversion required; bit 1 set if swapping required. */
807#define MIPS_CMP_INV 1
808#define MIPS_CMP_SWAP 2
809
810static const uint8_t mips_cmp_map[16] = {
811 [TCG_COND_LT] = 0,
812 [TCG_COND_LTU] = 0,
813 [TCG_COND_GE] = MIPS_CMP_INV,
814 [TCG_COND_GEU] = MIPS_CMP_INV,
815 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
816 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
817 [TCG_COND_GT] = MIPS_CMP_SWAP,
818 [TCG_COND_GTU] = MIPS_CMP_SWAP,
819};
820
821static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
822 TCGReg arg1, TCGReg arg2)
823{
824 MIPSInsn s_opc = OPC_SLTU;
825 int cmp_map;
826
827 switch (cond) {
828 case TCG_COND_EQ:
829 if (arg2 != 0) {
830 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
831 arg1 = ret;
832 }
833 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
834 break;
835
836 case TCG_COND_NE:
837 if (arg2 != 0) {
838 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
839 arg1 = ret;
840 }
841 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
842 break;
843
844 case TCG_COND_LT:
845 case TCG_COND_GE:
846 case TCG_COND_LE:
847 case TCG_COND_GT:
848 s_opc = OPC_SLT;
849 /* FALLTHRU */
850
851 case TCG_COND_LTU:
852 case TCG_COND_GEU:
853 case TCG_COND_LEU:
854 case TCG_COND_GTU:
855 cmp_map = mips_cmp_map[cond];
856 if (cmp_map & MIPS_CMP_SWAP) {
857 TCGReg t = arg1;
858 arg1 = arg2;
859 arg2 = t;
860 }
861 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
862 if (cmp_map & MIPS_CMP_INV) {
863 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
864 }
865 break;
866
867 default:
868 tcg_abort();
869 break;
870 }
871}
872
c068896f 873static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
bec16311 874 TCGReg arg2, TCGLabel *l)
afa05235 875{
c068896f
RH		 876 static const MIPSInsn b_zero[16] = {
877 [TCG_COND_LT] = OPC_BLTZ,
878 [TCG_COND_GT] = OPC_BGTZ,
879 [TCG_COND_LE] = OPC_BLEZ,
880 [TCG_COND_GE] = OPC_BGEZ,
881 };
882
c068896f
RH		 883 MIPSInsn s_opc = OPC_SLTU;
884 MIPSInsn b_opc;
885 int cmp_map;
afa05235
AJ		 886
887 switch (cond) {
888 case TCG_COND_EQ:
c068896f 889 b_opc = OPC_BEQ;
afa05235
AJ		 890 break;
891 case TCG_COND_NE:
c068896f 892 b_opc = OPC_BNE;
afa05235 893 break;
c068896f 894
afa05235 895 case TCG_COND_LT:
c068896f 896 case TCG_COND_GT:
afa05235 897 case TCG_COND_LE:
c068896f 898 case TCG_COND_GE:
0f46c064 899 if (arg2 == 0) {
c068896f
RH		 900 b_opc = b_zero[cond];
901 arg2 = arg1;
902 arg1 = 0;
903 break;
0f46c064 904 }
c068896f
RH		 905 s_opc = OPC_SLT;
906 /* FALLTHRU */
907
908 case TCG_COND_LTU:
909 case TCG_COND_GTU:
afa05235 910 case TCG_COND_LEU:
c068896f
RH		 911 case TCG_COND_GEU:
912 cmp_map = mips_cmp_map[cond];
913 if (cmp_map & MIPS_CMP_SWAP) {
914 TCGReg t = arg1;
915 arg1 = arg2;
916 arg2 = t;
0f46c064 917 }
c068896f
RH		 918 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
919 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
920 arg1 = TCG_TMP0;
921 arg2 = TCG_REG_ZERO;
afa05235 922 break;
c068896f 923
afa05235
AJ		 924 default:
925 tcg_abort();
926 break;
927 }
c068896f
RH		 928
929 tcg_out_opc_br(s, b_opc, arg1, arg2);
afa05235 930 if (l->has_value) {
ae0218e3 931 reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
afa05235 932 } else {
bec16311 933 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
afa05235
AJ		 934 }
935 tcg_out_nop(s);
936}
937
1db1c4d7
RH		 938static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
939 TCGReg al, TCGReg ah,
940 TCGReg bl, TCGReg bh)
941{
942 /* Merge highpart comparison into AH. */
943 if (bh != 0) {
944 if (ah != 0) {
945 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
946 ah = tmp0;
947 } else {
948 ah = bh;
949 }
950 }
951 /* Merge lowpart comparison into AL. */
952 if (bl != 0) {
953 if (al != 0) {
954 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
955 al = tmp1;
956 } else {
957 al = bl;
958 }
959 }
960 /* Merge high and low part comparisons into AL. */
961 if (ah != 0) {
962 if (al != 0) {
963 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
964 al = tmp0;
965 } else {
966 al = ah;
967 }
968 }
969 return al;
970}
971
9a2f0bfe
RH		 972static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
973 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
974{
975 TCGReg tmp0 = TCG_TMP0;
976 TCGReg tmp1 = ret;
977
eabb7b91 978 tcg_debug_assert(ret != TCG_TMP0);
9a2f0bfe 979 if (ret == ah || ret == bh) {
eabb7b91 980 tcg_debug_assert(ret != TCG_TMP1);
9a2f0bfe
RH		 981 tmp1 = TCG_TMP1;
982 }
983
984 switch (cond) {
985 case TCG_COND_EQ:
986 case TCG_COND_NE:
1db1c4d7
RH		 987 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
988 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
9a2f0bfe
RH		 989 break;
990
991 default:
992 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
993 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
994 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
995 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
996 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
997 break;
998 }
999}
1000
3401fd25 1001static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
bec16311 1002 TCGReg bl, TCGReg bh, TCGLabel *l)
3401fd25
RH		 1003{
1004 TCGCond b_cond = TCG_COND_NE;
1005 TCGReg tmp = TCG_TMP1;
1006
1007 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
1008 With setcond, we emit between 3 and 10 insns and only 1 branch,
1009 which ought to get better branch prediction. */
1010 switch (cond) {
1011 case TCG_COND_EQ:
1012 case TCG_COND_NE:
1013 b_cond = cond;
1014 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
afa05235 1015 break;
afa05235 1016
afa05235 1017 default:
5d831be2 1018 /* Minimize code size by preferring a compare not requiring INV. */
3401fd25
RH		 1019 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1020 cond = tcg_invert_cond(cond);
1021 b_cond = TCG_COND_EQ;
1022 }
1023 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
1024 break;
afa05235
AJ		 1025 }
1026
bec16311 1027 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
afa05235
AJ		 1028}
1029
7d7c4930 1030static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
137d6390 1031 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
7d7c4930 1032{
137d6390
JH		 1033 bool eqz = false;
1034
1035 /* If one of the values is zero, put it last to match SEL*Z instructions */
1036 if (use_mips32r6_instructions && v1 == 0) {
1037 v1 = v2;
1038 v2 = 0;
1039 cond = tcg_invert_cond(cond);
1040 }
33fac20b 1041
7d7c4930
AJ		 1042 switch (cond) {
1043 case TCG_COND_EQ:
137d6390 1044 eqz = true;
33fac20b 1045 /* FALLTHRU */
7d7c4930 1046 case TCG_COND_NE:
33fac20b 1047 if (c2 != 0) {
6c530e32 1048 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
33fac20b 1049 c1 = TCG_TMP0;
7d7c4930
AJ		 1050 }
1051 break;
33fac20b 1052
7d7c4930 1053 default:
5d831be2 1054 /* Minimize code size by preferring a compare not requiring INV. */
33fac20b
RH		 1055 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1056 cond = tcg_invert_cond(cond);
137d6390 1057 eqz = true;
33fac20b
RH		 1058 }
1059 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1060 c1 = TCG_TMP0;
7d7c4930
AJ		 1061 break;
1062 }
33fac20b 1063
137d6390
JH		 1064 if (use_mips32r6_instructions) {
1065 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1066 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1067
1068 if (v2 != 0) {
1069 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1070 }
1071 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1072 if (v2 != 0) {
1073 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1074 }
1075 } else {
1076 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1077
1078 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1079
1080 /* This should be guaranteed via constraints */
1081 tcg_debug_assert(v2 == ret);
1082 }
7d7c4930
AJ		 1083}
1084
ce0236cf 1085static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
9d8bf2d1
RH		 1086{
1087 /* Note that the ABI requires the called function's address to be
1088 loaded into T9, even if a direct branch is in range. */
1089 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1090
1091 /* But do try a direct branch, allowing the cpu better insn prefetch. */
ce0236cf
RH		 1092 if (tail) {
1093 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1094 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1095 }
1096 } else {
1097 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1098 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1099 }
9d8bf2d1 1100 }
ce0236cf 1101}
9d8bf2d1 1102
ce0236cf
RH		 1103static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
1104{
1105 tcg_out_call_int(s, arg, false);
9d8bf2d1
RH		 1106 tcg_out_nop(s);
1107}
1108
afa05235 1109#if defined(CONFIG_SOFTMMU)
659ef5cb
RH		 1110#include "tcg-ldst.inc.c"
1111
ce0236cf
RH		 1112static void * const qemu_ld_helpers[16] = {
1113 [MO_UB] = helper_ret_ldub_mmu,
1114 [MO_SB] = helper_ret_ldsb_mmu,
1115 [MO_LEUW] = helper_le_lduw_mmu,
1116 [MO_LESW] = helper_le_ldsw_mmu,
1117 [MO_LEUL] = helper_le_ldul_mmu,
1118 [MO_LEQ] = helper_le_ldq_mmu,
1119 [MO_BEUW] = helper_be_lduw_mmu,
1120 [MO_BESW] = helper_be_ldsw_mmu,
1121 [MO_BEUL] = helper_be_ldul_mmu,
1122 [MO_BEQ] = helper_be_ldq_mmu,
f0d70331
JG		 1123#if TCG_TARGET_REG_BITS == 64
1124 [MO_LESL] = helper_le_ldsl_mmu,
1125 [MO_BESL] = helper_be_ldsl_mmu,
1126#endif
e141ab52
BS		 1127};
1128
ce0236cf
RH		 1129static void * const qemu_st_helpers[16] = {
1130 [MO_UB] = helper_ret_stb_mmu,
1131 [MO_LEUW] = helper_le_stw_mmu,
1132 [MO_LEUL] = helper_le_stl_mmu,
1133 [MO_LEQ] = helper_le_stq_mmu,
1134 [MO_BEUW] = helper_be_stw_mmu,
1135 [MO_BEUL] = helper_be_stl_mmu,
1136 [MO_BEQ] = helper_be_stq_mmu,
e141ab52 1137};
afa05235 1138
9d8bf2d1
RH		 1139/* Helper routines for marshalling helper function arguments into
1140 * the correct registers and stack.
1141 * I is where we want to put this argument, and is updated and returned
1142 * for the next call. ARG is the argument itself.
1143 *
1144 * We provide routines for arguments which are: immediate, 32 bit
1145 * value in register, 16 and 8 bit values in register (which must be zero
1146 * extended before use) and 64 bit value in a lo:hi register pair.
1147 */
1148
1149static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
afa05235 1150{
9d8bf2d1
RH		 1151 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1152 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1153 } else {
f0d70331
JG		 1154 /* For N32 and N64, the initial offset is different. But there
1155 we also have 8 argument register so we don't run out here. */
1156 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
9d8bf2d1
RH		 1157 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1158 }
1159 return i + 1;
1160}
afa05235 1161
9d8bf2d1
RH		 1162static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1163{
6c530e32 1164 TCGReg tmp = TCG_TMP0;
9d8bf2d1
RH		 1165 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1166 tmp = tcg_target_call_iarg_regs[i];
1167 }
1168 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
1169 return tcg_out_call_iarg_reg(s, i, tmp);
1170}
1171
1172static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1173{
6c530e32 1174 TCGReg tmp = TCG_TMP0;
9d8bf2d1
RH		 1175 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1176 tmp = tcg_target_call_iarg_regs[i];
1177 }
1178 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1179 return tcg_out_call_iarg_reg(s, i, tmp);
1180}
1181
1182static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1183{
6c530e32 1184 TCGReg tmp = TCG_TMP0;
9d8bf2d1
RH		 1185 if (arg == 0) {
1186 tmp = TCG_REG_ZERO;
afa05235 1187 } else {
9d8bf2d1
RH		 1188 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1189 tmp = tcg_target_call_iarg_regs[i];
1190 }
1191 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
afa05235 1192 }
9d8bf2d1
RH		 1193 return tcg_out_call_iarg_reg(s, i, tmp);
1194}
1195
1196static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1197{
f0d70331 1198 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
9d8bf2d1
RH		 1199 i = (i + 1) & ~1;
1200 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1201 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1202 return i;
1203}
1204
269bd5d8
RH		 1205/* We expect to use a 16-bit negative offset from ENV. */
1206QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1207QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1208
ac33373e
RH		 1209/*
1210 * Perform the tlb comparison operation.
1211 * The complete host address is placed in BASE.
1212 * Clobbers TMP0, TMP1, TMP2, TMP3.
1213 */
9d8bf2d1 1214static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
81dfaf1a 1215 TCGReg addrh, TCGMemOpIdx oi,
9d8bf2d1
RH		 1216 tcg_insn_unit *label_ptr[2], bool is_load)
1217{
85aa8081
RH		 1218 TCGMemOp opc = get_memop(oi);
1219 unsigned s_bits = opc & MO_SIZE;
1220 unsigned a_bits = get_alignment_bits(opc);
81dfaf1a 1221 int mem_index = get_mmuidx(oi);
269bd5d8
RH		 1222 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1223 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1224 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
ac33373e
RH		 1225 int add_off = offsetof(CPUTLBEntry, addend);
1226 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
1227 : offsetof(CPUTLBEntry, addr_write));
ac33373e 1228 target_ulong mask;
9d8bf2d1 1229
ac33373e 1230 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
269bd5d8
RH		 1231 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1232 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
ac33373e
RH		 1233
1234 /* Extract the TLB index from the address into TMP3. */
1235 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
1236 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1237 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1238
1239 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1240 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1241
85aa8081
RH		 1242 /* We don't currently support unaligned accesses.
1243 We could do so with mips32r6. */
1244 if (a_bits < s_bits) {
1245 a_bits = s_bits;
1246 }
f0d70331 1247
ac33373e 1248 /* Mask the page bits, keeping the alignment bits to compare against. */
f0d70331
JG		 1249 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
1250
ac33373e 1251 /* Load the (low-half) tlb comparator. */
f0d70331 1252 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
ac33373e 1253 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
f0d70331
JG		 1254 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
1255 } else {
ac33373e
RH		 1256 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
1257 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1258 TCG_TMP0, TCG_TMP3, cmp_off);
f0d70331
JG		 1259 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
1260 /* No second compare is required here;
1261 load the tlb addend for the fast path. */
ac33373e 1262 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
5eb4f645 1263 }
6c530e32 1264 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
9d8bf2d1 1265
f0d70331
JG		 1266 /* Zero extend a 32-bit guest address for a 64-bit host. */
1267 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1268 tcg_out_ext32u(s, base, addrl);
1269 addrl = base;
1270 }
1271
9d8bf2d1 1272 label_ptr[0] = s->code_ptr;
6c530e32 1273 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
afa05235 1274
5eb4f645 1275 /* Load and test the high half tlb comparator. */
f0d70331 1276 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1 1277 /* delay slot */
ac33373e 1278 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
5eb4f645 1279
f0d70331 1280 /* Load the tlb addend for the fast path. */
ac33373e 1281 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
afa05235 1282
9d8bf2d1 1283 label_ptr[1] = s->code_ptr;
5eb4f645 1284 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
9d8bf2d1 1285 }
afa05235 1286
9d8bf2d1 1287 /* delay slot */
f0d70331 1288 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
9d8bf2d1 1289}
afa05235 1290
3972ef6f 1291static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
f0d70331 1292 TCGType ext,
9d8bf2d1
RH		 1293 TCGReg datalo, TCGReg datahi,
1294 TCGReg addrlo, TCGReg addrhi,
3972ef6f 1295 void *raddr, tcg_insn_unit *label_ptr[2])
9d8bf2d1
RH		 1296{
1297 TCGLabelQemuLdst *label = new_ldst_label(s);
1298
1299 label->is_ld = is_ld;
3972ef6f 1300 label->oi = oi;
f0d70331 1301 label->type = ext;
9d8bf2d1
RH		 1302 label->datalo_reg = datalo;
1303 label->datahi_reg = datahi;
1304 label->addrlo_reg = addrlo;
1305 label->addrhi_reg = addrhi;
9d8bf2d1
RH		 1306 label->raddr = raddr;
1307 label->label_ptr[0] = label_ptr[0];
f0d70331 1308 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1
RH		 1309 label->label_ptr[1] = label_ptr[1];
1310 }
1311}
1312
aeee05f5 1313static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
9d8bf2d1 1314{
a8f13961 1315 TCGMemOpIdx oi = l->oi;
3972ef6f 1316 TCGMemOp opc = get_memop(oi);
ce0236cf 1317 TCGReg v0;
9d8bf2d1
RH		 1318 int i;
1319
1320 /* resolve label address */
1321 reloc_pc16(l->label_ptr[0], s->code_ptr);
f0d70331 1322 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1
RH		 1323 reloc_pc16(l->label_ptr[1], s->code_ptr);
1324 }
1325
ce0236cf 1326 i = 1;
f0d70331 1327 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1
RH		 1328 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1329 } else {
1330 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1331 }
3972ef6f 1332 i = tcg_out_call_iarg_imm(s, i, oi);
ce0236cf 1333 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
2b7ec66f 1334 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
ce0236cf
RH		 1335 /* delay slot */
1336 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
9d8bf2d1 1337
ce0236cf 1338 v0 = l->datalo_reg;
f0d70331 1339 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
9d8bf2d1
RH		 1340 /* We eliminated V0 from the possible output registers, so it
1341 cannot be clobbered here. So we must move V1 first. */
ce0236cf
RH		 1342 if (MIPS_BE) {
1343 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1344 v0 = l->datahi_reg;
1345 } else {
1346 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1347 }
afa05235
AJ		 1348 }
1349
6d8ff4d8 1350 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
a31aa4ce
RH		 1351 reloc_pc16(s->code_ptr - 1, l->raddr);
1352
ce0236cf 1353 /* delay slot */
f0d70331
JG		 1354 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1355 /* we always sign-extend 32-bit loads */
1356 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
1357 } else {
1358 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1359 }
aeee05f5 1360 return true;
9d8bf2d1 1361}
afa05235 1362
aeee05f5 1363static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
9d8bf2d1 1364{
a8f13961 1365 TCGMemOpIdx oi = l->oi;
3972ef6f 1366 TCGMemOp opc = get_memop(oi);
9d8bf2d1
RH		 1367 TCGMemOp s_bits = opc & MO_SIZE;
1368 int i;
1369
1370 /* resolve label address */
1371 reloc_pc16(l->label_ptr[0], s->code_ptr);
f0d70331 1372 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1
RH		 1373 reloc_pc16(l->label_ptr[1], s->code_ptr);
1374 }
afa05235 1375
ce0236cf 1376 i = 1;
f0d70331 1377 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
9d8bf2d1 1378 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
cc01cc8e 1379 } else {
9d8bf2d1
RH		 1380 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1381 }
1382 switch (s_bits) {
1383 case MO_8:
1384 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1385 break;
1386 case MO_16:
1387 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1388 break;
1389 case MO_32:
1390 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1391 break;
1392 case MO_64:
f0d70331
JG		 1393 if (TCG_TARGET_REG_BITS == 32) {
1394 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1395 } else {
1396 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1397 }
9d8bf2d1
RH		 1398 break;
1399 default:
1400 tcg_abort();
cc01cc8e 1401 }
3972ef6f 1402 i = tcg_out_call_iarg_imm(s, i, oi);
9d8bf2d1 1403
ce0236cf
RH		 1404 /* Tail call to the store helper. Thus force the return address
1405 computation to take place in the return address register. */
1406 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1407 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
2b7ec66f 1408 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
ce0236cf
RH		 1409 /* delay slot */
1410 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
aeee05f5 1411 return true;
9d8bf2d1 1412}
afa05235
AJ		 1413#endif
1414
bb08afe9 1415static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
f0d70331 1416 TCGReg base, TCGMemOp opc, bool is_64)
9d8bf2d1 1417{
4214a8cb 1418 switch (opc & (MO_SSIZE | MO_BSWAP)) {
9d8bf2d1 1419 case MO_UB:
bb08afe9 1420 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
afa05235 1421 break;
9d8bf2d1 1422 case MO_SB:
bb08afe9 1423 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
afa05235 1424 break;
9d8bf2d1 1425 case MO_UW | MO_BSWAP:
6c530e32 1426 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
bb08afe9 1427 tcg_out_bswap16(s, lo, TCG_TMP1);
afa05235 1428 break;
9d8bf2d1 1429 case MO_UW:
bb08afe9 1430 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
afa05235 1431 break;
9d8bf2d1 1432 case MO_SW | MO_BSWAP:
6c530e32 1433 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
bb08afe9 1434 tcg_out_bswap16s(s, lo, TCG_TMP1);
afa05235 1435 break;
9d8bf2d1 1436 case MO_SW:
bb08afe9 1437 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
9d8bf2d1
RH		 1438 break;
1439 case MO_UL | MO_BSWAP:
f0d70331
JG		 1440 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1441 if (use_mips32r2_instructions) {
1442 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1443 tcg_out_bswap32u(s, lo, lo);
1444 } else {
1445 tcg_out_bswap_subr(s, bswap32u_addr);
1446 /* delay slot */
1447 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1448 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1449 }
1450 break;
1451 }
1452 /* FALLTHRU */
1453 case MO_SL | MO_BSWAP:
bb08afe9
JG		 1454 if (use_mips32r2_instructions) {
1455 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1456 tcg_out_bswap32(s, lo, lo);
1457 } else {
1458 tcg_out_bswap_subr(s, bswap32_addr);
1459 /* delay slot */
1460 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1461 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1462 }
9d8bf2d1
RH		 1463 break;
1464 case MO_UL:
f0d70331
JG		 1465 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1466 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1467 break;
1468 }
1469 /* FALLTHRU */
1470 case MO_SL:
bb08afe9 1471 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
9d8bf2d1
RH		 1472 break;
1473 case MO_Q | MO_BSWAP:
f0d70331
JG		 1474 if (TCG_TARGET_REG_BITS == 64) {
1475 if (use_mips32r2_instructions) {
1476 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1477 tcg_out_bswap64(s, lo, lo);
1478 } else {
1479 tcg_out_bswap_subr(s, bswap64_addr);
1480 /* delay slot */
1481 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1482 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1483 }
1484 } else if (use_mips32r2_instructions) {
bb08afe9
JG		 1485 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1486 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1487 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1488 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1489 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1490 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1491 } else {
1492 tcg_out_bswap_subr(s, bswap32_addr);
1493 /* delay slot */
1494 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1495 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1496 tcg_out_bswap_subr(s, bswap32_addr);
1497 /* delay slot */
1498 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1499 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1500 }
9d8bf2d1
RH		 1501 break;
1502 case MO_Q:
bb08afe9 1503 /* Prefer to load from offset 0 first, but allow for overlap. */
f0d70331
JG		 1504 if (TCG_TARGET_REG_BITS == 64) {
1505 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1506 } else if (MIPS_BE ? hi != base : lo == base) {
bb08afe9
JG		 1507 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1508 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1509 } else {
1510 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1511 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1512 }
afa05235
AJ		 1513 break;
1514 default:
1515 tcg_abort();
1516 }
afa05235
AJ		 1517}
1518
fbef2cc8 1519static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
afa05235 1520{
9d8bf2d1
RH		 1521 TCGReg addr_regl, addr_regh __attribute__((unused));
1522 TCGReg data_regl, data_regh;
59227d5d 1523 TCGMemOpIdx oi;
fbef2cc8 1524 TCGMemOp opc;
afa05235 1525#if defined(CONFIG_SOFTMMU)
9d8bf2d1 1526 tcg_insn_unit *label_ptr[2];
afa05235 1527#endif
bb08afe9 1528 TCGReg base = TCG_REG_A0;
9d8bf2d1 1529
afa05235 1530 data_regl = *args++;
f0d70331 1531 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
afa05235 1532 addr_regl = *args++;
f0d70331 1533 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1534 oi = *args++;
1535 opc = get_memop(oi);
9d8bf2d1 1536
0834c9ea 1537#if defined(CONFIG_SOFTMMU)
81dfaf1a 1538 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
f0d70331
JG		 1539 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1540 add_qemu_ldst_label(s, 1, oi,
1541 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1542 data_regl, data_regh, addr_regl, addr_regh,
3972ef6f 1543 s->code_ptr, label_ptr);
0834c9ea 1544#else
f0d70331
JG		 1545 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1546 tcg_out_ext32u(s, base, addr_regl);
1547 addr_regl = base;
1548 }
b76f21a7 1549 if (guest_base == 0 && data_regl != addr_regl) {
9d8bf2d1 1550 base = addr_regl;
b76f21a7 1551 } else if (guest_base == (int16_t)guest_base) {
f0d70331 1552 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
0834c9ea 1553 } else {
4df9cac5 1554 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
0834c9ea 1555 }
f0d70331 1556 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
9d8bf2d1
RH		 1557#endif
1558}
afa05235 1559
bb08afe9 1560static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
9d8bf2d1
RH		 1561 TCGReg base, TCGMemOp opc)
1562{
bb08afe9
JG		 1563 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1564 if ((lo | hi) == 0) {
1565 opc &= ~MO_BSWAP;
1566 }
1567
4214a8cb 1568 switch (opc & (MO_SIZE | MO_BSWAP)) {
9d8bf2d1 1569 case MO_8:
bb08afe9 1570 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
9d8bf2d1 1571 break;
afa05235 1572
9d8bf2d1 1573 case MO_16 | MO_BSWAP:
bb08afe9 1574 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
6c530e32 1575 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
bb08afe9 1576 lo = TCG_TMP1;
9d8bf2d1
RH		 1577 /* FALLTHRU */
1578 case MO_16:
bb08afe9 1579 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
afa05235 1580 break;
9d8bf2d1
RH		 1581
1582 case MO_32 | MO_BSWAP:
bb08afe9
JG		 1583 tcg_out_bswap32(s, TCG_TMP3, lo);
1584 lo = TCG_TMP3;
9d8bf2d1
RH		 1585 /* FALLTHRU */
1586 case MO_32:
bb08afe9 1587 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
afa05235 1588 break;
9d8bf2d1
RH		 1589
1590 case MO_64 | MO_BSWAP:
f0d70331
JG		 1591 if (TCG_TARGET_REG_BITS == 64) {
1592 tcg_out_bswap64(s, TCG_TMP3, lo);
1593 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1594 } else if (use_mips32r2_instructions) {
bb08afe9
JG		 1595 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1596 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1597 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1598 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1599 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1600 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1601 } else {
1602 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
1603 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1604 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
1605 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1606 }
afa05235 1607 break;
9d8bf2d1 1608 case MO_64:
f0d70331
JG		 1609 if (TCG_TARGET_REG_BITS == 64) {
1610 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1611 } else {
1612 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1613 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1614 }
afa05235 1615 break;
9d8bf2d1 1616
afa05235
AJ		 1617 default:
1618 tcg_abort();
1619 }
9d8bf2d1 1620}
afa05235 1621
fbef2cc8 1622static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
9d8bf2d1
RH		 1623{
1624 TCGReg addr_regl, addr_regh __attribute__((unused));
bb08afe9 1625 TCGReg data_regl, data_regh;
59227d5d 1626 TCGMemOpIdx oi;
fbef2cc8 1627 TCGMemOp opc;
9d8bf2d1
RH		 1628#if defined(CONFIG_SOFTMMU)
1629 tcg_insn_unit *label_ptr[2];
9d8bf2d1 1630#endif
bb08afe9 1631 TCGReg base = TCG_REG_A0;
9d8bf2d1
RH		 1632
1633 data_regl = *args++;
f0d70331 1634 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
9d8bf2d1 1635 addr_regl = *args++;
f0d70331 1636 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1637 oi = *args++;
1638 opc = get_memop(oi);
afa05235 1639
9d8bf2d1 1640#if defined(CONFIG_SOFTMMU)
81dfaf1a 1641 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
9d8bf2d1 1642 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
f0d70331
JG		 1643 add_qemu_ldst_label(s, 0, oi,
1644 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1645 data_regl, data_regh, addr_regl, addr_regh,
3972ef6f 1646 s->code_ptr, label_ptr);
cc01cc8e 1647#else
f0d70331
JG		 1648 base = TCG_REG_A0;
1649 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1650 tcg_out_ext32u(s, base, addr_regl);
1651 addr_regl = base;
1652 }
b76f21a7 1653 if (guest_base == 0) {
9d8bf2d1 1654 base = addr_regl;
f0d70331
JG		 1655 } else if (guest_base == (int16_t)guest_base) {
1656 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
cc01cc8e 1657 } else {
4df9cac5 1658 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
afa05235 1659 }
9d8bf2d1 1660 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
afa05235
AJ		 1661#endif
1662}
1663
6f0b9910
PK		 1664static void tcg_out_mb(TCGContext *s, TCGArg a0)
1665{
1666 static const MIPSInsn sync[] = {
1667 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1668 as the former is an ordering barrier and the latter
1669 is a completion barrier. */
1670 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1671 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1672 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1673 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1674 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1675 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1676 };
1677 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1678}
1679
2a1d9d41
RH		 1680static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1681 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1682{
1683 if (use_mips32r6_instructions) {
1684 if (a2 == width) {
1685 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1686 } else {
1687 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1688 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1689 }
1690 } else {
1691 if (a2 == width) {
1692 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1693 } else if (a0 == a2) {
1694 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1695 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1696 } else if (a0 != a1) {
1697 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1698 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1699 } else {
1700 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1701 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1702 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1703 }
1704 }
1705}
1706
a9751609 1707static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
afa05235
AJ		 1708 const TCGArg *args, const int *const_args)
1709{
4f048535 1710 MIPSInsn i1, i2;
22ee3a98
RH		 1711 TCGArg a0, a1, a2;
1712 int c2;
1713
1714 a0 = args[0];
1715 a1 = args[1];
1716 a2 = args[2];
1717 c2 = const_args[2];
1718
1719 switch (opc) {
afa05235 1720 case INDEX_op_exit_tb:
7dae901d 1721 {
7dae901d
RH		 1722 TCGReg b0 = TCG_REG_ZERO;
1723
0119b192 1724 a0 = (intptr_t)a0;
7dae901d
RH		 1725 if (a0 & ~0xffff) {
1726 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1727 b0 = TCG_REG_V0;
1728 }
1729 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
6c530e32 1730 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
7dae901d 1731 (uintptr_t)tb_ret_addr);
6c530e32 1732 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
7dae901d
RH		 1733 }
1734 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
f8c9eddb 1735 }
afa05235
AJ		 1736 break;
1737 case INDEX_op_goto_tb:
f309101c 1738 if (s->tb_jmp_insn_offset) {
afa05235 1739 /* direct jump method */
f309101c 1740 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
b6bfeea9
RH		 1741 /* Avoid clobbering the address during retranslation. */
1742 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
afa05235
AJ		 1743 } else {
1744 /* indirect jump method */
6c530e32 1745 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
f309101c 1746 (uintptr_t)(s->tb_jmp_target_addr + a0));
6c530e32 1747 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
afa05235
AJ		 1748 }
1749 tcg_out_nop(s);
9f754620 1750 set_jmp_reset_offset(s, a0);
afa05235 1751 break;
5786e068
AJ		 1752 case INDEX_op_goto_ptr:
1753 /* jmp to the given host address (could be epilogue) */
1754 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1755 tcg_out_nop(s);
1756 break;
afa05235 1757 case INDEX_op_br:
bec16311
RH		 1758 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1759 arg_label(a0));
afa05235
AJ		 1760 break;
1761
afa05235 1762 case INDEX_op_ld8u_i32:
0119b192 1763 case INDEX_op_ld8u_i64:
4f048535
RH		 1764 i1 = OPC_LBU;
1765 goto do_ldst;
afa05235 1766 case INDEX_op_ld8s_i32:
0119b192 1767 case INDEX_op_ld8s_i64:
4f048535
RH		 1768 i1 = OPC_LB;
1769 goto do_ldst;
afa05235 1770 case INDEX_op_ld16u_i32:
0119b192 1771 case INDEX_op_ld16u_i64:
4f048535
RH		 1772 i1 = OPC_LHU;
1773 goto do_ldst;
afa05235 1774 case INDEX_op_ld16s_i32:
0119b192 1775 case INDEX_op_ld16s_i64:
4f048535
RH		 1776 i1 = OPC_LH;
1777 goto do_ldst;
afa05235 1778 case INDEX_op_ld_i32:
0119b192 1779 case INDEX_op_ld32s_i64:
4f048535
RH		 1780 i1 = OPC_LW;
1781 goto do_ldst;
0119b192
JG		 1782 case INDEX_op_ld32u_i64:
1783 i1 = OPC_LWU;
1784 goto do_ldst;
1785 case INDEX_op_ld_i64:
1786 i1 = OPC_LD;
1787 goto do_ldst;
afa05235 1788 case INDEX_op_st8_i32:
0119b192 1789 case INDEX_op_st8_i64:
4f048535
RH		 1790 i1 = OPC_SB;
1791 goto do_ldst;
afa05235 1792 case INDEX_op_st16_i32:
0119b192 1793 case INDEX_op_st16_i64:
4f048535
RH		 1794 i1 = OPC_SH;
1795 goto do_ldst;
afa05235 1796 case INDEX_op_st_i32:
0119b192 1797 case INDEX_op_st32_i64:
4f048535 1798 i1 = OPC_SW;
0119b192
JG		 1799 goto do_ldst;
1800 case INDEX_op_st_i64:
1801 i1 = OPC_SD;
4f048535
RH		 1802 do_ldst:
1803 tcg_out_ldst(s, i1, a0, a1, a2);
afa05235
AJ		 1804 break;
1805
1806 case INDEX_op_add_i32:
4f048535
RH		 1807 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1808 goto do_binary;
0119b192
JG		 1809 case INDEX_op_add_i64:
1810 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1811 goto do_binary;
4f048535 1812 case INDEX_op_or_i32:
0119b192 1813 case INDEX_op_or_i64:
4f048535
RH		 1814 i1 = OPC_OR, i2 = OPC_ORI;
1815 goto do_binary;
1816 case INDEX_op_xor_i32:
0119b192 1817 case INDEX_op_xor_i64:
4f048535
RH		 1818 i1 = OPC_XOR, i2 = OPC_XORI;
1819 do_binary:
22ee3a98 1820 if (c2) {
4f048535
RH		 1821 tcg_out_opc_imm(s, i2, a0, a1, a2);
1822 break;
afa05235 1823 }
4f048535
RH		 1824 do_binaryv:
1825 tcg_out_opc_reg(s, i1, a0, a1, a2);
afa05235 1826 break;
4f048535 1827
afa05235 1828 case INDEX_op_sub_i32:
0119b192
JG		 1829 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1830 goto do_subtract;
1831 case INDEX_op_sub_i64:
1832 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1833 do_subtract:
22ee3a98 1834 if (c2) {
0119b192 1835 tcg_out_opc_imm(s, i2, a0, a1, -a2);
4f048535 1836 break;
afa05235 1837 }
0119b192 1838 goto do_binaryv;
4f048535
RH		 1839 case INDEX_op_and_i32:
1840 if (c2 && a2 != (uint16_t)a2) {
1841 int msb = ctz32(~a2) - 1;
eabb7b91
AJ		 1842 tcg_debug_assert(use_mips32r2_instructions);
1843 tcg_debug_assert(is_p2m1(a2));
4f048535
RH		 1844 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1845 break;
1846 }
1847 i1 = OPC_AND, i2 = OPC_ANDI;
1848 goto do_binary;
0119b192
JG		 1849 case INDEX_op_and_i64:
1850 if (c2 && a2 != (uint16_t)a2) {
1851 int msb = ctz64(~a2) - 1;
1852 tcg_debug_assert(use_mips32r2_instructions);
1853 tcg_debug_assert(is_p2m1(a2));
1854 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1855 break;
1856 }
1857 i1 = OPC_AND, i2 = OPC_ANDI;
1858 goto do_binary;
4f048535 1859 case INDEX_op_nor_i32:
0119b192 1860 case INDEX_op_nor_i64:
4f048535
RH		 1861 i1 = OPC_NOR;
1862 goto do_binaryv;
1863
afa05235 1864 case INDEX_op_mul_i32:
988902fc 1865 if (use_mips32_instructions) {
22ee3a98 1866 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
4f048535 1867 break;
988902fc 1868 }
4f048535
RH		 1869 i1 = OPC_MULT, i2 = OPC_MFLO;
1870 goto do_hilo1;
3c9a8f17 1871 case INDEX_op_mulsh_i32:
bc6d0c22
JH		 1872 if (use_mips32r6_instructions) {
1873 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1874 break;
1875 }
4f048535
RH		 1876 i1 = OPC_MULT, i2 = OPC_MFHI;
1877 goto do_hilo1;
3c9a8f17 1878 case INDEX_op_muluh_i32:
bc6d0c22
JH		 1879 if (use_mips32r6_instructions) {
1880 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1881 break;
1882 }
4f048535
RH		 1883 i1 = OPC_MULTU, i2 = OPC_MFHI;
1884 goto do_hilo1;
afa05235 1885 case INDEX_op_div_i32:
bc6d0c22
JH		 1886 if (use_mips32r6_instructions) {
1887 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1888 break;
1889 }
4f048535
RH		 1890 i1 = OPC_DIV, i2 = OPC_MFLO;
1891 goto do_hilo1;
afa05235 1892 case INDEX_op_divu_i32:
bc6d0c22
JH		 1893 if (use_mips32r6_instructions) {
1894 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1895 break;
1896 }
4f048535
RH		 1897 i1 = OPC_DIVU, i2 = OPC_MFLO;
1898 goto do_hilo1;
afa05235 1899 case INDEX_op_rem_i32:
bc6d0c22
JH		 1900 if (use_mips32r6_instructions) {
1901 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1902 break;
1903 }
4f048535
RH		 1904 i1 = OPC_DIV, i2 = OPC_MFHI;
1905 goto do_hilo1;
afa05235 1906 case INDEX_op_remu_i32:
bc6d0c22
JH		 1907 if (use_mips32r6_instructions) {
1908 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1909 break;
1910 }
4f048535 1911 i1 = OPC_DIVU, i2 = OPC_MFHI;
0119b192
JG		 1912 goto do_hilo1;
1913 case INDEX_op_mul_i64:
1914 if (use_mips32r6_instructions) {
1915 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1916 break;
1917 }
1918 i1 = OPC_DMULT, i2 = OPC_MFLO;
1919 goto do_hilo1;
1920 case INDEX_op_mulsh_i64:
1921 if (use_mips32r6_instructions) {
1922 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1923 break;
1924 }
1925 i1 = OPC_DMULT, i2 = OPC_MFHI;
1926 goto do_hilo1;
1927 case INDEX_op_muluh_i64:
1928 if (use_mips32r6_instructions) {
1929 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1930 break;
1931 }
1932 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1933 goto do_hilo1;
1934 case INDEX_op_div_i64:
1935 if (use_mips32r6_instructions) {
1936 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1937 break;
1938 }
1939 i1 = OPC_DDIV, i2 = OPC_MFLO;
1940 goto do_hilo1;
1941 case INDEX_op_divu_i64:
1942 if (use_mips32r6_instructions) {
1943 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1944 break;
1945 }
1946 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1947 goto do_hilo1;
1948 case INDEX_op_rem_i64:
1949 if (use_mips32r6_instructions) {
1950 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1951 break;
1952 }
1953 i1 = OPC_DDIV, i2 = OPC_MFHI;
1954 goto do_hilo1;
1955 case INDEX_op_remu_i64:
1956 if (use_mips32r6_instructions) {
1957 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1958 break;
1959 }
1960 i1 = OPC_DDIVU, i2 = OPC_MFHI;
4f048535
RH		 1961 do_hilo1:
1962 tcg_out_opc_reg(s, i1, 0, a1, a2);
1963 tcg_out_opc_reg(s, i2, a0, 0, 0);
afa05235
AJ		 1964 break;
1965
4f048535
RH		 1966 case INDEX_op_muls2_i32:
1967 i1 = OPC_MULT;
1968 goto do_hilo2;
1969 case INDEX_op_mulu2_i32:
1970 i1 = OPC_MULTU;
0119b192
JG		 1971 goto do_hilo2;
1972 case INDEX_op_muls2_i64:
1973 i1 = OPC_DMULT;
1974 goto do_hilo2;
1975 case INDEX_op_mulu2_i64:
1976 i1 = OPC_DMULTU;
4f048535
RH		 1977 do_hilo2:
1978 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1979 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1980 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
2b79487a 1981 break;
4f048535 1982
afa05235 1983 case INDEX_op_not_i32:
0119b192 1984 case INDEX_op_not_i64:
4f048535
RH		 1985 i1 = OPC_NOR;
1986 goto do_unary;
1987 case INDEX_op_bswap16_i32:
0119b192 1988 case INDEX_op_bswap16_i64:
4f048535
RH		 1989 i1 = OPC_WSBH;
1990 goto do_unary;
1991 case INDEX_op_ext8s_i32:
0119b192 1992 case INDEX_op_ext8s_i64:
4f048535
RH		 1993 i1 = OPC_SEB;
1994 goto do_unary;
1995 case INDEX_op_ext16s_i32:
0119b192 1996 case INDEX_op_ext16s_i64:
4f048535
RH		 1997 i1 = OPC_SEH;
1998 do_unary:
1999 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
afa05235
AJ		 2000 break;
2001
0119b192
JG		 2002 case INDEX_op_bswap32_i32:
2003 tcg_out_bswap32(s, a0, a1);
2004 break;
2005 case INDEX_op_bswap32_i64:
2006 tcg_out_bswap32u(s, a0, a1);
2007 break;
2008 case INDEX_op_bswap64_i64:
2009 tcg_out_bswap64(s, a0, a1);
2010 break;
2011 case INDEX_op_extrh_i64_i32:
2012 tcg_out_dsra(s, a0, a1, 32);
2013 break;
2014 case INDEX_op_ext32s_i64:
2015 case INDEX_op_ext_i32_i64:
2016 case INDEX_op_extrl_i64_i32:
2017 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
2018 break;
2019 case INDEX_op_ext32u_i64:
2020 case INDEX_op_extu_i32_i64:
2021 tcg_out_ext32u(s, a0, a1);
2022 break;
2023
afa05235 2024 case INDEX_op_sar_i32:
4f048535
RH		 2025 i1 = OPC_SRAV, i2 = OPC_SRA;
2026 goto do_shift;
afa05235 2027 case INDEX_op_shl_i32:
4f048535
RH		 2028 i1 = OPC_SLLV, i2 = OPC_SLL;
2029 goto do_shift;
afa05235 2030 case INDEX_op_shr_i32:
4f048535
RH		 2031 i1 = OPC_SRLV, i2 = OPC_SRL;
2032 goto do_shift;
2033 case INDEX_op_rotr_i32:
2034 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2035 do_shift:
22ee3a98 2036 if (c2) {
4f048535 2037 tcg_out_opc_sa(s, i2, a0, a1, a2);
0119b192 2038 break;
afa05235 2039 }
0119b192
JG		 2040 do_shiftv:
2041 tcg_out_opc_reg(s, i1, a0, a2, a1);
afa05235 2042 break;
9a152519 2043 case INDEX_op_rotl_i32:
22ee3a98
RH		 2044 if (c2) {
2045 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
9a152519 2046 } else {
22ee3a98
RH		 2047 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2048 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
9a152519
AJ		 2049 }
2050 break;
0119b192
JG		 2051 case INDEX_op_sar_i64:
2052 if (c2) {
2053 tcg_out_dsra(s, a0, a1, a2);
2054 break;
2055 }
2056 i1 = OPC_DSRAV;
2057 goto do_shiftv;
2058 case INDEX_op_shl_i64:
2059 if (c2) {
2060 tcg_out_dsll(s, a0, a1, a2);
2061 break;
2062 }
2063 i1 = OPC_DSLLV;
2064 goto do_shiftv;
2065 case INDEX_op_shr_i64:
2066 if (c2) {
2067 tcg_out_dsrl(s, a0, a1, a2);
2068 break;
2069 }
2070 i1 = OPC_DSRLV;
2071 goto do_shiftv;
2072 case INDEX_op_rotr_i64:
2073 if (c2) {
2074 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2075 break;
2076 }
2077 i1 = OPC_DROTRV;
2078 goto do_shiftv;
2079 case INDEX_op_rotl_i64:
2080 if (c2) {
2081 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2082 } else {
2083 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2084 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2085 }
c1cf85c9
AJ		 2086 break;
2087
2a1d9d41
RH		 2088 case INDEX_op_clz_i32:
2089 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2090 break;
2091 case INDEX_op_clz_i64:
2092 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2093 break;
2094
04f71aa3 2095 case INDEX_op_deposit_i32:
22ee3a98 2096 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
04f71aa3 2097 break;
0119b192
JG		 2098 case INDEX_op_deposit_i64:
2099 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2100 args[3] + args[4] - 1, args[3]);
2101 break;
befbb3ce 2102 case INDEX_op_extract_i32:
2f5a5f57 2103 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
befbb3ce
RH		 2104 break;
2105 case INDEX_op_extract_i64:
2106 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2f5a5f57 2107 args[3] - 1, a2);
befbb3ce 2108 break;
04f71aa3 2109
afa05235 2110 case INDEX_op_brcond_i32:
0119b192 2111 case INDEX_op_brcond_i64:
bec16311 2112 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
afa05235
AJ		 2113 break;
2114 case INDEX_op_brcond2_i32:
bec16311 2115 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
afa05235
AJ		 2116 break;
2117
7d7c4930 2118 case INDEX_op_movcond_i32:
0119b192 2119 case INDEX_op_movcond_i64:
137d6390 2120 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
7d7c4930
AJ		 2121 break;
2122
4cb26382 2123 case INDEX_op_setcond_i32:
0119b192 2124 case INDEX_op_setcond_i64:
22ee3a98 2125 tcg_out_setcond(s, args[3], a0, a1, a2);
4cb26382 2126 break;
434254aa 2127 case INDEX_op_setcond2_i32:
22ee3a98 2128 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
434254aa 2129 break;
4cb26382 2130
fbef2cc8
RH		 2131 case INDEX_op_qemu_ld_i32:
2132 tcg_out_qemu_ld(s, args, false);
afa05235 2133 break;
fbef2cc8
RH		 2134 case INDEX_op_qemu_ld_i64:
2135 tcg_out_qemu_ld(s, args, true);
afa05235 2136 break;
fbef2cc8
RH		 2137 case INDEX_op_qemu_st_i32:
2138 tcg_out_qemu_st(s, args, false);
afa05235 2139 break;
fbef2cc8
RH		 2140 case INDEX_op_qemu_st_i64:
2141 tcg_out_qemu_st(s, args, true);
afa05235
AJ		 2142 break;
2143
741f117d
RH		 2144 case INDEX_op_add2_i32:
2145 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2146 const_args[4], const_args[5], false);
2147 break;
2148 case INDEX_op_sub2_i32:
2149 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2150 const_args[4], const_args[5], true);
2151 break;
2152
6f0b9910
PK		 2153 case INDEX_op_mb:
2154 tcg_out_mb(s, a0);
2155 break;
96d0ee7f 2156 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
0119b192 2157 case INDEX_op_mov_i64:
96d0ee7f 2158 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
0119b192 2159 case INDEX_op_movi_i64:
96d0ee7f 2160 case INDEX_op_call: /* Always emitted via tcg_out_call. */
afa05235
AJ		 2161 default:
2162 tcg_abort();
2163 }
2164}
2165
89b2e37e
RH		 2166static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2167{
2168 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2169 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2170 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2171 static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
2172 static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
2173 static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
2174 static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
2175 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
2176 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2177 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2178 static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
2179 static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
2180 static const TCGTargetOpDef SZ_SZ_S
2181 = { .args_ct_str = { "SZ", "SZ", "S" } };
2182 static const TCGTargetOpDef SZ_SZ_S_S
2183 = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
2184 static const TCGTargetOpDef r_rZ_rN
2185 = { .args_ct_str = { "r", "rZ", "rN" } };
2186 static const TCGTargetOpDef r_rZ_rZ
2187 = { .args_ct_str = { "r", "rZ", "rZ" } };
2188 static const TCGTargetOpDef r_r_rIK
2189 = { .args_ct_str = { "r", "r", "rIK" } };
2190 static const TCGTargetOpDef r_r_rWZ
2191 = { .args_ct_str = { "r", "r", "rWZ" } };
2192 static const TCGTargetOpDef r_r_r_r
2193 = { .args_ct_str = { "r", "r", "r", "r" } };
2194 static const TCGTargetOpDef r_r_L_L
2195 = { .args_ct_str = { "r", "r", "L", "L" } };
2196 static const TCGTargetOpDef dep
2197 = { .args_ct_str = { "r", "0", "rZ" } };
2198 static const TCGTargetOpDef movc
2199 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
2200 static const TCGTargetOpDef movc_r6
2201 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2202 static const TCGTargetOpDef add2
2203 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
2204 static const TCGTargetOpDef br2
2205 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
2206 static const TCGTargetOpDef setc2
2207 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2208
2209 switch (op) {
2210 case INDEX_op_goto_ptr:
2211 return &r;
afa05235 2212
89b2e37e
RH		 2213 case INDEX_op_ld8u_i32:
2214 case INDEX_op_ld8s_i32:
2215 case INDEX_op_ld16u_i32:
2216 case INDEX_op_ld16s_i32:
2217 case INDEX_op_ld_i32:
2218 case INDEX_op_not_i32:
2219 case INDEX_op_bswap16_i32:
2220 case INDEX_op_bswap32_i32:
2221 case INDEX_op_ext8s_i32:
2222 case INDEX_op_ext16s_i32:
2223 case INDEX_op_extract_i32:
2224 case INDEX_op_ld8u_i64:
2225 case INDEX_op_ld8s_i64:
2226 case INDEX_op_ld16u_i64:
2227 case INDEX_op_ld16s_i64:
2228 case INDEX_op_ld32s_i64:
2229 case INDEX_op_ld32u_i64:
2230 case INDEX_op_ld_i64:
2231 case INDEX_op_not_i64:
2232 case INDEX_op_bswap16_i64:
2233 case INDEX_op_bswap32_i64:
2234 case INDEX_op_bswap64_i64:
2235 case INDEX_op_ext8s_i64:
2236 case INDEX_op_ext16s_i64:
2237 case INDEX_op_ext32s_i64:
2238 case INDEX_op_ext32u_i64:
2239 case INDEX_op_ext_i32_i64:
2240 case INDEX_op_extu_i32_i64:
2241 case INDEX_op_extrl_i64_i32:
2242 case INDEX_op_extrh_i64_i32:
2243 case INDEX_op_extract_i64:
2244 return &r_r;
afa05235 2245
89b2e37e
RH		 2246 case INDEX_op_st8_i32:
2247 case INDEX_op_st16_i32:
2248 case INDEX_op_st_i32:
2249 case INDEX_op_st8_i64:
2250 case INDEX_op_st16_i64:
2251 case INDEX_op_st32_i64:
2252 case INDEX_op_st_i64:
2253 return &rZ_r;
6f0b9910 2254
89b2e37e
RH		 2255 case INDEX_op_add_i32:
2256 case INDEX_op_add_i64:
2257 return &r_r_rJ;
2258 case INDEX_op_sub_i32:
2259 case INDEX_op_sub_i64:
2260 return &r_rZ_rN;
2261 case INDEX_op_mul_i32:
2262 case INDEX_op_mulsh_i32:
2263 case INDEX_op_muluh_i32:
2264 case INDEX_op_div_i32:
2265 case INDEX_op_divu_i32:
2266 case INDEX_op_rem_i32:
2267 case INDEX_op_remu_i32:
2268 case INDEX_op_nor_i32:
2269 case INDEX_op_setcond_i32:
2270 case INDEX_op_mul_i64:
2271 case INDEX_op_mulsh_i64:
2272 case INDEX_op_muluh_i64:
2273 case INDEX_op_div_i64:
2274 case INDEX_op_divu_i64:
2275 case INDEX_op_rem_i64:
2276 case INDEX_op_remu_i64:
2277 case INDEX_op_nor_i64:
2278 case INDEX_op_setcond_i64:
2279 return &r_rZ_rZ;
2280 case INDEX_op_muls2_i32:
2281 case INDEX_op_mulu2_i32:
2282 case INDEX_op_muls2_i64:
2283 case INDEX_op_mulu2_i64:
2284 return &r_r_r_r;
2285 case INDEX_op_and_i32:
2286 case INDEX_op_and_i64:
2287 return &r_r_rIK;
2288 case INDEX_op_or_i32:
2289 case INDEX_op_xor_i32:
2290 case INDEX_op_or_i64:
2291 case INDEX_op_xor_i64:
2292 return &r_r_rI;
2293 case INDEX_op_shl_i32:
2294 case INDEX_op_shr_i32:
2295 case INDEX_op_sar_i32:
2296 case INDEX_op_rotr_i32:
2297 case INDEX_op_rotl_i32:
2298 case INDEX_op_shl_i64:
2299 case INDEX_op_shr_i64:
2300 case INDEX_op_sar_i64:
2301 case INDEX_op_rotr_i64:
2302 case INDEX_op_rotl_i64:
2303 return &r_r_ri;
2304 case INDEX_op_clz_i32:
2305 case INDEX_op_clz_i64:
2306 return &r_r_rWZ;
afa05235 2307
89b2e37e
RH		 2308 case INDEX_op_deposit_i32:
2309 case INDEX_op_deposit_i64:
2310 return &dep;
2311 case INDEX_op_brcond_i32:
2312 case INDEX_op_brcond_i64:
2313 return &rZ_rZ;
2314 case INDEX_op_movcond_i32:
2315 case INDEX_op_movcond_i64:
2316 return use_mips32r6_instructions ? &movc_r6 : &movc;
f69d277e 2317
89b2e37e
RH		 2318 case INDEX_op_add2_i32:
2319 case INDEX_op_sub2_i32:
2320 return &add2;
2321 case INDEX_op_setcond2_i32:
2322 return &setc2;
2323 case INDEX_op_brcond2_i32:
2324 return &br2;
2325
2326 case INDEX_op_qemu_ld_i32:
2327 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2328 ? &r_L : &r_L_L);
2329 case INDEX_op_qemu_st_i32:
2330 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2331 ? &SZ_S : &SZ_S_S);
2332 case INDEX_op_qemu_ld_i64:
2333 return (TCG_TARGET_REG_BITS == 64 ? &r_L
2334 : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
2335 case INDEX_op_qemu_st_i64:
2336 return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
2337 : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
2338
2339 default:
2340 return NULL;
f69d277e 2341 }
f69d277e
RH		 2342}
2343
d453ec78 2344static const int tcg_target_callee_save_regs[] = {
cea5f9a2 2345 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
afa05235
AJ		 2346 TCG_REG_S1,
2347 TCG_REG_S2,
2348 TCG_REG_S3,
2349 TCG_REG_S4,
2350 TCG_REG_S5,
2351 TCG_REG_S6,
2352 TCG_REG_S7,
41883904 2353 TCG_REG_S8,
afa05235
AJ		 2354 TCG_REG_RA, /* should be last for ABI compliance */
2355};
2356
988902fc
AJ		 2357/* The Linux kernel doesn't provide any information about the available
2358 instruction set. Probe it using a signal handler. */
2359
988902fc
AJ		 2360
2361#ifndef use_movnz_instructions
2362bool use_movnz_instructions = false;
2363#endif
2364
2365#ifndef use_mips32_instructions
2366bool use_mips32_instructions = false;
2367#endif
2368
2369#ifndef use_mips32r2_instructions
2370bool use_mips32r2_instructions = false;
2371#endif
2372
2373static volatile sig_atomic_t got_sigill;
2374
2375static void sigill_handler(int signo, siginfo_t *si, void *data)
2376{
2377 /* Skip the faulty instruction */
2378 ucontext_t *uc = (ucontext_t *)data;
2379 uc->uc_mcontext.pc += 4;
2380
2381 got_sigill = 1;
2382}
2383
2384static void tcg_target_detect_isa(void)
2385{
2386 struct sigaction sa_old, sa_new;
2387
2388 memset(&sa_new, 0, sizeof(sa_new));
2389 sa_new.sa_flags = SA_SIGINFO;
2390 sa_new.sa_sigaction = sigill_handler;
2391 sigaction(SIGILL, &sa_new, &sa_old);
2392
2393 /* Probe for movn/movz, necessary to implement movcond. */
2394#ifndef use_movnz_instructions
2395 got_sigill = 0;
2396 asm volatile(".set push\n"
2397 ".set mips32\n"
2398 "movn $zero, $zero, $zero\n"
2399 "movz $zero, $zero, $zero\n"
2400 ".set pop\n"
2401 : : : );
2402 use_movnz_instructions = !got_sigill;
2403#endif
2404
2405 /* Probe for MIPS32 instructions. As no subsetting is allowed
2406 by the specification, it is only necessary to probe for one
2407 of the instructions. */
2408#ifndef use_mips32_instructions
2409 got_sigill = 0;
2410 asm volatile(".set push\n"
2411 ".set mips32\n"
2412 "mul $zero, $zero\n"
2413 ".set pop\n"
2414 : : : );
2415 use_mips32_instructions = !got_sigill;
2416#endif
2417
2418 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2419 available. As no subsetting is allowed by the specification,
2420 it is only necessary to probe for one of the instructions. */
2421#ifndef use_mips32r2_instructions
2422 if (use_mips32_instructions) {
2423 got_sigill = 0;
2424 asm volatile(".set push\n"
2425 ".set mips32r2\n"
2426 "seb $zero, $zero\n"
2427 ".set pop\n"
2428 : : : );
2429 use_mips32r2_instructions = !got_sigill;
2430 }
2431#endif
2432
2433 sigaction(SIGILL, &sa_old, NULL);
2434}
2435
bb08afe9
JG		 2436static tcg_insn_unit *align_code_ptr(TCGContext *s)
2437{
2438 uintptr_t p = (uintptr_t)s->code_ptr;
2439 if (p & 15) {
2440 p = (p + 15) & -16;
2441 s->code_ptr = (void *)p;
2442 }
2443 return s->code_ptr;
2444}
2445
0973b1cf
JG		 2446/* Stack frame parameters. */
2447#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2448#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2449#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2450
2451#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2452 + TCG_TARGET_STACK_ALIGN - 1) \
2453 & -TCG_TARGET_STACK_ALIGN)
2454#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2455
2456/* We're expecting to be able to use an immediate for frame allocation. */
2457QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2458
afa05235 2459/* Generate global QEMU prologue and epilogue code */
e4d58b41 2460static void tcg_target_qemu_prologue(TCGContext *s)
afa05235 2461{
0973b1cf
JG		 2462 int i;
2463
2464 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
afa05235
AJ		 2465
2466 /* TB prologue */
0973b1cf
JG		 2467 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2468 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2469 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2470 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
afa05235
AJ		 2471 }
2472
4df9cac5
JB		 2473#ifndef CONFIG_SOFTMMU
2474 if (guest_base) {
2475 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2476 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2477 }
2478#endif
2479
afa05235 2480 /* Call generated code */
ea15fb06 2481 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
0973b1cf 2482 /* delay slot */
cea5f9a2 2483 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
afa05235 2484
5786e068
AJ		 2485 /*
2486 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2487 * and fall through to the rest of the epilogue.
2488 */
2489 s->code_gen_epilogue = s->code_ptr;
2490 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2491
afa05235 2492 /* TB epilogue */
0973b1cf
JG		 2493 tb_ret_addr = s->code_ptr;
2494 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2495 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2496 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
afa05235
AJ		 2497 }
2498
2499 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
bb08afe9 2500 /* delay slot */
0973b1cf 2501 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
bb08afe9
JG		 2502
2503 if (use_mips32r2_instructions) {
2504 return;
2505 }
2506
7f54eaa3 2507 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
bb08afe9
JG		 2508 clobbers TCG_TMP1, TCG_TMP2. */
2509
2510 /*
2511 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2512 */
2513 bswap32_addr = align_code_ptr(s);
2514 /* t3 = (ssss)d000 */
2515 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2516 /* t1 = 000a */
2517 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2518 /* t2 = 00c0 */
2519 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2520 /* t3 = d00a */
2521 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2522 /* t1 = 0abc */
2523 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2524 /* t2 = 0c00 */
2525 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2526 /* t1 = 00b0 */
2527 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2528 /* t3 = dc0a */
2529 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2530 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2531 /* t3 = dcba -- delay slot */
2532 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
7f54eaa3
JG		 2533
2534 if (TCG_TARGET_REG_BITS == 32) {
2535 return;
2536 }
2537
2538 /*
2539 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2540 */
2541 bswap32u_addr = align_code_ptr(s);
2542 /* t1 = (0000)000d */
2543 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2544 /* t3 = 000a */
2545 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2546 /* t1 = (0000)d000 */
2547 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2548 /* t2 = 00c0 */
2549 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2550 /* t3 = d00a */
2551 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2552 /* t1 = 0abc */
2553 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2554 /* t2 = 0c00 */
2555 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2556 /* t1 = 00b0 */
2557 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2558 /* t3 = dc0a */
2559 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2560 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2561 /* t3 = dcba -- delay slot */
2562 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2563
2564 /*
2565 * bswap64 -- 64-bit swap. a0 = abcdefgh
2566 */
2567 bswap64_addr = align_code_ptr(s);
2568 /* t3 = h0000000 */
2569 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2570 /* t1 = 0000000a */
2571 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2572
2573 /* t2 = 000000g0 */
2574 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2575 /* t3 = h000000a */
2576 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2577 /* t1 = 00000abc */
2578 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2579 /* t2 = 0g000000 */
2580 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2581 /* t1 = 000000b0 */
2582 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2583
2584 /* t3 = hg00000a */
2585 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2586 /* t2 = 0000abcd */
2587 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2588 /* t3 = hg0000ba */
2589 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2590
2591 /* t1 = 000000c0 */
2592 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2593 /* t2 = 0000000d */
2594 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2595 /* t1 = 00000c00 */
2596 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2597 /* t2 = 0000d000 */
2598 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2599
2600 /* t3 = hg000cba */
2601 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2602 /* t1 = 00abcdef */
2603 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2604 /* t3 = hg00dcba */
2605 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2606
2607 /* t2 = 0000000f */
2608 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2609 /* t1 = 000000e0 */
2610 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2611 /* t2 = 00f00000 */
2612 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2613 /* t1 = 000e0000 */
2614 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2615
2616 /* t3 = hgf0dcba */
2617 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2618 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2619 /* t3 = hgfedcba -- delay slot */
2620 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
afa05235
AJ		 2621}
2622
e4d58b41 2623static void tcg_target_init(TCGContext *s)
afa05235 2624{
988902fc 2625 tcg_target_detect_isa();
d21369f5 2626 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
999b9416 2627 if (TCG_TARGET_REG_BITS == 64) {
d21369f5
RH		 2628 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2629 }
2630
2631 tcg_target_call_clobber_regs = 0;
2632 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2633 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2634 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2635 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2636 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2637 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2638 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2639 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2640 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2641 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2642 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2643 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2644 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2645 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2646 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2647 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
afa05235 2648
ccb1bb66 2649 s->reserved_regs = 0;
afa05235
AJ		 2650 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2651 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2652 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
6c530e32
RH		 2653 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2654 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
bb08afe9
JG		 2655 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2656 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
afa05235
AJ		 2657 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2658 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
3314e008 2659 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
afa05235 2660}
b6bfeea9 2661
a8583393
RH		 2662void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
2663 uintptr_t addr)
b6bfeea9 2664{
c82460a5 2665 atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2));
b6bfeea9
RH		 2666 flush_icache_range(jmp_addr, jmp_addr + 4);
2667}
98d69076
JG		 2668
2669typedef struct {
2670 DebugFrameHeader h;
2671 uint8_t fde_def_cfa[4];
2672 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2673} DebugFrame;
2674
2675#define ELF_HOST_MACHINE EM_MIPS
2676/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2677 which is good because they're really quite complicated for MIPS. */
2678
2679static const DebugFrame debug_frame = {
2680 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2681 .h.cie.id = -1,
2682 .h.cie.version = 1,
2683 .h.cie.code_align = 1,
2684 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2685 .h.cie.return_column = TCG_REG_RA,
2686
2687 /* Total FDE size does not include the "len" member. */
2688 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2689
2690 .fde_def_cfa = {
2691 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2692 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2693 (FRAME_SIZE >> 7)
2694 },
2695 .fde_reg_ofs = {
2696 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2697 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2698 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2699 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2700 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2701 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2702 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2703 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2704 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2705 }
2706};
2707
2708void tcg_register_jit(void *buf, size_t buf_size)
2709{
2710 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2711}
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