]>
Commit | Line | Data |
---|---|---|
afa05235 AJ |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> | |
5 | * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> | |
6 | * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
26 | ||
9d8bf2d1 RH |
27 | #ifdef HOST_WORDS_BIGENDIAN |
28 | # define MIPS_BE 1 | |
afa05235 | 29 | #else |
9d8bf2d1 | 30 | # define MIPS_BE 0 |
afa05235 AJ |
31 | #endif |
32 | ||
f0d70331 JG |
33 | #if TCG_TARGET_REG_BITS == 32 |
34 | # define LO_OFF (MIPS_BE * 4) | |
35 | # define HI_OFF (4 - LO_OFF) | |
36 | #else | |
37 | /* To assert at compile-time that these values are never used | |
38 | for TCG_TARGET_REG_BITS == 64. */ | |
8df8d529 | 39 | int link_error(void); |
f0d70331 JG |
40 | # define LO_OFF link_error() |
41 | # define HI_OFF link_error() | |
42 | #endif | |
9d8bf2d1 | 43 | |
8d8fdbae | 44 | #ifdef CONFIG_DEBUG_TCG |
afa05235 AJ |
45 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
46 | "zero", | |
47 | "at", | |
48 | "v0", | |
49 | "v1", | |
50 | "a0", | |
51 | "a1", | |
52 | "a2", | |
53 | "a3", | |
54 | "t0", | |
55 | "t1", | |
56 | "t2", | |
57 | "t3", | |
58 | "t4", | |
59 | "t5", | |
60 | "t6", | |
61 | "t7", | |
62 | "s0", | |
63 | "s1", | |
64 | "s2", | |
65 | "s3", | |
66 | "s4", | |
67 | "s5", | |
68 | "s6", | |
69 | "s7", | |
70 | "t8", | |
71 | "t9", | |
72 | "k0", | |
73 | "k1", | |
74 | "gp", | |
75 | "sp", | |
41883904 | 76 | "s8", |
afa05235 AJ |
77 | "ra", |
78 | }; | |
79 | #endif | |
80 | ||
6c530e32 | 81 | #define TCG_TMP0 TCG_REG_AT |
f216a35f | 82 | #define TCG_TMP1 TCG_REG_T9 |
bb08afe9 JG |
83 | #define TCG_TMP2 TCG_REG_T8 |
84 | #define TCG_TMP3 TCG_REG_T7 | |
6c530e32 | 85 | |
4df9cac5 JB |
86 | #ifndef CONFIG_SOFTMMU |
87 | #define TCG_GUEST_BASE_REG TCG_REG_S1 | |
88 | #endif | |
89 | ||
afa05235 | 90 | /* check if we really need so many registers :P */ |
2dc7553d | 91 | static const int tcg_target_reg_alloc_order[] = { |
41883904 | 92 | /* Call saved registers. */ |
afa05235 AJ |
93 | TCG_REG_S0, |
94 | TCG_REG_S1, | |
95 | TCG_REG_S2, | |
96 | TCG_REG_S3, | |
97 | TCG_REG_S4, | |
98 | TCG_REG_S5, | |
99 | TCG_REG_S6, | |
100 | TCG_REG_S7, | |
41883904 RH |
101 | TCG_REG_S8, |
102 | ||
103 | /* Call clobbered registers. */ | |
afa05235 AJ |
104 | TCG_REG_T4, |
105 | TCG_REG_T5, | |
106 | TCG_REG_T6, | |
107 | TCG_REG_T7, | |
108 | TCG_REG_T8, | |
109 | TCG_REG_T9, | |
41883904 | 110 | TCG_REG_V1, |
afa05235 | 111 | TCG_REG_V0, |
41883904 RH |
112 | |
113 | /* Argument registers, opposite order of allocation. */ | |
999b9416 JG |
114 | TCG_REG_T3, |
115 | TCG_REG_T2, | |
116 | TCG_REG_T1, | |
117 | TCG_REG_T0, | |
41883904 RH |
118 | TCG_REG_A3, |
119 | TCG_REG_A2, | |
120 | TCG_REG_A1, | |
121 | TCG_REG_A0, | |
afa05235 AJ |
122 | }; |
123 | ||
999b9416 | 124 | static const TCGReg tcg_target_call_iarg_regs[] = { |
afa05235 AJ |
125 | TCG_REG_A0, |
126 | TCG_REG_A1, | |
127 | TCG_REG_A2, | |
999b9416 JG |
128 | TCG_REG_A3, |
129 | #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 | |
130 | TCG_REG_T0, | |
131 | TCG_REG_T1, | |
132 | TCG_REG_T2, | |
133 | TCG_REG_T3, | |
134 | #endif | |
afa05235 AJ |
135 | }; |
136 | ||
5a0eed37 | 137 | static const TCGReg tcg_target_call_oarg_regs[2] = { |
afa05235 AJ |
138 | TCG_REG_V0, |
139 | TCG_REG_V1 | |
140 | }; | |
141 | ||
ae0218e3 | 142 | static tcg_insn_unit *tb_ret_addr; |
bb08afe9 | 143 | static tcg_insn_unit *bswap32_addr; |
7f54eaa3 JG |
144 | static tcg_insn_unit *bswap32u_addr; |
145 | static tcg_insn_unit *bswap64_addr; | |
afa05235 | 146 | |
ae0218e3 | 147 | static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) |
afa05235 | 148 | { |
ae0218e3 RH |
149 | /* Let the compiler perform the right-shift as part of the arithmetic. */ |
150 | ptrdiff_t disp = target - (pc + 1); | |
eabb7b91 | 151 | tcg_debug_assert(disp == (int16_t)disp); |
ae0218e3 | 152 | return disp & 0xffff; |
afa05235 AJ |
153 | } |
154 | ||
ae0218e3 | 155 | static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) |
afa05235 | 156 | { |
ae0218e3 | 157 | *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); |
afa05235 AJ |
158 | } |
159 | ||
ae0218e3 | 160 | static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target) |
afa05235 | 161 | { |
eabb7b91 | 162 | tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0); |
ae0218e3 | 163 | return ((uintptr_t)target >> 2) & 0x3ffffff; |
afa05235 AJ |
164 | } |
165 | ||
ae0218e3 | 166 | static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) |
afa05235 | 167 | { |
ae0218e3 | 168 | *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target)); |
afa05235 AJ |
169 | } |
170 | ||
6ac17786 | 171 | static bool patch_reloc(tcg_insn_unit *code_ptr, int type, |
2ba7fae2 | 172 | intptr_t value, intptr_t addend) |
afa05235 | 173 | { |
eabb7b91 AJ |
174 | tcg_debug_assert(type == R_MIPS_PC16); |
175 | tcg_debug_assert(addend == 0); | |
ae0218e3 | 176 | reloc_pc16(code_ptr, (tcg_insn_unit *)value); |
6ac17786 | 177 | return true; |
afa05235 AJ |
178 | } |
179 | ||
1c418268 | 180 | #define TCG_CT_CONST_ZERO 0x100 |
070603f6 RH |
181 | #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ |
182 | #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ | |
183 | #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ | |
184 | #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ | |
2a1d9d41 | 185 | #define TCG_CT_CONST_WSZ 0x2000 /* word size */ |
1c418268 RH |
186 | |
187 | static inline bool is_p2m1(tcg_target_long val) | |
188 | { | |
189 | return val && ((val + 1) & val) == 0; | |
190 | } | |
191 | ||
afa05235 | 192 | /* parse target specific constraints */ |
069ea736 RH |
193 | static const char *target_parse_constraint(TCGArgConstraint *ct, |
194 | const char *ct_str, TCGType type) | |
afa05235 | 195 | { |
069ea736 | 196 | switch(*ct_str++) { |
afa05235 AJ |
197 | case 'r': |
198 | ct->ct |= TCG_CT_REG; | |
d21369f5 | 199 | ct->u.regs = 0xffffffff; |
afa05235 | 200 | break; |
bb08afe9 | 201 | case 'L': /* qemu_ld input arg constraint */ |
afa05235 | 202 | ct->ct |= TCG_CT_REG; |
d21369f5 | 203 | ct->u.regs = 0xffffffff; |
afa05235 | 204 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); |
9d8bf2d1 | 205 | #if defined(CONFIG_SOFTMMU) |
f0d70331 | 206 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 RH |
207 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); |
208 | } | |
afa05235 AJ |
209 | #endif |
210 | break; | |
211 | case 'S': /* qemu_st constraint */ | |
212 | ct->ct |= TCG_CT_REG; | |
d21369f5 | 213 | ct->u.regs = 0xffffffff; |
afa05235 | 214 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); |
cc01cc8e | 215 | #if defined(CONFIG_SOFTMMU) |
f0d70331 | 216 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 RH |
217 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); |
218 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3); | |
f0d70331 JG |
219 | } else { |
220 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1); | |
9d8bf2d1 | 221 | } |
afa05235 AJ |
222 | #endif |
223 | break; | |
224 | case 'I': | |
225 | ct->ct |= TCG_CT_CONST_U16; | |
226 | break; | |
227 | case 'J': | |
228 | ct->ct |= TCG_CT_CONST_S16; | |
229 | break; | |
1c418268 RH |
230 | case 'K': |
231 | ct->ct |= TCG_CT_CONST_P2M1; | |
232 | break; | |
070603f6 RH |
233 | case 'N': |
234 | ct->ct |= TCG_CT_CONST_N16; | |
235 | break; | |
2a1d9d41 RH |
236 | case 'W': |
237 | ct->ct |= TCG_CT_CONST_WSZ; | |
238 | break; | |
afa05235 AJ |
239 | case 'Z': |
240 | /* We are cheating a bit here, using the fact that the register | |
241 | ZERO is also the register number 0. Hence there is no need | |
242 | to check for const_args in each instruction. */ | |
243 | ct->ct |= TCG_CT_CONST_ZERO; | |
244 | break; | |
245 | default: | |
069ea736 | 246 | return NULL; |
afa05235 | 247 | } |
069ea736 | 248 | return ct_str; |
afa05235 AJ |
249 | } |
250 | ||
251 | /* test if a constant matches the constraint */ | |
f6c6afc1 | 252 | static inline int tcg_target_const_match(tcg_target_long val, TCGType type, |
afa05235 AJ |
253 | const TCGArgConstraint *arg_ct) |
254 | { | |
255 | int ct; | |
256 | ct = arg_ct->ct; | |
1c418268 | 257 | if (ct & TCG_CT_CONST) { |
afa05235 | 258 | return 1; |
1c418268 | 259 | } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { |
afa05235 | 260 | return 1; |
1c418268 | 261 | } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { |
afa05235 | 262 | return 1; |
1c418268 | 263 | } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { |
afa05235 | 264 | return 1; |
070603f6 RH |
265 | } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { |
266 | return 1; | |
1c418268 RH |
267 | } else if ((ct & TCG_CT_CONST_P2M1) |
268 | && use_mips32r2_instructions && is_p2m1(val)) { | |
269 | return 1; | |
2a1d9d41 RH |
270 | } else if ((ct & TCG_CT_CONST_WSZ) |
271 | && val == (type == TCG_TYPE_I32 ? 32 : 64)) { | |
272 | return 1; | |
1c418268 RH |
273 | } |
274 | return 0; | |
afa05235 AJ |
275 | } |
276 | ||
277 | /* instruction opcodes */ | |
ac0f3b12 | 278 | typedef enum { |
57a701fc JG |
279 | OPC_J = 002 << 26, |
280 | OPC_JAL = 003 << 26, | |
281 | OPC_BEQ = 004 << 26, | |
282 | OPC_BNE = 005 << 26, | |
283 | OPC_BLEZ = 006 << 26, | |
284 | OPC_BGTZ = 007 << 26, | |
285 | OPC_ADDIU = 011 << 26, | |
286 | OPC_SLTI = 012 << 26, | |
287 | OPC_SLTIU = 013 << 26, | |
288 | OPC_ANDI = 014 << 26, | |
289 | OPC_ORI = 015 << 26, | |
290 | OPC_XORI = 016 << 26, | |
291 | OPC_LUI = 017 << 26, | |
292 | OPC_DADDIU = 031 << 26, | |
293 | OPC_LB = 040 << 26, | |
294 | OPC_LH = 041 << 26, | |
295 | OPC_LW = 043 << 26, | |
296 | OPC_LBU = 044 << 26, | |
297 | OPC_LHU = 045 << 26, | |
298 | OPC_LWU = 047 << 26, | |
299 | OPC_SB = 050 << 26, | |
300 | OPC_SH = 051 << 26, | |
301 | OPC_SW = 053 << 26, | |
302 | OPC_LD = 067 << 26, | |
303 | OPC_SD = 077 << 26, | |
304 | ||
305 | OPC_SPECIAL = 000 << 26, | |
306 | OPC_SLL = OPC_SPECIAL | 000, | |
307 | OPC_SRL = OPC_SPECIAL | 002, | |
308 | OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), | |
309 | OPC_SRA = OPC_SPECIAL | 003, | |
310 | OPC_SLLV = OPC_SPECIAL | 004, | |
311 | OPC_SRLV = OPC_SPECIAL | 006, | |
312 | OPC_ROTRV = OPC_SPECIAL | 006 | 0100, | |
313 | OPC_SRAV = OPC_SPECIAL | 007, | |
314 | OPC_JR_R5 = OPC_SPECIAL | 010, | |
315 | OPC_JALR = OPC_SPECIAL | 011, | |
316 | OPC_MOVZ = OPC_SPECIAL | 012, | |
317 | OPC_MOVN = OPC_SPECIAL | 013, | |
318 | OPC_SYNC = OPC_SPECIAL | 017, | |
319 | OPC_MFHI = OPC_SPECIAL | 020, | |
320 | OPC_MFLO = OPC_SPECIAL | 022, | |
321 | OPC_DSLLV = OPC_SPECIAL | 024, | |
322 | OPC_DSRLV = OPC_SPECIAL | 026, | |
323 | OPC_DROTRV = OPC_SPECIAL | 026 | 0100, | |
324 | OPC_DSRAV = OPC_SPECIAL | 027, | |
325 | OPC_MULT = OPC_SPECIAL | 030, | |
326 | OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, | |
327 | OPC_MUH = OPC_SPECIAL | 030 | 0300, | |
328 | OPC_MULTU = OPC_SPECIAL | 031, | |
329 | OPC_MULU = OPC_SPECIAL | 031 | 0200, | |
330 | OPC_MUHU = OPC_SPECIAL | 031 | 0300, | |
331 | OPC_DIV = OPC_SPECIAL | 032, | |
332 | OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, | |
333 | OPC_MOD = OPC_SPECIAL | 032 | 0300, | |
334 | OPC_DIVU = OPC_SPECIAL | 033, | |
335 | OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, | |
336 | OPC_MODU = OPC_SPECIAL | 033 | 0300, | |
337 | OPC_DMULT = OPC_SPECIAL | 034, | |
338 | OPC_DMUL = OPC_SPECIAL | 034 | 0200, | |
339 | OPC_DMUH = OPC_SPECIAL | 034 | 0300, | |
340 | OPC_DMULTU = OPC_SPECIAL | 035, | |
341 | OPC_DMULU = OPC_SPECIAL | 035 | 0200, | |
342 | OPC_DMUHU = OPC_SPECIAL | 035 | 0300, | |
343 | OPC_DDIV = OPC_SPECIAL | 036, | |
344 | OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, | |
345 | OPC_DMOD = OPC_SPECIAL | 036 | 0300, | |
346 | OPC_DDIVU = OPC_SPECIAL | 037, | |
347 | OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, | |
348 | OPC_DMODU = OPC_SPECIAL | 037 | 0300, | |
349 | OPC_ADDU = OPC_SPECIAL | 041, | |
350 | OPC_SUBU = OPC_SPECIAL | 043, | |
351 | OPC_AND = OPC_SPECIAL | 044, | |
352 | OPC_OR = OPC_SPECIAL | 045, | |
353 | OPC_XOR = OPC_SPECIAL | 046, | |
354 | OPC_NOR = OPC_SPECIAL | 047, | |
355 | OPC_SLT = OPC_SPECIAL | 052, | |
356 | OPC_SLTU = OPC_SPECIAL | 053, | |
357 | OPC_DADDU = OPC_SPECIAL | 055, | |
358 | OPC_DSUBU = OPC_SPECIAL | 057, | |
359 | OPC_SELEQZ = OPC_SPECIAL | 065, | |
360 | OPC_SELNEZ = OPC_SPECIAL | 067, | |
361 | OPC_DSLL = OPC_SPECIAL | 070, | |
362 | OPC_DSRL = OPC_SPECIAL | 072, | |
363 | OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), | |
364 | OPC_DSRA = OPC_SPECIAL | 073, | |
365 | OPC_DSLL32 = OPC_SPECIAL | 074, | |
366 | OPC_DSRL32 = OPC_SPECIAL | 076, | |
367 | OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), | |
368 | OPC_DSRA32 = OPC_SPECIAL | 077, | |
2a1d9d41 RH |
369 | OPC_CLZ_R6 = OPC_SPECIAL | 0120, |
370 | OPC_DCLZ_R6 = OPC_SPECIAL | 0122, | |
57a701fc JG |
371 | |
372 | OPC_REGIMM = 001 << 26, | |
373 | OPC_BLTZ = OPC_REGIMM | (000 << 16), | |
374 | OPC_BGEZ = OPC_REGIMM | (001 << 16), | |
375 | ||
376 | OPC_SPECIAL2 = 034 << 26, | |
377 | OPC_MUL_R5 = OPC_SPECIAL2 | 002, | |
2a1d9d41 RH |
378 | OPC_CLZ = OPC_SPECIAL2 | 040, |
379 | OPC_DCLZ = OPC_SPECIAL2 | 044, | |
57a701fc JG |
380 | |
381 | OPC_SPECIAL3 = 037 << 26, | |
382 | OPC_EXT = OPC_SPECIAL3 | 000, | |
383 | OPC_DEXTM = OPC_SPECIAL3 | 001, | |
384 | OPC_DEXTU = OPC_SPECIAL3 | 002, | |
385 | OPC_DEXT = OPC_SPECIAL3 | 003, | |
386 | OPC_INS = OPC_SPECIAL3 | 004, | |
387 | OPC_DINSM = OPC_SPECIAL3 | 005, | |
388 | OPC_DINSU = OPC_SPECIAL3 | 006, | |
389 | OPC_DINS = OPC_SPECIAL3 | 007, | |
390 | OPC_WSBH = OPC_SPECIAL3 | 00240, | |
391 | OPC_DSBH = OPC_SPECIAL3 | 00244, | |
392 | OPC_DSHD = OPC_SPECIAL3 | 00544, | |
393 | OPC_SEB = OPC_SPECIAL3 | 02040, | |
394 | OPC_SEH = OPC_SPECIAL3 | 03040, | |
6e0d0969 JH |
395 | |
396 | /* MIPS r6 doesn't have JR, JALR should be used instead */ | |
397 | OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, | |
bc6d0c22 JH |
398 | |
399 | /* | |
400 | * MIPS r6 replaces MUL with an alternative encoding which is | |
401 | * backwards-compatible at the assembly level. | |
402 | */ | |
403 | OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, | |
6f0b9910 PK |
404 | |
405 | /* MIPS r6 introduced names for weaker variants of SYNC. These are | |
406 | backward compatible to previous architecture revisions. */ | |
407 | OPC_SYNC_WMB = OPC_SYNC | 0x04 << 5, | |
408 | OPC_SYNC_MB = OPC_SYNC | 0x10 << 5, | |
409 | OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 5, | |
410 | OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 5, | |
411 | OPC_SYNC_RMB = OPC_SYNC | 0x13 << 5, | |
57a701fc JG |
412 | |
413 | /* Aliases for convenience. */ | |
414 | ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, | |
415 | ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, | |
416 | ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 | |
417 | ? OPC_SRL : OPC_DSRL, | |
ac0f3b12 | 418 | } MIPSInsn; |
afa05235 AJ |
419 | |
420 | /* | |
421 | * Type reg | |
422 | */ | |
ac0f3b12 | 423 | static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, |
5a0eed37 | 424 | TCGReg rd, TCGReg rs, TCGReg rt) |
afa05235 AJ |
425 | { |
426 | int32_t inst; | |
427 | ||
428 | inst = opc; | |
429 | inst |= (rs & 0x1F) << 21; | |
430 | inst |= (rt & 0x1F) << 16; | |
431 | inst |= (rd & 0x1F) << 11; | |
432 | tcg_out32(s, inst); | |
433 | } | |
434 | ||
435 | /* | |
436 | * Type immediate | |
437 | */ | |
ac0f3b12 | 438 | static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, |
5a0eed37 | 439 | TCGReg rt, TCGReg rs, TCGArg imm) |
afa05235 AJ |
440 | { |
441 | int32_t inst; | |
442 | ||
443 | inst = opc; | |
444 | inst |= (rs & 0x1F) << 21; | |
445 | inst |= (rt & 0x1F) << 16; | |
446 | inst |= (imm & 0xffff); | |
447 | tcg_out32(s, inst); | |
448 | } | |
449 | ||
1c418268 RH |
450 | /* |
451 | * Type bitfield | |
452 | */ | |
ac0f3b12 | 453 | static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, |
1c418268 RH |
454 | TCGReg rs, int msb, int lsb) |
455 | { | |
456 | int32_t inst; | |
457 | ||
458 | inst = opc; | |
459 | inst |= (rs & 0x1F) << 21; | |
460 | inst |= (rt & 0x1F) << 16; | |
461 | inst |= (msb & 0x1F) << 11; | |
462 | inst |= (lsb & 0x1F) << 6; | |
463 | tcg_out32(s, inst); | |
464 | } | |
465 | ||
0119b192 JG |
466 | static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, |
467 | MIPSInsn oph, TCGReg rt, TCGReg rs, | |
468 | int msb, int lsb) | |
469 | { | |
470 | if (lsb >= 32) { | |
471 | opc = oph; | |
472 | msb -= 32; | |
473 | lsb -= 32; | |
474 | } else if (msb >= 32) { | |
475 | opc = opm; | |
476 | msb -= 32; | |
477 | } | |
478 | tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); | |
479 | } | |
480 | ||
6d8ff4d8 AJ |
481 | /* |
482 | * Type branch | |
483 | */ | |
ac0f3b12 | 484 | static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, |
5a0eed37 | 485 | TCGReg rt, TCGReg rs) |
6d8ff4d8 | 486 | { |
8c1b0792 | 487 | tcg_out_opc_imm(s, opc, rt, rs, 0); |
6d8ff4d8 AJ |
488 | } |
489 | ||
afa05235 AJ |
490 | /* |
491 | * Type sa | |
492 | */ | |
ac0f3b12 | 493 | static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, |
5a0eed37 | 494 | TCGReg rd, TCGReg rt, TCGArg sa) |
afa05235 AJ |
495 | { |
496 | int32_t inst; | |
497 | ||
498 | inst = opc; | |
499 | inst |= (rt & 0x1F) << 16; | |
500 | inst |= (rd & 0x1F) << 11; | |
501 | inst |= (sa & 0x1F) << 6; | |
502 | tcg_out32(s, inst); | |
503 | ||
504 | } | |
505 | ||
0119b192 JG |
506 | static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, |
507 | TCGReg rd, TCGReg rt, TCGArg sa) | |
508 | { | |
509 | int32_t inst; | |
510 | ||
511 | inst = (sa & 32 ? opc2 : opc1); | |
512 | inst |= (rt & 0x1F) << 16; | |
513 | inst |= (rd & 0x1F) << 11; | |
514 | inst |= (sa & 0x1F) << 6; | |
515 | tcg_out32(s, inst); | |
516 | } | |
517 | ||
f8c9eddb RH |
518 | /* |
519 | * Type jump. | |
520 | * Returns true if the branch was in range and the insn was emitted. | |
521 | */ | |
ac0f3b12 | 522 | static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target) |
f8c9eddb RH |
523 | { |
524 | uintptr_t dest = (uintptr_t)target; | |
525 | uintptr_t from = (uintptr_t)s->code_ptr + 4; | |
526 | int32_t inst; | |
527 | ||
528 | /* The pc-region branch happens within the 256MB region of | |
529 | the delay slot (thus the +4). */ | |
530 | if ((from ^ dest) & -(1 << 28)) { | |
531 | return false; | |
532 | } | |
eabb7b91 | 533 | tcg_debug_assert((dest & 3) == 0); |
f8c9eddb RH |
534 | |
535 | inst = opc; | |
536 | inst |= (dest >> 2) & 0x3ffffff; | |
537 | tcg_out32(s, inst); | |
538 | return true; | |
539 | } | |
540 | ||
afa05235 AJ |
541 | static inline void tcg_out_nop(TCGContext *s) |
542 | { | |
543 | tcg_out32(s, 0); | |
544 | } | |
545 | ||
0119b192 JG |
546 | static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) |
547 | { | |
548 | tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); | |
549 | } | |
550 | ||
551 | static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) | |
552 | { | |
553 | tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); | |
554 | } | |
555 | ||
556 | static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) | |
557 | { | |
558 | tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); | |
559 | } | |
560 | ||
2a534aff RH |
561 | static inline void tcg_out_mov(TCGContext *s, TCGType type, |
562 | TCGReg ret, TCGReg arg) | |
afa05235 | 563 | { |
18fec301 AJ |
564 | /* Simple reg-reg move, optimising out the 'do nothing' case */ |
565 | if (ret != arg) { | |
2294d05d | 566 | tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); |
18fec301 | 567 | } |
afa05235 AJ |
568 | } |
569 | ||
2294d05d JG |
570 | static void tcg_out_movi(TCGContext *s, TCGType type, |
571 | TCGReg ret, tcg_target_long arg) | |
afa05235 | 572 | { |
2294d05d JG |
573 | if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { |
574 | arg = (int32_t)arg; | |
575 | } | |
afa05235 | 576 | if (arg == (int16_t)arg) { |
2294d05d JG |
577 | tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); |
578 | return; | |
579 | } | |
580 | if (arg == (uint16_t)arg) { | |
581 | tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); | |
582 | return; | |
583 | } | |
584 | if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { | |
585 | tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); | |
afa05235 | 586 | } else { |
2294d05d JG |
587 | tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); |
588 | if (arg & 0xffff0000ull) { | |
589 | tcg_out_dsll(s, ret, ret, 16); | |
590 | tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); | |
591 | tcg_out_dsll(s, ret, ret, 16); | |
592 | } else { | |
593 | tcg_out_dsll(s, ret, ret, 32); | |
7dae901d | 594 | } |
afa05235 | 595 | } |
2294d05d JG |
596 | if (arg & 0xffff) { |
597 | tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); | |
598 | } | |
afa05235 AJ |
599 | } |
600 | ||
5a0eed37 | 601 | static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) |
afa05235 | 602 | { |
988902fc AJ |
603 | if (use_mips32r2_instructions) { |
604 | tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); | |
605 | } else { | |
606 | /* ret and arg can't be register at */ | |
6c530e32 | 607 | if (ret == TCG_TMP0 || arg == TCG_TMP0) { |
988902fc AJ |
608 | tcg_abort(); |
609 | } | |
afa05235 | 610 | |
6c530e32 | 611 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); |
988902fc AJ |
612 | tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); |
613 | tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); | |
6c530e32 | 614 | tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); |
988902fc | 615 | } |
afa05235 AJ |
616 | } |
617 | ||
5a0eed37 | 618 | static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) |
afa05235 | 619 | { |
988902fc AJ |
620 | if (use_mips32r2_instructions) { |
621 | tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); | |
622 | tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); | |
623 | } else { | |
624 | /* ret and arg can't be register at */ | |
6c530e32 | 625 | if (ret == TCG_TMP0 || arg == TCG_TMP0) { |
988902fc AJ |
626 | tcg_abort(); |
627 | } | |
afa05235 | 628 | |
6c530e32 | 629 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); |
988902fc AJ |
630 | tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); |
631 | tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); | |
6c530e32 | 632 | tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); |
988902fc | 633 | } |
afa05235 AJ |
634 | } |
635 | ||
bb08afe9 JG |
636 | static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub) |
637 | { | |
638 | bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); | |
639 | tcg_debug_assert(ok); | |
640 | } | |
641 | ||
642 | static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) | |
afa05235 | 643 | { |
988902fc AJ |
644 | if (use_mips32r2_instructions) { |
645 | tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); | |
646 | tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); | |
647 | } else { | |
bb08afe9 JG |
648 | tcg_out_bswap_subr(s, bswap32_addr); |
649 | /* delay slot -- never omit the insn, like tcg_out_mov might. */ | |
650 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); | |
651 | tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); | |
988902fc | 652 | } |
afa05235 AJ |
653 | } |
654 | ||
0119b192 JG |
655 | static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) |
656 | { | |
657 | if (use_mips32r2_instructions) { | |
658 | tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); | |
659 | tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); | |
660 | tcg_out_dsrl(s, ret, ret, 32); | |
661 | } else { | |
7f54eaa3 JG |
662 | tcg_out_bswap_subr(s, bswap32u_addr); |
663 | /* delay slot -- never omit the insn, like tcg_out_mov might. */ | |
664 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); | |
665 | tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); | |
0119b192 JG |
666 | } |
667 | } | |
668 | ||
669 | static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) | |
670 | { | |
671 | if (use_mips32r2_instructions) { | |
672 | tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); | |
673 | tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); | |
674 | } else { | |
7f54eaa3 JG |
675 | tcg_out_bswap_subr(s, bswap64_addr); |
676 | /* delay slot -- never omit the insn, like tcg_out_mov might. */ | |
677 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); | |
678 | tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); | |
0119b192 JG |
679 | } |
680 | } | |
681 | ||
5a0eed37 | 682 | static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) |
116348de | 683 | { |
988902fc AJ |
684 | if (use_mips32r2_instructions) { |
685 | tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); | |
686 | } else { | |
687 | tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); | |
688 | tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); | |
689 | } | |
116348de AJ |
690 | } |
691 | ||
5a0eed37 | 692 | static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) |
116348de | 693 | { |
988902fc AJ |
694 | if (use_mips32r2_instructions) { |
695 | tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); | |
696 | } else { | |
697 | tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); | |
698 | tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); | |
699 | } | |
116348de AJ |
700 | } |
701 | ||
0119b192 JG |
702 | static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) |
703 | { | |
704 | if (use_mips32r2_instructions) { | |
705 | tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); | |
706 | } else { | |
707 | tcg_out_dsll(s, ret, arg, 32); | |
708 | tcg_out_dsrl(s, ret, ret, 32); | |
709 | } | |
710 | } | |
711 | ||
ac0f3b12 | 712 | static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, |
f9a71632 | 713 | TCGReg addr, intptr_t ofs) |
afa05235 | 714 | { |
f9a71632 RH |
715 | int16_t lo = ofs; |
716 | if (ofs != lo) { | |
6c530e32 | 717 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); |
f9a71632 | 718 | if (addr != TCG_REG_ZERO) { |
32b69707 | 719 | tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); |
f9a71632 | 720 | } |
6c530e32 | 721 | addr = TCG_TMP0; |
afa05235 | 722 | } |
f9a71632 | 723 | tcg_out_opc_imm(s, opc, data, addr, lo); |
afa05235 AJ |
724 | } |
725 | ||
2a534aff | 726 | static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, |
a05b5b9b | 727 | TCGReg arg1, intptr_t arg2) |
afa05235 | 728 | { |
32b69707 JG |
729 | MIPSInsn opc = OPC_LD; |
730 | if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { | |
731 | opc = OPC_LW; | |
732 | } | |
733 | tcg_out_ldst(s, opc, arg, arg1, arg2); | |
afa05235 AJ |
734 | } |
735 | ||
2a534aff | 736 | static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
a05b5b9b | 737 | TCGReg arg1, intptr_t arg2) |
afa05235 | 738 | { |
32b69707 JG |
739 | MIPSInsn opc = OPC_SD; |
740 | if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { | |
741 | opc = OPC_SW; | |
742 | } | |
743 | tcg_out_ldst(s, opc, arg, arg1, arg2); | |
afa05235 AJ |
744 | } |
745 | ||
59d7c14e RH |
746 | static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, |
747 | TCGReg base, intptr_t ofs) | |
748 | { | |
749 | if (val == 0) { | |
750 | tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); | |
751 | return true; | |
752 | } | |
753 | return false; | |
754 | } | |
755 | ||
d9f26847 AJ |
756 | static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, |
757 | TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, | |
758 | bool cbh, bool is_sub) | |
759 | { | |
760 | TCGReg th = TCG_TMP1; | |
761 | ||
762 | /* If we have a negative constant such that negating it would | |
763 | make the high part zero, we can (usually) eliminate one insn. */ | |
764 | if (cbl && cbh && bh == -1 && bl != 0) { | |
765 | bl = -bl; | |
766 | bh = 0; | |
767 | is_sub = !is_sub; | |
768 | } | |
769 | ||
770 | /* By operating on the high part first, we get to use the final | |
771 | carry operation to move back from the temporary. */ | |
772 | if (!cbh) { | |
773 | tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); | |
774 | } else if (bh != 0 || ah == rl) { | |
775 | tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); | |
776 | } else { | |
777 | th = ah; | |
778 | } | |
779 | ||
780 | /* Note that tcg optimization should eliminate the bl == 0 case. */ | |
781 | if (is_sub) { | |
782 | if (cbl) { | |
783 | tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); | |
784 | tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); | |
785 | } else { | |
786 | tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); | |
787 | tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); | |
788 | } | |
789 | tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); | |
790 | } else { | |
791 | if (cbl) { | |
792 | tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); | |
793 | tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); | |
794 | } else if (rl == al && rl == bl) { | |
161dec9d | 795 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); |
d9f26847 AJ |
796 | tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); |
797 | } else { | |
798 | tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); | |
799 | tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); | |
800 | } | |
801 | tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); | |
802 | } | |
803 | } | |
804 | ||
fd1cf666 RH |
805 | /* Bit 0 set if inversion required; bit 1 set if swapping required. */ |
806 | #define MIPS_CMP_INV 1 | |
807 | #define MIPS_CMP_SWAP 2 | |
808 | ||
809 | static const uint8_t mips_cmp_map[16] = { | |
810 | [TCG_COND_LT] = 0, | |
811 | [TCG_COND_LTU] = 0, | |
812 | [TCG_COND_GE] = MIPS_CMP_INV, | |
813 | [TCG_COND_GEU] = MIPS_CMP_INV, | |
814 | [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, | |
815 | [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, | |
816 | [TCG_COND_GT] = MIPS_CMP_SWAP, | |
817 | [TCG_COND_GTU] = MIPS_CMP_SWAP, | |
818 | }; | |
819 | ||
820 | static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, | |
821 | TCGReg arg1, TCGReg arg2) | |
822 | { | |
823 | MIPSInsn s_opc = OPC_SLTU; | |
824 | int cmp_map; | |
825 | ||
826 | switch (cond) { | |
827 | case TCG_COND_EQ: | |
828 | if (arg2 != 0) { | |
829 | tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); | |
830 | arg1 = ret; | |
831 | } | |
832 | tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); | |
833 | break; | |
834 | ||
835 | case TCG_COND_NE: | |
836 | if (arg2 != 0) { | |
837 | tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); | |
838 | arg1 = ret; | |
839 | } | |
840 | tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); | |
841 | break; | |
842 | ||
843 | case TCG_COND_LT: | |
844 | case TCG_COND_GE: | |
845 | case TCG_COND_LE: | |
846 | case TCG_COND_GT: | |
847 | s_opc = OPC_SLT; | |
848 | /* FALLTHRU */ | |
849 | ||
850 | case TCG_COND_LTU: | |
851 | case TCG_COND_GEU: | |
852 | case TCG_COND_LEU: | |
853 | case TCG_COND_GTU: | |
854 | cmp_map = mips_cmp_map[cond]; | |
855 | if (cmp_map & MIPS_CMP_SWAP) { | |
856 | TCGReg t = arg1; | |
857 | arg1 = arg2; | |
858 | arg2 = t; | |
859 | } | |
860 | tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); | |
861 | if (cmp_map & MIPS_CMP_INV) { | |
862 | tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); | |
863 | } | |
864 | break; | |
865 | ||
866 | default: | |
867 | tcg_abort(); | |
868 | break; | |
869 | } | |
870 | } | |
871 | ||
c068896f | 872 | static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 873 | TCGReg arg2, TCGLabel *l) |
afa05235 | 874 | { |
c068896f RH |
875 | static const MIPSInsn b_zero[16] = { |
876 | [TCG_COND_LT] = OPC_BLTZ, | |
877 | [TCG_COND_GT] = OPC_BGTZ, | |
878 | [TCG_COND_LE] = OPC_BLEZ, | |
879 | [TCG_COND_GE] = OPC_BGEZ, | |
880 | }; | |
881 | ||
c068896f RH |
882 | MIPSInsn s_opc = OPC_SLTU; |
883 | MIPSInsn b_opc; | |
884 | int cmp_map; | |
afa05235 AJ |
885 | |
886 | switch (cond) { | |
887 | case TCG_COND_EQ: | |
c068896f | 888 | b_opc = OPC_BEQ; |
afa05235 AJ |
889 | break; |
890 | case TCG_COND_NE: | |
c068896f | 891 | b_opc = OPC_BNE; |
afa05235 | 892 | break; |
c068896f | 893 | |
afa05235 | 894 | case TCG_COND_LT: |
c068896f | 895 | case TCG_COND_GT: |
afa05235 | 896 | case TCG_COND_LE: |
c068896f | 897 | case TCG_COND_GE: |
0f46c064 | 898 | if (arg2 == 0) { |
c068896f RH |
899 | b_opc = b_zero[cond]; |
900 | arg2 = arg1; | |
901 | arg1 = 0; | |
902 | break; | |
0f46c064 | 903 | } |
c068896f RH |
904 | s_opc = OPC_SLT; |
905 | /* FALLTHRU */ | |
906 | ||
907 | case TCG_COND_LTU: | |
908 | case TCG_COND_GTU: | |
afa05235 | 909 | case TCG_COND_LEU: |
c068896f RH |
910 | case TCG_COND_GEU: |
911 | cmp_map = mips_cmp_map[cond]; | |
912 | if (cmp_map & MIPS_CMP_SWAP) { | |
913 | TCGReg t = arg1; | |
914 | arg1 = arg2; | |
915 | arg2 = t; | |
0f46c064 | 916 | } |
c068896f RH |
917 | tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); |
918 | b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); | |
919 | arg1 = TCG_TMP0; | |
920 | arg2 = TCG_REG_ZERO; | |
afa05235 | 921 | break; |
c068896f | 922 | |
afa05235 AJ |
923 | default: |
924 | tcg_abort(); | |
925 | break; | |
926 | } | |
c068896f RH |
927 | |
928 | tcg_out_opc_br(s, b_opc, arg1, arg2); | |
afa05235 | 929 | if (l->has_value) { |
ae0218e3 | 930 | reloc_pc16(s->code_ptr - 1, l->u.value_ptr); |
afa05235 | 931 | } else { |
bec16311 | 932 | tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); |
afa05235 AJ |
933 | } |
934 | tcg_out_nop(s); | |
935 | } | |
936 | ||
1db1c4d7 RH |
937 | static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, |
938 | TCGReg al, TCGReg ah, | |
939 | TCGReg bl, TCGReg bh) | |
940 | { | |
941 | /* Merge highpart comparison into AH. */ | |
942 | if (bh != 0) { | |
943 | if (ah != 0) { | |
944 | tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); | |
945 | ah = tmp0; | |
946 | } else { | |
947 | ah = bh; | |
948 | } | |
949 | } | |
950 | /* Merge lowpart comparison into AL. */ | |
951 | if (bl != 0) { | |
952 | if (al != 0) { | |
953 | tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); | |
954 | al = tmp1; | |
955 | } else { | |
956 | al = bl; | |
957 | } | |
958 | } | |
959 | /* Merge high and low part comparisons into AL. */ | |
960 | if (ah != 0) { | |
961 | if (al != 0) { | |
962 | tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); | |
963 | al = tmp0; | |
964 | } else { | |
965 | al = ah; | |
966 | } | |
967 | } | |
968 | return al; | |
969 | } | |
970 | ||
9a2f0bfe RH |
971 | static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, |
972 | TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) | |
973 | { | |
974 | TCGReg tmp0 = TCG_TMP0; | |
975 | TCGReg tmp1 = ret; | |
976 | ||
eabb7b91 | 977 | tcg_debug_assert(ret != TCG_TMP0); |
9a2f0bfe | 978 | if (ret == ah || ret == bh) { |
eabb7b91 | 979 | tcg_debug_assert(ret != TCG_TMP1); |
9a2f0bfe RH |
980 | tmp1 = TCG_TMP1; |
981 | } | |
982 | ||
983 | switch (cond) { | |
984 | case TCG_COND_EQ: | |
985 | case TCG_COND_NE: | |
1db1c4d7 RH |
986 | tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); |
987 | tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); | |
9a2f0bfe RH |
988 | break; |
989 | ||
990 | default: | |
991 | tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); | |
992 | tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); | |
993 | tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); | |
994 | tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); | |
995 | tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); | |
996 | break; | |
997 | } | |
998 | } | |
999 | ||
3401fd25 | 1000 | static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, |
bec16311 | 1001 | TCGReg bl, TCGReg bh, TCGLabel *l) |
3401fd25 RH |
1002 | { |
1003 | TCGCond b_cond = TCG_COND_NE; | |
1004 | TCGReg tmp = TCG_TMP1; | |
1005 | ||
1006 | /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. | |
1007 | With setcond, we emit between 3 and 10 insns and only 1 branch, | |
1008 | which ought to get better branch prediction. */ | |
1009 | switch (cond) { | |
1010 | case TCG_COND_EQ: | |
1011 | case TCG_COND_NE: | |
1012 | b_cond = cond; | |
1013 | tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); | |
afa05235 | 1014 | break; |
afa05235 | 1015 | |
afa05235 | 1016 | default: |
5d831be2 | 1017 | /* Minimize code size by preferring a compare not requiring INV. */ |
3401fd25 RH |
1018 | if (mips_cmp_map[cond] & MIPS_CMP_INV) { |
1019 | cond = tcg_invert_cond(cond); | |
1020 | b_cond = TCG_COND_EQ; | |
1021 | } | |
1022 | tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); | |
1023 | break; | |
afa05235 AJ |
1024 | } |
1025 | ||
bec16311 | 1026 | tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); |
afa05235 AJ |
1027 | } |
1028 | ||
7d7c4930 | 1029 | static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, |
137d6390 | 1030 | TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) |
7d7c4930 | 1031 | { |
137d6390 JH |
1032 | bool eqz = false; |
1033 | ||
1034 | /* If one of the values is zero, put it last to match SEL*Z instructions */ | |
1035 | if (use_mips32r6_instructions && v1 == 0) { | |
1036 | v1 = v2; | |
1037 | v2 = 0; | |
1038 | cond = tcg_invert_cond(cond); | |
1039 | } | |
33fac20b | 1040 | |
7d7c4930 AJ |
1041 | switch (cond) { |
1042 | case TCG_COND_EQ: | |
137d6390 | 1043 | eqz = true; |
33fac20b | 1044 | /* FALLTHRU */ |
7d7c4930 | 1045 | case TCG_COND_NE: |
33fac20b | 1046 | if (c2 != 0) { |
6c530e32 | 1047 | tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); |
33fac20b | 1048 | c1 = TCG_TMP0; |
7d7c4930 AJ |
1049 | } |
1050 | break; | |
33fac20b | 1051 | |
7d7c4930 | 1052 | default: |
5d831be2 | 1053 | /* Minimize code size by preferring a compare not requiring INV. */ |
33fac20b RH |
1054 | if (mips_cmp_map[cond] & MIPS_CMP_INV) { |
1055 | cond = tcg_invert_cond(cond); | |
137d6390 | 1056 | eqz = true; |
33fac20b RH |
1057 | } |
1058 | tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); | |
1059 | c1 = TCG_TMP0; | |
7d7c4930 AJ |
1060 | break; |
1061 | } | |
33fac20b | 1062 | |
137d6390 JH |
1063 | if (use_mips32r6_instructions) { |
1064 | MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; | |
1065 | MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; | |
1066 | ||
1067 | if (v2 != 0) { | |
1068 | tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); | |
1069 | } | |
1070 | tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); | |
1071 | if (v2 != 0) { | |
1072 | tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); | |
1073 | } | |
1074 | } else { | |
1075 | MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; | |
1076 | ||
1077 | tcg_out_opc_reg(s, m_opc, ret, v1, c1); | |
1078 | ||
1079 | /* This should be guaranteed via constraints */ | |
1080 | tcg_debug_assert(v2 == ret); | |
1081 | } | |
7d7c4930 AJ |
1082 | } |
1083 | ||
ce0236cf | 1084 | static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) |
9d8bf2d1 RH |
1085 | { |
1086 | /* Note that the ABI requires the called function's address to be | |
1087 | loaded into T9, even if a direct branch is in range. */ | |
1088 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); | |
1089 | ||
1090 | /* But do try a direct branch, allowing the cpu better insn prefetch. */ | |
ce0236cf RH |
1091 | if (tail) { |
1092 | if (!tcg_out_opc_jmp(s, OPC_J, arg)) { | |
1093 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); | |
1094 | } | |
1095 | } else { | |
1096 | if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { | |
1097 | tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); | |
1098 | } | |
9d8bf2d1 | 1099 | } |
ce0236cf | 1100 | } |
9d8bf2d1 | 1101 | |
ce0236cf RH |
1102 | static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) |
1103 | { | |
1104 | tcg_out_call_int(s, arg, false); | |
9d8bf2d1 RH |
1105 | tcg_out_nop(s); |
1106 | } | |
1107 | ||
afa05235 | 1108 | #if defined(CONFIG_SOFTMMU) |
659ef5cb RH |
1109 | #include "tcg-ldst.inc.c" |
1110 | ||
ce0236cf RH |
1111 | static void * const qemu_ld_helpers[16] = { |
1112 | [MO_UB] = helper_ret_ldub_mmu, | |
1113 | [MO_SB] = helper_ret_ldsb_mmu, | |
1114 | [MO_LEUW] = helper_le_lduw_mmu, | |
1115 | [MO_LESW] = helper_le_ldsw_mmu, | |
1116 | [MO_LEUL] = helper_le_ldul_mmu, | |
1117 | [MO_LEQ] = helper_le_ldq_mmu, | |
1118 | [MO_BEUW] = helper_be_lduw_mmu, | |
1119 | [MO_BESW] = helper_be_ldsw_mmu, | |
1120 | [MO_BEUL] = helper_be_ldul_mmu, | |
1121 | [MO_BEQ] = helper_be_ldq_mmu, | |
f0d70331 JG |
1122 | #if TCG_TARGET_REG_BITS == 64 |
1123 | [MO_LESL] = helper_le_ldsl_mmu, | |
1124 | [MO_BESL] = helper_be_ldsl_mmu, | |
1125 | #endif | |
e141ab52 BS |
1126 | }; |
1127 | ||
ce0236cf RH |
1128 | static void * const qemu_st_helpers[16] = { |
1129 | [MO_UB] = helper_ret_stb_mmu, | |
1130 | [MO_LEUW] = helper_le_stw_mmu, | |
1131 | [MO_LEUL] = helper_le_stl_mmu, | |
1132 | [MO_LEQ] = helper_le_stq_mmu, | |
1133 | [MO_BEUW] = helper_be_stw_mmu, | |
1134 | [MO_BEUL] = helper_be_stl_mmu, | |
1135 | [MO_BEQ] = helper_be_stq_mmu, | |
e141ab52 | 1136 | }; |
afa05235 | 1137 | |
9d8bf2d1 RH |
1138 | /* Helper routines for marshalling helper function arguments into |
1139 | * the correct registers and stack. | |
1140 | * I is where we want to put this argument, and is updated and returned | |
1141 | * for the next call. ARG is the argument itself. | |
1142 | * | |
1143 | * We provide routines for arguments which are: immediate, 32 bit | |
1144 | * value in register, 16 and 8 bit values in register (which must be zero | |
1145 | * extended before use) and 64 bit value in a lo:hi register pair. | |
1146 | */ | |
1147 | ||
1148 | static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) | |
afa05235 | 1149 | { |
9d8bf2d1 RH |
1150 | if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { |
1151 | tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); | |
1152 | } else { | |
f0d70331 JG |
1153 | /* For N32 and N64, the initial offset is different. But there |
1154 | we also have 8 argument register so we don't run out here. */ | |
1155 | tcg_debug_assert(TCG_TARGET_REG_BITS == 32); | |
9d8bf2d1 RH |
1156 | tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); |
1157 | } | |
1158 | return i + 1; | |
1159 | } | |
afa05235 | 1160 | |
9d8bf2d1 RH |
1161 | static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) |
1162 | { | |
6c530e32 | 1163 | TCGReg tmp = TCG_TMP0; |
9d8bf2d1 RH |
1164 | if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { |
1165 | tmp = tcg_target_call_iarg_regs[i]; | |
1166 | } | |
1167 | tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); | |
1168 | return tcg_out_call_iarg_reg(s, i, tmp); | |
1169 | } | |
1170 | ||
1171 | static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) | |
1172 | { | |
6c530e32 | 1173 | TCGReg tmp = TCG_TMP0; |
9d8bf2d1 RH |
1174 | if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { |
1175 | tmp = tcg_target_call_iarg_regs[i]; | |
1176 | } | |
1177 | tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); | |
1178 | return tcg_out_call_iarg_reg(s, i, tmp); | |
1179 | } | |
1180 | ||
1181 | static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) | |
1182 | { | |
6c530e32 | 1183 | TCGReg tmp = TCG_TMP0; |
9d8bf2d1 RH |
1184 | if (arg == 0) { |
1185 | tmp = TCG_REG_ZERO; | |
afa05235 | 1186 | } else { |
9d8bf2d1 RH |
1187 | if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { |
1188 | tmp = tcg_target_call_iarg_regs[i]; | |
1189 | } | |
1190 | tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); | |
afa05235 | 1191 | } |
9d8bf2d1 RH |
1192 | return tcg_out_call_iarg_reg(s, i, tmp); |
1193 | } | |
1194 | ||
1195 | static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) | |
1196 | { | |
f0d70331 | 1197 | tcg_debug_assert(TCG_TARGET_REG_BITS == 32); |
9d8bf2d1 RH |
1198 | i = (i + 1) & ~1; |
1199 | i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); | |
1200 | i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); | |
1201 | return i; | |
1202 | } | |
1203 | ||
ac33373e RH |
1204 | /* We expect tlb_mask to be before tlb_table. */ |
1205 | QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < | |
1206 | offsetof(CPUArchState, tlb_mask)); | |
1207 | ||
1208 | /* We expect tlb_mask to be "near" tlb_table. */ | |
1209 | QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - | |
1210 | offsetof(CPUArchState, tlb_mask) >= 0x8000); | |
1211 | ||
1212 | /* | |
1213 | * Perform the tlb comparison operation. | |
1214 | * The complete host address is placed in BASE. | |
1215 | * Clobbers TMP0, TMP1, TMP2, TMP3. | |
1216 | */ | |
9d8bf2d1 | 1217 | static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, |
81dfaf1a | 1218 | TCGReg addrh, TCGMemOpIdx oi, |
9d8bf2d1 RH |
1219 | tcg_insn_unit *label_ptr[2], bool is_load) |
1220 | { | |
85aa8081 RH |
1221 | TCGMemOp opc = get_memop(oi); |
1222 | unsigned s_bits = opc & MO_SIZE; | |
1223 | unsigned a_bits = get_alignment_bits(opc); | |
81dfaf1a | 1224 | int mem_index = get_mmuidx(oi); |
ac33373e RH |
1225 | int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); |
1226 | int table_off = offsetof(CPUArchState, tlb_table[mem_index]); | |
1227 | int add_off = offsetof(CPUTLBEntry, addend); | |
1228 | int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) | |
1229 | : offsetof(CPUTLBEntry, addr_write)); | |
1230 | TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; | |
1231 | target_ulong mask; | |
9d8bf2d1 | 1232 | |
ac33373e RH |
1233 | if (table_off > 0x7fff) { |
1234 | int mask_hi = mask_off - (int16_t)mask_off; | |
1235 | int table_hi = table_off - (int16_t)table_off; | |
1236 | ||
1237 | table_base = TCG_TMP1; | |
1238 | if (likely(mask_hi == table_hi)) { | |
1239 | mask_base = table_base; | |
1240 | tcg_out_opc_imm(s, OPC_LUI, mask_base, TCG_REG_ZERO, mask_hi >> 16); | |
1241 | tcg_out_opc_reg(s, ALIAS_PADD, mask_base, mask_base, TCG_AREG0); | |
1242 | mask_off -= mask_hi; | |
1243 | table_off -= mask_hi; | |
1244 | } else { | |
1245 | if (mask_hi != 0) { | |
1246 | mask_base = TCG_TMP0; | |
1247 | tcg_out_opc_imm(s, OPC_LUI, | |
1248 | mask_base, TCG_REG_ZERO, mask_hi >> 16); | |
1249 | tcg_out_opc_reg(s, ALIAS_PADD, | |
1250 | mask_base, mask_base, TCG_AREG0); | |
1251 | } | |
1252 | table_off -= mask_off; | |
1253 | mask_off -= mask_hi; | |
1254 | tcg_out_opc_imm(s, ALIAS_PADDI, table_base, mask_base, mask_off); | |
1255 | } | |
9d8bf2d1 RH |
1256 | } |
1257 | ||
ac33373e RH |
1258 | /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ |
1259 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, mask_base, mask_off); | |
1260 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, table_base, table_off); | |
1261 | ||
1262 | /* Extract the TLB index from the address into TMP3. */ | |
1263 | tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, | |
1264 | TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); | |
1265 | tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); | |
1266 | ||
1267 | /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ | |
1268 | tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
1269 | ||
85aa8081 RH |
1270 | /* We don't currently support unaligned accesses. |
1271 | We could do so with mips32r6. */ | |
1272 | if (a_bits < s_bits) { | |
1273 | a_bits = s_bits; | |
1274 | } | |
f0d70331 | 1275 | |
ac33373e | 1276 | /* Mask the page bits, keeping the alignment bits to compare against. */ |
f0d70331 JG |
1277 | mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); |
1278 | ||
ac33373e | 1279 | /* Load the (low-half) tlb comparator. */ |
f0d70331 | 1280 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
ac33373e | 1281 | tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); |
f0d70331 JG |
1282 | tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); |
1283 | } else { | |
ac33373e RH |
1284 | tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD |
1285 | : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), | |
1286 | TCG_TMP0, TCG_TMP3, cmp_off); | |
f0d70331 JG |
1287 | tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); |
1288 | /* No second compare is required here; | |
1289 | load the tlb addend for the fast path. */ | |
ac33373e | 1290 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); |
5eb4f645 | 1291 | } |
6c530e32 | 1292 | tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); |
9d8bf2d1 | 1293 | |
f0d70331 JG |
1294 | /* Zero extend a 32-bit guest address for a 64-bit host. */ |
1295 | if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { | |
1296 | tcg_out_ext32u(s, base, addrl); | |
1297 | addrl = base; | |
1298 | } | |
1299 | ||
9d8bf2d1 | 1300 | label_ptr[0] = s->code_ptr; |
6c530e32 | 1301 | tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); |
afa05235 | 1302 | |
5eb4f645 | 1303 | /* Load and test the high half tlb comparator. */ |
f0d70331 | 1304 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 | 1305 | /* delay slot */ |
ac33373e | 1306 | tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); |
5eb4f645 | 1307 | |
f0d70331 | 1308 | /* Load the tlb addend for the fast path. */ |
ac33373e | 1309 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); |
afa05235 | 1310 | |
9d8bf2d1 | 1311 | label_ptr[1] = s->code_ptr; |
5eb4f645 | 1312 | tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); |
9d8bf2d1 | 1313 | } |
afa05235 | 1314 | |
9d8bf2d1 | 1315 | /* delay slot */ |
f0d70331 | 1316 | tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); |
9d8bf2d1 | 1317 | } |
afa05235 | 1318 | |
3972ef6f | 1319 | static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, |
f0d70331 | 1320 | TCGType ext, |
9d8bf2d1 RH |
1321 | TCGReg datalo, TCGReg datahi, |
1322 | TCGReg addrlo, TCGReg addrhi, | |
3972ef6f | 1323 | void *raddr, tcg_insn_unit *label_ptr[2]) |
9d8bf2d1 RH |
1324 | { |
1325 | TCGLabelQemuLdst *label = new_ldst_label(s); | |
1326 | ||
1327 | label->is_ld = is_ld; | |
3972ef6f | 1328 | label->oi = oi; |
f0d70331 | 1329 | label->type = ext; |
9d8bf2d1 RH |
1330 | label->datalo_reg = datalo; |
1331 | label->datahi_reg = datahi; | |
1332 | label->addrlo_reg = addrlo; | |
1333 | label->addrhi_reg = addrhi; | |
9d8bf2d1 RH |
1334 | label->raddr = raddr; |
1335 | label->label_ptr[0] = label_ptr[0]; | |
f0d70331 | 1336 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 RH |
1337 | label->label_ptr[1] = label_ptr[1]; |
1338 | } | |
1339 | } | |
1340 | ||
1341 | static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) | |
1342 | { | |
a8f13961 | 1343 | TCGMemOpIdx oi = l->oi; |
3972ef6f | 1344 | TCGMemOp opc = get_memop(oi); |
ce0236cf | 1345 | TCGReg v0; |
9d8bf2d1 RH |
1346 | int i; |
1347 | ||
1348 | /* resolve label address */ | |
1349 | reloc_pc16(l->label_ptr[0], s->code_ptr); | |
f0d70331 | 1350 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 RH |
1351 | reloc_pc16(l->label_ptr[1], s->code_ptr); |
1352 | } | |
1353 | ||
ce0236cf | 1354 | i = 1; |
f0d70331 | 1355 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 RH |
1356 | i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); |
1357 | } else { | |
1358 | i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); | |
1359 | } | |
3972ef6f | 1360 | i = tcg_out_call_iarg_imm(s, i, oi); |
ce0236cf | 1361 | i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); |
2b7ec66f | 1362 | tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); |
ce0236cf RH |
1363 | /* delay slot */ |
1364 | tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); | |
9d8bf2d1 | 1365 | |
ce0236cf | 1366 | v0 = l->datalo_reg; |
f0d70331 | 1367 | if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { |
9d8bf2d1 RH |
1368 | /* We eliminated V0 from the possible output registers, so it |
1369 | cannot be clobbered here. So we must move V1 first. */ | |
ce0236cf RH |
1370 | if (MIPS_BE) { |
1371 | tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); | |
1372 | v0 = l->datahi_reg; | |
1373 | } else { | |
1374 | tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); | |
1375 | } | |
afa05235 AJ |
1376 | } |
1377 | ||
6d8ff4d8 | 1378 | tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); |
a31aa4ce RH |
1379 | reloc_pc16(s->code_ptr - 1, l->raddr); |
1380 | ||
ce0236cf | 1381 | /* delay slot */ |
f0d70331 JG |
1382 | if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { |
1383 | /* we always sign-extend 32-bit loads */ | |
1384 | tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); | |
1385 | } else { | |
1386 | tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); | |
1387 | } | |
9d8bf2d1 | 1388 | } |
afa05235 | 1389 | |
9d8bf2d1 RH |
1390 | static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) |
1391 | { | |
a8f13961 | 1392 | TCGMemOpIdx oi = l->oi; |
3972ef6f | 1393 | TCGMemOp opc = get_memop(oi); |
9d8bf2d1 RH |
1394 | TCGMemOp s_bits = opc & MO_SIZE; |
1395 | int i; | |
1396 | ||
1397 | /* resolve label address */ | |
1398 | reloc_pc16(l->label_ptr[0], s->code_ptr); | |
f0d70331 | 1399 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 RH |
1400 | reloc_pc16(l->label_ptr[1], s->code_ptr); |
1401 | } | |
afa05235 | 1402 | |
ce0236cf | 1403 | i = 1; |
f0d70331 | 1404 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
9d8bf2d1 | 1405 | i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); |
cc01cc8e | 1406 | } else { |
9d8bf2d1 RH |
1407 | i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); |
1408 | } | |
1409 | switch (s_bits) { | |
1410 | case MO_8: | |
1411 | i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); | |
1412 | break; | |
1413 | case MO_16: | |
1414 | i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); | |
1415 | break; | |
1416 | case MO_32: | |
1417 | i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); | |
1418 | break; | |
1419 | case MO_64: | |
f0d70331 JG |
1420 | if (TCG_TARGET_REG_BITS == 32) { |
1421 | i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); | |
1422 | } else { | |
1423 | i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); | |
1424 | } | |
9d8bf2d1 RH |
1425 | break; |
1426 | default: | |
1427 | tcg_abort(); | |
cc01cc8e | 1428 | } |
3972ef6f | 1429 | i = tcg_out_call_iarg_imm(s, i, oi); |
9d8bf2d1 | 1430 | |
ce0236cf RH |
1431 | /* Tail call to the store helper. Thus force the return address |
1432 | computation to take place in the return address register. */ | |
1433 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); | |
1434 | i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); | |
2b7ec66f | 1435 | tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); |
ce0236cf RH |
1436 | /* delay slot */ |
1437 | tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); | |
9d8bf2d1 | 1438 | } |
afa05235 AJ |
1439 | #endif |
1440 | ||
bb08afe9 | 1441 | static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, |
f0d70331 | 1442 | TCGReg base, TCGMemOp opc, bool is_64) |
9d8bf2d1 | 1443 | { |
4214a8cb | 1444 | switch (opc & (MO_SSIZE | MO_BSWAP)) { |
9d8bf2d1 | 1445 | case MO_UB: |
bb08afe9 | 1446 | tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); |
afa05235 | 1447 | break; |
9d8bf2d1 | 1448 | case MO_SB: |
bb08afe9 | 1449 | tcg_out_opc_imm(s, OPC_LB, lo, base, 0); |
afa05235 | 1450 | break; |
9d8bf2d1 | 1451 | case MO_UW | MO_BSWAP: |
6c530e32 | 1452 | tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); |
bb08afe9 | 1453 | tcg_out_bswap16(s, lo, TCG_TMP1); |
afa05235 | 1454 | break; |
9d8bf2d1 | 1455 | case MO_UW: |
bb08afe9 | 1456 | tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); |
afa05235 | 1457 | break; |
9d8bf2d1 | 1458 | case MO_SW | MO_BSWAP: |
6c530e32 | 1459 | tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); |
bb08afe9 | 1460 | tcg_out_bswap16s(s, lo, TCG_TMP1); |
afa05235 | 1461 | break; |
9d8bf2d1 | 1462 | case MO_SW: |
bb08afe9 | 1463 | tcg_out_opc_imm(s, OPC_LH, lo, base, 0); |
9d8bf2d1 RH |
1464 | break; |
1465 | case MO_UL | MO_BSWAP: | |
f0d70331 JG |
1466 | if (TCG_TARGET_REG_BITS == 64 && is_64) { |
1467 | if (use_mips32r2_instructions) { | |
1468 | tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); | |
1469 | tcg_out_bswap32u(s, lo, lo); | |
1470 | } else { | |
1471 | tcg_out_bswap_subr(s, bswap32u_addr); | |
1472 | /* delay slot */ | |
1473 | tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); | |
1474 | tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); | |
1475 | } | |
1476 | break; | |
1477 | } | |
1478 | /* FALLTHRU */ | |
1479 | case MO_SL | MO_BSWAP: | |
bb08afe9 JG |
1480 | if (use_mips32r2_instructions) { |
1481 | tcg_out_opc_imm(s, OPC_LW, lo, base, 0); | |
1482 | tcg_out_bswap32(s, lo, lo); | |
1483 | } else { | |
1484 | tcg_out_bswap_subr(s, bswap32_addr); | |
1485 | /* delay slot */ | |
1486 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); | |
1487 | tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); | |
1488 | } | |
9d8bf2d1 RH |
1489 | break; |
1490 | case MO_UL: | |
f0d70331 JG |
1491 | if (TCG_TARGET_REG_BITS == 64 && is_64) { |
1492 | tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); | |
1493 | break; | |
1494 | } | |
1495 | /* FALLTHRU */ | |
1496 | case MO_SL: | |
bb08afe9 | 1497 | tcg_out_opc_imm(s, OPC_LW, lo, base, 0); |
9d8bf2d1 RH |
1498 | break; |
1499 | case MO_Q | MO_BSWAP: | |
f0d70331 JG |
1500 | if (TCG_TARGET_REG_BITS == 64) { |
1501 | if (use_mips32r2_instructions) { | |
1502 | tcg_out_opc_imm(s, OPC_LD, lo, base, 0); | |
1503 | tcg_out_bswap64(s, lo, lo); | |
1504 | } else { | |
1505 | tcg_out_bswap_subr(s, bswap64_addr); | |
1506 | /* delay slot */ | |
1507 | tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); | |
1508 | tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); | |
1509 | } | |
1510 | } else if (use_mips32r2_instructions) { | |
bb08afe9 JG |
1511 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); |
1512 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); | |
1513 | tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); | |
1514 | tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); | |
1515 | tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); | |
1516 | tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); | |
1517 | } else { | |
1518 | tcg_out_bswap_subr(s, bswap32_addr); | |
1519 | /* delay slot */ | |
1520 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); | |
1521 | tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); | |
1522 | tcg_out_bswap_subr(s, bswap32_addr); | |
1523 | /* delay slot */ | |
1524 | tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); | |
1525 | tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); | |
1526 | } | |
9d8bf2d1 RH |
1527 | break; |
1528 | case MO_Q: | |
bb08afe9 | 1529 | /* Prefer to load from offset 0 first, but allow for overlap. */ |
f0d70331 JG |
1530 | if (TCG_TARGET_REG_BITS == 64) { |
1531 | tcg_out_opc_imm(s, OPC_LD, lo, base, 0); | |
1532 | } else if (MIPS_BE ? hi != base : lo == base) { | |
bb08afe9 JG |
1533 | tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); |
1534 | tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); | |
1535 | } else { | |
1536 | tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); | |
1537 | tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); | |
1538 | } | |
afa05235 AJ |
1539 | break; |
1540 | default: | |
1541 | tcg_abort(); | |
1542 | } | |
afa05235 AJ |
1543 | } |
1544 | ||
fbef2cc8 | 1545 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) |
afa05235 | 1546 | { |
9d8bf2d1 RH |
1547 | TCGReg addr_regl, addr_regh __attribute__((unused)); |
1548 | TCGReg data_regl, data_regh; | |
59227d5d | 1549 | TCGMemOpIdx oi; |
fbef2cc8 | 1550 | TCGMemOp opc; |
afa05235 | 1551 | #if defined(CONFIG_SOFTMMU) |
9d8bf2d1 | 1552 | tcg_insn_unit *label_ptr[2]; |
afa05235 | 1553 | #endif |
bb08afe9 | 1554 | TCGReg base = TCG_REG_A0; |
9d8bf2d1 | 1555 | |
afa05235 | 1556 | data_regl = *args++; |
f0d70331 | 1557 | data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); |
afa05235 | 1558 | addr_regl = *args++; |
f0d70331 | 1559 | addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); |
59227d5d RH |
1560 | oi = *args++; |
1561 | opc = get_memop(oi); | |
9d8bf2d1 | 1562 | |
0834c9ea | 1563 | #if defined(CONFIG_SOFTMMU) |
81dfaf1a | 1564 | tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); |
f0d70331 JG |
1565 | tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); |
1566 | add_qemu_ldst_label(s, 1, oi, | |
1567 | (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), | |
1568 | data_regl, data_regh, addr_regl, addr_regh, | |
3972ef6f | 1569 | s->code_ptr, label_ptr); |
0834c9ea | 1570 | #else |
f0d70331 JG |
1571 | if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { |
1572 | tcg_out_ext32u(s, base, addr_regl); | |
1573 | addr_regl = base; | |
1574 | } | |
b76f21a7 | 1575 | if (guest_base == 0 && data_regl != addr_regl) { |
9d8bf2d1 | 1576 | base = addr_regl; |
b76f21a7 | 1577 | } else if (guest_base == (int16_t)guest_base) { |
f0d70331 | 1578 | tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); |
0834c9ea | 1579 | } else { |
4df9cac5 | 1580 | tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); |
0834c9ea | 1581 | } |
f0d70331 | 1582 | tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); |
9d8bf2d1 RH |
1583 | #endif |
1584 | } | |
afa05235 | 1585 | |
bb08afe9 | 1586 | static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, |
9d8bf2d1 RH |
1587 | TCGReg base, TCGMemOp opc) |
1588 | { | |
bb08afe9 JG |
1589 | /* Don't clutter the code below with checks to avoid bswapping ZERO. */ |
1590 | if ((lo | hi) == 0) { | |
1591 | opc &= ~MO_BSWAP; | |
1592 | } | |
1593 | ||
4214a8cb | 1594 | switch (opc & (MO_SIZE | MO_BSWAP)) { |
9d8bf2d1 | 1595 | case MO_8: |
bb08afe9 | 1596 | tcg_out_opc_imm(s, OPC_SB, lo, base, 0); |
9d8bf2d1 | 1597 | break; |
afa05235 | 1598 | |
9d8bf2d1 | 1599 | case MO_16 | MO_BSWAP: |
bb08afe9 | 1600 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff); |
6c530e32 | 1601 | tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1); |
bb08afe9 | 1602 | lo = TCG_TMP1; |
9d8bf2d1 RH |
1603 | /* FALLTHRU */ |
1604 | case MO_16: | |
bb08afe9 | 1605 | tcg_out_opc_imm(s, OPC_SH, lo, base, 0); |
afa05235 | 1606 | break; |
9d8bf2d1 RH |
1607 | |
1608 | case MO_32 | MO_BSWAP: | |
bb08afe9 JG |
1609 | tcg_out_bswap32(s, TCG_TMP3, lo); |
1610 | lo = TCG_TMP3; | |
9d8bf2d1 RH |
1611 | /* FALLTHRU */ |
1612 | case MO_32: | |
bb08afe9 | 1613 | tcg_out_opc_imm(s, OPC_SW, lo, base, 0); |
afa05235 | 1614 | break; |
9d8bf2d1 RH |
1615 | |
1616 | case MO_64 | MO_BSWAP: | |
f0d70331 JG |
1617 | if (TCG_TARGET_REG_BITS == 64) { |
1618 | tcg_out_bswap64(s, TCG_TMP3, lo); | |
1619 | tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); | |
1620 | } else if (use_mips32r2_instructions) { | |
bb08afe9 JG |
1621 | tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); |
1622 | tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); | |
1623 | tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); | |
1624 | tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); | |
1625 | tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); | |
1626 | tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); | |
1627 | } else { | |
1628 | tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi); | |
1629 | tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); | |
1630 | tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo); | |
1631 | tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); | |
1632 | } | |
afa05235 | 1633 | break; |
9d8bf2d1 | 1634 | case MO_64: |
f0d70331 JG |
1635 | if (TCG_TARGET_REG_BITS == 64) { |
1636 | tcg_out_opc_imm(s, OPC_SD, lo, base, 0); | |
1637 | } else { | |
1638 | tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); | |
1639 | tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); | |
1640 | } | |
afa05235 | 1641 | break; |
9d8bf2d1 | 1642 | |
afa05235 AJ |
1643 | default: |
1644 | tcg_abort(); | |
1645 | } | |
9d8bf2d1 | 1646 | } |
afa05235 | 1647 | |
fbef2cc8 | 1648 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) |
9d8bf2d1 RH |
1649 | { |
1650 | TCGReg addr_regl, addr_regh __attribute__((unused)); | |
bb08afe9 | 1651 | TCGReg data_regl, data_regh; |
59227d5d | 1652 | TCGMemOpIdx oi; |
fbef2cc8 | 1653 | TCGMemOp opc; |
9d8bf2d1 RH |
1654 | #if defined(CONFIG_SOFTMMU) |
1655 | tcg_insn_unit *label_ptr[2]; | |
9d8bf2d1 | 1656 | #endif |
bb08afe9 | 1657 | TCGReg base = TCG_REG_A0; |
9d8bf2d1 RH |
1658 | |
1659 | data_regl = *args++; | |
f0d70331 | 1660 | data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); |
9d8bf2d1 | 1661 | addr_regl = *args++; |
f0d70331 | 1662 | addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); |
59227d5d RH |
1663 | oi = *args++; |
1664 | opc = get_memop(oi); | |
afa05235 | 1665 | |
9d8bf2d1 | 1666 | #if defined(CONFIG_SOFTMMU) |
81dfaf1a | 1667 | tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); |
9d8bf2d1 | 1668 | tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); |
f0d70331 JG |
1669 | add_qemu_ldst_label(s, 0, oi, |
1670 | (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), | |
1671 | data_regl, data_regh, addr_regl, addr_regh, | |
3972ef6f | 1672 | s->code_ptr, label_ptr); |
cc01cc8e | 1673 | #else |
f0d70331 JG |
1674 | base = TCG_REG_A0; |
1675 | if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { | |
1676 | tcg_out_ext32u(s, base, addr_regl); | |
1677 | addr_regl = base; | |
1678 | } | |
b76f21a7 | 1679 | if (guest_base == 0) { |
9d8bf2d1 | 1680 | base = addr_regl; |
f0d70331 JG |
1681 | } else if (guest_base == (int16_t)guest_base) { |
1682 | tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); | |
cc01cc8e | 1683 | } else { |
4df9cac5 | 1684 | tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); |
afa05235 | 1685 | } |
9d8bf2d1 | 1686 | tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); |
afa05235 AJ |
1687 | #endif |
1688 | } | |
1689 | ||
6f0b9910 PK |
1690 | static void tcg_out_mb(TCGContext *s, TCGArg a0) |
1691 | { | |
1692 | static const MIPSInsn sync[] = { | |
1693 | /* Note that SYNC_MB is a slightly weaker than SYNC 0, | |
1694 | as the former is an ordering barrier and the latter | |
1695 | is a completion barrier. */ | |
1696 | [0 ... TCG_MO_ALL] = OPC_SYNC_MB, | |
1697 | [TCG_MO_LD_LD] = OPC_SYNC_RMB, | |
1698 | [TCG_MO_ST_ST] = OPC_SYNC_WMB, | |
1699 | [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, | |
1700 | [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, | |
1701 | [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, | |
1702 | }; | |
1703 | tcg_out32(s, sync[a0 & TCG_MO_ALL]); | |
1704 | } | |
1705 | ||
2a1d9d41 RH |
1706 | static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, |
1707 | int width, TCGReg a0, TCGReg a1, TCGArg a2) | |
1708 | { | |
1709 | if (use_mips32r6_instructions) { | |
1710 | if (a2 == width) { | |
1711 | tcg_out_opc_reg(s, opcv6, a0, a1, 0); | |
1712 | } else { | |
1713 | tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); | |
1714 | tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); | |
1715 | } | |
1716 | } else { | |
1717 | if (a2 == width) { | |
1718 | tcg_out_opc_reg(s, opcv2, a0, a1, a1); | |
1719 | } else if (a0 == a2) { | |
1720 | tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); | |
1721 | tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); | |
1722 | } else if (a0 != a1) { | |
1723 | tcg_out_opc_reg(s, opcv2, a0, a1, a1); | |
1724 | tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); | |
1725 | } else { | |
1726 | tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); | |
1727 | tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); | |
1728 | tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); | |
1729 | } | |
1730 | } | |
1731 | } | |
1732 | ||
a9751609 | 1733 | static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, |
afa05235 AJ |
1734 | const TCGArg *args, const int *const_args) |
1735 | { | |
4f048535 | 1736 | MIPSInsn i1, i2; |
22ee3a98 RH |
1737 | TCGArg a0, a1, a2; |
1738 | int c2; | |
1739 | ||
1740 | a0 = args[0]; | |
1741 | a1 = args[1]; | |
1742 | a2 = args[2]; | |
1743 | c2 = const_args[2]; | |
1744 | ||
1745 | switch (opc) { | |
afa05235 | 1746 | case INDEX_op_exit_tb: |
7dae901d | 1747 | { |
7dae901d RH |
1748 | TCGReg b0 = TCG_REG_ZERO; |
1749 | ||
0119b192 | 1750 | a0 = (intptr_t)a0; |
7dae901d RH |
1751 | if (a0 & ~0xffff) { |
1752 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); | |
1753 | b0 = TCG_REG_V0; | |
1754 | } | |
1755 | if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { | |
6c530e32 | 1756 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, |
7dae901d | 1757 | (uintptr_t)tb_ret_addr); |
6c530e32 | 1758 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); |
7dae901d RH |
1759 | } |
1760 | tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); | |
f8c9eddb | 1761 | } |
afa05235 AJ |
1762 | break; |
1763 | case INDEX_op_goto_tb: | |
f309101c | 1764 | if (s->tb_jmp_insn_offset) { |
afa05235 | 1765 | /* direct jump method */ |
f309101c | 1766 | s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); |
b6bfeea9 RH |
1767 | /* Avoid clobbering the address during retranslation. */ |
1768 | tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); | |
afa05235 AJ |
1769 | } else { |
1770 | /* indirect jump method */ | |
6c530e32 | 1771 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, |
f309101c | 1772 | (uintptr_t)(s->tb_jmp_target_addr + a0)); |
6c530e32 | 1773 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); |
afa05235 AJ |
1774 | } |
1775 | tcg_out_nop(s); | |
9f754620 | 1776 | set_jmp_reset_offset(s, a0); |
afa05235 | 1777 | break; |
5786e068 AJ |
1778 | case INDEX_op_goto_ptr: |
1779 | /* jmp to the given host address (could be epilogue) */ | |
1780 | tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); | |
1781 | tcg_out_nop(s); | |
1782 | break; | |
afa05235 | 1783 | case INDEX_op_br: |
bec16311 RH |
1784 | tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, |
1785 | arg_label(a0)); | |
afa05235 AJ |
1786 | break; |
1787 | ||
afa05235 | 1788 | case INDEX_op_ld8u_i32: |
0119b192 | 1789 | case INDEX_op_ld8u_i64: |
4f048535 RH |
1790 | i1 = OPC_LBU; |
1791 | goto do_ldst; | |
afa05235 | 1792 | case INDEX_op_ld8s_i32: |
0119b192 | 1793 | case INDEX_op_ld8s_i64: |
4f048535 RH |
1794 | i1 = OPC_LB; |
1795 | goto do_ldst; | |
afa05235 | 1796 | case INDEX_op_ld16u_i32: |
0119b192 | 1797 | case INDEX_op_ld16u_i64: |
4f048535 RH |
1798 | i1 = OPC_LHU; |
1799 | goto do_ldst; | |
afa05235 | 1800 | case INDEX_op_ld16s_i32: |
0119b192 | 1801 | case INDEX_op_ld16s_i64: |
4f048535 RH |
1802 | i1 = OPC_LH; |
1803 | goto do_ldst; | |
afa05235 | 1804 | case INDEX_op_ld_i32: |
0119b192 | 1805 | case INDEX_op_ld32s_i64: |
4f048535 RH |
1806 | i1 = OPC_LW; |
1807 | goto do_ldst; | |
0119b192 JG |
1808 | case INDEX_op_ld32u_i64: |
1809 | i1 = OPC_LWU; | |
1810 | goto do_ldst; | |
1811 | case INDEX_op_ld_i64: | |
1812 | i1 = OPC_LD; | |
1813 | goto do_ldst; | |
afa05235 | 1814 | case INDEX_op_st8_i32: |
0119b192 | 1815 | case INDEX_op_st8_i64: |
4f048535 RH |
1816 | i1 = OPC_SB; |
1817 | goto do_ldst; | |
afa05235 | 1818 | case INDEX_op_st16_i32: |
0119b192 | 1819 | case INDEX_op_st16_i64: |
4f048535 RH |
1820 | i1 = OPC_SH; |
1821 | goto do_ldst; | |
afa05235 | 1822 | case INDEX_op_st_i32: |
0119b192 | 1823 | case INDEX_op_st32_i64: |
4f048535 | 1824 | i1 = OPC_SW; |
0119b192 JG |
1825 | goto do_ldst; |
1826 | case INDEX_op_st_i64: | |
1827 | i1 = OPC_SD; | |
4f048535 RH |
1828 | do_ldst: |
1829 | tcg_out_ldst(s, i1, a0, a1, a2); | |
afa05235 AJ |
1830 | break; |
1831 | ||
1832 | case INDEX_op_add_i32: | |
4f048535 RH |
1833 | i1 = OPC_ADDU, i2 = OPC_ADDIU; |
1834 | goto do_binary; | |
0119b192 JG |
1835 | case INDEX_op_add_i64: |
1836 | i1 = OPC_DADDU, i2 = OPC_DADDIU; | |
1837 | goto do_binary; | |
4f048535 | 1838 | case INDEX_op_or_i32: |
0119b192 | 1839 | case INDEX_op_or_i64: |
4f048535 RH |
1840 | i1 = OPC_OR, i2 = OPC_ORI; |
1841 | goto do_binary; | |
1842 | case INDEX_op_xor_i32: | |
0119b192 | 1843 | case INDEX_op_xor_i64: |
4f048535 RH |
1844 | i1 = OPC_XOR, i2 = OPC_XORI; |
1845 | do_binary: | |
22ee3a98 | 1846 | if (c2) { |
4f048535 RH |
1847 | tcg_out_opc_imm(s, i2, a0, a1, a2); |
1848 | break; | |
afa05235 | 1849 | } |
4f048535 RH |
1850 | do_binaryv: |
1851 | tcg_out_opc_reg(s, i1, a0, a1, a2); | |
afa05235 | 1852 | break; |
4f048535 | 1853 | |
afa05235 | 1854 | case INDEX_op_sub_i32: |
0119b192 JG |
1855 | i1 = OPC_SUBU, i2 = OPC_ADDIU; |
1856 | goto do_subtract; | |
1857 | case INDEX_op_sub_i64: | |
1858 | i1 = OPC_DSUBU, i2 = OPC_DADDIU; | |
1859 | do_subtract: | |
22ee3a98 | 1860 | if (c2) { |
0119b192 | 1861 | tcg_out_opc_imm(s, i2, a0, a1, -a2); |
4f048535 | 1862 | break; |
afa05235 | 1863 | } |
0119b192 | 1864 | goto do_binaryv; |
4f048535 RH |
1865 | case INDEX_op_and_i32: |
1866 | if (c2 && a2 != (uint16_t)a2) { | |
1867 | int msb = ctz32(~a2) - 1; | |
eabb7b91 AJ |
1868 | tcg_debug_assert(use_mips32r2_instructions); |
1869 | tcg_debug_assert(is_p2m1(a2)); | |
4f048535 RH |
1870 | tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); |
1871 | break; | |
1872 | } | |
1873 | i1 = OPC_AND, i2 = OPC_ANDI; | |
1874 | goto do_binary; | |
0119b192 JG |
1875 | case INDEX_op_and_i64: |
1876 | if (c2 && a2 != (uint16_t)a2) { | |
1877 | int msb = ctz64(~a2) - 1; | |
1878 | tcg_debug_assert(use_mips32r2_instructions); | |
1879 | tcg_debug_assert(is_p2m1(a2)); | |
1880 | tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); | |
1881 | break; | |
1882 | } | |
1883 | i1 = OPC_AND, i2 = OPC_ANDI; | |
1884 | goto do_binary; | |
4f048535 | 1885 | case INDEX_op_nor_i32: |
0119b192 | 1886 | case INDEX_op_nor_i64: |
4f048535 RH |
1887 | i1 = OPC_NOR; |
1888 | goto do_binaryv; | |
1889 | ||
afa05235 | 1890 | case INDEX_op_mul_i32: |
988902fc | 1891 | if (use_mips32_instructions) { |
22ee3a98 | 1892 | tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); |
4f048535 | 1893 | break; |
988902fc | 1894 | } |
4f048535 RH |
1895 | i1 = OPC_MULT, i2 = OPC_MFLO; |
1896 | goto do_hilo1; | |
3c9a8f17 | 1897 | case INDEX_op_mulsh_i32: |
bc6d0c22 JH |
1898 | if (use_mips32r6_instructions) { |
1899 | tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); | |
1900 | break; | |
1901 | } | |
4f048535 RH |
1902 | i1 = OPC_MULT, i2 = OPC_MFHI; |
1903 | goto do_hilo1; | |
3c9a8f17 | 1904 | case INDEX_op_muluh_i32: |
bc6d0c22 JH |
1905 | if (use_mips32r6_instructions) { |
1906 | tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); | |
1907 | break; | |
1908 | } | |
4f048535 RH |
1909 | i1 = OPC_MULTU, i2 = OPC_MFHI; |
1910 | goto do_hilo1; | |
afa05235 | 1911 | case INDEX_op_div_i32: |
bc6d0c22 JH |
1912 | if (use_mips32r6_instructions) { |
1913 | tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); | |
1914 | break; | |
1915 | } | |
4f048535 RH |
1916 | i1 = OPC_DIV, i2 = OPC_MFLO; |
1917 | goto do_hilo1; | |
afa05235 | 1918 | case INDEX_op_divu_i32: |
bc6d0c22 JH |
1919 | if (use_mips32r6_instructions) { |
1920 | tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); | |
1921 | break; | |
1922 | } | |
4f048535 RH |
1923 | i1 = OPC_DIVU, i2 = OPC_MFLO; |
1924 | goto do_hilo1; | |
afa05235 | 1925 | case INDEX_op_rem_i32: |
bc6d0c22 JH |
1926 | if (use_mips32r6_instructions) { |
1927 | tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); | |
1928 | break; | |
1929 | } | |
4f048535 RH |
1930 | i1 = OPC_DIV, i2 = OPC_MFHI; |
1931 | goto do_hilo1; | |
afa05235 | 1932 | case INDEX_op_remu_i32: |
bc6d0c22 JH |
1933 | if (use_mips32r6_instructions) { |
1934 | tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); | |
1935 | break; | |
1936 | } | |
4f048535 | 1937 | i1 = OPC_DIVU, i2 = OPC_MFHI; |
0119b192 JG |
1938 | goto do_hilo1; |
1939 | case INDEX_op_mul_i64: | |
1940 | if (use_mips32r6_instructions) { | |
1941 | tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); | |
1942 | break; | |
1943 | } | |
1944 | i1 = OPC_DMULT, i2 = OPC_MFLO; | |
1945 | goto do_hilo1; | |
1946 | case INDEX_op_mulsh_i64: | |
1947 | if (use_mips32r6_instructions) { | |
1948 | tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); | |
1949 | break; | |
1950 | } | |
1951 | i1 = OPC_DMULT, i2 = OPC_MFHI; | |
1952 | goto do_hilo1; | |
1953 | case INDEX_op_muluh_i64: | |
1954 | if (use_mips32r6_instructions) { | |
1955 | tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); | |
1956 | break; | |
1957 | } | |
1958 | i1 = OPC_DMULTU, i2 = OPC_MFHI; | |
1959 | goto do_hilo1; | |
1960 | case INDEX_op_div_i64: | |
1961 | if (use_mips32r6_instructions) { | |
1962 | tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); | |
1963 | break; | |
1964 | } | |
1965 | i1 = OPC_DDIV, i2 = OPC_MFLO; | |
1966 | goto do_hilo1; | |
1967 | case INDEX_op_divu_i64: | |
1968 | if (use_mips32r6_instructions) { | |
1969 | tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); | |
1970 | break; | |
1971 | } | |
1972 | i1 = OPC_DDIVU, i2 = OPC_MFLO; | |
1973 | goto do_hilo1; | |
1974 | case INDEX_op_rem_i64: | |
1975 | if (use_mips32r6_instructions) { | |
1976 | tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); | |
1977 | break; | |
1978 | } | |
1979 | i1 = OPC_DDIV, i2 = OPC_MFHI; | |
1980 | goto do_hilo1; | |
1981 | case INDEX_op_remu_i64: | |
1982 | if (use_mips32r6_instructions) { | |
1983 | tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); | |
1984 | break; | |
1985 | } | |
1986 | i1 = OPC_DDIVU, i2 = OPC_MFHI; | |
4f048535 RH |
1987 | do_hilo1: |
1988 | tcg_out_opc_reg(s, i1, 0, a1, a2); | |
1989 | tcg_out_opc_reg(s, i2, a0, 0, 0); | |
afa05235 AJ |
1990 | break; |
1991 | ||
4f048535 RH |
1992 | case INDEX_op_muls2_i32: |
1993 | i1 = OPC_MULT; | |
1994 | goto do_hilo2; | |
1995 | case INDEX_op_mulu2_i32: | |
1996 | i1 = OPC_MULTU; | |
0119b192 JG |
1997 | goto do_hilo2; |
1998 | case INDEX_op_muls2_i64: | |
1999 | i1 = OPC_DMULT; | |
2000 | goto do_hilo2; | |
2001 | case INDEX_op_mulu2_i64: | |
2002 | i1 = OPC_DMULTU; | |
4f048535 RH |
2003 | do_hilo2: |
2004 | tcg_out_opc_reg(s, i1, 0, a2, args[3]); | |
2005 | tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); | |
2006 | tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); | |
2b79487a | 2007 | break; |
4f048535 | 2008 | |
afa05235 | 2009 | case INDEX_op_not_i32: |
0119b192 | 2010 | case INDEX_op_not_i64: |
4f048535 RH |
2011 | i1 = OPC_NOR; |
2012 | goto do_unary; | |
2013 | case INDEX_op_bswap16_i32: | |
0119b192 | 2014 | case INDEX_op_bswap16_i64: |
4f048535 RH |
2015 | i1 = OPC_WSBH; |
2016 | goto do_unary; | |
2017 | case INDEX_op_ext8s_i32: | |
0119b192 | 2018 | case INDEX_op_ext8s_i64: |
4f048535 RH |
2019 | i1 = OPC_SEB; |
2020 | goto do_unary; | |
2021 | case INDEX_op_ext16s_i32: | |
0119b192 | 2022 | case INDEX_op_ext16s_i64: |
4f048535 RH |
2023 | i1 = OPC_SEH; |
2024 | do_unary: | |
2025 | tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); | |
afa05235 AJ |
2026 | break; |
2027 | ||
0119b192 JG |
2028 | case INDEX_op_bswap32_i32: |
2029 | tcg_out_bswap32(s, a0, a1); | |
2030 | break; | |
2031 | case INDEX_op_bswap32_i64: | |
2032 | tcg_out_bswap32u(s, a0, a1); | |
2033 | break; | |
2034 | case INDEX_op_bswap64_i64: | |
2035 | tcg_out_bswap64(s, a0, a1); | |
2036 | break; | |
2037 | case INDEX_op_extrh_i64_i32: | |
2038 | tcg_out_dsra(s, a0, a1, 32); | |
2039 | break; | |
2040 | case INDEX_op_ext32s_i64: | |
2041 | case INDEX_op_ext_i32_i64: | |
2042 | case INDEX_op_extrl_i64_i32: | |
2043 | tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); | |
2044 | break; | |
2045 | case INDEX_op_ext32u_i64: | |
2046 | case INDEX_op_extu_i32_i64: | |
2047 | tcg_out_ext32u(s, a0, a1); | |
2048 | break; | |
2049 | ||
afa05235 | 2050 | case INDEX_op_sar_i32: |
4f048535 RH |
2051 | i1 = OPC_SRAV, i2 = OPC_SRA; |
2052 | goto do_shift; | |
afa05235 | 2053 | case INDEX_op_shl_i32: |
4f048535 RH |
2054 | i1 = OPC_SLLV, i2 = OPC_SLL; |
2055 | goto do_shift; | |
afa05235 | 2056 | case INDEX_op_shr_i32: |
4f048535 RH |
2057 | i1 = OPC_SRLV, i2 = OPC_SRL; |
2058 | goto do_shift; | |
2059 | case INDEX_op_rotr_i32: | |
2060 | i1 = OPC_ROTRV, i2 = OPC_ROTR; | |
2061 | do_shift: | |
22ee3a98 | 2062 | if (c2) { |
4f048535 | 2063 | tcg_out_opc_sa(s, i2, a0, a1, a2); |
0119b192 | 2064 | break; |
afa05235 | 2065 | } |
0119b192 JG |
2066 | do_shiftv: |
2067 | tcg_out_opc_reg(s, i1, a0, a2, a1); | |
afa05235 | 2068 | break; |
9a152519 | 2069 | case INDEX_op_rotl_i32: |
22ee3a98 RH |
2070 | if (c2) { |
2071 | tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); | |
9a152519 | 2072 | } else { |
22ee3a98 RH |
2073 | tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); |
2074 | tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); | |
9a152519 AJ |
2075 | } |
2076 | break; | |
0119b192 JG |
2077 | case INDEX_op_sar_i64: |
2078 | if (c2) { | |
2079 | tcg_out_dsra(s, a0, a1, a2); | |
2080 | break; | |
2081 | } | |
2082 | i1 = OPC_DSRAV; | |
2083 | goto do_shiftv; | |
2084 | case INDEX_op_shl_i64: | |
2085 | if (c2) { | |
2086 | tcg_out_dsll(s, a0, a1, a2); | |
2087 | break; | |
2088 | } | |
2089 | i1 = OPC_DSLLV; | |
2090 | goto do_shiftv; | |
2091 | case INDEX_op_shr_i64: | |
2092 | if (c2) { | |
2093 | tcg_out_dsrl(s, a0, a1, a2); | |
2094 | break; | |
2095 | } | |
2096 | i1 = OPC_DSRLV; | |
2097 | goto do_shiftv; | |
2098 | case INDEX_op_rotr_i64: | |
2099 | if (c2) { | |
2100 | tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); | |
2101 | break; | |
2102 | } | |
2103 | i1 = OPC_DROTRV; | |
2104 | goto do_shiftv; | |
2105 | case INDEX_op_rotl_i64: | |
2106 | if (c2) { | |
2107 | tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); | |
2108 | } else { | |
2109 | tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); | |
2110 | tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); | |
2111 | } | |
c1cf85c9 AJ |
2112 | break; |
2113 | ||
2a1d9d41 RH |
2114 | case INDEX_op_clz_i32: |
2115 | tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); | |
2116 | break; | |
2117 | case INDEX_op_clz_i64: | |
2118 | tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); | |
2119 | break; | |
2120 | ||
04f71aa3 | 2121 | case INDEX_op_deposit_i32: |
22ee3a98 | 2122 | tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); |
04f71aa3 | 2123 | break; |
0119b192 JG |
2124 | case INDEX_op_deposit_i64: |
2125 | tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, | |
2126 | args[3] + args[4] - 1, args[3]); | |
2127 | break; | |
befbb3ce | 2128 | case INDEX_op_extract_i32: |
2f5a5f57 | 2129 | tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); |
befbb3ce RH |
2130 | break; |
2131 | case INDEX_op_extract_i64: | |
2132 | tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, | |
2f5a5f57 | 2133 | args[3] - 1, a2); |
befbb3ce | 2134 | break; |
04f71aa3 | 2135 | |
afa05235 | 2136 | case INDEX_op_brcond_i32: |
0119b192 | 2137 | case INDEX_op_brcond_i64: |
bec16311 | 2138 | tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); |
afa05235 AJ |
2139 | break; |
2140 | case INDEX_op_brcond2_i32: | |
bec16311 | 2141 | tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); |
afa05235 AJ |
2142 | break; |
2143 | ||
7d7c4930 | 2144 | case INDEX_op_movcond_i32: |
0119b192 | 2145 | case INDEX_op_movcond_i64: |
137d6390 | 2146 | tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); |
7d7c4930 AJ |
2147 | break; |
2148 | ||
4cb26382 | 2149 | case INDEX_op_setcond_i32: |
0119b192 | 2150 | case INDEX_op_setcond_i64: |
22ee3a98 | 2151 | tcg_out_setcond(s, args[3], a0, a1, a2); |
4cb26382 | 2152 | break; |
434254aa | 2153 | case INDEX_op_setcond2_i32: |
22ee3a98 | 2154 | tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); |
434254aa | 2155 | break; |
4cb26382 | 2156 | |
fbef2cc8 RH |
2157 | case INDEX_op_qemu_ld_i32: |
2158 | tcg_out_qemu_ld(s, args, false); | |
afa05235 | 2159 | break; |
fbef2cc8 RH |
2160 | case INDEX_op_qemu_ld_i64: |
2161 | tcg_out_qemu_ld(s, args, true); | |
afa05235 | 2162 | break; |
fbef2cc8 RH |
2163 | case INDEX_op_qemu_st_i32: |
2164 | tcg_out_qemu_st(s, args, false); | |
afa05235 | 2165 | break; |
fbef2cc8 RH |
2166 | case INDEX_op_qemu_st_i64: |
2167 | tcg_out_qemu_st(s, args, true); | |
afa05235 AJ |
2168 | break; |
2169 | ||
741f117d RH |
2170 | case INDEX_op_add2_i32: |
2171 | tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], | |
2172 | const_args[4], const_args[5], false); | |
2173 | break; | |
2174 | case INDEX_op_sub2_i32: | |
2175 | tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], | |
2176 | const_args[4], const_args[5], true); | |
2177 | break; | |
2178 | ||
6f0b9910 PK |
2179 | case INDEX_op_mb: |
2180 | tcg_out_mb(s, a0); | |
2181 | break; | |
96d0ee7f | 2182 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ |
0119b192 | 2183 | case INDEX_op_mov_i64: |
96d0ee7f | 2184 | case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ |
0119b192 | 2185 | case INDEX_op_movi_i64: |
96d0ee7f | 2186 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ |
afa05235 AJ |
2187 | default: |
2188 | tcg_abort(); | |
2189 | } | |
2190 | } | |
2191 | ||
89b2e37e RH |
2192 | static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) |
2193 | { | |
2194 | static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; | |
2195 | static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; | |
2196 | static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; | |
2197 | static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; | |
2198 | static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } }; | |
2199 | static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } }; | |
2200 | static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; | |
2201 | static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; | |
2202 | static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; | |
2203 | static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; | |
2204 | static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } }; | |
2205 | static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } }; | |
2206 | static const TCGTargetOpDef SZ_SZ_S | |
2207 | = { .args_ct_str = { "SZ", "SZ", "S" } }; | |
2208 | static const TCGTargetOpDef SZ_SZ_S_S | |
2209 | = { .args_ct_str = { "SZ", "SZ", "S", "S" } }; | |
2210 | static const TCGTargetOpDef r_rZ_rN | |
2211 | = { .args_ct_str = { "r", "rZ", "rN" } }; | |
2212 | static const TCGTargetOpDef r_rZ_rZ | |
2213 | = { .args_ct_str = { "r", "rZ", "rZ" } }; | |
2214 | static const TCGTargetOpDef r_r_rIK | |
2215 | = { .args_ct_str = { "r", "r", "rIK" } }; | |
2216 | static const TCGTargetOpDef r_r_rWZ | |
2217 | = { .args_ct_str = { "r", "r", "rWZ" } }; | |
2218 | static const TCGTargetOpDef r_r_r_r | |
2219 | = { .args_ct_str = { "r", "r", "r", "r" } }; | |
2220 | static const TCGTargetOpDef r_r_L_L | |
2221 | = { .args_ct_str = { "r", "r", "L", "L" } }; | |
2222 | static const TCGTargetOpDef dep | |
2223 | = { .args_ct_str = { "r", "0", "rZ" } }; | |
2224 | static const TCGTargetOpDef movc | |
2225 | = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } }; | |
2226 | static const TCGTargetOpDef movc_r6 | |
2227 | = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; | |
2228 | static const TCGTargetOpDef add2 | |
2229 | = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } }; | |
2230 | static const TCGTargetOpDef br2 | |
2231 | = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; | |
2232 | static const TCGTargetOpDef setc2 | |
2233 | = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; | |
2234 | ||
2235 | switch (op) { | |
2236 | case INDEX_op_goto_ptr: | |
2237 | return &r; | |
afa05235 | 2238 | |
89b2e37e RH |
2239 | case INDEX_op_ld8u_i32: |
2240 | case INDEX_op_ld8s_i32: | |
2241 | case INDEX_op_ld16u_i32: | |
2242 | case INDEX_op_ld16s_i32: | |
2243 | case INDEX_op_ld_i32: | |
2244 | case INDEX_op_not_i32: | |
2245 | case INDEX_op_bswap16_i32: | |
2246 | case INDEX_op_bswap32_i32: | |
2247 | case INDEX_op_ext8s_i32: | |
2248 | case INDEX_op_ext16s_i32: | |
2249 | case INDEX_op_extract_i32: | |
2250 | case INDEX_op_ld8u_i64: | |
2251 | case INDEX_op_ld8s_i64: | |
2252 | case INDEX_op_ld16u_i64: | |
2253 | case INDEX_op_ld16s_i64: | |
2254 | case INDEX_op_ld32s_i64: | |
2255 | case INDEX_op_ld32u_i64: | |
2256 | case INDEX_op_ld_i64: | |
2257 | case INDEX_op_not_i64: | |
2258 | case INDEX_op_bswap16_i64: | |
2259 | case INDEX_op_bswap32_i64: | |
2260 | case INDEX_op_bswap64_i64: | |
2261 | case INDEX_op_ext8s_i64: | |
2262 | case INDEX_op_ext16s_i64: | |
2263 | case INDEX_op_ext32s_i64: | |
2264 | case INDEX_op_ext32u_i64: | |
2265 | case INDEX_op_ext_i32_i64: | |
2266 | case INDEX_op_extu_i32_i64: | |
2267 | case INDEX_op_extrl_i64_i32: | |
2268 | case INDEX_op_extrh_i64_i32: | |
2269 | case INDEX_op_extract_i64: | |
2270 | return &r_r; | |
afa05235 | 2271 | |
89b2e37e RH |
2272 | case INDEX_op_st8_i32: |
2273 | case INDEX_op_st16_i32: | |
2274 | case INDEX_op_st_i32: | |
2275 | case INDEX_op_st8_i64: | |
2276 | case INDEX_op_st16_i64: | |
2277 | case INDEX_op_st32_i64: | |
2278 | case INDEX_op_st_i64: | |
2279 | return &rZ_r; | |
6f0b9910 | 2280 | |
89b2e37e RH |
2281 | case INDEX_op_add_i32: |
2282 | case INDEX_op_add_i64: | |
2283 | return &r_r_rJ; | |
2284 | case INDEX_op_sub_i32: | |
2285 | case INDEX_op_sub_i64: | |
2286 | return &r_rZ_rN; | |
2287 | case INDEX_op_mul_i32: | |
2288 | case INDEX_op_mulsh_i32: | |
2289 | case INDEX_op_muluh_i32: | |
2290 | case INDEX_op_div_i32: | |
2291 | case INDEX_op_divu_i32: | |
2292 | case INDEX_op_rem_i32: | |
2293 | case INDEX_op_remu_i32: | |
2294 | case INDEX_op_nor_i32: | |
2295 | case INDEX_op_setcond_i32: | |
2296 | case INDEX_op_mul_i64: | |
2297 | case INDEX_op_mulsh_i64: | |
2298 | case INDEX_op_muluh_i64: | |
2299 | case INDEX_op_div_i64: | |
2300 | case INDEX_op_divu_i64: | |
2301 | case INDEX_op_rem_i64: | |
2302 | case INDEX_op_remu_i64: | |
2303 | case INDEX_op_nor_i64: | |
2304 | case INDEX_op_setcond_i64: | |
2305 | return &r_rZ_rZ; | |
2306 | case INDEX_op_muls2_i32: | |
2307 | case INDEX_op_mulu2_i32: | |
2308 | case INDEX_op_muls2_i64: | |
2309 | case INDEX_op_mulu2_i64: | |
2310 | return &r_r_r_r; | |
2311 | case INDEX_op_and_i32: | |
2312 | case INDEX_op_and_i64: | |
2313 | return &r_r_rIK; | |
2314 | case INDEX_op_or_i32: | |
2315 | case INDEX_op_xor_i32: | |
2316 | case INDEX_op_or_i64: | |
2317 | case INDEX_op_xor_i64: | |
2318 | return &r_r_rI; | |
2319 | case INDEX_op_shl_i32: | |
2320 | case INDEX_op_shr_i32: | |
2321 | case INDEX_op_sar_i32: | |
2322 | case INDEX_op_rotr_i32: | |
2323 | case INDEX_op_rotl_i32: | |
2324 | case INDEX_op_shl_i64: | |
2325 | case INDEX_op_shr_i64: | |
2326 | case INDEX_op_sar_i64: | |
2327 | case INDEX_op_rotr_i64: | |
2328 | case INDEX_op_rotl_i64: | |
2329 | return &r_r_ri; | |
2330 | case INDEX_op_clz_i32: | |
2331 | case INDEX_op_clz_i64: | |
2332 | return &r_r_rWZ; | |
afa05235 | 2333 | |
89b2e37e RH |
2334 | case INDEX_op_deposit_i32: |
2335 | case INDEX_op_deposit_i64: | |
2336 | return &dep; | |
2337 | case INDEX_op_brcond_i32: | |
2338 | case INDEX_op_brcond_i64: | |
2339 | return &rZ_rZ; | |
2340 | case INDEX_op_movcond_i32: | |
2341 | case INDEX_op_movcond_i64: | |
2342 | return use_mips32r6_instructions ? &movc_r6 : &movc; | |
f69d277e | 2343 | |
89b2e37e RH |
2344 | case INDEX_op_add2_i32: |
2345 | case INDEX_op_sub2_i32: | |
2346 | return &add2; | |
2347 | case INDEX_op_setcond2_i32: | |
2348 | return &setc2; | |
2349 | case INDEX_op_brcond2_i32: | |
2350 | return &br2; | |
2351 | ||
2352 | case INDEX_op_qemu_ld_i32: | |
2353 | return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 | |
2354 | ? &r_L : &r_L_L); | |
2355 | case INDEX_op_qemu_st_i32: | |
2356 | return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 | |
2357 | ? &SZ_S : &SZ_S_S); | |
2358 | case INDEX_op_qemu_ld_i64: | |
2359 | return (TCG_TARGET_REG_BITS == 64 ? &r_L | |
2360 | : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L); | |
2361 | case INDEX_op_qemu_st_i64: | |
2362 | return (TCG_TARGET_REG_BITS == 64 ? &SZ_S | |
2363 | : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S); | |
2364 | ||
2365 | default: | |
2366 | return NULL; | |
f69d277e | 2367 | } |
f69d277e RH |
2368 | } |
2369 | ||
d453ec78 | 2370 | static const int tcg_target_callee_save_regs[] = { |
cea5f9a2 | 2371 | TCG_REG_S0, /* used for the global env (TCG_AREG0) */ |
afa05235 AJ |
2372 | TCG_REG_S1, |
2373 | TCG_REG_S2, | |
2374 | TCG_REG_S3, | |
2375 | TCG_REG_S4, | |
2376 | TCG_REG_S5, | |
2377 | TCG_REG_S6, | |
2378 | TCG_REG_S7, | |
41883904 | 2379 | TCG_REG_S8, |
afa05235 AJ |
2380 | TCG_REG_RA, /* should be last for ABI compliance */ |
2381 | }; | |
2382 | ||
988902fc AJ |
2383 | /* The Linux kernel doesn't provide any information about the available |
2384 | instruction set. Probe it using a signal handler. */ | |
2385 | ||
988902fc AJ |
2386 | |
2387 | #ifndef use_movnz_instructions | |
2388 | bool use_movnz_instructions = false; | |
2389 | #endif | |
2390 | ||
2391 | #ifndef use_mips32_instructions | |
2392 | bool use_mips32_instructions = false; | |
2393 | #endif | |
2394 | ||
2395 | #ifndef use_mips32r2_instructions | |
2396 | bool use_mips32r2_instructions = false; | |
2397 | #endif | |
2398 | ||
2399 | static volatile sig_atomic_t got_sigill; | |
2400 | ||
2401 | static void sigill_handler(int signo, siginfo_t *si, void *data) | |
2402 | { | |
2403 | /* Skip the faulty instruction */ | |
2404 | ucontext_t *uc = (ucontext_t *)data; | |
2405 | uc->uc_mcontext.pc += 4; | |
2406 | ||
2407 | got_sigill = 1; | |
2408 | } | |
2409 | ||
2410 | static void tcg_target_detect_isa(void) | |
2411 | { | |
2412 | struct sigaction sa_old, sa_new; | |
2413 | ||
2414 | memset(&sa_new, 0, sizeof(sa_new)); | |
2415 | sa_new.sa_flags = SA_SIGINFO; | |
2416 | sa_new.sa_sigaction = sigill_handler; | |
2417 | sigaction(SIGILL, &sa_new, &sa_old); | |
2418 | ||
2419 | /* Probe for movn/movz, necessary to implement movcond. */ | |
2420 | #ifndef use_movnz_instructions | |
2421 | got_sigill = 0; | |
2422 | asm volatile(".set push\n" | |
2423 | ".set mips32\n" | |
2424 | "movn $zero, $zero, $zero\n" | |
2425 | "movz $zero, $zero, $zero\n" | |
2426 | ".set pop\n" | |
2427 | : : : ); | |
2428 | use_movnz_instructions = !got_sigill; | |
2429 | #endif | |
2430 | ||
2431 | /* Probe for MIPS32 instructions. As no subsetting is allowed | |
2432 | by the specification, it is only necessary to probe for one | |
2433 | of the instructions. */ | |
2434 | #ifndef use_mips32_instructions | |
2435 | got_sigill = 0; | |
2436 | asm volatile(".set push\n" | |
2437 | ".set mips32\n" | |
2438 | "mul $zero, $zero\n" | |
2439 | ".set pop\n" | |
2440 | : : : ); | |
2441 | use_mips32_instructions = !got_sigill; | |
2442 | #endif | |
2443 | ||
2444 | /* Probe for MIPS32r2 instructions if MIPS32 instructions are | |
2445 | available. As no subsetting is allowed by the specification, | |
2446 | it is only necessary to probe for one of the instructions. */ | |
2447 | #ifndef use_mips32r2_instructions | |
2448 | if (use_mips32_instructions) { | |
2449 | got_sigill = 0; | |
2450 | asm volatile(".set push\n" | |
2451 | ".set mips32r2\n" | |
2452 | "seb $zero, $zero\n" | |
2453 | ".set pop\n" | |
2454 | : : : ); | |
2455 | use_mips32r2_instructions = !got_sigill; | |
2456 | } | |
2457 | #endif | |
2458 | ||
2459 | sigaction(SIGILL, &sa_old, NULL); | |
2460 | } | |
2461 | ||
bb08afe9 JG |
2462 | static tcg_insn_unit *align_code_ptr(TCGContext *s) |
2463 | { | |
2464 | uintptr_t p = (uintptr_t)s->code_ptr; | |
2465 | if (p & 15) { | |
2466 | p = (p + 15) & -16; | |
2467 | s->code_ptr = (void *)p; | |
2468 | } | |
2469 | return s->code_ptr; | |
2470 | } | |
2471 | ||
0973b1cf JG |
2472 | /* Stack frame parameters. */ |
2473 | #define REG_SIZE (TCG_TARGET_REG_BITS / 8) | |
2474 | #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) | |
2475 | #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) | |
2476 | ||
2477 | #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ | |
2478 | + TCG_TARGET_STACK_ALIGN - 1) \ | |
2479 | & -TCG_TARGET_STACK_ALIGN) | |
2480 | #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) | |
2481 | ||
2482 | /* We're expecting to be able to use an immediate for frame allocation. */ | |
2483 | QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); | |
2484 | ||
afa05235 | 2485 | /* Generate global QEMU prologue and epilogue code */ |
e4d58b41 | 2486 | static void tcg_target_qemu_prologue(TCGContext *s) |
afa05235 | 2487 | { |
0973b1cf JG |
2488 | int i; |
2489 | ||
2490 | tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); | |
afa05235 AJ |
2491 | |
2492 | /* TB prologue */ | |
0973b1cf JG |
2493 | tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); |
2494 | for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { | |
2495 | tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], | |
2496 | TCG_REG_SP, SAVE_OFS + i * REG_SIZE); | |
afa05235 AJ |
2497 | } |
2498 | ||
4df9cac5 JB |
2499 | #ifndef CONFIG_SOFTMMU |
2500 | if (guest_base) { | |
2501 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); | |
2502 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); | |
2503 | } | |
2504 | #endif | |
2505 | ||
afa05235 | 2506 | /* Call generated code */ |
ea15fb06 | 2507 | tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); |
0973b1cf | 2508 | /* delay slot */ |
cea5f9a2 | 2509 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); |
afa05235 | 2510 | |
5786e068 AJ |
2511 | /* |
2512 | * Return path for goto_ptr. Set return value to 0, a-la exit_tb, | |
2513 | * and fall through to the rest of the epilogue. | |
2514 | */ | |
2515 | s->code_gen_epilogue = s->code_ptr; | |
2516 | tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); | |
2517 | ||
afa05235 | 2518 | /* TB epilogue */ |
0973b1cf JG |
2519 | tb_ret_addr = s->code_ptr; |
2520 | for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { | |
2521 | tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], | |
2522 | TCG_REG_SP, SAVE_OFS + i * REG_SIZE); | |
afa05235 AJ |
2523 | } |
2524 | ||
2525 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); | |
bb08afe9 | 2526 | /* delay slot */ |
0973b1cf | 2527 | tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); |
bb08afe9 JG |
2528 | |
2529 | if (use_mips32r2_instructions) { | |
2530 | return; | |
2531 | } | |
2532 | ||
7f54eaa3 | 2533 | /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; |
bb08afe9 JG |
2534 | clobbers TCG_TMP1, TCG_TMP2. */ |
2535 | ||
2536 | /* | |
2537 | * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. | |
2538 | */ | |
2539 | bswap32_addr = align_code_ptr(s); | |
2540 | /* t3 = (ssss)d000 */ | |
2541 | tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); | |
2542 | /* t1 = 000a */ | |
2543 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); | |
2544 | /* t2 = 00c0 */ | |
2545 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); | |
2546 | /* t3 = d00a */ | |
2547 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2548 | /* t1 = 0abc */ | |
2549 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); | |
2550 | /* t2 = 0c00 */ | |
2551 | tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); | |
2552 | /* t1 = 00b0 */ | |
2553 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); | |
2554 | /* t3 = dc0a */ | |
2555 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2556 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); | |
2557 | /* t3 = dcba -- delay slot */ | |
2558 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
7f54eaa3 JG |
2559 | |
2560 | if (TCG_TARGET_REG_BITS == 32) { | |
2561 | return; | |
2562 | } | |
2563 | ||
2564 | /* | |
2565 | * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. | |
2566 | */ | |
2567 | bswap32u_addr = align_code_ptr(s); | |
2568 | /* t1 = (0000)000d */ | |
2569 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); | |
2570 | /* t3 = 000a */ | |
2571 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); | |
2572 | /* t1 = (0000)d000 */ | |
2573 | tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); | |
2574 | /* t2 = 00c0 */ | |
2575 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); | |
2576 | /* t3 = d00a */ | |
2577 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2578 | /* t1 = 0abc */ | |
2579 | tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); | |
2580 | /* t2 = 0c00 */ | |
2581 | tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); | |
2582 | /* t1 = 00b0 */ | |
2583 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); | |
2584 | /* t3 = dc0a */ | |
2585 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2586 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); | |
2587 | /* t3 = dcba -- delay slot */ | |
2588 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2589 | ||
2590 | /* | |
2591 | * bswap64 -- 64-bit swap. a0 = abcdefgh | |
2592 | */ | |
2593 | bswap64_addr = align_code_ptr(s); | |
2594 | /* t3 = h0000000 */ | |
2595 | tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); | |
2596 | /* t1 = 0000000a */ | |
2597 | tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); | |
2598 | ||
2599 | /* t2 = 000000g0 */ | |
2600 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); | |
2601 | /* t3 = h000000a */ | |
2602 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2603 | /* t1 = 00000abc */ | |
2604 | tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); | |
2605 | /* t2 = 0g000000 */ | |
2606 | tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); | |
2607 | /* t1 = 000000b0 */ | |
2608 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); | |
2609 | ||
2610 | /* t3 = hg00000a */ | |
2611 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2612 | /* t2 = 0000abcd */ | |
2613 | tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); | |
2614 | /* t3 = hg0000ba */ | |
2615 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2616 | ||
2617 | /* t1 = 000000c0 */ | |
2618 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); | |
2619 | /* t2 = 0000000d */ | |
2620 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); | |
2621 | /* t1 = 00000c00 */ | |
2622 | tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); | |
2623 | /* t2 = 0000d000 */ | |
2624 | tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); | |
2625 | ||
2626 | /* t3 = hg000cba */ | |
2627 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
2628 | /* t1 = 00abcdef */ | |
2629 | tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); | |
2630 | /* t3 = hg00dcba */ | |
2631 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2632 | ||
2633 | /* t2 = 0000000f */ | |
2634 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); | |
2635 | /* t1 = 000000e0 */ | |
2636 | tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); | |
2637 | /* t2 = 00f00000 */ | |
2638 | tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); | |
2639 | /* t1 = 000e0000 */ | |
2640 | tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); | |
2641 | ||
2642 | /* t3 = hgf0dcba */ | |
2643 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); | |
2644 | tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); | |
2645 | /* t3 = hgfedcba -- delay slot */ | |
2646 | tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); | |
afa05235 AJ |
2647 | } |
2648 | ||
e4d58b41 | 2649 | static void tcg_target_init(TCGContext *s) |
afa05235 | 2650 | { |
988902fc | 2651 | tcg_target_detect_isa(); |
d21369f5 | 2652 | tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; |
999b9416 | 2653 | if (TCG_TARGET_REG_BITS == 64) { |
d21369f5 RH |
2654 | tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; |
2655 | } | |
2656 | ||
2657 | tcg_target_call_clobber_regs = 0; | |
2658 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); | |
2659 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); | |
2660 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); | |
2661 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); | |
2662 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); | |
2663 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); | |
2664 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); | |
2665 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); | |
2666 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); | |
2667 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); | |
2668 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); | |
2669 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); | |
2670 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); | |
2671 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); | |
2672 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); | |
2673 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); | |
afa05235 | 2674 | |
ccb1bb66 | 2675 | s->reserved_regs = 0; |
afa05235 AJ |
2676 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ |
2677 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ | |
2678 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ | |
6c530e32 RH |
2679 | tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ |
2680 | tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ | |
bb08afe9 JG |
2681 | tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ |
2682 | tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ | |
afa05235 AJ |
2683 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ |
2684 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ | |
3314e008 | 2685 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ |
afa05235 | 2686 | } |
b6bfeea9 | 2687 | |
a8583393 RH |
2688 | void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, |
2689 | uintptr_t addr) | |
b6bfeea9 | 2690 | { |
c82460a5 | 2691 | atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); |
b6bfeea9 RH |
2692 | flush_icache_range(jmp_addr, jmp_addr + 4); |
2693 | } | |
98d69076 JG |
2694 | |
2695 | typedef struct { | |
2696 | DebugFrameHeader h; | |
2697 | uint8_t fde_def_cfa[4]; | |
2698 | uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; | |
2699 | } DebugFrame; | |
2700 | ||
2701 | #define ELF_HOST_MACHINE EM_MIPS | |
2702 | /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, | |
2703 | which is good because they're really quite complicated for MIPS. */ | |
2704 | ||
2705 | static const DebugFrame debug_frame = { | |
2706 | .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ | |
2707 | .h.cie.id = -1, | |
2708 | .h.cie.version = 1, | |
2709 | .h.cie.code_align = 1, | |
2710 | .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ | |
2711 | .h.cie.return_column = TCG_REG_RA, | |
2712 | ||
2713 | /* Total FDE size does not include the "len" member. */ | |
2714 | .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), | |
2715 | ||
2716 | .fde_def_cfa = { | |
2717 | 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ | |
2718 | (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ | |
2719 | (FRAME_SIZE >> 7) | |
2720 | }, | |
2721 | .fde_reg_ofs = { | |
2722 | 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ | |
2723 | 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ | |
2724 | 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ | |
2725 | 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ | |
2726 | 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ | |
2727 | 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ | |
2728 | 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ | |
2729 | 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ | |
2730 | 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ | |
2731 | } | |
2732 | }; | |
2733 | ||
2734 | void tcg_register_jit(void *buf, size_t buf_size) | |
2735 | { | |
2736 | tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); | |
2737 | } |