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8f2e8c07
KB
1/*
2 * Optimizations for Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2010 Samsung Electronics.
5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
757e725b 26#include "qemu/osdep.h"
8f2e8c07 27#include "qemu-common.h"
00f6da6a 28#include "exec/cpu-common.h"
8f2e8c07
KB
29#include "tcg-op.h"
30
8f2e8c07
KB
31#define CASE_OP_32_64(x) \
32 glue(glue(case INDEX_op_, x), _i32): \
33 glue(glue(case INDEX_op_, x), _i64)
8f2e8c07 34
170ba88f
RH
35#define CASE_OP_32_64_VEC(x) \
36 glue(glue(case INDEX_op_, x), _i32): \
37 glue(glue(case INDEX_op_, x), _i64): \
38 glue(glue(case INDEX_op_, x), _vec)
39
22613af4 40struct tcg_temp_info {
b41059dd 41 bool is_const;
6349039d
RH
42 TCGTemp *prev_copy;
43 TCGTemp *next_copy;
22613af4 44 tcg_target_ulong val;
3a9d8b17 45 tcg_target_ulong mask;
22613af4
KB
46};
47
6349039d 48static inline struct tcg_temp_info *ts_info(TCGTemp *ts)
d9c769c6 49{
6349039d 50 return ts->state_ptr;
d9c769c6
AJ
51}
52
6349039d 53static inline struct tcg_temp_info *arg_info(TCGArg arg)
d9c769c6 54{
6349039d
RH
55 return ts_info(arg_temp(arg));
56}
57
58static inline bool ts_is_const(TCGTemp *ts)
59{
60 return ts_info(ts)->is_const;
61}
62
63static inline bool arg_is_const(TCGArg arg)
64{
65 return ts_is_const(arg_temp(arg));
66}
67
68static inline bool ts_is_copy(TCGTemp *ts)
69{
70 return ts_info(ts)->next_copy != ts;
d9c769c6
AJ
71}
72
b41059dd 73/* Reset TEMP's state, possibly removing the temp for the list of copies. */
6349039d
RH
74static void reset_ts(TCGTemp *ts)
75{
76 struct tcg_temp_info *ti = ts_info(ts);
77 struct tcg_temp_info *pi = ts_info(ti->prev_copy);
78 struct tcg_temp_info *ni = ts_info(ti->next_copy);
79
80 ni->prev_copy = ti->prev_copy;
81 pi->next_copy = ti->next_copy;
82 ti->next_copy = ts;
83 ti->prev_copy = ts;
84 ti->is_const = false;
85 ti->mask = -1;
86}
87
88static void reset_temp(TCGArg arg)
22613af4 89{
6349039d 90 reset_ts(arg_temp(arg));
22613af4
KB
91}
92
1208d7dd 93/* Initialize and activate a temporary. */
34184b07
EC
94static void init_ts_info(struct tcg_temp_info *infos,
95 TCGTempSet *temps_used, TCGTemp *ts)
1208d7dd 96{
6349039d 97 size_t idx = temp_idx(ts);
34184b07
EC
98 if (!test_bit(idx, temps_used->l)) {
99 struct tcg_temp_info *ti = &infos[idx];
6349039d
RH
100
101 ts->state_ptr = ti;
102 ti->next_copy = ts;
103 ti->prev_copy = ts;
104 ti->is_const = false;
105 ti->mask = -1;
34184b07 106 set_bit(idx, temps_used->l);
1208d7dd
AJ
107 }
108}
109
34184b07
EC
110static void init_arg_info(struct tcg_temp_info *infos,
111 TCGTempSet *temps_used, TCGArg arg)
6349039d 112{
34184b07 113 init_ts_info(infos, temps_used, arg_temp(arg));
6349039d
RH
114}
115
6349039d 116static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
e590d4e6 117{
6349039d 118 TCGTemp *i;
e590d4e6
AJ
119
120 /* If this is already a global, we can't do better. */
fa477d25 121 if (ts->temp_global) {
6349039d 122 return ts;
e590d4e6
AJ
123 }
124
125 /* Search for a global first. */
6349039d
RH
126 for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
127 if (i->temp_global) {
e590d4e6
AJ
128 return i;
129 }
130 }
131
132 /* If it is a temp, search for a temp local. */
fa477d25 133 if (!ts->temp_local) {
6349039d
RH
134 for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
135 if (ts->temp_local) {
e590d4e6
AJ
136 return i;
137 }
138 }
139 }
140
141 /* Failure to find a better representation, return the same temp. */
6349039d 142 return ts;
e590d4e6
AJ
143}
144
6349039d 145static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2)
e590d4e6 146{
6349039d 147 TCGTemp *i;
e590d4e6 148
6349039d 149 if (ts1 == ts2) {
e590d4e6
AJ
150 return true;
151 }
152
6349039d 153 if (!ts_is_copy(ts1) || !ts_is_copy(ts2)) {
e590d4e6
AJ
154 return false;
155 }
156
6349039d
RH
157 for (i = ts_info(ts1)->next_copy; i != ts1; i = ts_info(i)->next_copy) {
158 if (i == ts2) {
e590d4e6
AJ
159 return true;
160 }
161 }
162
163 return false;
164}
165
6349039d
RH
166static bool args_are_copies(TCGArg arg1, TCGArg arg2)
167{
168 return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
169}
170
acd93701 171static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
97a79eb7 172{
170ba88f
RH
173 const TCGOpDef *def;
174 TCGOpcode new_op;
97a79eb7 175 tcg_target_ulong mask;
6349039d 176 struct tcg_temp_info *di = arg_info(dst);
97a79eb7 177
170ba88f
RH
178 def = &tcg_op_defs[op->opc];
179 if (def->flags & TCG_OPF_VECTOR) {
180 new_op = INDEX_op_dupi_vec;
181 } else if (def->flags & TCG_OPF_64BIT) {
182 new_op = INDEX_op_movi_i64;
183 } else {
184 new_op = INDEX_op_movi_i32;
185 }
97a79eb7 186 op->opc = new_op;
170ba88f
RH
187 /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
188 op->args[0] = dst;
189 op->args[1] = val;
97a79eb7
AJ
190
191 reset_temp(dst);
6349039d
RH
192 di->is_const = true;
193 di->val = val;
97a79eb7 194 mask = val;
96152126 195 if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) {
97a79eb7
AJ
196 /* High bits of the destination are now garbage. */
197 mask |= ~0xffffffffull;
198 }
6349039d 199 di->mask = mask;
97a79eb7
AJ
200}
201
acd93701 202static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
22613af4 203{
6349039d
RH
204 TCGTemp *dst_ts = arg_temp(dst);
205 TCGTemp *src_ts = arg_temp(src);
170ba88f 206 const TCGOpDef *def;
6349039d
RH
207 struct tcg_temp_info *di;
208 struct tcg_temp_info *si;
209 tcg_target_ulong mask;
210 TCGOpcode new_op;
211
212 if (ts_are_copies(dst_ts, src_ts)) {
5365718a
AJ
213 tcg_op_remove(s, op);
214 return;
215 }
216
6349039d
RH
217 reset_ts(dst_ts);
218 di = ts_info(dst_ts);
219 si = ts_info(src_ts);
170ba88f
RH
220 def = &tcg_op_defs[op->opc];
221 if (def->flags & TCG_OPF_VECTOR) {
222 new_op = INDEX_op_mov_vec;
223 } else if (def->flags & TCG_OPF_64BIT) {
224 new_op = INDEX_op_mov_i64;
225 } else {
226 new_op = INDEX_op_mov_i32;
227 }
c45cb8bb 228 op->opc = new_op;
170ba88f 229 /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
6349039d
RH
230 op->args[0] = dst;
231 op->args[1] = src;
a62f6f56 232
6349039d 233 mask = si->mask;
24666baf
RH
234 if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
235 /* High bits of the destination are now garbage. */
236 mask |= ~0xffffffffull;
237 }
6349039d 238 di->mask = mask;
e590d4e6 239
6349039d
RH
240 if (src_ts->type == dst_ts->type) {
241 struct tcg_temp_info *ni = ts_info(si->next_copy);
242
243 di->next_copy = si->next_copy;
244 di->prev_copy = src_ts;
245 ni->prev_copy = dst_ts;
246 si->next_copy = dst_ts;
247 di->is_const = si->is_const;
248 di->val = si->val;
249 }
22613af4
KB
250}
251
fe0de7aa 252static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
53108fb5 253{
03271524
RH
254 uint64_t l64, h64;
255
53108fb5
KB
256 switch (op) {
257 CASE_OP_32_64(add):
258 return x + y;
259
260 CASE_OP_32_64(sub):
261 return x - y;
262
263 CASE_OP_32_64(mul):
264 return x * y;
265
9a81090b
KB
266 CASE_OP_32_64(and):
267 return x & y;
268
269 CASE_OP_32_64(or):
270 return x | y;
271
272 CASE_OP_32_64(xor):
273 return x ^ y;
274
55c0975c 275 case INDEX_op_shl_i32:
50c5c4d1 276 return (uint32_t)x << (y & 31);
55c0975c 277
55c0975c 278 case INDEX_op_shl_i64:
50c5c4d1 279 return (uint64_t)x << (y & 63);
55c0975c
KB
280
281 case INDEX_op_shr_i32:
50c5c4d1 282 return (uint32_t)x >> (y & 31);
55c0975c 283
55c0975c 284 case INDEX_op_shr_i64:
50c5c4d1 285 return (uint64_t)x >> (y & 63);
55c0975c
KB
286
287 case INDEX_op_sar_i32:
50c5c4d1 288 return (int32_t)x >> (y & 31);
55c0975c 289
55c0975c 290 case INDEX_op_sar_i64:
50c5c4d1 291 return (int64_t)x >> (y & 63);
55c0975c
KB
292
293 case INDEX_op_rotr_i32:
50c5c4d1 294 return ror32(x, y & 31);
55c0975c 295
55c0975c 296 case INDEX_op_rotr_i64:
50c5c4d1 297 return ror64(x, y & 63);
55c0975c
KB
298
299 case INDEX_op_rotl_i32:
50c5c4d1 300 return rol32(x, y & 31);
55c0975c 301
55c0975c 302 case INDEX_op_rotl_i64:
50c5c4d1 303 return rol64(x, y & 63);
25c4d9cc
RH
304
305 CASE_OP_32_64(not):
a640f031 306 return ~x;
25c4d9cc 307
cb25c80a
RH
308 CASE_OP_32_64(neg):
309 return -x;
310
311 CASE_OP_32_64(andc):
312 return x & ~y;
313
314 CASE_OP_32_64(orc):
315 return x | ~y;
316
317 CASE_OP_32_64(eqv):
318 return ~(x ^ y);
319
320 CASE_OP_32_64(nand):
321 return ~(x & y);
322
323 CASE_OP_32_64(nor):
324 return ~(x | y);
325
0e28d006
RH
326 case INDEX_op_clz_i32:
327 return (uint32_t)x ? clz32(x) : y;
328
329 case INDEX_op_clz_i64:
330 return x ? clz64(x) : y;
331
332 case INDEX_op_ctz_i32:
333 return (uint32_t)x ? ctz32(x) : y;
334
335 case INDEX_op_ctz_i64:
336 return x ? ctz64(x) : y;
337
a768e4e9
RH
338 case INDEX_op_ctpop_i32:
339 return ctpop32(x);
340
341 case INDEX_op_ctpop_i64:
342 return ctpop64(x);
343
25c4d9cc 344 CASE_OP_32_64(ext8s):
a640f031 345 return (int8_t)x;
25c4d9cc
RH
346
347 CASE_OP_32_64(ext16s):
a640f031 348 return (int16_t)x;
25c4d9cc
RH
349
350 CASE_OP_32_64(ext8u):
a640f031 351 return (uint8_t)x;
25c4d9cc
RH
352
353 CASE_OP_32_64(ext16u):
a640f031
KB
354 return (uint16_t)x;
355
6498594c
RH
356 CASE_OP_32_64(bswap16):
357 return bswap16(x);
358
359 CASE_OP_32_64(bswap32):
360 return bswap32(x);
361
362 case INDEX_op_bswap64_i64:
363 return bswap64(x);
364
8bcb5c8f 365 case INDEX_op_ext_i32_i64:
a640f031
KB
366 case INDEX_op_ext32s_i64:
367 return (int32_t)x;
368
8bcb5c8f 369 case INDEX_op_extu_i32_i64:
609ad705 370 case INDEX_op_extrl_i64_i32:
a640f031
KB
371 case INDEX_op_ext32u_i64:
372 return (uint32_t)x;
a640f031 373
609ad705
RH
374 case INDEX_op_extrh_i64_i32:
375 return (uint64_t)x >> 32;
376
03271524
RH
377 case INDEX_op_muluh_i32:
378 return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32;
379 case INDEX_op_mulsh_i32:
380 return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
381
382 case INDEX_op_muluh_i64:
383 mulu64(&l64, &h64, x, y);
384 return h64;
385 case INDEX_op_mulsh_i64:
386 muls64(&l64, &h64, x, y);
387 return h64;
388
01547f7f
RH
389 case INDEX_op_div_i32:
390 /* Avoid crashing on divide by zero, otherwise undefined. */
391 return (int32_t)x / ((int32_t)y ? : 1);
392 case INDEX_op_divu_i32:
393 return (uint32_t)x / ((uint32_t)y ? : 1);
394 case INDEX_op_div_i64:
395 return (int64_t)x / ((int64_t)y ? : 1);
396 case INDEX_op_divu_i64:
397 return (uint64_t)x / ((uint64_t)y ? : 1);
398
399 case INDEX_op_rem_i32:
400 return (int32_t)x % ((int32_t)y ? : 1);
401 case INDEX_op_remu_i32:
402 return (uint32_t)x % ((uint32_t)y ? : 1);
403 case INDEX_op_rem_i64:
404 return (int64_t)x % ((int64_t)y ? : 1);
405 case INDEX_op_remu_i64:
406 return (uint64_t)x % ((uint64_t)y ? : 1);
407
53108fb5
KB
408 default:
409 fprintf(stderr,
410 "Unrecognized operation %d in do_constant_folding.\n", op);
411 tcg_abort();
412 }
413}
414
fe0de7aa 415static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y)
53108fb5 416{
170ba88f 417 const TCGOpDef *def = &tcg_op_defs[op];
53108fb5 418 TCGArg res = do_constant_folding_2(op, x, y);
170ba88f 419 if (!(def->flags & TCG_OPF_64BIT)) {
29f3ff8d 420 res = (int32_t)res;
53108fb5 421 }
53108fb5
KB
422 return res;
423}
424
9519da7e
RH
425static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c)
426{
427 switch (c) {
428 case TCG_COND_EQ:
429 return x == y;
430 case TCG_COND_NE:
431 return x != y;
432 case TCG_COND_LT:
433 return (int32_t)x < (int32_t)y;
434 case TCG_COND_GE:
435 return (int32_t)x >= (int32_t)y;
436 case TCG_COND_LE:
437 return (int32_t)x <= (int32_t)y;
438 case TCG_COND_GT:
439 return (int32_t)x > (int32_t)y;
440 case TCG_COND_LTU:
441 return x < y;
442 case TCG_COND_GEU:
443 return x >= y;
444 case TCG_COND_LEU:
445 return x <= y;
446 case TCG_COND_GTU:
447 return x > y;
448 default:
449 tcg_abort();
450 }
451}
452
453static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c)
454{
455 switch (c) {
456 case TCG_COND_EQ:
457 return x == y;
458 case TCG_COND_NE:
459 return x != y;
460 case TCG_COND_LT:
461 return (int64_t)x < (int64_t)y;
462 case TCG_COND_GE:
463 return (int64_t)x >= (int64_t)y;
464 case TCG_COND_LE:
465 return (int64_t)x <= (int64_t)y;
466 case TCG_COND_GT:
467 return (int64_t)x > (int64_t)y;
468 case TCG_COND_LTU:
469 return x < y;
470 case TCG_COND_GEU:
471 return x >= y;
472 case TCG_COND_LEU:
473 return x <= y;
474 case TCG_COND_GTU:
475 return x > y;
476 default:
477 tcg_abort();
478 }
479}
480
481static bool do_constant_folding_cond_eq(TCGCond c)
482{
483 switch (c) {
484 case TCG_COND_GT:
485 case TCG_COND_LTU:
486 case TCG_COND_LT:
487 case TCG_COND_GTU:
488 case TCG_COND_NE:
489 return 0;
490 case TCG_COND_GE:
491 case TCG_COND_GEU:
492 case TCG_COND_LE:
493 case TCG_COND_LEU:
494 case TCG_COND_EQ:
495 return 1;
496 default:
497 tcg_abort();
498 }
499}
500
b336ceb6
AJ
501/* Return 2 if the condition can't be simplified, and the result
502 of the condition (0 or 1) if it can */
f8dd19e5
AJ
503static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
504 TCGArg y, TCGCond c)
505{
6349039d
RH
506 tcg_target_ulong xv = arg_info(x)->val;
507 tcg_target_ulong yv = arg_info(y)->val;
508 if (arg_is_const(x) && arg_is_const(y)) {
170ba88f
RH
509 const TCGOpDef *def = &tcg_op_defs[op];
510 tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR));
511 if (def->flags & TCG_OPF_64BIT) {
6349039d 512 return do_constant_folding_cond_64(xv, yv, c);
170ba88f
RH
513 } else {
514 return do_constant_folding_cond_32(xv, yv, c);
b336ceb6 515 }
6349039d 516 } else if (args_are_copies(x, y)) {
9519da7e 517 return do_constant_folding_cond_eq(c);
6349039d 518 } else if (arg_is_const(y) && yv == 0) {
b336ceb6 519 switch (c) {
f8dd19e5 520 case TCG_COND_LTU:
b336ceb6 521 return 0;
f8dd19e5 522 case TCG_COND_GEU:
b336ceb6
AJ
523 return 1;
524 default:
525 return 2;
f8dd19e5 526 }
f8dd19e5 527 }
550276ae 528 return 2;
f8dd19e5
AJ
529}
530
6c4382f8
RH
531/* Return 2 if the condition can't be simplified, and the result
532 of the condition (0 or 1) if it can */
533static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
534{
535 TCGArg al = p1[0], ah = p1[1];
536 TCGArg bl = p2[0], bh = p2[1];
537
6349039d
RH
538 if (arg_is_const(bl) && arg_is_const(bh)) {
539 tcg_target_ulong blv = arg_info(bl)->val;
540 tcg_target_ulong bhv = arg_info(bh)->val;
541 uint64_t b = deposit64(blv, 32, 32, bhv);
6c4382f8 542
6349039d
RH
543 if (arg_is_const(al) && arg_is_const(ah)) {
544 tcg_target_ulong alv = arg_info(al)->val;
545 tcg_target_ulong ahv = arg_info(ah)->val;
546 uint64_t a = deposit64(alv, 32, 32, ahv);
6c4382f8
RH
547 return do_constant_folding_cond_64(a, b, c);
548 }
549 if (b == 0) {
550 switch (c) {
551 case TCG_COND_LTU:
552 return 0;
553 case TCG_COND_GEU:
554 return 1;
555 default:
556 break;
557 }
558 }
559 }
6349039d 560 if (args_are_copies(al, bl) && args_are_copies(ah, bh)) {
6c4382f8
RH
561 return do_constant_folding_cond_eq(c);
562 }
563 return 2;
564}
565
24c9ae4e
RH
566static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2)
567{
568 TCGArg a1 = *p1, a2 = *p2;
569 int sum = 0;
6349039d
RH
570 sum += arg_is_const(a1);
571 sum -= arg_is_const(a2);
24c9ae4e
RH
572
573 /* Prefer the constant in second argument, and then the form
574 op a, a, b, which is better handled on non-RISC hosts. */
575 if (sum > 0 || (sum == 0 && dest == a2)) {
576 *p1 = a2;
577 *p2 = a1;
578 return true;
579 }
580 return false;
581}
582
0bfcb865
RH
583static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
584{
585 int sum = 0;
6349039d
RH
586 sum += arg_is_const(p1[0]);
587 sum += arg_is_const(p1[1]);
588 sum -= arg_is_const(p2[0]);
589 sum -= arg_is_const(p2[1]);
0bfcb865
RH
590 if (sum > 0) {
591 TCGArg t;
592 t = p1[0], p1[0] = p2[0], p2[0] = t;
593 t = p1[1], p1[1] = p2[1], p2[1] = t;
594 return true;
595 }
596 return false;
597}
598
22613af4 599/* Propagate constants and copies, fold constant expressions. */
36e60ef6 600void tcg_optimize(TCGContext *s)
8f2e8c07 601{
15fa08f8
RH
602 int nb_temps, nb_globals;
603 TCGOp *op, *op_next, *prev_mb = NULL;
34184b07
EC
604 struct tcg_temp_info *infos;
605 TCGTempSet temps_used;
5d8f5363 606
22613af4
KB
607 /* Array VALS has an element for each temp.
608 If this temp holds a constant then its value is kept in VALS' element.
e590d4e6
AJ
609 If this temp is a copy of other ones then the other copies are
610 available through the doubly linked circular list. */
8f2e8c07
KB
611
612 nb_temps = s->nb_temps;
613 nb_globals = s->nb_globals;
34184b07
EC
614 bitmap_zero(temps_used.l, nb_temps);
615 infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps);
8f2e8c07 616
15fa08f8 617 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
24666baf 618 tcg_target_ulong mask, partmask, affected;
c45cb8bb 619 int nb_oargs, nb_iargs, i;
cf066674 620 TCGArg tmp;
c45cb8bb
RH
621 TCGOpcode opc = op->opc;
622 const TCGOpDef *def = &tcg_op_defs[opc];
623
1208d7dd
AJ
624 /* Count the arguments, and initialize the temps that are
625 going to be used */
c45cb8bb 626 if (opc == INDEX_op_call) {
cd9090aa
RH
627 nb_oargs = TCGOP_CALLO(op);
628 nb_iargs = TCGOP_CALLI(op);
1208d7dd 629 for (i = 0; i < nb_oargs + nb_iargs; i++) {
6349039d
RH
630 TCGTemp *ts = arg_temp(op->args[i]);
631 if (ts) {
34184b07 632 init_ts_info(infos, &temps_used, ts);
1208d7dd
AJ
633 }
634 }
1ff8c541 635 } else {
cf066674
RH
636 nb_oargs = def->nb_oargs;
637 nb_iargs = def->nb_iargs;
1208d7dd 638 for (i = 0; i < nb_oargs + nb_iargs; i++) {
34184b07 639 init_arg_info(infos, &temps_used, op->args[i]);
1208d7dd 640 }
cf066674
RH
641 }
642
643 /* Do copy propagation */
644 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
6349039d
RH
645 TCGTemp *ts = arg_temp(op->args[i]);
646 if (ts && ts_is_copy(ts)) {
647 op->args[i] = temp_arg(find_better_copy(s, ts));
22613af4
KB
648 }
649 }
650
53108fb5 651 /* For commutative operations make constant second argument */
c45cb8bb 652 switch (opc) {
170ba88f
RH
653 CASE_OP_32_64_VEC(add):
654 CASE_OP_32_64_VEC(mul):
655 CASE_OP_32_64_VEC(and):
656 CASE_OP_32_64_VEC(or):
657 CASE_OP_32_64_VEC(xor):
cb25c80a
RH
658 CASE_OP_32_64(eqv):
659 CASE_OP_32_64(nand):
660 CASE_OP_32_64(nor):
03271524
RH
661 CASE_OP_32_64(muluh):
662 CASE_OP_32_64(mulsh):
acd93701 663 swap_commutative(op->args[0], &op->args[1], &op->args[2]);
53108fb5 664 break;
65a7cce1 665 CASE_OP_32_64(brcond):
acd93701
RH
666 if (swap_commutative(-1, &op->args[0], &op->args[1])) {
667 op->args[2] = tcg_swap_cond(op->args[2]);
65a7cce1
AJ
668 }
669 break;
670 CASE_OP_32_64(setcond):
acd93701
RH
671 if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
672 op->args[3] = tcg_swap_cond(op->args[3]);
65a7cce1
AJ
673 }
674 break;
fa01a208 675 CASE_OP_32_64(movcond):
acd93701
RH
676 if (swap_commutative(-1, &op->args[1], &op->args[2])) {
677 op->args[5] = tcg_swap_cond(op->args[5]);
5d8f5363
RH
678 }
679 /* For movcond, we canonicalize the "false" input reg to match
680 the destination reg so that the tcg backend can implement
681 a "move if true" operation. */
acd93701
RH
682 if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
683 op->args[5] = tcg_invert_cond(op->args[5]);
fa01a208 684 }
1e484e61 685 break;
d7156f7c 686 CASE_OP_32_64(add2):
acd93701
RH
687 swap_commutative(op->args[0], &op->args[2], &op->args[4]);
688 swap_commutative(op->args[1], &op->args[3], &op->args[5]);
1e484e61 689 break;
d7156f7c 690 CASE_OP_32_64(mulu2):
4d3203fd 691 CASE_OP_32_64(muls2):
acd93701 692 swap_commutative(op->args[0], &op->args[2], &op->args[3]);
1414968a 693 break;
0bfcb865 694 case INDEX_op_brcond2_i32:
acd93701
RH
695 if (swap_commutative2(&op->args[0], &op->args[2])) {
696 op->args[4] = tcg_swap_cond(op->args[4]);
0bfcb865
RH
697 }
698 break;
699 case INDEX_op_setcond2_i32:
acd93701
RH
700 if (swap_commutative2(&op->args[1], &op->args[3])) {
701 op->args[5] = tcg_swap_cond(op->args[5]);
0bfcb865
RH
702 }
703 break;
53108fb5
KB
704 default:
705 break;
706 }
707
2d497542
RH
708 /* Simplify expressions for "shift/rot r, 0, a => movi r, 0",
709 and "sub r, 0, a => neg r, a" case. */
c45cb8bb 710 switch (opc) {
01ee5282
AJ
711 CASE_OP_32_64(shl):
712 CASE_OP_32_64(shr):
713 CASE_OP_32_64(sar):
714 CASE_OP_32_64(rotl):
715 CASE_OP_32_64(rotr):
6349039d
RH
716 if (arg_is_const(op->args[1])
717 && arg_info(op->args[1])->val == 0) {
acd93701 718 tcg_opt_gen_movi(s, op, op->args[0], 0);
01ee5282
AJ
719 continue;
720 }
721 break;
170ba88f 722 CASE_OP_32_64_VEC(sub):
2d497542
RH
723 {
724 TCGOpcode neg_op;
725 bool have_neg;
726
6349039d 727 if (arg_is_const(op->args[2])) {
2d497542
RH
728 /* Proceed with possible constant folding. */
729 break;
730 }
c45cb8bb 731 if (opc == INDEX_op_sub_i32) {
2d497542
RH
732 neg_op = INDEX_op_neg_i32;
733 have_neg = TCG_TARGET_HAS_neg_i32;
170ba88f 734 } else if (opc == INDEX_op_sub_i64) {
2d497542
RH
735 neg_op = INDEX_op_neg_i64;
736 have_neg = TCG_TARGET_HAS_neg_i64;
ac383dde
RH
737 } else if (TCG_TARGET_HAS_neg_vec) {
738 TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64;
739 unsigned vece = TCGOP_VECE(op);
170ba88f 740 neg_op = INDEX_op_neg_vec;
ac383dde
RH
741 have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0;
742 } else {
743 break;
2d497542
RH
744 }
745 if (!have_neg) {
746 break;
747 }
6349039d
RH
748 if (arg_is_const(op->args[1])
749 && arg_info(op->args[1])->val == 0) {
c45cb8bb 750 op->opc = neg_op;
acd93701
RH
751 reset_temp(op->args[0]);
752 op->args[1] = op->args[2];
2d497542
RH
753 continue;
754 }
755 }
756 break;
170ba88f 757 CASE_OP_32_64_VEC(xor):
e201b564 758 CASE_OP_32_64(nand):
6349039d
RH
759 if (!arg_is_const(op->args[1])
760 && arg_is_const(op->args[2])
761 && arg_info(op->args[2])->val == -1) {
e201b564
RH
762 i = 1;
763 goto try_not;
764 }
765 break;
766 CASE_OP_32_64(nor):
6349039d
RH
767 if (!arg_is_const(op->args[1])
768 && arg_is_const(op->args[2])
769 && arg_info(op->args[2])->val == 0) {
e201b564
RH
770 i = 1;
771 goto try_not;
772 }
773 break;
170ba88f 774 CASE_OP_32_64_VEC(andc):
6349039d
RH
775 if (!arg_is_const(op->args[2])
776 && arg_is_const(op->args[1])
777 && arg_info(op->args[1])->val == -1) {
e201b564
RH
778 i = 2;
779 goto try_not;
780 }
781 break;
170ba88f 782 CASE_OP_32_64_VEC(orc):
e201b564 783 CASE_OP_32_64(eqv):
6349039d
RH
784 if (!arg_is_const(op->args[2])
785 && arg_is_const(op->args[1])
786 && arg_info(op->args[1])->val == 0) {
e201b564
RH
787 i = 2;
788 goto try_not;
789 }
790 break;
791 try_not:
792 {
793 TCGOpcode not_op;
794 bool have_not;
795
170ba88f
RH
796 if (def->flags & TCG_OPF_VECTOR) {
797 not_op = INDEX_op_not_vec;
798 have_not = TCG_TARGET_HAS_not_vec;
799 } else if (def->flags & TCG_OPF_64BIT) {
e201b564
RH
800 not_op = INDEX_op_not_i64;
801 have_not = TCG_TARGET_HAS_not_i64;
802 } else {
803 not_op = INDEX_op_not_i32;
804 have_not = TCG_TARGET_HAS_not_i32;
805 }
806 if (!have_not) {
807 break;
808 }
c45cb8bb 809 op->opc = not_op;
acd93701
RH
810 reset_temp(op->args[0]);
811 op->args[1] = op->args[i];
e201b564
RH
812 continue;
813 }
01ee5282
AJ
814 default:
815 break;
816 }
817
464a1441 818 /* Simplify expression for "op r, a, const => mov r, a" cases */
c45cb8bb 819 switch (opc) {
170ba88f
RH
820 CASE_OP_32_64_VEC(add):
821 CASE_OP_32_64_VEC(sub):
822 CASE_OP_32_64_VEC(or):
823 CASE_OP_32_64_VEC(xor):
824 CASE_OP_32_64_VEC(andc):
55c0975c
KB
825 CASE_OP_32_64(shl):
826 CASE_OP_32_64(shr):
827 CASE_OP_32_64(sar):
25c4d9cc
RH
828 CASE_OP_32_64(rotl):
829 CASE_OP_32_64(rotr):
6349039d
RH
830 if (!arg_is_const(op->args[1])
831 && arg_is_const(op->args[2])
832 && arg_info(op->args[2])->val == 0) {
acd93701 833 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
97a79eb7 834 continue;
53108fb5
KB
835 }
836 break;
170ba88f
RH
837 CASE_OP_32_64_VEC(and):
838 CASE_OP_32_64_VEC(orc):
464a1441 839 CASE_OP_32_64(eqv):
6349039d
RH
840 if (!arg_is_const(op->args[1])
841 && arg_is_const(op->args[2])
842 && arg_info(op->args[2])->val == -1) {
acd93701 843 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
97a79eb7 844 continue;
464a1441
RH
845 }
846 break;
56e49438
AJ
847 default:
848 break;
849 }
850
3031244b
AJ
851 /* Simplify using known-zero bits. Currently only ops with a single
852 output argument is supported. */
3a9d8b17 853 mask = -1;
633f6502 854 affected = -1;
c45cb8bb 855 switch (opc) {
3a9d8b17 856 CASE_OP_32_64(ext8s):
6349039d 857 if ((arg_info(op->args[1])->mask & 0x80) != 0) {
3a9d8b17
PB
858 break;
859 }
860 CASE_OP_32_64(ext8u):
861 mask = 0xff;
862 goto and_const;
863 CASE_OP_32_64(ext16s):
6349039d 864 if ((arg_info(op->args[1])->mask & 0x8000) != 0) {
3a9d8b17
PB
865 break;
866 }
867 CASE_OP_32_64(ext16u):
868 mask = 0xffff;
869 goto and_const;
870 case INDEX_op_ext32s_i64:
6349039d 871 if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
3a9d8b17
PB
872 break;
873 }
874 case INDEX_op_ext32u_i64:
875 mask = 0xffffffffU;
876 goto and_const;
877
878 CASE_OP_32_64(and):
6349039d
RH
879 mask = arg_info(op->args[2])->mask;
880 if (arg_is_const(op->args[2])) {
3a9d8b17 881 and_const:
6349039d 882 affected = arg_info(op->args[1])->mask & ~mask;
3a9d8b17 883 }
6349039d 884 mask = arg_info(op->args[1])->mask & mask;
3a9d8b17
PB
885 break;
886
8bcb5c8f 887 case INDEX_op_ext_i32_i64:
6349039d 888 if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
8bcb5c8f
AJ
889 break;
890 }
891 case INDEX_op_extu_i32_i64:
892 /* We do not compute affected as it is a size changing op. */
6349039d 893 mask = (uint32_t)arg_info(op->args[1])->mask;
8bcb5c8f
AJ
894 break;
895
23ec69ed
RH
896 CASE_OP_32_64(andc):
897 /* Known-zeros does not imply known-ones. Therefore unless
acd93701 898 op->args[2] is constant, we can't infer anything from it. */
6349039d
RH
899 if (arg_is_const(op->args[2])) {
900 mask = ~arg_info(op->args[2])->mask;
23ec69ed
RH
901 goto and_const;
902 }
6349039d
RH
903 /* But we certainly know nothing outside args[1] may be set. */
904 mask = arg_info(op->args[1])->mask;
23ec69ed
RH
905 break;
906
e46b225a 907 case INDEX_op_sar_i32:
6349039d
RH
908 if (arg_is_const(op->args[2])) {
909 tmp = arg_info(op->args[2])->val & 31;
910 mask = (int32_t)arg_info(op->args[1])->mask >> tmp;
e46b225a
AJ
911 }
912 break;
913 case INDEX_op_sar_i64:
6349039d
RH
914 if (arg_is_const(op->args[2])) {
915 tmp = arg_info(op->args[2])->val & 63;
916 mask = (int64_t)arg_info(op->args[1])->mask >> tmp;
3a9d8b17
PB
917 }
918 break;
919
e46b225a 920 case INDEX_op_shr_i32:
6349039d
RH
921 if (arg_is_const(op->args[2])) {
922 tmp = arg_info(op->args[2])->val & 31;
923 mask = (uint32_t)arg_info(op->args[1])->mask >> tmp;
e46b225a
AJ
924 }
925 break;
926 case INDEX_op_shr_i64:
6349039d
RH
927 if (arg_is_const(op->args[2])) {
928 tmp = arg_info(op->args[2])->val & 63;
929 mask = (uint64_t)arg_info(op->args[1])->mask >> tmp;
3a9d8b17
PB
930 }
931 break;
932
609ad705 933 case INDEX_op_extrl_i64_i32:
6349039d 934 mask = (uint32_t)arg_info(op->args[1])->mask;
609ad705
RH
935 break;
936 case INDEX_op_extrh_i64_i32:
6349039d 937 mask = (uint64_t)arg_info(op->args[1])->mask >> 32;
4bb7a41e
RH
938 break;
939
3a9d8b17 940 CASE_OP_32_64(shl):
6349039d
RH
941 if (arg_is_const(op->args[2])) {
942 tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1);
943 mask = arg_info(op->args[1])->mask << tmp;
3a9d8b17
PB
944 }
945 break;
946
947 CASE_OP_32_64(neg):
948 /* Set to 1 all bits to the left of the rightmost. */
6349039d
RH
949 mask = -(arg_info(op->args[1])->mask
950 & -arg_info(op->args[1])->mask);
3a9d8b17
PB
951 break;
952
953 CASE_OP_32_64(deposit):
6349039d
RH
954 mask = deposit64(arg_info(op->args[1])->mask,
955 op->args[3], op->args[4],
956 arg_info(op->args[2])->mask);
3a9d8b17
PB
957 break;
958
7ec8bab3 959 CASE_OP_32_64(extract):
6349039d
RH
960 mask = extract64(arg_info(op->args[1])->mask,
961 op->args[2], op->args[3]);
acd93701 962 if (op->args[2] == 0) {
6349039d 963 affected = arg_info(op->args[1])->mask & ~mask;
7ec8bab3
RH
964 }
965 break;
966 CASE_OP_32_64(sextract):
6349039d 967 mask = sextract64(arg_info(op->args[1])->mask,
acd93701
RH
968 op->args[2], op->args[3]);
969 if (op->args[2] == 0 && (tcg_target_long)mask >= 0) {
6349039d 970 affected = arg_info(op->args[1])->mask & ~mask;
7ec8bab3
RH
971 }
972 break;
973
3a9d8b17
PB
974 CASE_OP_32_64(or):
975 CASE_OP_32_64(xor):
6349039d 976 mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask;
3a9d8b17
PB
977 break;
978
0e28d006
RH
979 case INDEX_op_clz_i32:
980 case INDEX_op_ctz_i32:
6349039d 981 mask = arg_info(op->args[2])->mask | 31;
0e28d006
RH
982 break;
983
984 case INDEX_op_clz_i64:
985 case INDEX_op_ctz_i64:
6349039d 986 mask = arg_info(op->args[2])->mask | 63;
0e28d006
RH
987 break;
988
a768e4e9
RH
989 case INDEX_op_ctpop_i32:
990 mask = 32 | 31;
991 break;
992 case INDEX_op_ctpop_i64:
993 mask = 64 | 63;
994 break;
995
3a9d8b17 996 CASE_OP_32_64(setcond):
a763551a 997 case INDEX_op_setcond2_i32:
3a9d8b17
PB
998 mask = 1;
999 break;
1000
1001 CASE_OP_32_64(movcond):
6349039d 1002 mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask;
3a9d8b17
PB
1003 break;
1004
c8d70272 1005 CASE_OP_32_64(ld8u):
c8d70272
AJ
1006 mask = 0xff;
1007 break;
1008 CASE_OP_32_64(ld16u):
c8d70272
AJ
1009 mask = 0xffff;
1010 break;
1011 case INDEX_op_ld32u_i64:
c8d70272
AJ
1012 mask = 0xffffffffu;
1013 break;
1014
1015 CASE_OP_32_64(qemu_ld):
1016 {
acd93701 1017 TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
59227d5d 1018 TCGMemOp mop = get_memop(oi);
c8d70272
AJ
1019 if (!(mop & MO_SIGN)) {
1020 mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
1021 }
1022 }
1023 break;
1024
3a9d8b17
PB
1025 default:
1026 break;
1027 }
1028
bc8d688f
RH
1029 /* 32-bit ops generate 32-bit results. For the result is zero test
1030 below, we can ignore high bits, but for further optimizations we
1031 need to record that the high bits contain garbage. */
24666baf 1032 partmask = mask;
bc8d688f 1033 if (!(def->flags & TCG_OPF_64BIT)) {
24666baf
RH
1034 mask |= ~(tcg_target_ulong)0xffffffffu;
1035 partmask &= 0xffffffffu;
1036 affected &= 0xffffffffu;
f096dc96
AJ
1037 }
1038
24666baf 1039 if (partmask == 0) {
eabb7b91 1040 tcg_debug_assert(nb_oargs == 1);
acd93701 1041 tcg_opt_gen_movi(s, op, op->args[0], 0);
633f6502
PB
1042 continue;
1043 }
1044 if (affected == 0) {
eabb7b91 1045 tcg_debug_assert(nb_oargs == 1);
acd93701 1046 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
633f6502
PB
1047 continue;
1048 }
1049
56e49438 1050 /* Simplify expression for "op r, a, 0 => movi r, 0" cases */
c45cb8bb 1051 switch (opc) {
170ba88f
RH
1052 CASE_OP_32_64_VEC(and):
1053 CASE_OP_32_64_VEC(mul):
03271524
RH
1054 CASE_OP_32_64(muluh):
1055 CASE_OP_32_64(mulsh):
6349039d
RH
1056 if (arg_is_const(op->args[2])
1057 && arg_info(op->args[2])->val == 0) {
acd93701 1058 tcg_opt_gen_movi(s, op, op->args[0], 0);
53108fb5
KB
1059 continue;
1060 }
1061 break;
56e49438
AJ
1062 default:
1063 break;
1064 }
1065
1066 /* Simplify expression for "op r, a, a => mov r, a" cases */
c45cb8bb 1067 switch (opc) {
170ba88f
RH
1068 CASE_OP_32_64_VEC(or):
1069 CASE_OP_32_64_VEC(and):
6349039d 1070 if (args_are_copies(op->args[1], op->args[2])) {
acd93701 1071 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
9a81090b
KB
1072 continue;
1073 }
1074 break;
fe0de7aa
BS
1075 default:
1076 break;
53108fb5
KB
1077 }
1078
3c94193e 1079 /* Simplify expression for "op r, a, a => movi r, 0" cases */
c45cb8bb 1080 switch (opc) {
170ba88f
RH
1081 CASE_OP_32_64_VEC(andc):
1082 CASE_OP_32_64_VEC(sub):
1083 CASE_OP_32_64_VEC(xor):
6349039d 1084 if (args_are_copies(op->args[1], op->args[2])) {
acd93701 1085 tcg_opt_gen_movi(s, op, op->args[0], 0);
3c94193e
AJ
1086 continue;
1087 }
1088 break;
1089 default:
1090 break;
1091 }
1092
22613af4
KB
1093 /* Propagate constants through copy operations and do constant
1094 folding. Constants will be substituted to arguments by register
1095 allocator where needed and possible. Also detect copies. */
c45cb8bb 1096 switch (opc) {
170ba88f 1097 CASE_OP_32_64_VEC(mov):
acd93701 1098 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
97a79eb7 1099 break;
22613af4 1100 CASE_OP_32_64(movi):
170ba88f 1101 case INDEX_op_dupi_vec:
acd93701 1102 tcg_opt_gen_movi(s, op, op->args[0], op->args[1]);
22613af4 1103 break;
6e14e91b 1104
170ba88f
RH
1105 case INDEX_op_dup_vec:
1106 if (arg_is_const(op->args[1])) {
1107 tmp = arg_info(op->args[1])->val;
1108 tmp = dup_const(TCGOP_VECE(op), tmp);
1109 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1fb57da7 1110 break;
170ba88f 1111 }
1fb57da7 1112 goto do_default;
170ba88f 1113
a640f031 1114 CASE_OP_32_64(not):
cb25c80a 1115 CASE_OP_32_64(neg):
25c4d9cc
RH
1116 CASE_OP_32_64(ext8s):
1117 CASE_OP_32_64(ext8u):
1118 CASE_OP_32_64(ext16s):
1119 CASE_OP_32_64(ext16u):
a768e4e9 1120 CASE_OP_32_64(ctpop):
6498594c
RH
1121 CASE_OP_32_64(bswap16):
1122 CASE_OP_32_64(bswap32):
1123 case INDEX_op_bswap64_i64:
a640f031
KB
1124 case INDEX_op_ext32s_i64:
1125 case INDEX_op_ext32u_i64:
8bcb5c8f
AJ
1126 case INDEX_op_ext_i32_i64:
1127 case INDEX_op_extu_i32_i64:
609ad705
RH
1128 case INDEX_op_extrl_i64_i32:
1129 case INDEX_op_extrh_i64_i32:
6349039d
RH
1130 if (arg_is_const(op->args[1])) {
1131 tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
acd93701 1132 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1133 break;
a640f031 1134 }
6e14e91b
RH
1135 goto do_default;
1136
53108fb5
KB
1137 CASE_OP_32_64(add):
1138 CASE_OP_32_64(sub):
1139 CASE_OP_32_64(mul):
9a81090b
KB
1140 CASE_OP_32_64(or):
1141 CASE_OP_32_64(and):
1142 CASE_OP_32_64(xor):
55c0975c
KB
1143 CASE_OP_32_64(shl):
1144 CASE_OP_32_64(shr):
1145 CASE_OP_32_64(sar):
25c4d9cc
RH
1146 CASE_OP_32_64(rotl):
1147 CASE_OP_32_64(rotr):
cb25c80a
RH
1148 CASE_OP_32_64(andc):
1149 CASE_OP_32_64(orc):
1150 CASE_OP_32_64(eqv):
1151 CASE_OP_32_64(nand):
1152 CASE_OP_32_64(nor):
03271524
RH
1153 CASE_OP_32_64(muluh):
1154 CASE_OP_32_64(mulsh):
01547f7f
RH
1155 CASE_OP_32_64(div):
1156 CASE_OP_32_64(divu):
1157 CASE_OP_32_64(rem):
1158 CASE_OP_32_64(remu):
6349039d
RH
1159 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1160 tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
1161 arg_info(op->args[2])->val);
acd93701 1162 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1163 break;
53108fb5 1164 }
6e14e91b
RH
1165 goto do_default;
1166
0e28d006
RH
1167 CASE_OP_32_64(clz):
1168 CASE_OP_32_64(ctz):
6349039d
RH
1169 if (arg_is_const(op->args[1])) {
1170 TCGArg v = arg_info(op->args[1])->val;
0e28d006
RH
1171 if (v != 0) {
1172 tmp = do_constant_folding(opc, v, 0);
acd93701 1173 tcg_opt_gen_movi(s, op, op->args[0], tmp);
0e28d006 1174 } else {
acd93701 1175 tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
0e28d006
RH
1176 }
1177 break;
1178 }
1179 goto do_default;
1180
7ef55fc9 1181 CASE_OP_32_64(deposit):
6349039d
RH
1182 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1183 tmp = deposit64(arg_info(op->args[1])->val,
1184 op->args[3], op->args[4],
1185 arg_info(op->args[2])->val);
acd93701 1186 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1187 break;
7ef55fc9 1188 }
6e14e91b
RH
1189 goto do_default;
1190
7ec8bab3 1191 CASE_OP_32_64(extract):
6349039d
RH
1192 if (arg_is_const(op->args[1])) {
1193 tmp = extract64(arg_info(op->args[1])->val,
acd93701
RH
1194 op->args[2], op->args[3]);
1195 tcg_opt_gen_movi(s, op, op->args[0], tmp);
7ec8bab3
RH
1196 break;
1197 }
1198 goto do_default;
1199
1200 CASE_OP_32_64(sextract):
6349039d
RH
1201 if (arg_is_const(op->args[1])) {
1202 tmp = sextract64(arg_info(op->args[1])->val,
acd93701
RH
1203 op->args[2], op->args[3]);
1204 tcg_opt_gen_movi(s, op, op->args[0], tmp);
7ec8bab3
RH
1205 break;
1206 }
1207 goto do_default;
1208
fce1296f
RH
1209 CASE_OP_32_64(extract2):
1210 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1211 TCGArg v1 = arg_info(op->args[1])->val;
1212 TCGArg v2 = arg_info(op->args[2])->val;
1213
1214 if (opc == INDEX_op_extract2_i64) {
1215 tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
1216 } else {
1217 tmp = (v1 >> op->args[3]) | (v2 << (32 - op->args[3]));
1218 tmp = (int32_t)tmp;
1219 }
1220 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1221 break;
1222 }
1223 goto do_default;
1224
f8dd19e5 1225 CASE_OP_32_64(setcond):
acd93701
RH
1226 tmp = do_constant_folding_cond(opc, op->args[1],
1227 op->args[2], op->args[3]);
b336ceb6 1228 if (tmp != 2) {
acd93701 1229 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1230 break;
f8dd19e5 1231 }
6e14e91b
RH
1232 goto do_default;
1233
fbeaa26c 1234 CASE_OP_32_64(brcond):
acd93701
RH
1235 tmp = do_constant_folding_cond(opc, op->args[0],
1236 op->args[1], op->args[2]);
b336ceb6
AJ
1237 if (tmp != 2) {
1238 if (tmp) {
34184b07 1239 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1240 op->opc = INDEX_op_br;
acd93701 1241 op->args[0] = op->args[3];
fbeaa26c 1242 } else {
0c627cdc 1243 tcg_op_remove(s, op);
fbeaa26c 1244 }
6e14e91b 1245 break;
fbeaa26c 1246 }
6e14e91b
RH
1247 goto do_default;
1248
fa01a208 1249 CASE_OP_32_64(movcond):
acd93701
RH
1250 tmp = do_constant_folding_cond(opc, op->args[1],
1251 op->args[2], op->args[5]);
b336ceb6 1252 if (tmp != 2) {
acd93701 1253 tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
6e14e91b 1254 break;
fa01a208 1255 }
6349039d
RH
1256 if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
1257 tcg_target_ulong tv = arg_info(op->args[3])->val;
1258 tcg_target_ulong fv = arg_info(op->args[4])->val;
acd93701 1259 TCGCond cond = op->args[5];
333b21b8
RH
1260 if (fv == 1 && tv == 0) {
1261 cond = tcg_invert_cond(cond);
1262 } else if (!(tv == 1 && fv == 0)) {
1263 goto do_default;
1264 }
acd93701 1265 op->args[3] = cond;
333b21b8
RH
1266 op->opc = opc = (opc == INDEX_op_movcond_i32
1267 ? INDEX_op_setcond_i32
1268 : INDEX_op_setcond_i64);
1269 nb_iargs = 2;
1270 }
6e14e91b 1271 goto do_default;
212c328d
RH
1272
1273 case INDEX_op_add2_i32:
1274 case INDEX_op_sub2_i32:
6349039d
RH
1275 if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])
1276 && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
1277 uint32_t al = arg_info(op->args[2])->val;
1278 uint32_t ah = arg_info(op->args[3])->val;
1279 uint32_t bl = arg_info(op->args[4])->val;
1280 uint32_t bh = arg_info(op->args[5])->val;
212c328d
RH
1281 uint64_t a = ((uint64_t)ah << 32) | al;
1282 uint64_t b = ((uint64_t)bh << 32) | bl;
1283 TCGArg rl, rh;
ac1043f6 1284 TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32);
212c328d 1285
c45cb8bb 1286 if (opc == INDEX_op_add2_i32) {
212c328d
RH
1287 a += b;
1288 } else {
1289 a -= b;
1290 }
1291
acd93701
RH
1292 rl = op->args[0];
1293 rh = op->args[1];
1294 tcg_opt_gen_movi(s, op, rl, (int32_t)a);
1295 tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32));
212c328d
RH
1296 break;
1297 }
1298 goto do_default;
1414968a
RH
1299
1300 case INDEX_op_mulu2_i32:
6349039d
RH
1301 if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
1302 uint32_t a = arg_info(op->args[2])->val;
1303 uint32_t b = arg_info(op->args[3])->val;
1414968a
RH
1304 uint64_t r = (uint64_t)a * b;
1305 TCGArg rl, rh;
ac1043f6 1306 TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32);
1414968a 1307
acd93701
RH
1308 rl = op->args[0];
1309 rh = op->args[1];
1310 tcg_opt_gen_movi(s, op, rl, (int32_t)r);
1311 tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32));
1414968a
RH
1312 break;
1313 }
1314 goto do_default;
6e14e91b 1315
bc1473ef 1316 case INDEX_op_brcond2_i32:
acd93701
RH
1317 tmp = do_constant_folding_cond2(&op->args[0], &op->args[2],
1318 op->args[4]);
6c4382f8
RH
1319 if (tmp != 2) {
1320 if (tmp) {
a763551a 1321 do_brcond_true:
34184b07 1322 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1323 op->opc = INDEX_op_br;
acd93701 1324 op->args[0] = op->args[5];
6c4382f8 1325 } else {
a763551a 1326 do_brcond_false:
0c627cdc 1327 tcg_op_remove(s, op);
6c4382f8 1328 }
acd93701
RH
1329 } else if ((op->args[4] == TCG_COND_LT
1330 || op->args[4] == TCG_COND_GE)
6349039d
RH
1331 && arg_is_const(op->args[2])
1332 && arg_info(op->args[2])->val == 0
1333 && arg_is_const(op->args[3])
1334 && arg_info(op->args[3])->val == 0) {
6c4382f8
RH
1335 /* Simplify LT/GE comparisons vs zero to a single compare
1336 vs the high word of the input. */
a763551a 1337 do_brcond_high:
34184b07 1338 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1339 op->opc = INDEX_op_brcond_i32;
acd93701
RH
1340 op->args[0] = op->args[1];
1341 op->args[1] = op->args[3];
1342 op->args[2] = op->args[4];
1343 op->args[3] = op->args[5];
1344 } else if (op->args[4] == TCG_COND_EQ) {
a763551a
RH
1345 /* Simplify EQ comparisons where one of the pairs
1346 can be simplified. */
1347 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1348 op->args[0], op->args[2],
1349 TCG_COND_EQ);
a763551a
RH
1350 if (tmp == 0) {
1351 goto do_brcond_false;
1352 } else if (tmp == 1) {
1353 goto do_brcond_high;
1354 }
1355 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1356 op->args[1], op->args[3],
1357 TCG_COND_EQ);
a763551a
RH
1358 if (tmp == 0) {
1359 goto do_brcond_false;
1360 } else if (tmp != 1) {
1361 goto do_default;
1362 }
1363 do_brcond_low:
34184b07 1364 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1365 op->opc = INDEX_op_brcond_i32;
acd93701
RH
1366 op->args[1] = op->args[2];
1367 op->args[2] = op->args[4];
1368 op->args[3] = op->args[5];
1369 } else if (op->args[4] == TCG_COND_NE) {
a763551a
RH
1370 /* Simplify NE comparisons where one of the pairs
1371 can be simplified. */
1372 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1373 op->args[0], op->args[2],
1374 TCG_COND_NE);
a763551a
RH
1375 if (tmp == 0) {
1376 goto do_brcond_high;
1377 } else if (tmp == 1) {
1378 goto do_brcond_true;
1379 }
1380 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1381 op->args[1], op->args[3],
1382 TCG_COND_NE);
a763551a
RH
1383 if (tmp == 0) {
1384 goto do_brcond_low;
1385 } else if (tmp == 1) {
1386 goto do_brcond_true;
1387 }
1388 goto do_default;
6c4382f8
RH
1389 } else {
1390 goto do_default;
bc1473ef 1391 }
6c4382f8 1392 break;
bc1473ef
RH
1393
1394 case INDEX_op_setcond2_i32:
acd93701
RH
1395 tmp = do_constant_folding_cond2(&op->args[1], &op->args[3],
1396 op->args[5]);
6c4382f8 1397 if (tmp != 2) {
a763551a 1398 do_setcond_const:
acd93701
RH
1399 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1400 } else if ((op->args[5] == TCG_COND_LT
1401 || op->args[5] == TCG_COND_GE)
6349039d
RH
1402 && arg_is_const(op->args[3])
1403 && arg_info(op->args[3])->val == 0
1404 && arg_is_const(op->args[4])
1405 && arg_info(op->args[4])->val == 0) {
6c4382f8
RH
1406 /* Simplify LT/GE comparisons vs zero to a single compare
1407 vs the high word of the input. */
a763551a 1408 do_setcond_high:
acd93701 1409 reset_temp(op->args[0]);
6349039d 1410 arg_info(op->args[0])->mask = 1;
c45cb8bb 1411 op->opc = INDEX_op_setcond_i32;
acd93701
RH
1412 op->args[1] = op->args[2];
1413 op->args[2] = op->args[4];
1414 op->args[3] = op->args[5];
1415 } else if (op->args[5] == TCG_COND_EQ) {
a763551a
RH
1416 /* Simplify EQ comparisons where one of the pairs
1417 can be simplified. */
1418 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1419 op->args[1], op->args[3],
1420 TCG_COND_EQ);
a763551a
RH
1421 if (tmp == 0) {
1422 goto do_setcond_const;
1423 } else if (tmp == 1) {
1424 goto do_setcond_high;
1425 }
1426 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1427 op->args[2], op->args[4],
1428 TCG_COND_EQ);
a763551a
RH
1429 if (tmp == 0) {
1430 goto do_setcond_high;
1431 } else if (tmp != 1) {
1432 goto do_default;
1433 }
1434 do_setcond_low:
acd93701 1435 reset_temp(op->args[0]);
6349039d 1436 arg_info(op->args[0])->mask = 1;
c45cb8bb 1437 op->opc = INDEX_op_setcond_i32;
acd93701
RH
1438 op->args[2] = op->args[3];
1439 op->args[3] = op->args[5];
1440 } else if (op->args[5] == TCG_COND_NE) {
a763551a
RH
1441 /* Simplify NE comparisons where one of the pairs
1442 can be simplified. */
1443 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1444 op->args[1], op->args[3],
1445 TCG_COND_NE);
a763551a
RH
1446 if (tmp == 0) {
1447 goto do_setcond_high;
1448 } else if (tmp == 1) {
1449 goto do_setcond_const;
1450 }
1451 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1452 op->args[2], op->args[4],
1453 TCG_COND_NE);
a763551a
RH
1454 if (tmp == 0) {
1455 goto do_setcond_low;
1456 } else if (tmp == 1) {
1457 goto do_setcond_const;
1458 }
1459 goto do_default;
6c4382f8
RH
1460 } else {
1461 goto do_default;
bc1473ef 1462 }
6c4382f8 1463 break;
bc1473ef 1464
8f2e8c07 1465 case INDEX_op_call:
acd93701 1466 if (!(op->args[nb_oargs + nb_iargs + 1]
cf066674 1467 & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
22613af4 1468 for (i = 0; i < nb_globals; i++) {
1208d7dd 1469 if (test_bit(i, temps_used.l)) {
6349039d 1470 reset_ts(&s->temps[i]);
1208d7dd 1471 }
22613af4
KB
1472 }
1473 }
cf066674 1474 goto do_reset_output;
6e14e91b 1475
8f2e8c07 1476 default:
6e14e91b
RH
1477 do_default:
1478 /* Default case: we know nothing about operation (or were unable
1479 to compute the operation result) so no propagation is done.
1480 We trash everything if the operation is the end of a basic
3a9d8b17
PB
1481 block, otherwise we only trash the output args. "mask" is
1482 the non-zero bits mask for the first output arg. */
a2550660 1483 if (def->flags & TCG_OPF_BB_END) {
34184b07 1484 bitmap_zero(temps_used.l, nb_temps);
a2550660 1485 } else {
cf066674
RH
1486 do_reset_output:
1487 for (i = 0; i < nb_oargs; i++) {
acd93701 1488 reset_temp(op->args[i]);
3031244b
AJ
1489 /* Save the corresponding known-zero bits mask for the
1490 first output argument (only one supported so far). */
1491 if (i == 0) {
6349039d 1492 arg_info(op->args[i])->mask = mask;
3031244b 1493 }
a2550660 1494 }
22613af4 1495 }
8f2e8c07
KB
1496 break;
1497 }
34f93921
PK
1498
1499 /* Eliminate duplicate and redundant fence instructions. */
acd93701 1500 if (prev_mb) {
34f93921
PK
1501 switch (opc) {
1502 case INDEX_op_mb:
1503 /* Merge two barriers of the same type into one,
1504 * or a weaker barrier into a stronger one,
1505 * or two weaker barriers into a stronger one.
1506 * mb X; mb Y => mb X|Y
1507 * mb; strl => mb; st
1508 * ldaq; mb => ld; mb
1509 * ldaq; strl => ld; mb; st
1510 * Other combinations are also merged into a strong
1511 * barrier. This is stricter than specified but for
1512 * the purposes of TCG is better than not optimizing.
1513 */
acd93701 1514 prev_mb->args[0] |= op->args[0];
34f93921
PK
1515 tcg_op_remove(s, op);
1516 break;
1517
1518 default:
1519 /* Opcodes that end the block stop the optimization. */
1520 if ((def->flags & TCG_OPF_BB_END) == 0) {
1521 break;
1522 }
1523 /* fallthru */
1524 case INDEX_op_qemu_ld_i32:
1525 case INDEX_op_qemu_ld_i64:
1526 case INDEX_op_qemu_st_i32:
1527 case INDEX_op_qemu_st_i64:
1528 case INDEX_op_call:
1529 /* Opcodes that touch guest memory stop the optimization. */
acd93701 1530 prev_mb = NULL;
34f93921
PK
1531 break;
1532 }
1533 } else if (opc == INDEX_op_mb) {
acd93701 1534 prev_mb = op;
34f93921 1535 }
8f2e8c07 1536 }
8f2e8c07 1537}