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CommitLineData
8f2e8c07
KB
1/*
2 * Optimizations for Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2010 Samsung Electronics.
5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
757e725b 26#include "qemu/osdep.h"
8f2e8c07 27#include "qemu-common.h"
00f6da6a 28#include "exec/cpu-common.h"
8f2e8c07
KB
29#include "tcg-op.h"
30
8f2e8c07
KB
31#define CASE_OP_32_64(x) \
32 glue(glue(case INDEX_op_, x), _i32): \
33 glue(glue(case INDEX_op_, x), _i64)
8f2e8c07 34
170ba88f
RH
35#define CASE_OP_32_64_VEC(x) \
36 glue(glue(case INDEX_op_, x), _i32): \
37 glue(glue(case INDEX_op_, x), _i64): \
38 glue(glue(case INDEX_op_, x), _vec)
39
22613af4 40struct tcg_temp_info {
b41059dd 41 bool is_const;
6349039d
RH
42 TCGTemp *prev_copy;
43 TCGTemp *next_copy;
22613af4 44 tcg_target_ulong val;
3a9d8b17 45 tcg_target_ulong mask;
22613af4
KB
46};
47
6349039d 48static inline struct tcg_temp_info *ts_info(TCGTemp *ts)
d9c769c6 49{
6349039d 50 return ts->state_ptr;
d9c769c6
AJ
51}
52
6349039d 53static inline struct tcg_temp_info *arg_info(TCGArg arg)
d9c769c6 54{
6349039d
RH
55 return ts_info(arg_temp(arg));
56}
57
58static inline bool ts_is_const(TCGTemp *ts)
59{
60 return ts_info(ts)->is_const;
61}
62
63static inline bool arg_is_const(TCGArg arg)
64{
65 return ts_is_const(arg_temp(arg));
66}
67
68static inline bool ts_is_copy(TCGTemp *ts)
69{
70 return ts_info(ts)->next_copy != ts;
d9c769c6
AJ
71}
72
b41059dd 73/* Reset TEMP's state, possibly removing the temp for the list of copies. */
6349039d
RH
74static void reset_ts(TCGTemp *ts)
75{
76 struct tcg_temp_info *ti = ts_info(ts);
77 struct tcg_temp_info *pi = ts_info(ti->prev_copy);
78 struct tcg_temp_info *ni = ts_info(ti->next_copy);
79
80 ni->prev_copy = ti->prev_copy;
81 pi->next_copy = ti->next_copy;
82 ti->next_copy = ts;
83 ti->prev_copy = ts;
84 ti->is_const = false;
85 ti->mask = -1;
86}
87
88static void reset_temp(TCGArg arg)
22613af4 89{
6349039d 90 reset_ts(arg_temp(arg));
22613af4
KB
91}
92
1208d7dd 93/* Initialize and activate a temporary. */
34184b07
EC
94static void init_ts_info(struct tcg_temp_info *infos,
95 TCGTempSet *temps_used, TCGTemp *ts)
1208d7dd 96{
6349039d 97 size_t idx = temp_idx(ts);
34184b07
EC
98 if (!test_bit(idx, temps_used->l)) {
99 struct tcg_temp_info *ti = &infos[idx];
6349039d
RH
100
101 ts->state_ptr = ti;
102 ti->next_copy = ts;
103 ti->prev_copy = ts;
104 ti->is_const = false;
105 ti->mask = -1;
34184b07 106 set_bit(idx, temps_used->l);
1208d7dd
AJ
107 }
108}
109
34184b07
EC
110static void init_arg_info(struct tcg_temp_info *infos,
111 TCGTempSet *temps_used, TCGArg arg)
6349039d 112{
34184b07 113 init_ts_info(infos, temps_used, arg_temp(arg));
6349039d
RH
114}
115
6349039d 116static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
e590d4e6 117{
6349039d 118 TCGTemp *i;
e590d4e6
AJ
119
120 /* If this is already a global, we can't do better. */
fa477d25 121 if (ts->temp_global) {
6349039d 122 return ts;
e590d4e6
AJ
123 }
124
125 /* Search for a global first. */
6349039d
RH
126 for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
127 if (i->temp_global) {
e590d4e6
AJ
128 return i;
129 }
130 }
131
132 /* If it is a temp, search for a temp local. */
fa477d25 133 if (!ts->temp_local) {
6349039d
RH
134 for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
135 if (ts->temp_local) {
e590d4e6
AJ
136 return i;
137 }
138 }
139 }
140
141 /* Failure to find a better representation, return the same temp. */
6349039d 142 return ts;
e590d4e6
AJ
143}
144
6349039d 145static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2)
e590d4e6 146{
6349039d 147 TCGTemp *i;
e590d4e6 148
6349039d 149 if (ts1 == ts2) {
e590d4e6
AJ
150 return true;
151 }
152
6349039d 153 if (!ts_is_copy(ts1) || !ts_is_copy(ts2)) {
e590d4e6
AJ
154 return false;
155 }
156
6349039d
RH
157 for (i = ts_info(ts1)->next_copy; i != ts1; i = ts_info(i)->next_copy) {
158 if (i == ts2) {
e590d4e6
AJ
159 return true;
160 }
161 }
162
163 return false;
164}
165
6349039d
RH
166static bool args_are_copies(TCGArg arg1, TCGArg arg2)
167{
168 return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
169}
170
acd93701 171static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
97a79eb7 172{
170ba88f
RH
173 const TCGOpDef *def;
174 TCGOpcode new_op;
97a79eb7 175 tcg_target_ulong mask;
6349039d 176 struct tcg_temp_info *di = arg_info(dst);
97a79eb7 177
170ba88f
RH
178 def = &tcg_op_defs[op->opc];
179 if (def->flags & TCG_OPF_VECTOR) {
180 new_op = INDEX_op_dupi_vec;
181 } else if (def->flags & TCG_OPF_64BIT) {
182 new_op = INDEX_op_movi_i64;
183 } else {
184 new_op = INDEX_op_movi_i32;
185 }
97a79eb7 186 op->opc = new_op;
170ba88f
RH
187 /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
188 op->args[0] = dst;
189 op->args[1] = val;
97a79eb7
AJ
190
191 reset_temp(dst);
6349039d
RH
192 di->is_const = true;
193 di->val = val;
97a79eb7 194 mask = val;
96152126 195 if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) {
97a79eb7
AJ
196 /* High bits of the destination are now garbage. */
197 mask |= ~0xffffffffull;
198 }
6349039d 199 di->mask = mask;
97a79eb7
AJ
200}
201
acd93701 202static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
22613af4 203{
6349039d
RH
204 TCGTemp *dst_ts = arg_temp(dst);
205 TCGTemp *src_ts = arg_temp(src);
170ba88f 206 const TCGOpDef *def;
6349039d
RH
207 struct tcg_temp_info *di;
208 struct tcg_temp_info *si;
209 tcg_target_ulong mask;
210 TCGOpcode new_op;
211
212 if (ts_are_copies(dst_ts, src_ts)) {
5365718a
AJ
213 tcg_op_remove(s, op);
214 return;
215 }
216
6349039d
RH
217 reset_ts(dst_ts);
218 di = ts_info(dst_ts);
219 si = ts_info(src_ts);
170ba88f
RH
220 def = &tcg_op_defs[op->opc];
221 if (def->flags & TCG_OPF_VECTOR) {
222 new_op = INDEX_op_mov_vec;
223 } else if (def->flags & TCG_OPF_64BIT) {
224 new_op = INDEX_op_mov_i64;
225 } else {
226 new_op = INDEX_op_mov_i32;
227 }
c45cb8bb 228 op->opc = new_op;
170ba88f 229 /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
6349039d
RH
230 op->args[0] = dst;
231 op->args[1] = src;
a62f6f56 232
6349039d 233 mask = si->mask;
24666baf
RH
234 if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
235 /* High bits of the destination are now garbage. */
236 mask |= ~0xffffffffull;
237 }
6349039d 238 di->mask = mask;
e590d4e6 239
6349039d
RH
240 if (src_ts->type == dst_ts->type) {
241 struct tcg_temp_info *ni = ts_info(si->next_copy);
242
243 di->next_copy = si->next_copy;
244 di->prev_copy = src_ts;
245 ni->prev_copy = dst_ts;
246 si->next_copy = dst_ts;
247 di->is_const = si->is_const;
248 di->val = si->val;
249 }
22613af4
KB
250}
251
fe0de7aa 252static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
53108fb5 253{
03271524
RH
254 uint64_t l64, h64;
255
53108fb5
KB
256 switch (op) {
257 CASE_OP_32_64(add):
258 return x + y;
259
260 CASE_OP_32_64(sub):
261 return x - y;
262
263 CASE_OP_32_64(mul):
264 return x * y;
265
9a81090b
KB
266 CASE_OP_32_64(and):
267 return x & y;
268
269 CASE_OP_32_64(or):
270 return x | y;
271
272 CASE_OP_32_64(xor):
273 return x ^ y;
274
55c0975c 275 case INDEX_op_shl_i32:
50c5c4d1 276 return (uint32_t)x << (y & 31);
55c0975c 277
55c0975c 278 case INDEX_op_shl_i64:
50c5c4d1 279 return (uint64_t)x << (y & 63);
55c0975c
KB
280
281 case INDEX_op_shr_i32:
50c5c4d1 282 return (uint32_t)x >> (y & 31);
55c0975c 283
55c0975c 284 case INDEX_op_shr_i64:
50c5c4d1 285 return (uint64_t)x >> (y & 63);
55c0975c
KB
286
287 case INDEX_op_sar_i32:
50c5c4d1 288 return (int32_t)x >> (y & 31);
55c0975c 289
55c0975c 290 case INDEX_op_sar_i64:
50c5c4d1 291 return (int64_t)x >> (y & 63);
55c0975c
KB
292
293 case INDEX_op_rotr_i32:
50c5c4d1 294 return ror32(x, y & 31);
55c0975c 295
55c0975c 296 case INDEX_op_rotr_i64:
50c5c4d1 297 return ror64(x, y & 63);
55c0975c
KB
298
299 case INDEX_op_rotl_i32:
50c5c4d1 300 return rol32(x, y & 31);
55c0975c 301
55c0975c 302 case INDEX_op_rotl_i64:
50c5c4d1 303 return rol64(x, y & 63);
25c4d9cc
RH
304
305 CASE_OP_32_64(not):
a640f031 306 return ~x;
25c4d9cc 307
cb25c80a
RH
308 CASE_OP_32_64(neg):
309 return -x;
310
311 CASE_OP_32_64(andc):
312 return x & ~y;
313
314 CASE_OP_32_64(orc):
315 return x | ~y;
316
317 CASE_OP_32_64(eqv):
318 return ~(x ^ y);
319
320 CASE_OP_32_64(nand):
321 return ~(x & y);
322
323 CASE_OP_32_64(nor):
324 return ~(x | y);
325
0e28d006
RH
326 case INDEX_op_clz_i32:
327 return (uint32_t)x ? clz32(x) : y;
328
329 case INDEX_op_clz_i64:
330 return x ? clz64(x) : y;
331
332 case INDEX_op_ctz_i32:
333 return (uint32_t)x ? ctz32(x) : y;
334
335 case INDEX_op_ctz_i64:
336 return x ? ctz64(x) : y;
337
a768e4e9
RH
338 case INDEX_op_ctpop_i32:
339 return ctpop32(x);
340
341 case INDEX_op_ctpop_i64:
342 return ctpop64(x);
343
25c4d9cc 344 CASE_OP_32_64(ext8s):
a640f031 345 return (int8_t)x;
25c4d9cc
RH
346
347 CASE_OP_32_64(ext16s):
a640f031 348 return (int16_t)x;
25c4d9cc
RH
349
350 CASE_OP_32_64(ext8u):
a640f031 351 return (uint8_t)x;
25c4d9cc
RH
352
353 CASE_OP_32_64(ext16u):
a640f031
KB
354 return (uint16_t)x;
355
8bcb5c8f 356 case INDEX_op_ext_i32_i64:
a640f031
KB
357 case INDEX_op_ext32s_i64:
358 return (int32_t)x;
359
8bcb5c8f 360 case INDEX_op_extu_i32_i64:
609ad705 361 case INDEX_op_extrl_i64_i32:
a640f031
KB
362 case INDEX_op_ext32u_i64:
363 return (uint32_t)x;
a640f031 364
609ad705
RH
365 case INDEX_op_extrh_i64_i32:
366 return (uint64_t)x >> 32;
367
03271524
RH
368 case INDEX_op_muluh_i32:
369 return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32;
370 case INDEX_op_mulsh_i32:
371 return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
372
373 case INDEX_op_muluh_i64:
374 mulu64(&l64, &h64, x, y);
375 return h64;
376 case INDEX_op_mulsh_i64:
377 muls64(&l64, &h64, x, y);
378 return h64;
379
01547f7f
RH
380 case INDEX_op_div_i32:
381 /* Avoid crashing on divide by zero, otherwise undefined. */
382 return (int32_t)x / ((int32_t)y ? : 1);
383 case INDEX_op_divu_i32:
384 return (uint32_t)x / ((uint32_t)y ? : 1);
385 case INDEX_op_div_i64:
386 return (int64_t)x / ((int64_t)y ? : 1);
387 case INDEX_op_divu_i64:
388 return (uint64_t)x / ((uint64_t)y ? : 1);
389
390 case INDEX_op_rem_i32:
391 return (int32_t)x % ((int32_t)y ? : 1);
392 case INDEX_op_remu_i32:
393 return (uint32_t)x % ((uint32_t)y ? : 1);
394 case INDEX_op_rem_i64:
395 return (int64_t)x % ((int64_t)y ? : 1);
396 case INDEX_op_remu_i64:
397 return (uint64_t)x % ((uint64_t)y ? : 1);
398
53108fb5
KB
399 default:
400 fprintf(stderr,
401 "Unrecognized operation %d in do_constant_folding.\n", op);
402 tcg_abort();
403 }
404}
405
fe0de7aa 406static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y)
53108fb5 407{
170ba88f 408 const TCGOpDef *def = &tcg_op_defs[op];
53108fb5 409 TCGArg res = do_constant_folding_2(op, x, y);
170ba88f 410 if (!(def->flags & TCG_OPF_64BIT)) {
29f3ff8d 411 res = (int32_t)res;
53108fb5 412 }
53108fb5
KB
413 return res;
414}
415
9519da7e
RH
416static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c)
417{
418 switch (c) {
419 case TCG_COND_EQ:
420 return x == y;
421 case TCG_COND_NE:
422 return x != y;
423 case TCG_COND_LT:
424 return (int32_t)x < (int32_t)y;
425 case TCG_COND_GE:
426 return (int32_t)x >= (int32_t)y;
427 case TCG_COND_LE:
428 return (int32_t)x <= (int32_t)y;
429 case TCG_COND_GT:
430 return (int32_t)x > (int32_t)y;
431 case TCG_COND_LTU:
432 return x < y;
433 case TCG_COND_GEU:
434 return x >= y;
435 case TCG_COND_LEU:
436 return x <= y;
437 case TCG_COND_GTU:
438 return x > y;
439 default:
440 tcg_abort();
441 }
442}
443
444static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c)
445{
446 switch (c) {
447 case TCG_COND_EQ:
448 return x == y;
449 case TCG_COND_NE:
450 return x != y;
451 case TCG_COND_LT:
452 return (int64_t)x < (int64_t)y;
453 case TCG_COND_GE:
454 return (int64_t)x >= (int64_t)y;
455 case TCG_COND_LE:
456 return (int64_t)x <= (int64_t)y;
457 case TCG_COND_GT:
458 return (int64_t)x > (int64_t)y;
459 case TCG_COND_LTU:
460 return x < y;
461 case TCG_COND_GEU:
462 return x >= y;
463 case TCG_COND_LEU:
464 return x <= y;
465 case TCG_COND_GTU:
466 return x > y;
467 default:
468 tcg_abort();
469 }
470}
471
472static bool do_constant_folding_cond_eq(TCGCond c)
473{
474 switch (c) {
475 case TCG_COND_GT:
476 case TCG_COND_LTU:
477 case TCG_COND_LT:
478 case TCG_COND_GTU:
479 case TCG_COND_NE:
480 return 0;
481 case TCG_COND_GE:
482 case TCG_COND_GEU:
483 case TCG_COND_LE:
484 case TCG_COND_LEU:
485 case TCG_COND_EQ:
486 return 1;
487 default:
488 tcg_abort();
489 }
490}
491
b336ceb6
AJ
492/* Return 2 if the condition can't be simplified, and the result
493 of the condition (0 or 1) if it can */
f8dd19e5
AJ
494static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
495 TCGArg y, TCGCond c)
496{
6349039d
RH
497 tcg_target_ulong xv = arg_info(x)->val;
498 tcg_target_ulong yv = arg_info(y)->val;
499 if (arg_is_const(x) && arg_is_const(y)) {
170ba88f
RH
500 const TCGOpDef *def = &tcg_op_defs[op];
501 tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR));
502 if (def->flags & TCG_OPF_64BIT) {
6349039d 503 return do_constant_folding_cond_64(xv, yv, c);
170ba88f
RH
504 } else {
505 return do_constant_folding_cond_32(xv, yv, c);
b336ceb6 506 }
6349039d 507 } else if (args_are_copies(x, y)) {
9519da7e 508 return do_constant_folding_cond_eq(c);
6349039d 509 } else if (arg_is_const(y) && yv == 0) {
b336ceb6 510 switch (c) {
f8dd19e5 511 case TCG_COND_LTU:
b336ceb6 512 return 0;
f8dd19e5 513 case TCG_COND_GEU:
b336ceb6
AJ
514 return 1;
515 default:
516 return 2;
f8dd19e5 517 }
f8dd19e5 518 }
550276ae 519 return 2;
f8dd19e5
AJ
520}
521
6c4382f8
RH
522/* Return 2 if the condition can't be simplified, and the result
523 of the condition (0 or 1) if it can */
524static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
525{
526 TCGArg al = p1[0], ah = p1[1];
527 TCGArg bl = p2[0], bh = p2[1];
528
6349039d
RH
529 if (arg_is_const(bl) && arg_is_const(bh)) {
530 tcg_target_ulong blv = arg_info(bl)->val;
531 tcg_target_ulong bhv = arg_info(bh)->val;
532 uint64_t b = deposit64(blv, 32, 32, bhv);
6c4382f8 533
6349039d
RH
534 if (arg_is_const(al) && arg_is_const(ah)) {
535 tcg_target_ulong alv = arg_info(al)->val;
536 tcg_target_ulong ahv = arg_info(ah)->val;
537 uint64_t a = deposit64(alv, 32, 32, ahv);
6c4382f8
RH
538 return do_constant_folding_cond_64(a, b, c);
539 }
540 if (b == 0) {
541 switch (c) {
542 case TCG_COND_LTU:
543 return 0;
544 case TCG_COND_GEU:
545 return 1;
546 default:
547 break;
548 }
549 }
550 }
6349039d 551 if (args_are_copies(al, bl) && args_are_copies(ah, bh)) {
6c4382f8
RH
552 return do_constant_folding_cond_eq(c);
553 }
554 return 2;
555}
556
24c9ae4e
RH
557static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2)
558{
559 TCGArg a1 = *p1, a2 = *p2;
560 int sum = 0;
6349039d
RH
561 sum += arg_is_const(a1);
562 sum -= arg_is_const(a2);
24c9ae4e
RH
563
564 /* Prefer the constant in second argument, and then the form
565 op a, a, b, which is better handled on non-RISC hosts. */
566 if (sum > 0 || (sum == 0 && dest == a2)) {
567 *p1 = a2;
568 *p2 = a1;
569 return true;
570 }
571 return false;
572}
573
0bfcb865
RH
574static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
575{
576 int sum = 0;
6349039d
RH
577 sum += arg_is_const(p1[0]);
578 sum += arg_is_const(p1[1]);
579 sum -= arg_is_const(p2[0]);
580 sum -= arg_is_const(p2[1]);
0bfcb865
RH
581 if (sum > 0) {
582 TCGArg t;
583 t = p1[0], p1[0] = p2[0], p2[0] = t;
584 t = p1[1], p1[1] = p2[1], p2[1] = t;
585 return true;
586 }
587 return false;
588}
589
22613af4 590/* Propagate constants and copies, fold constant expressions. */
36e60ef6 591void tcg_optimize(TCGContext *s)
8f2e8c07 592{
15fa08f8
RH
593 int nb_temps, nb_globals;
594 TCGOp *op, *op_next, *prev_mb = NULL;
34184b07
EC
595 struct tcg_temp_info *infos;
596 TCGTempSet temps_used;
5d8f5363 597
22613af4
KB
598 /* Array VALS has an element for each temp.
599 If this temp holds a constant then its value is kept in VALS' element.
e590d4e6
AJ
600 If this temp is a copy of other ones then the other copies are
601 available through the doubly linked circular list. */
8f2e8c07
KB
602
603 nb_temps = s->nb_temps;
604 nb_globals = s->nb_globals;
34184b07
EC
605 bitmap_zero(temps_used.l, nb_temps);
606 infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps);
8f2e8c07 607
15fa08f8 608 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
24666baf 609 tcg_target_ulong mask, partmask, affected;
c45cb8bb 610 int nb_oargs, nb_iargs, i;
cf066674 611 TCGArg tmp;
c45cb8bb
RH
612 TCGOpcode opc = op->opc;
613 const TCGOpDef *def = &tcg_op_defs[opc];
614
1208d7dd
AJ
615 /* Count the arguments, and initialize the temps that are
616 going to be used */
c45cb8bb 617 if (opc == INDEX_op_call) {
cd9090aa
RH
618 nb_oargs = TCGOP_CALLO(op);
619 nb_iargs = TCGOP_CALLI(op);
1208d7dd 620 for (i = 0; i < nb_oargs + nb_iargs; i++) {
6349039d
RH
621 TCGTemp *ts = arg_temp(op->args[i]);
622 if (ts) {
34184b07 623 init_ts_info(infos, &temps_used, ts);
1208d7dd
AJ
624 }
625 }
1ff8c541 626 } else {
cf066674
RH
627 nb_oargs = def->nb_oargs;
628 nb_iargs = def->nb_iargs;
1208d7dd 629 for (i = 0; i < nb_oargs + nb_iargs; i++) {
34184b07 630 init_arg_info(infos, &temps_used, op->args[i]);
1208d7dd 631 }
cf066674
RH
632 }
633
634 /* Do copy propagation */
635 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
6349039d
RH
636 TCGTemp *ts = arg_temp(op->args[i]);
637 if (ts && ts_is_copy(ts)) {
638 op->args[i] = temp_arg(find_better_copy(s, ts));
22613af4
KB
639 }
640 }
641
53108fb5 642 /* For commutative operations make constant second argument */
c45cb8bb 643 switch (opc) {
170ba88f
RH
644 CASE_OP_32_64_VEC(add):
645 CASE_OP_32_64_VEC(mul):
646 CASE_OP_32_64_VEC(and):
647 CASE_OP_32_64_VEC(or):
648 CASE_OP_32_64_VEC(xor):
cb25c80a
RH
649 CASE_OP_32_64(eqv):
650 CASE_OP_32_64(nand):
651 CASE_OP_32_64(nor):
03271524
RH
652 CASE_OP_32_64(muluh):
653 CASE_OP_32_64(mulsh):
acd93701 654 swap_commutative(op->args[0], &op->args[1], &op->args[2]);
53108fb5 655 break;
65a7cce1 656 CASE_OP_32_64(brcond):
acd93701
RH
657 if (swap_commutative(-1, &op->args[0], &op->args[1])) {
658 op->args[2] = tcg_swap_cond(op->args[2]);
65a7cce1
AJ
659 }
660 break;
661 CASE_OP_32_64(setcond):
acd93701
RH
662 if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
663 op->args[3] = tcg_swap_cond(op->args[3]);
65a7cce1
AJ
664 }
665 break;
fa01a208 666 CASE_OP_32_64(movcond):
acd93701
RH
667 if (swap_commutative(-1, &op->args[1], &op->args[2])) {
668 op->args[5] = tcg_swap_cond(op->args[5]);
5d8f5363
RH
669 }
670 /* For movcond, we canonicalize the "false" input reg to match
671 the destination reg so that the tcg backend can implement
672 a "move if true" operation. */
acd93701
RH
673 if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
674 op->args[5] = tcg_invert_cond(op->args[5]);
fa01a208 675 }
1e484e61 676 break;
d7156f7c 677 CASE_OP_32_64(add2):
acd93701
RH
678 swap_commutative(op->args[0], &op->args[2], &op->args[4]);
679 swap_commutative(op->args[1], &op->args[3], &op->args[5]);
1e484e61 680 break;
d7156f7c 681 CASE_OP_32_64(mulu2):
4d3203fd 682 CASE_OP_32_64(muls2):
acd93701 683 swap_commutative(op->args[0], &op->args[2], &op->args[3]);
1414968a 684 break;
0bfcb865 685 case INDEX_op_brcond2_i32:
acd93701
RH
686 if (swap_commutative2(&op->args[0], &op->args[2])) {
687 op->args[4] = tcg_swap_cond(op->args[4]);
0bfcb865
RH
688 }
689 break;
690 case INDEX_op_setcond2_i32:
acd93701
RH
691 if (swap_commutative2(&op->args[1], &op->args[3])) {
692 op->args[5] = tcg_swap_cond(op->args[5]);
0bfcb865
RH
693 }
694 break;
53108fb5
KB
695 default:
696 break;
697 }
698
2d497542
RH
699 /* Simplify expressions for "shift/rot r, 0, a => movi r, 0",
700 and "sub r, 0, a => neg r, a" case. */
c45cb8bb 701 switch (opc) {
01ee5282
AJ
702 CASE_OP_32_64(shl):
703 CASE_OP_32_64(shr):
704 CASE_OP_32_64(sar):
705 CASE_OP_32_64(rotl):
706 CASE_OP_32_64(rotr):
6349039d
RH
707 if (arg_is_const(op->args[1])
708 && arg_info(op->args[1])->val == 0) {
acd93701 709 tcg_opt_gen_movi(s, op, op->args[0], 0);
01ee5282
AJ
710 continue;
711 }
712 break;
170ba88f 713 CASE_OP_32_64_VEC(sub):
2d497542
RH
714 {
715 TCGOpcode neg_op;
716 bool have_neg;
717
6349039d 718 if (arg_is_const(op->args[2])) {
2d497542
RH
719 /* Proceed with possible constant folding. */
720 break;
721 }
c45cb8bb 722 if (opc == INDEX_op_sub_i32) {
2d497542
RH
723 neg_op = INDEX_op_neg_i32;
724 have_neg = TCG_TARGET_HAS_neg_i32;
170ba88f 725 } else if (opc == INDEX_op_sub_i64) {
2d497542
RH
726 neg_op = INDEX_op_neg_i64;
727 have_neg = TCG_TARGET_HAS_neg_i64;
170ba88f
RH
728 } else {
729 neg_op = INDEX_op_neg_vec;
730 have_neg = TCG_TARGET_HAS_neg_vec;
2d497542
RH
731 }
732 if (!have_neg) {
733 break;
734 }
6349039d
RH
735 if (arg_is_const(op->args[1])
736 && arg_info(op->args[1])->val == 0) {
c45cb8bb 737 op->opc = neg_op;
acd93701
RH
738 reset_temp(op->args[0]);
739 op->args[1] = op->args[2];
2d497542
RH
740 continue;
741 }
742 }
743 break;
170ba88f 744 CASE_OP_32_64_VEC(xor):
e201b564 745 CASE_OP_32_64(nand):
6349039d
RH
746 if (!arg_is_const(op->args[1])
747 && arg_is_const(op->args[2])
748 && arg_info(op->args[2])->val == -1) {
e201b564
RH
749 i = 1;
750 goto try_not;
751 }
752 break;
753 CASE_OP_32_64(nor):
6349039d
RH
754 if (!arg_is_const(op->args[1])
755 && arg_is_const(op->args[2])
756 && arg_info(op->args[2])->val == 0) {
e201b564
RH
757 i = 1;
758 goto try_not;
759 }
760 break;
170ba88f 761 CASE_OP_32_64_VEC(andc):
6349039d
RH
762 if (!arg_is_const(op->args[2])
763 && arg_is_const(op->args[1])
764 && arg_info(op->args[1])->val == -1) {
e201b564
RH
765 i = 2;
766 goto try_not;
767 }
768 break;
170ba88f 769 CASE_OP_32_64_VEC(orc):
e201b564 770 CASE_OP_32_64(eqv):
6349039d
RH
771 if (!arg_is_const(op->args[2])
772 && arg_is_const(op->args[1])
773 && arg_info(op->args[1])->val == 0) {
e201b564
RH
774 i = 2;
775 goto try_not;
776 }
777 break;
778 try_not:
779 {
780 TCGOpcode not_op;
781 bool have_not;
782
170ba88f
RH
783 if (def->flags & TCG_OPF_VECTOR) {
784 not_op = INDEX_op_not_vec;
785 have_not = TCG_TARGET_HAS_not_vec;
786 } else if (def->flags & TCG_OPF_64BIT) {
e201b564
RH
787 not_op = INDEX_op_not_i64;
788 have_not = TCG_TARGET_HAS_not_i64;
789 } else {
790 not_op = INDEX_op_not_i32;
791 have_not = TCG_TARGET_HAS_not_i32;
792 }
793 if (!have_not) {
794 break;
795 }
c45cb8bb 796 op->opc = not_op;
acd93701
RH
797 reset_temp(op->args[0]);
798 op->args[1] = op->args[i];
e201b564
RH
799 continue;
800 }
01ee5282
AJ
801 default:
802 break;
803 }
804
464a1441 805 /* Simplify expression for "op r, a, const => mov r, a" cases */
c45cb8bb 806 switch (opc) {
170ba88f
RH
807 CASE_OP_32_64_VEC(add):
808 CASE_OP_32_64_VEC(sub):
809 CASE_OP_32_64_VEC(or):
810 CASE_OP_32_64_VEC(xor):
811 CASE_OP_32_64_VEC(andc):
55c0975c
KB
812 CASE_OP_32_64(shl):
813 CASE_OP_32_64(shr):
814 CASE_OP_32_64(sar):
25c4d9cc
RH
815 CASE_OP_32_64(rotl):
816 CASE_OP_32_64(rotr):
6349039d
RH
817 if (!arg_is_const(op->args[1])
818 && arg_is_const(op->args[2])
819 && arg_info(op->args[2])->val == 0) {
acd93701 820 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
97a79eb7 821 continue;
53108fb5
KB
822 }
823 break;
170ba88f
RH
824 CASE_OP_32_64_VEC(and):
825 CASE_OP_32_64_VEC(orc):
464a1441 826 CASE_OP_32_64(eqv):
6349039d
RH
827 if (!arg_is_const(op->args[1])
828 && arg_is_const(op->args[2])
829 && arg_info(op->args[2])->val == -1) {
acd93701 830 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
97a79eb7 831 continue;
464a1441
RH
832 }
833 break;
56e49438
AJ
834 default:
835 break;
836 }
837
3031244b
AJ
838 /* Simplify using known-zero bits. Currently only ops with a single
839 output argument is supported. */
3a9d8b17 840 mask = -1;
633f6502 841 affected = -1;
c45cb8bb 842 switch (opc) {
3a9d8b17 843 CASE_OP_32_64(ext8s):
6349039d 844 if ((arg_info(op->args[1])->mask & 0x80) != 0) {
3a9d8b17
PB
845 break;
846 }
847 CASE_OP_32_64(ext8u):
848 mask = 0xff;
849 goto and_const;
850 CASE_OP_32_64(ext16s):
6349039d 851 if ((arg_info(op->args[1])->mask & 0x8000) != 0) {
3a9d8b17
PB
852 break;
853 }
854 CASE_OP_32_64(ext16u):
855 mask = 0xffff;
856 goto and_const;
857 case INDEX_op_ext32s_i64:
6349039d 858 if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
3a9d8b17
PB
859 break;
860 }
861 case INDEX_op_ext32u_i64:
862 mask = 0xffffffffU;
863 goto and_const;
864
865 CASE_OP_32_64(and):
6349039d
RH
866 mask = arg_info(op->args[2])->mask;
867 if (arg_is_const(op->args[2])) {
3a9d8b17 868 and_const:
6349039d 869 affected = arg_info(op->args[1])->mask & ~mask;
3a9d8b17 870 }
6349039d 871 mask = arg_info(op->args[1])->mask & mask;
3a9d8b17
PB
872 break;
873
8bcb5c8f 874 case INDEX_op_ext_i32_i64:
6349039d 875 if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
8bcb5c8f
AJ
876 break;
877 }
878 case INDEX_op_extu_i32_i64:
879 /* We do not compute affected as it is a size changing op. */
6349039d 880 mask = (uint32_t)arg_info(op->args[1])->mask;
8bcb5c8f
AJ
881 break;
882
23ec69ed
RH
883 CASE_OP_32_64(andc):
884 /* Known-zeros does not imply known-ones. Therefore unless
acd93701 885 op->args[2] is constant, we can't infer anything from it. */
6349039d
RH
886 if (arg_is_const(op->args[2])) {
887 mask = ~arg_info(op->args[2])->mask;
23ec69ed
RH
888 goto and_const;
889 }
6349039d
RH
890 /* But we certainly know nothing outside args[1] may be set. */
891 mask = arg_info(op->args[1])->mask;
23ec69ed
RH
892 break;
893
e46b225a 894 case INDEX_op_sar_i32:
6349039d
RH
895 if (arg_is_const(op->args[2])) {
896 tmp = arg_info(op->args[2])->val & 31;
897 mask = (int32_t)arg_info(op->args[1])->mask >> tmp;
e46b225a
AJ
898 }
899 break;
900 case INDEX_op_sar_i64:
6349039d
RH
901 if (arg_is_const(op->args[2])) {
902 tmp = arg_info(op->args[2])->val & 63;
903 mask = (int64_t)arg_info(op->args[1])->mask >> tmp;
3a9d8b17
PB
904 }
905 break;
906
e46b225a 907 case INDEX_op_shr_i32:
6349039d
RH
908 if (arg_is_const(op->args[2])) {
909 tmp = arg_info(op->args[2])->val & 31;
910 mask = (uint32_t)arg_info(op->args[1])->mask >> tmp;
e46b225a
AJ
911 }
912 break;
913 case INDEX_op_shr_i64:
6349039d
RH
914 if (arg_is_const(op->args[2])) {
915 tmp = arg_info(op->args[2])->val & 63;
916 mask = (uint64_t)arg_info(op->args[1])->mask >> tmp;
3a9d8b17
PB
917 }
918 break;
919
609ad705 920 case INDEX_op_extrl_i64_i32:
6349039d 921 mask = (uint32_t)arg_info(op->args[1])->mask;
609ad705
RH
922 break;
923 case INDEX_op_extrh_i64_i32:
6349039d 924 mask = (uint64_t)arg_info(op->args[1])->mask >> 32;
4bb7a41e
RH
925 break;
926
3a9d8b17 927 CASE_OP_32_64(shl):
6349039d
RH
928 if (arg_is_const(op->args[2])) {
929 tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1);
930 mask = arg_info(op->args[1])->mask << tmp;
3a9d8b17
PB
931 }
932 break;
933
934 CASE_OP_32_64(neg):
935 /* Set to 1 all bits to the left of the rightmost. */
6349039d
RH
936 mask = -(arg_info(op->args[1])->mask
937 & -arg_info(op->args[1])->mask);
3a9d8b17
PB
938 break;
939
940 CASE_OP_32_64(deposit):
6349039d
RH
941 mask = deposit64(arg_info(op->args[1])->mask,
942 op->args[3], op->args[4],
943 arg_info(op->args[2])->mask);
3a9d8b17
PB
944 break;
945
7ec8bab3 946 CASE_OP_32_64(extract):
6349039d
RH
947 mask = extract64(arg_info(op->args[1])->mask,
948 op->args[2], op->args[3]);
acd93701 949 if (op->args[2] == 0) {
6349039d 950 affected = arg_info(op->args[1])->mask & ~mask;
7ec8bab3
RH
951 }
952 break;
953 CASE_OP_32_64(sextract):
6349039d 954 mask = sextract64(arg_info(op->args[1])->mask,
acd93701
RH
955 op->args[2], op->args[3]);
956 if (op->args[2] == 0 && (tcg_target_long)mask >= 0) {
6349039d 957 affected = arg_info(op->args[1])->mask & ~mask;
7ec8bab3
RH
958 }
959 break;
960
3a9d8b17
PB
961 CASE_OP_32_64(or):
962 CASE_OP_32_64(xor):
6349039d 963 mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask;
3a9d8b17
PB
964 break;
965
0e28d006
RH
966 case INDEX_op_clz_i32:
967 case INDEX_op_ctz_i32:
6349039d 968 mask = arg_info(op->args[2])->mask | 31;
0e28d006
RH
969 break;
970
971 case INDEX_op_clz_i64:
972 case INDEX_op_ctz_i64:
6349039d 973 mask = arg_info(op->args[2])->mask | 63;
0e28d006
RH
974 break;
975
a768e4e9
RH
976 case INDEX_op_ctpop_i32:
977 mask = 32 | 31;
978 break;
979 case INDEX_op_ctpop_i64:
980 mask = 64 | 63;
981 break;
982
3a9d8b17 983 CASE_OP_32_64(setcond):
a763551a 984 case INDEX_op_setcond2_i32:
3a9d8b17
PB
985 mask = 1;
986 break;
987
988 CASE_OP_32_64(movcond):
6349039d 989 mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask;
3a9d8b17
PB
990 break;
991
c8d70272 992 CASE_OP_32_64(ld8u):
c8d70272
AJ
993 mask = 0xff;
994 break;
995 CASE_OP_32_64(ld16u):
c8d70272
AJ
996 mask = 0xffff;
997 break;
998 case INDEX_op_ld32u_i64:
c8d70272
AJ
999 mask = 0xffffffffu;
1000 break;
1001
1002 CASE_OP_32_64(qemu_ld):
1003 {
acd93701 1004 TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
59227d5d 1005 TCGMemOp mop = get_memop(oi);
c8d70272
AJ
1006 if (!(mop & MO_SIGN)) {
1007 mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
1008 }
1009 }
1010 break;
1011
3a9d8b17
PB
1012 default:
1013 break;
1014 }
1015
bc8d688f
RH
1016 /* 32-bit ops generate 32-bit results. For the result is zero test
1017 below, we can ignore high bits, but for further optimizations we
1018 need to record that the high bits contain garbage. */
24666baf 1019 partmask = mask;
bc8d688f 1020 if (!(def->flags & TCG_OPF_64BIT)) {
24666baf
RH
1021 mask |= ~(tcg_target_ulong)0xffffffffu;
1022 partmask &= 0xffffffffu;
1023 affected &= 0xffffffffu;
f096dc96
AJ
1024 }
1025
24666baf 1026 if (partmask == 0) {
eabb7b91 1027 tcg_debug_assert(nb_oargs == 1);
acd93701 1028 tcg_opt_gen_movi(s, op, op->args[0], 0);
633f6502
PB
1029 continue;
1030 }
1031 if (affected == 0) {
eabb7b91 1032 tcg_debug_assert(nb_oargs == 1);
acd93701 1033 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
633f6502
PB
1034 continue;
1035 }
1036
56e49438 1037 /* Simplify expression for "op r, a, 0 => movi r, 0" cases */
c45cb8bb 1038 switch (opc) {
170ba88f
RH
1039 CASE_OP_32_64_VEC(and):
1040 CASE_OP_32_64_VEC(mul):
03271524
RH
1041 CASE_OP_32_64(muluh):
1042 CASE_OP_32_64(mulsh):
6349039d
RH
1043 if (arg_is_const(op->args[2])
1044 && arg_info(op->args[2])->val == 0) {
acd93701 1045 tcg_opt_gen_movi(s, op, op->args[0], 0);
53108fb5
KB
1046 continue;
1047 }
1048 break;
56e49438
AJ
1049 default:
1050 break;
1051 }
1052
1053 /* Simplify expression for "op r, a, a => mov r, a" cases */
c45cb8bb 1054 switch (opc) {
170ba88f
RH
1055 CASE_OP_32_64_VEC(or):
1056 CASE_OP_32_64_VEC(and):
6349039d 1057 if (args_are_copies(op->args[1], op->args[2])) {
acd93701 1058 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
9a81090b
KB
1059 continue;
1060 }
1061 break;
fe0de7aa
BS
1062 default:
1063 break;
53108fb5
KB
1064 }
1065
3c94193e 1066 /* Simplify expression for "op r, a, a => movi r, 0" cases */
c45cb8bb 1067 switch (opc) {
170ba88f
RH
1068 CASE_OP_32_64_VEC(andc):
1069 CASE_OP_32_64_VEC(sub):
1070 CASE_OP_32_64_VEC(xor):
6349039d 1071 if (args_are_copies(op->args[1], op->args[2])) {
acd93701 1072 tcg_opt_gen_movi(s, op, op->args[0], 0);
3c94193e
AJ
1073 continue;
1074 }
1075 break;
1076 default:
1077 break;
1078 }
1079
22613af4
KB
1080 /* Propagate constants through copy operations and do constant
1081 folding. Constants will be substituted to arguments by register
1082 allocator where needed and possible. Also detect copies. */
c45cb8bb 1083 switch (opc) {
170ba88f 1084 CASE_OP_32_64_VEC(mov):
acd93701 1085 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
97a79eb7 1086 break;
22613af4 1087 CASE_OP_32_64(movi):
170ba88f 1088 case INDEX_op_dupi_vec:
acd93701 1089 tcg_opt_gen_movi(s, op, op->args[0], op->args[1]);
22613af4 1090 break;
6e14e91b 1091
170ba88f
RH
1092 case INDEX_op_dup_vec:
1093 if (arg_is_const(op->args[1])) {
1094 tmp = arg_info(op->args[1])->val;
1095 tmp = dup_const(TCGOP_VECE(op), tmp);
1096 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1097 continue;
1098 }
1099 break;
1100
a640f031 1101 CASE_OP_32_64(not):
cb25c80a 1102 CASE_OP_32_64(neg):
25c4d9cc
RH
1103 CASE_OP_32_64(ext8s):
1104 CASE_OP_32_64(ext8u):
1105 CASE_OP_32_64(ext16s):
1106 CASE_OP_32_64(ext16u):
a768e4e9 1107 CASE_OP_32_64(ctpop):
a640f031
KB
1108 case INDEX_op_ext32s_i64:
1109 case INDEX_op_ext32u_i64:
8bcb5c8f
AJ
1110 case INDEX_op_ext_i32_i64:
1111 case INDEX_op_extu_i32_i64:
609ad705
RH
1112 case INDEX_op_extrl_i64_i32:
1113 case INDEX_op_extrh_i64_i32:
6349039d
RH
1114 if (arg_is_const(op->args[1])) {
1115 tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
acd93701 1116 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1117 break;
a640f031 1118 }
6e14e91b
RH
1119 goto do_default;
1120
53108fb5
KB
1121 CASE_OP_32_64(add):
1122 CASE_OP_32_64(sub):
1123 CASE_OP_32_64(mul):
9a81090b
KB
1124 CASE_OP_32_64(or):
1125 CASE_OP_32_64(and):
1126 CASE_OP_32_64(xor):
55c0975c
KB
1127 CASE_OP_32_64(shl):
1128 CASE_OP_32_64(shr):
1129 CASE_OP_32_64(sar):
25c4d9cc
RH
1130 CASE_OP_32_64(rotl):
1131 CASE_OP_32_64(rotr):
cb25c80a
RH
1132 CASE_OP_32_64(andc):
1133 CASE_OP_32_64(orc):
1134 CASE_OP_32_64(eqv):
1135 CASE_OP_32_64(nand):
1136 CASE_OP_32_64(nor):
03271524
RH
1137 CASE_OP_32_64(muluh):
1138 CASE_OP_32_64(mulsh):
01547f7f
RH
1139 CASE_OP_32_64(div):
1140 CASE_OP_32_64(divu):
1141 CASE_OP_32_64(rem):
1142 CASE_OP_32_64(remu):
6349039d
RH
1143 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1144 tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
1145 arg_info(op->args[2])->val);
acd93701 1146 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1147 break;
53108fb5 1148 }
6e14e91b
RH
1149 goto do_default;
1150
0e28d006
RH
1151 CASE_OP_32_64(clz):
1152 CASE_OP_32_64(ctz):
6349039d
RH
1153 if (arg_is_const(op->args[1])) {
1154 TCGArg v = arg_info(op->args[1])->val;
0e28d006
RH
1155 if (v != 0) {
1156 tmp = do_constant_folding(opc, v, 0);
acd93701 1157 tcg_opt_gen_movi(s, op, op->args[0], tmp);
0e28d006 1158 } else {
acd93701 1159 tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
0e28d006
RH
1160 }
1161 break;
1162 }
1163 goto do_default;
1164
7ef55fc9 1165 CASE_OP_32_64(deposit):
6349039d
RH
1166 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1167 tmp = deposit64(arg_info(op->args[1])->val,
1168 op->args[3], op->args[4],
1169 arg_info(op->args[2])->val);
acd93701 1170 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1171 break;
7ef55fc9 1172 }
6e14e91b
RH
1173 goto do_default;
1174
7ec8bab3 1175 CASE_OP_32_64(extract):
6349039d
RH
1176 if (arg_is_const(op->args[1])) {
1177 tmp = extract64(arg_info(op->args[1])->val,
acd93701
RH
1178 op->args[2], op->args[3]);
1179 tcg_opt_gen_movi(s, op, op->args[0], tmp);
7ec8bab3
RH
1180 break;
1181 }
1182 goto do_default;
1183
1184 CASE_OP_32_64(sextract):
6349039d
RH
1185 if (arg_is_const(op->args[1])) {
1186 tmp = sextract64(arg_info(op->args[1])->val,
acd93701
RH
1187 op->args[2], op->args[3]);
1188 tcg_opt_gen_movi(s, op, op->args[0], tmp);
7ec8bab3
RH
1189 break;
1190 }
1191 goto do_default;
1192
f8dd19e5 1193 CASE_OP_32_64(setcond):
acd93701
RH
1194 tmp = do_constant_folding_cond(opc, op->args[1],
1195 op->args[2], op->args[3]);
b336ceb6 1196 if (tmp != 2) {
acd93701 1197 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1198 break;
f8dd19e5 1199 }
6e14e91b
RH
1200 goto do_default;
1201
fbeaa26c 1202 CASE_OP_32_64(brcond):
acd93701
RH
1203 tmp = do_constant_folding_cond(opc, op->args[0],
1204 op->args[1], op->args[2]);
b336ceb6
AJ
1205 if (tmp != 2) {
1206 if (tmp) {
34184b07 1207 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1208 op->opc = INDEX_op_br;
acd93701 1209 op->args[0] = op->args[3];
fbeaa26c 1210 } else {
0c627cdc 1211 tcg_op_remove(s, op);
fbeaa26c 1212 }
6e14e91b 1213 break;
fbeaa26c 1214 }
6e14e91b
RH
1215 goto do_default;
1216
fa01a208 1217 CASE_OP_32_64(movcond):
acd93701
RH
1218 tmp = do_constant_folding_cond(opc, op->args[1],
1219 op->args[2], op->args[5]);
b336ceb6 1220 if (tmp != 2) {
acd93701 1221 tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
6e14e91b 1222 break;
fa01a208 1223 }
6349039d
RH
1224 if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
1225 tcg_target_ulong tv = arg_info(op->args[3])->val;
1226 tcg_target_ulong fv = arg_info(op->args[4])->val;
acd93701 1227 TCGCond cond = op->args[5];
333b21b8
RH
1228 if (fv == 1 && tv == 0) {
1229 cond = tcg_invert_cond(cond);
1230 } else if (!(tv == 1 && fv == 0)) {
1231 goto do_default;
1232 }
acd93701 1233 op->args[3] = cond;
333b21b8
RH
1234 op->opc = opc = (opc == INDEX_op_movcond_i32
1235 ? INDEX_op_setcond_i32
1236 : INDEX_op_setcond_i64);
1237 nb_iargs = 2;
1238 }
6e14e91b 1239 goto do_default;
212c328d
RH
1240
1241 case INDEX_op_add2_i32:
1242 case INDEX_op_sub2_i32:
6349039d
RH
1243 if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])
1244 && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
1245 uint32_t al = arg_info(op->args[2])->val;
1246 uint32_t ah = arg_info(op->args[3])->val;
1247 uint32_t bl = arg_info(op->args[4])->val;
1248 uint32_t bh = arg_info(op->args[5])->val;
212c328d
RH
1249 uint64_t a = ((uint64_t)ah << 32) | al;
1250 uint64_t b = ((uint64_t)bh << 32) | bl;
1251 TCGArg rl, rh;
5a18407f 1252 TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2);
212c328d 1253
c45cb8bb 1254 if (opc == INDEX_op_add2_i32) {
212c328d
RH
1255 a += b;
1256 } else {
1257 a -= b;
1258 }
1259
acd93701
RH
1260 rl = op->args[0];
1261 rh = op->args[1];
1262 tcg_opt_gen_movi(s, op, rl, (int32_t)a);
1263 tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32));
212c328d
RH
1264 break;
1265 }
1266 goto do_default;
1414968a
RH
1267
1268 case INDEX_op_mulu2_i32:
6349039d
RH
1269 if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
1270 uint32_t a = arg_info(op->args[2])->val;
1271 uint32_t b = arg_info(op->args[3])->val;
1414968a
RH
1272 uint64_t r = (uint64_t)a * b;
1273 TCGArg rl, rh;
5a18407f 1274 TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2);
1414968a 1275
acd93701
RH
1276 rl = op->args[0];
1277 rh = op->args[1];
1278 tcg_opt_gen_movi(s, op, rl, (int32_t)r);
1279 tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32));
1414968a
RH
1280 break;
1281 }
1282 goto do_default;
6e14e91b 1283
bc1473ef 1284 case INDEX_op_brcond2_i32:
acd93701
RH
1285 tmp = do_constant_folding_cond2(&op->args[0], &op->args[2],
1286 op->args[4]);
6c4382f8
RH
1287 if (tmp != 2) {
1288 if (tmp) {
a763551a 1289 do_brcond_true:
34184b07 1290 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1291 op->opc = INDEX_op_br;
acd93701 1292 op->args[0] = op->args[5];
6c4382f8 1293 } else {
a763551a 1294 do_brcond_false:
0c627cdc 1295 tcg_op_remove(s, op);
6c4382f8 1296 }
acd93701
RH
1297 } else if ((op->args[4] == TCG_COND_LT
1298 || op->args[4] == TCG_COND_GE)
6349039d
RH
1299 && arg_is_const(op->args[2])
1300 && arg_info(op->args[2])->val == 0
1301 && arg_is_const(op->args[3])
1302 && arg_info(op->args[3])->val == 0) {
6c4382f8
RH
1303 /* Simplify LT/GE comparisons vs zero to a single compare
1304 vs the high word of the input. */
a763551a 1305 do_brcond_high:
34184b07 1306 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1307 op->opc = INDEX_op_brcond_i32;
acd93701
RH
1308 op->args[0] = op->args[1];
1309 op->args[1] = op->args[3];
1310 op->args[2] = op->args[4];
1311 op->args[3] = op->args[5];
1312 } else if (op->args[4] == TCG_COND_EQ) {
a763551a
RH
1313 /* Simplify EQ comparisons where one of the pairs
1314 can be simplified. */
1315 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1316 op->args[0], op->args[2],
1317 TCG_COND_EQ);
a763551a
RH
1318 if (tmp == 0) {
1319 goto do_brcond_false;
1320 } else if (tmp == 1) {
1321 goto do_brcond_high;
1322 }
1323 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1324 op->args[1], op->args[3],
1325 TCG_COND_EQ);
a763551a
RH
1326 if (tmp == 0) {
1327 goto do_brcond_false;
1328 } else if (tmp != 1) {
1329 goto do_default;
1330 }
1331 do_brcond_low:
34184b07 1332 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1333 op->opc = INDEX_op_brcond_i32;
acd93701
RH
1334 op->args[1] = op->args[2];
1335 op->args[2] = op->args[4];
1336 op->args[3] = op->args[5];
1337 } else if (op->args[4] == TCG_COND_NE) {
a763551a
RH
1338 /* Simplify NE comparisons where one of the pairs
1339 can be simplified. */
1340 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1341 op->args[0], op->args[2],
1342 TCG_COND_NE);
a763551a
RH
1343 if (tmp == 0) {
1344 goto do_brcond_high;
1345 } else if (tmp == 1) {
1346 goto do_brcond_true;
1347 }
1348 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1349 op->args[1], op->args[3],
1350 TCG_COND_NE);
a763551a
RH
1351 if (tmp == 0) {
1352 goto do_brcond_low;
1353 } else if (tmp == 1) {
1354 goto do_brcond_true;
1355 }
1356 goto do_default;
6c4382f8
RH
1357 } else {
1358 goto do_default;
bc1473ef 1359 }
6c4382f8 1360 break;
bc1473ef
RH
1361
1362 case INDEX_op_setcond2_i32:
acd93701
RH
1363 tmp = do_constant_folding_cond2(&op->args[1], &op->args[3],
1364 op->args[5]);
6c4382f8 1365 if (tmp != 2) {
a763551a 1366 do_setcond_const:
acd93701
RH
1367 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1368 } else if ((op->args[5] == TCG_COND_LT
1369 || op->args[5] == TCG_COND_GE)
6349039d
RH
1370 && arg_is_const(op->args[3])
1371 && arg_info(op->args[3])->val == 0
1372 && arg_is_const(op->args[4])
1373 && arg_info(op->args[4])->val == 0) {
6c4382f8
RH
1374 /* Simplify LT/GE comparisons vs zero to a single compare
1375 vs the high word of the input. */
a763551a 1376 do_setcond_high:
acd93701 1377 reset_temp(op->args[0]);
6349039d 1378 arg_info(op->args[0])->mask = 1;
c45cb8bb 1379 op->opc = INDEX_op_setcond_i32;
acd93701
RH
1380 op->args[1] = op->args[2];
1381 op->args[2] = op->args[4];
1382 op->args[3] = op->args[5];
1383 } else if (op->args[5] == TCG_COND_EQ) {
a763551a
RH
1384 /* Simplify EQ comparisons where one of the pairs
1385 can be simplified. */
1386 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1387 op->args[1], op->args[3],
1388 TCG_COND_EQ);
a763551a
RH
1389 if (tmp == 0) {
1390 goto do_setcond_const;
1391 } else if (tmp == 1) {
1392 goto do_setcond_high;
1393 }
1394 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1395 op->args[2], op->args[4],
1396 TCG_COND_EQ);
a763551a
RH
1397 if (tmp == 0) {
1398 goto do_setcond_high;
1399 } else if (tmp != 1) {
1400 goto do_default;
1401 }
1402 do_setcond_low:
acd93701 1403 reset_temp(op->args[0]);
6349039d 1404 arg_info(op->args[0])->mask = 1;
c45cb8bb 1405 op->opc = INDEX_op_setcond_i32;
acd93701
RH
1406 op->args[2] = op->args[3];
1407 op->args[3] = op->args[5];
1408 } else if (op->args[5] == TCG_COND_NE) {
a763551a
RH
1409 /* Simplify NE comparisons where one of the pairs
1410 can be simplified. */
1411 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1412 op->args[1], op->args[3],
1413 TCG_COND_NE);
a763551a
RH
1414 if (tmp == 0) {
1415 goto do_setcond_high;
1416 } else if (tmp == 1) {
1417 goto do_setcond_const;
1418 }
1419 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1420 op->args[2], op->args[4],
1421 TCG_COND_NE);
a763551a
RH
1422 if (tmp == 0) {
1423 goto do_setcond_low;
1424 } else if (tmp == 1) {
1425 goto do_setcond_const;
1426 }
1427 goto do_default;
6c4382f8
RH
1428 } else {
1429 goto do_default;
bc1473ef 1430 }
6c4382f8 1431 break;
bc1473ef 1432
8f2e8c07 1433 case INDEX_op_call:
acd93701 1434 if (!(op->args[nb_oargs + nb_iargs + 1]
cf066674 1435 & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
22613af4 1436 for (i = 0; i < nb_globals; i++) {
1208d7dd 1437 if (test_bit(i, temps_used.l)) {
6349039d 1438 reset_ts(&s->temps[i]);
1208d7dd 1439 }
22613af4
KB
1440 }
1441 }
cf066674 1442 goto do_reset_output;
6e14e91b 1443
8f2e8c07 1444 default:
6e14e91b
RH
1445 do_default:
1446 /* Default case: we know nothing about operation (or were unable
1447 to compute the operation result) so no propagation is done.
1448 We trash everything if the operation is the end of a basic
3a9d8b17
PB
1449 block, otherwise we only trash the output args. "mask" is
1450 the non-zero bits mask for the first output arg. */
a2550660 1451 if (def->flags & TCG_OPF_BB_END) {
34184b07 1452 bitmap_zero(temps_used.l, nb_temps);
a2550660 1453 } else {
cf066674
RH
1454 do_reset_output:
1455 for (i = 0; i < nb_oargs; i++) {
acd93701 1456 reset_temp(op->args[i]);
3031244b
AJ
1457 /* Save the corresponding known-zero bits mask for the
1458 first output argument (only one supported so far). */
1459 if (i == 0) {
6349039d 1460 arg_info(op->args[i])->mask = mask;
3031244b 1461 }
a2550660 1462 }
22613af4 1463 }
8f2e8c07
KB
1464 break;
1465 }
34f93921
PK
1466
1467 /* Eliminate duplicate and redundant fence instructions. */
acd93701 1468 if (prev_mb) {
34f93921
PK
1469 switch (opc) {
1470 case INDEX_op_mb:
1471 /* Merge two barriers of the same type into one,
1472 * or a weaker barrier into a stronger one,
1473 * or two weaker barriers into a stronger one.
1474 * mb X; mb Y => mb X|Y
1475 * mb; strl => mb; st
1476 * ldaq; mb => ld; mb
1477 * ldaq; strl => ld; mb; st
1478 * Other combinations are also merged into a strong
1479 * barrier. This is stricter than specified but for
1480 * the purposes of TCG is better than not optimizing.
1481 */
acd93701 1482 prev_mb->args[0] |= op->args[0];
34f93921
PK
1483 tcg_op_remove(s, op);
1484 break;
1485
1486 default:
1487 /* Opcodes that end the block stop the optimization. */
1488 if ((def->flags & TCG_OPF_BB_END) == 0) {
1489 break;
1490 }
1491 /* fallthru */
1492 case INDEX_op_qemu_ld_i32:
1493 case INDEX_op_qemu_ld_i64:
1494 case INDEX_op_qemu_st_i32:
1495 case INDEX_op_qemu_st_i64:
1496 case INDEX_op_call:
1497 /* Opcodes that touch guest memory stop the optimization. */
acd93701 1498 prev_mb = NULL;
34f93921
PK
1499 break;
1500 }
1501 } else if (opc == INDEX_op_mb) {
acd93701 1502 prev_mb = op;
34f93921 1503 }
8f2e8c07 1504 }
8f2e8c07 1505}