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1 | /* |
2 | * Optimizations for Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2010 Samsung Electronics. | |
5 | * Contributed by Kirill Batuzov <batuzovk@ispras.ru> | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
757e725b | 26 | #include "qemu/osdep.h" |
dcb32f1d | 27 | #include "tcg/tcg-op.h" |
90163900 | 28 | #include "tcg-internal.h" |
8f2e8c07 | 29 | |
8f2e8c07 KB |
30 | #define CASE_OP_32_64(x) \ |
31 | glue(glue(case INDEX_op_, x), _i32): \ | |
32 | glue(glue(case INDEX_op_, x), _i64) | |
8f2e8c07 | 33 | |
170ba88f RH |
34 | #define CASE_OP_32_64_VEC(x) \ |
35 | glue(glue(case INDEX_op_, x), _i32): \ | |
36 | glue(glue(case INDEX_op_, x), _i64): \ | |
37 | glue(glue(case INDEX_op_, x), _vec) | |
38 | ||
6fcb98ed | 39 | typedef struct TempOptInfo { |
b41059dd | 40 | bool is_const; |
6349039d RH |
41 | TCGTemp *prev_copy; |
42 | TCGTemp *next_copy; | |
54795544 | 43 | uint64_t val; |
b1fde411 | 44 | uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */ |
6fcb98ed | 45 | } TempOptInfo; |
22613af4 | 46 | |
3b3f847d | 47 | typedef struct OptContext { |
dc84988a | 48 | TCGContext *tcg; |
3b3f847d RH |
49 | TCGTempSet temps_used; |
50 | } OptContext; | |
51 | ||
6fcb98ed | 52 | static inline TempOptInfo *ts_info(TCGTemp *ts) |
d9c769c6 | 53 | { |
6349039d | 54 | return ts->state_ptr; |
d9c769c6 AJ |
55 | } |
56 | ||
6fcb98ed | 57 | static inline TempOptInfo *arg_info(TCGArg arg) |
d9c769c6 | 58 | { |
6349039d RH |
59 | return ts_info(arg_temp(arg)); |
60 | } | |
61 | ||
62 | static inline bool ts_is_const(TCGTemp *ts) | |
63 | { | |
64 | return ts_info(ts)->is_const; | |
65 | } | |
66 | ||
67 | static inline bool arg_is_const(TCGArg arg) | |
68 | { | |
69 | return ts_is_const(arg_temp(arg)); | |
70 | } | |
71 | ||
72 | static inline bool ts_is_copy(TCGTemp *ts) | |
73 | { | |
74 | return ts_info(ts)->next_copy != ts; | |
d9c769c6 AJ |
75 | } |
76 | ||
b41059dd | 77 | /* Reset TEMP's state, possibly removing the temp for the list of copies. */ |
6349039d RH |
78 | static void reset_ts(TCGTemp *ts) |
79 | { | |
6fcb98ed RH |
80 | TempOptInfo *ti = ts_info(ts); |
81 | TempOptInfo *pi = ts_info(ti->prev_copy); | |
82 | TempOptInfo *ni = ts_info(ti->next_copy); | |
6349039d RH |
83 | |
84 | ni->prev_copy = ti->prev_copy; | |
85 | pi->next_copy = ti->next_copy; | |
86 | ti->next_copy = ts; | |
87 | ti->prev_copy = ts; | |
88 | ti->is_const = false; | |
b1fde411 | 89 | ti->z_mask = -1; |
6349039d RH |
90 | } |
91 | ||
92 | static void reset_temp(TCGArg arg) | |
22613af4 | 93 | { |
6349039d | 94 | reset_ts(arg_temp(arg)); |
22613af4 KB |
95 | } |
96 | ||
1208d7dd | 97 | /* Initialize and activate a temporary. */ |
3b3f847d | 98 | static void init_ts_info(OptContext *ctx, TCGTemp *ts) |
1208d7dd | 99 | { |
6349039d | 100 | size_t idx = temp_idx(ts); |
8f17a975 | 101 | TempOptInfo *ti; |
6349039d | 102 | |
3b3f847d | 103 | if (test_bit(idx, ctx->temps_used.l)) { |
8f17a975 RH |
104 | return; |
105 | } | |
3b3f847d | 106 | set_bit(idx, ctx->temps_used.l); |
8f17a975 RH |
107 | |
108 | ti = ts->state_ptr; | |
109 | if (ti == NULL) { | |
110 | ti = tcg_malloc(sizeof(TempOptInfo)); | |
6349039d | 111 | ts->state_ptr = ti; |
8f17a975 RH |
112 | } |
113 | ||
114 | ti->next_copy = ts; | |
115 | ti->prev_copy = ts; | |
116 | if (ts->kind == TEMP_CONST) { | |
117 | ti->is_const = true; | |
118 | ti->val = ts->val; | |
b1fde411 | 119 | ti->z_mask = ts->val; |
8f17a975 RH |
120 | if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { |
121 | /* High bits of a 32-bit quantity are garbage. */ | |
b1fde411 | 122 | ti->z_mask |= ~0xffffffffull; |
c0522136 | 123 | } |
8f17a975 RH |
124 | } else { |
125 | ti->is_const = false; | |
b1fde411 | 126 | ti->z_mask = -1; |
1208d7dd AJ |
127 | } |
128 | } | |
129 | ||
3b3f847d | 130 | static void init_arg_info(OptContext *ctx, TCGArg arg) |
6349039d | 131 | { |
3b3f847d | 132 | init_ts_info(ctx, arg_temp(arg)); |
6349039d RH |
133 | } |
134 | ||
6349039d | 135 | static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) |
e590d4e6 | 136 | { |
4c868ce6 | 137 | TCGTemp *i, *g, *l; |
e590d4e6 | 138 | |
4c868ce6 RH |
139 | /* If this is already readonly, we can't do better. */ |
140 | if (temp_readonly(ts)) { | |
6349039d | 141 | return ts; |
e590d4e6 AJ |
142 | } |
143 | ||
4c868ce6 | 144 | g = l = NULL; |
6349039d | 145 | for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { |
4c868ce6 | 146 | if (temp_readonly(i)) { |
e590d4e6 | 147 | return i; |
4c868ce6 RH |
148 | } else if (i->kind > ts->kind) { |
149 | if (i->kind == TEMP_GLOBAL) { | |
150 | g = i; | |
151 | } else if (i->kind == TEMP_LOCAL) { | |
152 | l = i; | |
e590d4e6 AJ |
153 | } |
154 | } | |
155 | } | |
156 | ||
4c868ce6 RH |
157 | /* If we didn't find a better representation, return the same temp. */ |
158 | return g ? g : l ? l : ts; | |
e590d4e6 AJ |
159 | } |
160 | ||
6349039d | 161 | static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) |
e590d4e6 | 162 | { |
6349039d | 163 | TCGTemp *i; |
e590d4e6 | 164 | |
6349039d | 165 | if (ts1 == ts2) { |
e590d4e6 AJ |
166 | return true; |
167 | } | |
168 | ||
6349039d | 169 | if (!ts_is_copy(ts1) || !ts_is_copy(ts2)) { |
e590d4e6 AJ |
170 | return false; |
171 | } | |
172 | ||
6349039d RH |
173 | for (i = ts_info(ts1)->next_copy; i != ts1; i = ts_info(i)->next_copy) { |
174 | if (i == ts2) { | |
e590d4e6 AJ |
175 | return true; |
176 | } | |
177 | } | |
178 | ||
179 | return false; | |
180 | } | |
181 | ||
6349039d RH |
182 | static bool args_are_copies(TCGArg arg1, TCGArg arg2) |
183 | { | |
184 | return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); | |
185 | } | |
186 | ||
dc84988a | 187 | static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) |
22613af4 | 188 | { |
6349039d RH |
189 | TCGTemp *dst_ts = arg_temp(dst); |
190 | TCGTemp *src_ts = arg_temp(src); | |
170ba88f | 191 | const TCGOpDef *def; |
6fcb98ed RH |
192 | TempOptInfo *di; |
193 | TempOptInfo *si; | |
b1fde411 | 194 | uint64_t z_mask; |
6349039d RH |
195 | TCGOpcode new_op; |
196 | ||
197 | if (ts_are_copies(dst_ts, src_ts)) { | |
dc84988a | 198 | tcg_op_remove(ctx->tcg, op); |
5365718a AJ |
199 | return; |
200 | } | |
201 | ||
6349039d RH |
202 | reset_ts(dst_ts); |
203 | di = ts_info(dst_ts); | |
204 | si = ts_info(src_ts); | |
170ba88f RH |
205 | def = &tcg_op_defs[op->opc]; |
206 | if (def->flags & TCG_OPF_VECTOR) { | |
207 | new_op = INDEX_op_mov_vec; | |
208 | } else if (def->flags & TCG_OPF_64BIT) { | |
209 | new_op = INDEX_op_mov_i64; | |
210 | } else { | |
211 | new_op = INDEX_op_mov_i32; | |
212 | } | |
c45cb8bb | 213 | op->opc = new_op; |
170ba88f | 214 | /* TCGOP_VECL and TCGOP_VECE remain unchanged. */ |
6349039d RH |
215 | op->args[0] = dst; |
216 | op->args[1] = src; | |
a62f6f56 | 217 | |
b1fde411 | 218 | z_mask = si->z_mask; |
24666baf RH |
219 | if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) { |
220 | /* High bits of the destination are now garbage. */ | |
b1fde411 | 221 | z_mask |= ~0xffffffffull; |
24666baf | 222 | } |
b1fde411 | 223 | di->z_mask = z_mask; |
e590d4e6 | 224 | |
6349039d | 225 | if (src_ts->type == dst_ts->type) { |
6fcb98ed | 226 | TempOptInfo *ni = ts_info(si->next_copy); |
6349039d RH |
227 | |
228 | di->next_copy = si->next_copy; | |
229 | di->prev_copy = src_ts; | |
230 | ni->prev_copy = dst_ts; | |
231 | si->next_copy = dst_ts; | |
232 | di->is_const = si->is_const; | |
233 | di->val = si->val; | |
234 | } | |
22613af4 KB |
235 | } |
236 | ||
dc84988a RH |
237 | static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op, |
238 | TCGArg dst, uint64_t val) | |
8fe35e04 RH |
239 | { |
240 | const TCGOpDef *def = &tcg_op_defs[op->opc]; | |
241 | TCGType type; | |
242 | TCGTemp *tv; | |
243 | ||
244 | if (def->flags & TCG_OPF_VECTOR) { | |
245 | type = TCGOP_VECL(op) + TCG_TYPE_V64; | |
246 | } else if (def->flags & TCG_OPF_64BIT) { | |
247 | type = TCG_TYPE_I64; | |
248 | } else { | |
249 | type = TCG_TYPE_I32; | |
250 | } | |
251 | ||
252 | /* Convert movi to mov with constant temp. */ | |
253 | tv = tcg_constant_internal(type, val); | |
3b3f847d | 254 | init_ts_info(ctx, tv); |
dc84988a | 255 | tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv)); |
8fe35e04 RH |
256 | } |
257 | ||
54795544 | 258 | static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) |
53108fb5 | 259 | { |
03271524 RH |
260 | uint64_t l64, h64; |
261 | ||
53108fb5 KB |
262 | switch (op) { |
263 | CASE_OP_32_64(add): | |
264 | return x + y; | |
265 | ||
266 | CASE_OP_32_64(sub): | |
267 | return x - y; | |
268 | ||
269 | CASE_OP_32_64(mul): | |
270 | return x * y; | |
271 | ||
9a81090b KB |
272 | CASE_OP_32_64(and): |
273 | return x & y; | |
274 | ||
275 | CASE_OP_32_64(or): | |
276 | return x | y; | |
277 | ||
278 | CASE_OP_32_64(xor): | |
279 | return x ^ y; | |
280 | ||
55c0975c | 281 | case INDEX_op_shl_i32: |
50c5c4d1 | 282 | return (uint32_t)x << (y & 31); |
55c0975c | 283 | |
55c0975c | 284 | case INDEX_op_shl_i64: |
50c5c4d1 | 285 | return (uint64_t)x << (y & 63); |
55c0975c KB |
286 | |
287 | case INDEX_op_shr_i32: | |
50c5c4d1 | 288 | return (uint32_t)x >> (y & 31); |
55c0975c | 289 | |
55c0975c | 290 | case INDEX_op_shr_i64: |
50c5c4d1 | 291 | return (uint64_t)x >> (y & 63); |
55c0975c KB |
292 | |
293 | case INDEX_op_sar_i32: | |
50c5c4d1 | 294 | return (int32_t)x >> (y & 31); |
55c0975c | 295 | |
55c0975c | 296 | case INDEX_op_sar_i64: |
50c5c4d1 | 297 | return (int64_t)x >> (y & 63); |
55c0975c KB |
298 | |
299 | case INDEX_op_rotr_i32: | |
50c5c4d1 | 300 | return ror32(x, y & 31); |
55c0975c | 301 | |
55c0975c | 302 | case INDEX_op_rotr_i64: |
50c5c4d1 | 303 | return ror64(x, y & 63); |
55c0975c KB |
304 | |
305 | case INDEX_op_rotl_i32: | |
50c5c4d1 | 306 | return rol32(x, y & 31); |
55c0975c | 307 | |
55c0975c | 308 | case INDEX_op_rotl_i64: |
50c5c4d1 | 309 | return rol64(x, y & 63); |
25c4d9cc RH |
310 | |
311 | CASE_OP_32_64(not): | |
a640f031 | 312 | return ~x; |
25c4d9cc | 313 | |
cb25c80a RH |
314 | CASE_OP_32_64(neg): |
315 | return -x; | |
316 | ||
317 | CASE_OP_32_64(andc): | |
318 | return x & ~y; | |
319 | ||
320 | CASE_OP_32_64(orc): | |
321 | return x | ~y; | |
322 | ||
323 | CASE_OP_32_64(eqv): | |
324 | return ~(x ^ y); | |
325 | ||
326 | CASE_OP_32_64(nand): | |
327 | return ~(x & y); | |
328 | ||
329 | CASE_OP_32_64(nor): | |
330 | return ~(x | y); | |
331 | ||
0e28d006 RH |
332 | case INDEX_op_clz_i32: |
333 | return (uint32_t)x ? clz32(x) : y; | |
334 | ||
335 | case INDEX_op_clz_i64: | |
336 | return x ? clz64(x) : y; | |
337 | ||
338 | case INDEX_op_ctz_i32: | |
339 | return (uint32_t)x ? ctz32(x) : y; | |
340 | ||
341 | case INDEX_op_ctz_i64: | |
342 | return x ? ctz64(x) : y; | |
343 | ||
a768e4e9 RH |
344 | case INDEX_op_ctpop_i32: |
345 | return ctpop32(x); | |
346 | ||
347 | case INDEX_op_ctpop_i64: | |
348 | return ctpop64(x); | |
349 | ||
25c4d9cc | 350 | CASE_OP_32_64(ext8s): |
a640f031 | 351 | return (int8_t)x; |
25c4d9cc RH |
352 | |
353 | CASE_OP_32_64(ext16s): | |
a640f031 | 354 | return (int16_t)x; |
25c4d9cc RH |
355 | |
356 | CASE_OP_32_64(ext8u): | |
a640f031 | 357 | return (uint8_t)x; |
25c4d9cc RH |
358 | |
359 | CASE_OP_32_64(ext16u): | |
a640f031 KB |
360 | return (uint16_t)x; |
361 | ||
6498594c | 362 | CASE_OP_32_64(bswap16): |
0b76ff8f RH |
363 | x = bswap16(x); |
364 | return y & TCG_BSWAP_OS ? (int16_t)x : x; | |
6498594c RH |
365 | |
366 | CASE_OP_32_64(bswap32): | |
0b76ff8f RH |
367 | x = bswap32(x); |
368 | return y & TCG_BSWAP_OS ? (int32_t)x : x; | |
6498594c RH |
369 | |
370 | case INDEX_op_bswap64_i64: | |
371 | return bswap64(x); | |
372 | ||
8bcb5c8f | 373 | case INDEX_op_ext_i32_i64: |
a640f031 KB |
374 | case INDEX_op_ext32s_i64: |
375 | return (int32_t)x; | |
376 | ||
8bcb5c8f | 377 | case INDEX_op_extu_i32_i64: |
609ad705 | 378 | case INDEX_op_extrl_i64_i32: |
a640f031 KB |
379 | case INDEX_op_ext32u_i64: |
380 | return (uint32_t)x; | |
a640f031 | 381 | |
609ad705 RH |
382 | case INDEX_op_extrh_i64_i32: |
383 | return (uint64_t)x >> 32; | |
384 | ||
03271524 RH |
385 | case INDEX_op_muluh_i32: |
386 | return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32; | |
387 | case INDEX_op_mulsh_i32: | |
388 | return ((int64_t)(int32_t)x * (int32_t)y) >> 32; | |
389 | ||
390 | case INDEX_op_muluh_i64: | |
391 | mulu64(&l64, &h64, x, y); | |
392 | return h64; | |
393 | case INDEX_op_mulsh_i64: | |
394 | muls64(&l64, &h64, x, y); | |
395 | return h64; | |
396 | ||
01547f7f RH |
397 | case INDEX_op_div_i32: |
398 | /* Avoid crashing on divide by zero, otherwise undefined. */ | |
399 | return (int32_t)x / ((int32_t)y ? : 1); | |
400 | case INDEX_op_divu_i32: | |
401 | return (uint32_t)x / ((uint32_t)y ? : 1); | |
402 | case INDEX_op_div_i64: | |
403 | return (int64_t)x / ((int64_t)y ? : 1); | |
404 | case INDEX_op_divu_i64: | |
405 | return (uint64_t)x / ((uint64_t)y ? : 1); | |
406 | ||
407 | case INDEX_op_rem_i32: | |
408 | return (int32_t)x % ((int32_t)y ? : 1); | |
409 | case INDEX_op_remu_i32: | |
410 | return (uint32_t)x % ((uint32_t)y ? : 1); | |
411 | case INDEX_op_rem_i64: | |
412 | return (int64_t)x % ((int64_t)y ? : 1); | |
413 | case INDEX_op_remu_i64: | |
414 | return (uint64_t)x % ((uint64_t)y ? : 1); | |
415 | ||
53108fb5 KB |
416 | default: |
417 | fprintf(stderr, | |
418 | "Unrecognized operation %d in do_constant_folding.\n", op); | |
419 | tcg_abort(); | |
420 | } | |
421 | } | |
422 | ||
54795544 | 423 | static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y) |
53108fb5 | 424 | { |
170ba88f | 425 | const TCGOpDef *def = &tcg_op_defs[op]; |
54795544 | 426 | uint64_t res = do_constant_folding_2(op, x, y); |
170ba88f | 427 | if (!(def->flags & TCG_OPF_64BIT)) { |
29f3ff8d | 428 | res = (int32_t)res; |
53108fb5 | 429 | } |
53108fb5 KB |
430 | return res; |
431 | } | |
432 | ||
9519da7e RH |
433 | static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c) |
434 | { | |
435 | switch (c) { | |
436 | case TCG_COND_EQ: | |
437 | return x == y; | |
438 | case TCG_COND_NE: | |
439 | return x != y; | |
440 | case TCG_COND_LT: | |
441 | return (int32_t)x < (int32_t)y; | |
442 | case TCG_COND_GE: | |
443 | return (int32_t)x >= (int32_t)y; | |
444 | case TCG_COND_LE: | |
445 | return (int32_t)x <= (int32_t)y; | |
446 | case TCG_COND_GT: | |
447 | return (int32_t)x > (int32_t)y; | |
448 | case TCG_COND_LTU: | |
449 | return x < y; | |
450 | case TCG_COND_GEU: | |
451 | return x >= y; | |
452 | case TCG_COND_LEU: | |
453 | return x <= y; | |
454 | case TCG_COND_GTU: | |
455 | return x > y; | |
456 | default: | |
457 | tcg_abort(); | |
458 | } | |
459 | } | |
460 | ||
461 | static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c) | |
462 | { | |
463 | switch (c) { | |
464 | case TCG_COND_EQ: | |
465 | return x == y; | |
466 | case TCG_COND_NE: | |
467 | return x != y; | |
468 | case TCG_COND_LT: | |
469 | return (int64_t)x < (int64_t)y; | |
470 | case TCG_COND_GE: | |
471 | return (int64_t)x >= (int64_t)y; | |
472 | case TCG_COND_LE: | |
473 | return (int64_t)x <= (int64_t)y; | |
474 | case TCG_COND_GT: | |
475 | return (int64_t)x > (int64_t)y; | |
476 | case TCG_COND_LTU: | |
477 | return x < y; | |
478 | case TCG_COND_GEU: | |
479 | return x >= y; | |
480 | case TCG_COND_LEU: | |
481 | return x <= y; | |
482 | case TCG_COND_GTU: | |
483 | return x > y; | |
484 | default: | |
485 | tcg_abort(); | |
486 | } | |
487 | } | |
488 | ||
489 | static bool do_constant_folding_cond_eq(TCGCond c) | |
490 | { | |
491 | switch (c) { | |
492 | case TCG_COND_GT: | |
493 | case TCG_COND_LTU: | |
494 | case TCG_COND_LT: | |
495 | case TCG_COND_GTU: | |
496 | case TCG_COND_NE: | |
497 | return 0; | |
498 | case TCG_COND_GE: | |
499 | case TCG_COND_GEU: | |
500 | case TCG_COND_LE: | |
501 | case TCG_COND_LEU: | |
502 | case TCG_COND_EQ: | |
503 | return 1; | |
504 | default: | |
505 | tcg_abort(); | |
506 | } | |
507 | } | |
508 | ||
b336ceb6 AJ |
509 | /* Return 2 if the condition can't be simplified, and the result |
510 | of the condition (0 or 1) if it can */ | |
f8dd19e5 AJ |
511 | static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, |
512 | TCGArg y, TCGCond c) | |
513 | { | |
54795544 RH |
514 | uint64_t xv = arg_info(x)->val; |
515 | uint64_t yv = arg_info(y)->val; | |
516 | ||
6349039d | 517 | if (arg_is_const(x) && arg_is_const(y)) { |
170ba88f RH |
518 | const TCGOpDef *def = &tcg_op_defs[op]; |
519 | tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR)); | |
520 | if (def->flags & TCG_OPF_64BIT) { | |
6349039d | 521 | return do_constant_folding_cond_64(xv, yv, c); |
170ba88f RH |
522 | } else { |
523 | return do_constant_folding_cond_32(xv, yv, c); | |
b336ceb6 | 524 | } |
6349039d | 525 | } else if (args_are_copies(x, y)) { |
9519da7e | 526 | return do_constant_folding_cond_eq(c); |
6349039d | 527 | } else if (arg_is_const(y) && yv == 0) { |
b336ceb6 | 528 | switch (c) { |
f8dd19e5 | 529 | case TCG_COND_LTU: |
b336ceb6 | 530 | return 0; |
f8dd19e5 | 531 | case TCG_COND_GEU: |
b336ceb6 AJ |
532 | return 1; |
533 | default: | |
534 | return 2; | |
f8dd19e5 | 535 | } |
f8dd19e5 | 536 | } |
550276ae | 537 | return 2; |
f8dd19e5 AJ |
538 | } |
539 | ||
6c4382f8 RH |
540 | /* Return 2 if the condition can't be simplified, and the result |
541 | of the condition (0 or 1) if it can */ | |
542 | static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) | |
543 | { | |
544 | TCGArg al = p1[0], ah = p1[1]; | |
545 | TCGArg bl = p2[0], bh = p2[1]; | |
546 | ||
6349039d RH |
547 | if (arg_is_const(bl) && arg_is_const(bh)) { |
548 | tcg_target_ulong blv = arg_info(bl)->val; | |
549 | tcg_target_ulong bhv = arg_info(bh)->val; | |
550 | uint64_t b = deposit64(blv, 32, 32, bhv); | |
6c4382f8 | 551 | |
6349039d RH |
552 | if (arg_is_const(al) && arg_is_const(ah)) { |
553 | tcg_target_ulong alv = arg_info(al)->val; | |
554 | tcg_target_ulong ahv = arg_info(ah)->val; | |
555 | uint64_t a = deposit64(alv, 32, 32, ahv); | |
6c4382f8 RH |
556 | return do_constant_folding_cond_64(a, b, c); |
557 | } | |
558 | if (b == 0) { | |
559 | switch (c) { | |
560 | case TCG_COND_LTU: | |
561 | return 0; | |
562 | case TCG_COND_GEU: | |
563 | return 1; | |
564 | default: | |
565 | break; | |
566 | } | |
567 | } | |
568 | } | |
6349039d | 569 | if (args_are_copies(al, bl) && args_are_copies(ah, bh)) { |
6c4382f8 RH |
570 | return do_constant_folding_cond_eq(c); |
571 | } | |
572 | return 2; | |
573 | } | |
574 | ||
24c9ae4e RH |
575 | static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) |
576 | { | |
577 | TCGArg a1 = *p1, a2 = *p2; | |
578 | int sum = 0; | |
6349039d RH |
579 | sum += arg_is_const(a1); |
580 | sum -= arg_is_const(a2); | |
24c9ae4e RH |
581 | |
582 | /* Prefer the constant in second argument, and then the form | |
583 | op a, a, b, which is better handled on non-RISC hosts. */ | |
584 | if (sum > 0 || (sum == 0 && dest == a2)) { | |
585 | *p1 = a2; | |
586 | *p2 = a1; | |
587 | return true; | |
588 | } | |
589 | return false; | |
590 | } | |
591 | ||
0bfcb865 RH |
592 | static bool swap_commutative2(TCGArg *p1, TCGArg *p2) |
593 | { | |
594 | int sum = 0; | |
6349039d RH |
595 | sum += arg_is_const(p1[0]); |
596 | sum += arg_is_const(p1[1]); | |
597 | sum -= arg_is_const(p2[0]); | |
598 | sum -= arg_is_const(p2[1]); | |
0bfcb865 RH |
599 | if (sum > 0) { |
600 | TCGArg t; | |
601 | t = p1[0], p1[0] = p2[0], p2[0] = t; | |
602 | t = p1[1], p1[1] = p2[1], p2[1] = t; | |
603 | return true; | |
604 | } | |
605 | return false; | |
606 | } | |
607 | ||
22613af4 | 608 | /* Propagate constants and copies, fold constant expressions. */ |
36e60ef6 | 609 | void tcg_optimize(TCGContext *s) |
8f2e8c07 | 610 | { |
8f17a975 | 611 | int nb_temps, nb_globals, i; |
15fa08f8 | 612 | TCGOp *op, *op_next, *prev_mb = NULL; |
dc84988a | 613 | OptContext ctx = { .tcg = s }; |
5d8f5363 | 614 | |
22613af4 KB |
615 | /* Array VALS has an element for each temp. |
616 | If this temp holds a constant then its value is kept in VALS' element. | |
e590d4e6 AJ |
617 | If this temp is a copy of other ones then the other copies are |
618 | available through the doubly linked circular list. */ | |
8f2e8c07 KB |
619 | |
620 | nb_temps = s->nb_temps; | |
621 | nb_globals = s->nb_globals; | |
8f17a975 | 622 | |
8f17a975 RH |
623 | for (i = 0; i < nb_temps; ++i) { |
624 | s->temps[i].state_ptr = NULL; | |
625 | } | |
8f2e8c07 | 626 | |
15fa08f8 | 627 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { |
b1fde411 | 628 | uint64_t z_mask, partmask, affected, tmp; |
8f17a975 | 629 | int nb_oargs, nb_iargs; |
c45cb8bb RH |
630 | TCGOpcode opc = op->opc; |
631 | const TCGOpDef *def = &tcg_op_defs[opc]; | |
632 | ||
1208d7dd AJ |
633 | /* Count the arguments, and initialize the temps that are |
634 | going to be used */ | |
c45cb8bb | 635 | if (opc == INDEX_op_call) { |
cd9090aa RH |
636 | nb_oargs = TCGOP_CALLO(op); |
637 | nb_iargs = TCGOP_CALLI(op); | |
1208d7dd | 638 | for (i = 0; i < nb_oargs + nb_iargs; i++) { |
6349039d RH |
639 | TCGTemp *ts = arg_temp(op->args[i]); |
640 | if (ts) { | |
3b3f847d | 641 | init_ts_info(&ctx, ts); |
1208d7dd AJ |
642 | } |
643 | } | |
1ff8c541 | 644 | } else { |
cf066674 RH |
645 | nb_oargs = def->nb_oargs; |
646 | nb_iargs = def->nb_iargs; | |
1208d7dd | 647 | for (i = 0; i < nb_oargs + nb_iargs; i++) { |
3b3f847d | 648 | init_arg_info(&ctx, op->args[i]); |
1208d7dd | 649 | } |
cf066674 RH |
650 | } |
651 | ||
652 | /* Do copy propagation */ | |
653 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { | |
6349039d RH |
654 | TCGTemp *ts = arg_temp(op->args[i]); |
655 | if (ts && ts_is_copy(ts)) { | |
656 | op->args[i] = temp_arg(find_better_copy(s, ts)); | |
22613af4 KB |
657 | } |
658 | } | |
659 | ||
53108fb5 | 660 | /* For commutative operations make constant second argument */ |
c45cb8bb | 661 | switch (opc) { |
170ba88f RH |
662 | CASE_OP_32_64_VEC(add): |
663 | CASE_OP_32_64_VEC(mul): | |
664 | CASE_OP_32_64_VEC(and): | |
665 | CASE_OP_32_64_VEC(or): | |
666 | CASE_OP_32_64_VEC(xor): | |
cb25c80a RH |
667 | CASE_OP_32_64(eqv): |
668 | CASE_OP_32_64(nand): | |
669 | CASE_OP_32_64(nor): | |
03271524 RH |
670 | CASE_OP_32_64(muluh): |
671 | CASE_OP_32_64(mulsh): | |
acd93701 | 672 | swap_commutative(op->args[0], &op->args[1], &op->args[2]); |
53108fb5 | 673 | break; |
65a7cce1 | 674 | CASE_OP_32_64(brcond): |
acd93701 RH |
675 | if (swap_commutative(-1, &op->args[0], &op->args[1])) { |
676 | op->args[2] = tcg_swap_cond(op->args[2]); | |
65a7cce1 AJ |
677 | } |
678 | break; | |
679 | CASE_OP_32_64(setcond): | |
acd93701 RH |
680 | if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { |
681 | op->args[3] = tcg_swap_cond(op->args[3]); | |
65a7cce1 AJ |
682 | } |
683 | break; | |
fa01a208 | 684 | CASE_OP_32_64(movcond): |
acd93701 RH |
685 | if (swap_commutative(-1, &op->args[1], &op->args[2])) { |
686 | op->args[5] = tcg_swap_cond(op->args[5]); | |
5d8f5363 RH |
687 | } |
688 | /* For movcond, we canonicalize the "false" input reg to match | |
689 | the destination reg so that the tcg backend can implement | |
690 | a "move if true" operation. */ | |
acd93701 RH |
691 | if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) { |
692 | op->args[5] = tcg_invert_cond(op->args[5]); | |
fa01a208 | 693 | } |
1e484e61 | 694 | break; |
d7156f7c | 695 | CASE_OP_32_64(add2): |
acd93701 RH |
696 | swap_commutative(op->args[0], &op->args[2], &op->args[4]); |
697 | swap_commutative(op->args[1], &op->args[3], &op->args[5]); | |
1e484e61 | 698 | break; |
d7156f7c | 699 | CASE_OP_32_64(mulu2): |
4d3203fd | 700 | CASE_OP_32_64(muls2): |
acd93701 | 701 | swap_commutative(op->args[0], &op->args[2], &op->args[3]); |
1414968a | 702 | break; |
0bfcb865 | 703 | case INDEX_op_brcond2_i32: |
acd93701 RH |
704 | if (swap_commutative2(&op->args[0], &op->args[2])) { |
705 | op->args[4] = tcg_swap_cond(op->args[4]); | |
0bfcb865 RH |
706 | } |
707 | break; | |
708 | case INDEX_op_setcond2_i32: | |
acd93701 RH |
709 | if (swap_commutative2(&op->args[1], &op->args[3])) { |
710 | op->args[5] = tcg_swap_cond(op->args[5]); | |
0bfcb865 RH |
711 | } |
712 | break; | |
53108fb5 KB |
713 | default: |
714 | break; | |
715 | } | |
716 | ||
2d497542 RH |
717 | /* Simplify expressions for "shift/rot r, 0, a => movi r, 0", |
718 | and "sub r, 0, a => neg r, a" case. */ | |
c45cb8bb | 719 | switch (opc) { |
01ee5282 AJ |
720 | CASE_OP_32_64(shl): |
721 | CASE_OP_32_64(shr): | |
722 | CASE_OP_32_64(sar): | |
723 | CASE_OP_32_64(rotl): | |
724 | CASE_OP_32_64(rotr): | |
6349039d RH |
725 | if (arg_is_const(op->args[1]) |
726 | && arg_info(op->args[1])->val == 0) { | |
dc84988a | 727 | tcg_opt_gen_movi(&ctx, op, op->args[0], 0); |
01ee5282 AJ |
728 | continue; |
729 | } | |
730 | break; | |
170ba88f | 731 | CASE_OP_32_64_VEC(sub): |
2d497542 RH |
732 | { |
733 | TCGOpcode neg_op; | |
734 | bool have_neg; | |
735 | ||
6349039d | 736 | if (arg_is_const(op->args[2])) { |
2d497542 RH |
737 | /* Proceed with possible constant folding. */ |
738 | break; | |
739 | } | |
c45cb8bb | 740 | if (opc == INDEX_op_sub_i32) { |
2d497542 RH |
741 | neg_op = INDEX_op_neg_i32; |
742 | have_neg = TCG_TARGET_HAS_neg_i32; | |
170ba88f | 743 | } else if (opc == INDEX_op_sub_i64) { |
2d497542 RH |
744 | neg_op = INDEX_op_neg_i64; |
745 | have_neg = TCG_TARGET_HAS_neg_i64; | |
ac383dde RH |
746 | } else if (TCG_TARGET_HAS_neg_vec) { |
747 | TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64; | |
748 | unsigned vece = TCGOP_VECE(op); | |
170ba88f | 749 | neg_op = INDEX_op_neg_vec; |
ac383dde RH |
750 | have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0; |
751 | } else { | |
752 | break; | |
2d497542 RH |
753 | } |
754 | if (!have_neg) { | |
755 | break; | |
756 | } | |
6349039d RH |
757 | if (arg_is_const(op->args[1]) |
758 | && arg_info(op->args[1])->val == 0) { | |
c45cb8bb | 759 | op->opc = neg_op; |
acd93701 RH |
760 | reset_temp(op->args[0]); |
761 | op->args[1] = op->args[2]; | |
2d497542 RH |
762 | continue; |
763 | } | |
764 | } | |
765 | break; | |
170ba88f | 766 | CASE_OP_32_64_VEC(xor): |
e201b564 | 767 | CASE_OP_32_64(nand): |
6349039d RH |
768 | if (!arg_is_const(op->args[1]) |
769 | && arg_is_const(op->args[2]) | |
770 | && arg_info(op->args[2])->val == -1) { | |
e201b564 RH |
771 | i = 1; |
772 | goto try_not; | |
773 | } | |
774 | break; | |
775 | CASE_OP_32_64(nor): | |
6349039d RH |
776 | if (!arg_is_const(op->args[1]) |
777 | && arg_is_const(op->args[2]) | |
778 | && arg_info(op->args[2])->val == 0) { | |
e201b564 RH |
779 | i = 1; |
780 | goto try_not; | |
781 | } | |
782 | break; | |
170ba88f | 783 | CASE_OP_32_64_VEC(andc): |
6349039d RH |
784 | if (!arg_is_const(op->args[2]) |
785 | && arg_is_const(op->args[1]) | |
786 | && arg_info(op->args[1])->val == -1) { | |
e201b564 RH |
787 | i = 2; |
788 | goto try_not; | |
789 | } | |
790 | break; | |
170ba88f | 791 | CASE_OP_32_64_VEC(orc): |
e201b564 | 792 | CASE_OP_32_64(eqv): |
6349039d RH |
793 | if (!arg_is_const(op->args[2]) |
794 | && arg_is_const(op->args[1]) | |
795 | && arg_info(op->args[1])->val == 0) { | |
e201b564 RH |
796 | i = 2; |
797 | goto try_not; | |
798 | } | |
799 | break; | |
800 | try_not: | |
801 | { | |
802 | TCGOpcode not_op; | |
803 | bool have_not; | |
804 | ||
170ba88f RH |
805 | if (def->flags & TCG_OPF_VECTOR) { |
806 | not_op = INDEX_op_not_vec; | |
807 | have_not = TCG_TARGET_HAS_not_vec; | |
808 | } else if (def->flags & TCG_OPF_64BIT) { | |
e201b564 RH |
809 | not_op = INDEX_op_not_i64; |
810 | have_not = TCG_TARGET_HAS_not_i64; | |
811 | } else { | |
812 | not_op = INDEX_op_not_i32; | |
813 | have_not = TCG_TARGET_HAS_not_i32; | |
814 | } | |
815 | if (!have_not) { | |
816 | break; | |
817 | } | |
c45cb8bb | 818 | op->opc = not_op; |
acd93701 RH |
819 | reset_temp(op->args[0]); |
820 | op->args[1] = op->args[i]; | |
e201b564 RH |
821 | continue; |
822 | } | |
01ee5282 AJ |
823 | default: |
824 | break; | |
825 | } | |
826 | ||
464a1441 | 827 | /* Simplify expression for "op r, a, const => mov r, a" cases */ |
c45cb8bb | 828 | switch (opc) { |
170ba88f RH |
829 | CASE_OP_32_64_VEC(add): |
830 | CASE_OP_32_64_VEC(sub): | |
831 | CASE_OP_32_64_VEC(or): | |
832 | CASE_OP_32_64_VEC(xor): | |
833 | CASE_OP_32_64_VEC(andc): | |
55c0975c KB |
834 | CASE_OP_32_64(shl): |
835 | CASE_OP_32_64(shr): | |
836 | CASE_OP_32_64(sar): | |
25c4d9cc RH |
837 | CASE_OP_32_64(rotl): |
838 | CASE_OP_32_64(rotr): | |
6349039d RH |
839 | if (!arg_is_const(op->args[1]) |
840 | && arg_is_const(op->args[2]) | |
841 | && arg_info(op->args[2])->val == 0) { | |
dc84988a | 842 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
97a79eb7 | 843 | continue; |
53108fb5 KB |
844 | } |
845 | break; | |
170ba88f RH |
846 | CASE_OP_32_64_VEC(and): |
847 | CASE_OP_32_64_VEC(orc): | |
464a1441 | 848 | CASE_OP_32_64(eqv): |
6349039d RH |
849 | if (!arg_is_const(op->args[1]) |
850 | && arg_is_const(op->args[2]) | |
851 | && arg_info(op->args[2])->val == -1) { | |
dc84988a | 852 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
97a79eb7 | 853 | continue; |
464a1441 RH |
854 | } |
855 | break; | |
56e49438 AJ |
856 | default: |
857 | break; | |
858 | } | |
859 | ||
3031244b AJ |
860 | /* Simplify using known-zero bits. Currently only ops with a single |
861 | output argument is supported. */ | |
b1fde411 | 862 | z_mask = -1; |
633f6502 | 863 | affected = -1; |
c45cb8bb | 864 | switch (opc) { |
3a9d8b17 | 865 | CASE_OP_32_64(ext8s): |
b1fde411 | 866 | if ((arg_info(op->args[1])->z_mask & 0x80) != 0) { |
3a9d8b17 PB |
867 | break; |
868 | } | |
d84568b7 | 869 | QEMU_FALLTHROUGH; |
3a9d8b17 | 870 | CASE_OP_32_64(ext8u): |
b1fde411 | 871 | z_mask = 0xff; |
3a9d8b17 PB |
872 | goto and_const; |
873 | CASE_OP_32_64(ext16s): | |
b1fde411 | 874 | if ((arg_info(op->args[1])->z_mask & 0x8000) != 0) { |
3a9d8b17 PB |
875 | break; |
876 | } | |
d84568b7 | 877 | QEMU_FALLTHROUGH; |
3a9d8b17 | 878 | CASE_OP_32_64(ext16u): |
b1fde411 | 879 | z_mask = 0xffff; |
3a9d8b17 PB |
880 | goto and_const; |
881 | case INDEX_op_ext32s_i64: | |
b1fde411 | 882 | if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) { |
3a9d8b17 PB |
883 | break; |
884 | } | |
d84568b7 | 885 | QEMU_FALLTHROUGH; |
3a9d8b17 | 886 | case INDEX_op_ext32u_i64: |
b1fde411 | 887 | z_mask = 0xffffffffU; |
3a9d8b17 PB |
888 | goto and_const; |
889 | ||
890 | CASE_OP_32_64(and): | |
b1fde411 | 891 | z_mask = arg_info(op->args[2])->z_mask; |
6349039d | 892 | if (arg_is_const(op->args[2])) { |
3a9d8b17 | 893 | and_const: |
b1fde411 | 894 | affected = arg_info(op->args[1])->z_mask & ~z_mask; |
3a9d8b17 | 895 | } |
b1fde411 | 896 | z_mask = arg_info(op->args[1])->z_mask & z_mask; |
3a9d8b17 PB |
897 | break; |
898 | ||
8bcb5c8f | 899 | case INDEX_op_ext_i32_i64: |
b1fde411 | 900 | if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) { |
8bcb5c8f AJ |
901 | break; |
902 | } | |
d84568b7 | 903 | QEMU_FALLTHROUGH; |
8bcb5c8f AJ |
904 | case INDEX_op_extu_i32_i64: |
905 | /* We do not compute affected as it is a size changing op. */ | |
b1fde411 | 906 | z_mask = (uint32_t)arg_info(op->args[1])->z_mask; |
8bcb5c8f AJ |
907 | break; |
908 | ||
23ec69ed RH |
909 | CASE_OP_32_64(andc): |
910 | /* Known-zeros does not imply known-ones. Therefore unless | |
acd93701 | 911 | op->args[2] is constant, we can't infer anything from it. */ |
6349039d | 912 | if (arg_is_const(op->args[2])) { |
b1fde411 | 913 | z_mask = ~arg_info(op->args[2])->z_mask; |
23ec69ed RH |
914 | goto and_const; |
915 | } | |
6349039d | 916 | /* But we certainly know nothing outside args[1] may be set. */ |
b1fde411 | 917 | z_mask = arg_info(op->args[1])->z_mask; |
23ec69ed RH |
918 | break; |
919 | ||
e46b225a | 920 | case INDEX_op_sar_i32: |
6349039d RH |
921 | if (arg_is_const(op->args[2])) { |
922 | tmp = arg_info(op->args[2])->val & 31; | |
b1fde411 | 923 | z_mask = (int32_t)arg_info(op->args[1])->z_mask >> tmp; |
e46b225a AJ |
924 | } |
925 | break; | |
926 | case INDEX_op_sar_i64: | |
6349039d RH |
927 | if (arg_is_const(op->args[2])) { |
928 | tmp = arg_info(op->args[2])->val & 63; | |
b1fde411 | 929 | z_mask = (int64_t)arg_info(op->args[1])->z_mask >> tmp; |
3a9d8b17 PB |
930 | } |
931 | break; | |
932 | ||
e46b225a | 933 | case INDEX_op_shr_i32: |
6349039d RH |
934 | if (arg_is_const(op->args[2])) { |
935 | tmp = arg_info(op->args[2])->val & 31; | |
b1fde411 | 936 | z_mask = (uint32_t)arg_info(op->args[1])->z_mask >> tmp; |
e46b225a AJ |
937 | } |
938 | break; | |
939 | case INDEX_op_shr_i64: | |
6349039d RH |
940 | if (arg_is_const(op->args[2])) { |
941 | tmp = arg_info(op->args[2])->val & 63; | |
b1fde411 | 942 | z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> tmp; |
3a9d8b17 PB |
943 | } |
944 | break; | |
945 | ||
609ad705 | 946 | case INDEX_op_extrl_i64_i32: |
b1fde411 | 947 | z_mask = (uint32_t)arg_info(op->args[1])->z_mask; |
609ad705 RH |
948 | break; |
949 | case INDEX_op_extrh_i64_i32: | |
b1fde411 | 950 | z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> 32; |
4bb7a41e RH |
951 | break; |
952 | ||
3a9d8b17 | 953 | CASE_OP_32_64(shl): |
6349039d RH |
954 | if (arg_is_const(op->args[2])) { |
955 | tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1); | |
b1fde411 | 956 | z_mask = arg_info(op->args[1])->z_mask << tmp; |
3a9d8b17 PB |
957 | } |
958 | break; | |
959 | ||
960 | CASE_OP_32_64(neg): | |
961 | /* Set to 1 all bits to the left of the rightmost. */ | |
b1fde411 RH |
962 | z_mask = -(arg_info(op->args[1])->z_mask |
963 | & -arg_info(op->args[1])->z_mask); | |
3a9d8b17 PB |
964 | break; |
965 | ||
966 | CASE_OP_32_64(deposit): | |
b1fde411 RH |
967 | z_mask = deposit64(arg_info(op->args[1])->z_mask, |
968 | op->args[3], op->args[4], | |
969 | arg_info(op->args[2])->z_mask); | |
3a9d8b17 PB |
970 | break; |
971 | ||
7ec8bab3 | 972 | CASE_OP_32_64(extract): |
b1fde411 RH |
973 | z_mask = extract64(arg_info(op->args[1])->z_mask, |
974 | op->args[2], op->args[3]); | |
acd93701 | 975 | if (op->args[2] == 0) { |
b1fde411 | 976 | affected = arg_info(op->args[1])->z_mask & ~z_mask; |
7ec8bab3 RH |
977 | } |
978 | break; | |
979 | CASE_OP_32_64(sextract): | |
b1fde411 RH |
980 | z_mask = sextract64(arg_info(op->args[1])->z_mask, |
981 | op->args[2], op->args[3]); | |
982 | if (op->args[2] == 0 && (tcg_target_long)z_mask >= 0) { | |
983 | affected = arg_info(op->args[1])->z_mask & ~z_mask; | |
7ec8bab3 RH |
984 | } |
985 | break; | |
986 | ||
3a9d8b17 PB |
987 | CASE_OP_32_64(or): |
988 | CASE_OP_32_64(xor): | |
b1fde411 RH |
989 | z_mask = arg_info(op->args[1])->z_mask |
990 | | arg_info(op->args[2])->z_mask; | |
3a9d8b17 PB |
991 | break; |
992 | ||
0e28d006 RH |
993 | case INDEX_op_clz_i32: |
994 | case INDEX_op_ctz_i32: | |
b1fde411 | 995 | z_mask = arg_info(op->args[2])->z_mask | 31; |
0e28d006 RH |
996 | break; |
997 | ||
998 | case INDEX_op_clz_i64: | |
999 | case INDEX_op_ctz_i64: | |
b1fde411 | 1000 | z_mask = arg_info(op->args[2])->z_mask | 63; |
0e28d006 RH |
1001 | break; |
1002 | ||
a768e4e9 | 1003 | case INDEX_op_ctpop_i32: |
b1fde411 | 1004 | z_mask = 32 | 31; |
a768e4e9 RH |
1005 | break; |
1006 | case INDEX_op_ctpop_i64: | |
b1fde411 | 1007 | z_mask = 64 | 63; |
a768e4e9 RH |
1008 | break; |
1009 | ||
3a9d8b17 | 1010 | CASE_OP_32_64(setcond): |
a763551a | 1011 | case INDEX_op_setcond2_i32: |
b1fde411 | 1012 | z_mask = 1; |
3a9d8b17 PB |
1013 | break; |
1014 | ||
1015 | CASE_OP_32_64(movcond): | |
b1fde411 RH |
1016 | z_mask = arg_info(op->args[3])->z_mask |
1017 | | arg_info(op->args[4])->z_mask; | |
3a9d8b17 PB |
1018 | break; |
1019 | ||
c8d70272 | 1020 | CASE_OP_32_64(ld8u): |
b1fde411 | 1021 | z_mask = 0xff; |
c8d70272 AJ |
1022 | break; |
1023 | CASE_OP_32_64(ld16u): | |
b1fde411 | 1024 | z_mask = 0xffff; |
c8d70272 AJ |
1025 | break; |
1026 | case INDEX_op_ld32u_i64: | |
b1fde411 | 1027 | z_mask = 0xffffffffu; |
c8d70272 AJ |
1028 | break; |
1029 | ||
1030 | CASE_OP_32_64(qemu_ld): | |
1031 | { | |
9002ffcb | 1032 | MemOpIdx oi = op->args[nb_oargs + nb_iargs]; |
14776ab5 | 1033 | MemOp mop = get_memop(oi); |
c8d70272 | 1034 | if (!(mop & MO_SIGN)) { |
b1fde411 | 1035 | z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; |
c8d70272 AJ |
1036 | } |
1037 | } | |
1038 | break; | |
1039 | ||
0b76ff8f | 1040 | CASE_OP_32_64(bswap16): |
b1fde411 RH |
1041 | z_mask = arg_info(op->args[1])->z_mask; |
1042 | if (z_mask <= 0xffff) { | |
0b76ff8f RH |
1043 | op->args[2] |= TCG_BSWAP_IZ; |
1044 | } | |
b1fde411 | 1045 | z_mask = bswap16(z_mask); |
0b76ff8f RH |
1046 | switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { |
1047 | case TCG_BSWAP_OZ: | |
1048 | break; | |
1049 | case TCG_BSWAP_OS: | |
b1fde411 | 1050 | z_mask = (int16_t)z_mask; |
0b76ff8f RH |
1051 | break; |
1052 | default: /* undefined high bits */ | |
b1fde411 | 1053 | z_mask |= MAKE_64BIT_MASK(16, 48); |
0b76ff8f RH |
1054 | break; |
1055 | } | |
1056 | break; | |
1057 | ||
1058 | case INDEX_op_bswap32_i64: | |
b1fde411 RH |
1059 | z_mask = arg_info(op->args[1])->z_mask; |
1060 | if (z_mask <= 0xffffffffu) { | |
0b76ff8f RH |
1061 | op->args[2] |= TCG_BSWAP_IZ; |
1062 | } | |
b1fde411 | 1063 | z_mask = bswap32(z_mask); |
0b76ff8f RH |
1064 | switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { |
1065 | case TCG_BSWAP_OZ: | |
1066 | break; | |
1067 | case TCG_BSWAP_OS: | |
b1fde411 | 1068 | z_mask = (int32_t)z_mask; |
0b76ff8f RH |
1069 | break; |
1070 | default: /* undefined high bits */ | |
b1fde411 | 1071 | z_mask |= MAKE_64BIT_MASK(32, 32); |
0b76ff8f RH |
1072 | break; |
1073 | } | |
1074 | break; | |
1075 | ||
3a9d8b17 PB |
1076 | default: |
1077 | break; | |
1078 | } | |
1079 | ||
bc8d688f RH |
1080 | /* 32-bit ops generate 32-bit results. For the result is zero test |
1081 | below, we can ignore high bits, but for further optimizations we | |
1082 | need to record that the high bits contain garbage. */ | |
b1fde411 | 1083 | partmask = z_mask; |
bc8d688f | 1084 | if (!(def->flags & TCG_OPF_64BIT)) { |
b1fde411 | 1085 | z_mask |= ~(tcg_target_ulong)0xffffffffu; |
24666baf RH |
1086 | partmask &= 0xffffffffu; |
1087 | affected &= 0xffffffffu; | |
f096dc96 AJ |
1088 | } |
1089 | ||
24666baf | 1090 | if (partmask == 0) { |
eabb7b91 | 1091 | tcg_debug_assert(nb_oargs == 1); |
dc84988a | 1092 | tcg_opt_gen_movi(&ctx, op, op->args[0], 0); |
633f6502 PB |
1093 | continue; |
1094 | } | |
1095 | if (affected == 0) { | |
eabb7b91 | 1096 | tcg_debug_assert(nb_oargs == 1); |
dc84988a | 1097 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
633f6502 PB |
1098 | continue; |
1099 | } | |
1100 | ||
56e49438 | 1101 | /* Simplify expression for "op r, a, 0 => movi r, 0" cases */ |
c45cb8bb | 1102 | switch (opc) { |
170ba88f RH |
1103 | CASE_OP_32_64_VEC(and): |
1104 | CASE_OP_32_64_VEC(mul): | |
03271524 RH |
1105 | CASE_OP_32_64(muluh): |
1106 | CASE_OP_32_64(mulsh): | |
6349039d RH |
1107 | if (arg_is_const(op->args[2]) |
1108 | && arg_info(op->args[2])->val == 0) { | |
dc84988a | 1109 | tcg_opt_gen_movi(&ctx, op, op->args[0], 0); |
53108fb5 KB |
1110 | continue; |
1111 | } | |
1112 | break; | |
56e49438 AJ |
1113 | default: |
1114 | break; | |
1115 | } | |
1116 | ||
1117 | /* Simplify expression for "op r, a, a => mov r, a" cases */ | |
c45cb8bb | 1118 | switch (opc) { |
170ba88f RH |
1119 | CASE_OP_32_64_VEC(or): |
1120 | CASE_OP_32_64_VEC(and): | |
6349039d | 1121 | if (args_are_copies(op->args[1], op->args[2])) { |
dc84988a | 1122 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
9a81090b KB |
1123 | continue; |
1124 | } | |
1125 | break; | |
fe0de7aa BS |
1126 | default: |
1127 | break; | |
53108fb5 KB |
1128 | } |
1129 | ||
3c94193e | 1130 | /* Simplify expression for "op r, a, a => movi r, 0" cases */ |
c45cb8bb | 1131 | switch (opc) { |
170ba88f RH |
1132 | CASE_OP_32_64_VEC(andc): |
1133 | CASE_OP_32_64_VEC(sub): | |
1134 | CASE_OP_32_64_VEC(xor): | |
6349039d | 1135 | if (args_are_copies(op->args[1], op->args[2])) { |
dc84988a | 1136 | tcg_opt_gen_movi(&ctx, op, op->args[0], 0); |
3c94193e AJ |
1137 | continue; |
1138 | } | |
1139 | break; | |
1140 | default: | |
1141 | break; | |
1142 | } | |
1143 | ||
22613af4 KB |
1144 | /* Propagate constants through copy operations and do constant |
1145 | folding. Constants will be substituted to arguments by register | |
1146 | allocator where needed and possible. Also detect copies. */ | |
c45cb8bb | 1147 | switch (opc) { |
170ba88f | 1148 | CASE_OP_32_64_VEC(mov): |
dc84988a | 1149 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); |
b10f3833 | 1150 | continue; |
6e14e91b | 1151 | |
170ba88f RH |
1152 | case INDEX_op_dup_vec: |
1153 | if (arg_is_const(op->args[1])) { | |
1154 | tmp = arg_info(op->args[1])->val; | |
1155 | tmp = dup_const(TCGOP_VECE(op), tmp); | |
dc84988a | 1156 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1157 | continue; |
170ba88f | 1158 | } |
b10f3833 | 1159 | break; |
170ba88f | 1160 | |
1dc4fe70 RH |
1161 | case INDEX_op_dup2_vec: |
1162 | assert(TCG_TARGET_REG_BITS == 32); | |
1163 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | |
dc84988a | 1164 | tcg_opt_gen_movi(&ctx, op, op->args[0], |
0b4286dd RH |
1165 | deposit64(arg_info(op->args[1])->val, 32, 32, |
1166 | arg_info(op->args[2])->val)); | |
b10f3833 | 1167 | continue; |
1dc4fe70 RH |
1168 | } else if (args_are_copies(op->args[1], op->args[2])) { |
1169 | op->opc = INDEX_op_dup_vec; | |
1170 | TCGOP_VECE(op) = MO_32; | |
1171 | nb_iargs = 1; | |
1172 | } | |
b10f3833 | 1173 | break; |
1dc4fe70 | 1174 | |
a640f031 | 1175 | CASE_OP_32_64(not): |
cb25c80a | 1176 | CASE_OP_32_64(neg): |
25c4d9cc RH |
1177 | CASE_OP_32_64(ext8s): |
1178 | CASE_OP_32_64(ext8u): | |
1179 | CASE_OP_32_64(ext16s): | |
1180 | CASE_OP_32_64(ext16u): | |
a768e4e9 | 1181 | CASE_OP_32_64(ctpop): |
a640f031 KB |
1182 | case INDEX_op_ext32s_i64: |
1183 | case INDEX_op_ext32u_i64: | |
8bcb5c8f AJ |
1184 | case INDEX_op_ext_i32_i64: |
1185 | case INDEX_op_extu_i32_i64: | |
609ad705 RH |
1186 | case INDEX_op_extrl_i64_i32: |
1187 | case INDEX_op_extrh_i64_i32: | |
6349039d RH |
1188 | if (arg_is_const(op->args[1])) { |
1189 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); | |
dc84988a | 1190 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1191 | continue; |
a640f031 | 1192 | } |
b10f3833 | 1193 | break; |
6e14e91b | 1194 | |
0b76ff8f RH |
1195 | CASE_OP_32_64(bswap16): |
1196 | CASE_OP_32_64(bswap32): | |
1197 | case INDEX_op_bswap64_i64: | |
1198 | if (arg_is_const(op->args[1])) { | |
1199 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, | |
1200 | op->args[2]); | |
dc84988a | 1201 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1202 | continue; |
0b76ff8f | 1203 | } |
b10f3833 | 1204 | break; |
0b76ff8f | 1205 | |
53108fb5 KB |
1206 | CASE_OP_32_64(add): |
1207 | CASE_OP_32_64(sub): | |
1208 | CASE_OP_32_64(mul): | |
9a81090b KB |
1209 | CASE_OP_32_64(or): |
1210 | CASE_OP_32_64(and): | |
1211 | CASE_OP_32_64(xor): | |
55c0975c KB |
1212 | CASE_OP_32_64(shl): |
1213 | CASE_OP_32_64(shr): | |
1214 | CASE_OP_32_64(sar): | |
25c4d9cc RH |
1215 | CASE_OP_32_64(rotl): |
1216 | CASE_OP_32_64(rotr): | |
cb25c80a RH |
1217 | CASE_OP_32_64(andc): |
1218 | CASE_OP_32_64(orc): | |
1219 | CASE_OP_32_64(eqv): | |
1220 | CASE_OP_32_64(nand): | |
1221 | CASE_OP_32_64(nor): | |
03271524 RH |
1222 | CASE_OP_32_64(muluh): |
1223 | CASE_OP_32_64(mulsh): | |
01547f7f RH |
1224 | CASE_OP_32_64(div): |
1225 | CASE_OP_32_64(divu): | |
1226 | CASE_OP_32_64(rem): | |
1227 | CASE_OP_32_64(remu): | |
6349039d RH |
1228 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { |
1229 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, | |
1230 | arg_info(op->args[2])->val); | |
dc84988a | 1231 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1232 | continue; |
53108fb5 | 1233 | } |
b10f3833 | 1234 | break; |
6e14e91b | 1235 | |
0e28d006 RH |
1236 | CASE_OP_32_64(clz): |
1237 | CASE_OP_32_64(ctz): | |
6349039d RH |
1238 | if (arg_is_const(op->args[1])) { |
1239 | TCGArg v = arg_info(op->args[1])->val; | |
0e28d006 RH |
1240 | if (v != 0) { |
1241 | tmp = do_constant_folding(opc, v, 0); | |
dc84988a | 1242 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
0e28d006 | 1243 | } else { |
dc84988a | 1244 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[2]); |
0e28d006 | 1245 | } |
b10f3833 | 1246 | continue; |
0e28d006 | 1247 | } |
b10f3833 | 1248 | break; |
0e28d006 | 1249 | |
7ef55fc9 | 1250 | CASE_OP_32_64(deposit): |
6349039d RH |
1251 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { |
1252 | tmp = deposit64(arg_info(op->args[1])->val, | |
1253 | op->args[3], op->args[4], | |
1254 | arg_info(op->args[2])->val); | |
dc84988a | 1255 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1256 | continue; |
7ef55fc9 | 1257 | } |
b10f3833 | 1258 | break; |
6e14e91b | 1259 | |
7ec8bab3 | 1260 | CASE_OP_32_64(extract): |
6349039d RH |
1261 | if (arg_is_const(op->args[1])) { |
1262 | tmp = extract64(arg_info(op->args[1])->val, | |
acd93701 | 1263 | op->args[2], op->args[3]); |
dc84988a | 1264 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1265 | continue; |
7ec8bab3 | 1266 | } |
b10f3833 | 1267 | break; |
7ec8bab3 RH |
1268 | |
1269 | CASE_OP_32_64(sextract): | |
6349039d RH |
1270 | if (arg_is_const(op->args[1])) { |
1271 | tmp = sextract64(arg_info(op->args[1])->val, | |
acd93701 | 1272 | op->args[2], op->args[3]); |
dc84988a | 1273 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1274 | continue; |
7ec8bab3 | 1275 | } |
b10f3833 | 1276 | break; |
7ec8bab3 | 1277 | |
fce1296f RH |
1278 | CASE_OP_32_64(extract2): |
1279 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | |
54795544 RH |
1280 | uint64_t v1 = arg_info(op->args[1])->val; |
1281 | uint64_t v2 = arg_info(op->args[2])->val; | |
1282 | int shr = op->args[3]; | |
fce1296f RH |
1283 | |
1284 | if (opc == INDEX_op_extract2_i64) { | |
54795544 | 1285 | tmp = (v1 >> shr) | (v2 << (64 - shr)); |
fce1296f | 1286 | } else { |
54795544 RH |
1287 | tmp = (int32_t)(((uint32_t)v1 >> shr) | |
1288 | ((uint32_t)v2 << (32 - shr))); | |
fce1296f | 1289 | } |
dc84988a | 1290 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1291 | continue; |
fce1296f | 1292 | } |
b10f3833 | 1293 | break; |
fce1296f | 1294 | |
f8dd19e5 | 1295 | CASE_OP_32_64(setcond): |
acd93701 RH |
1296 | tmp = do_constant_folding_cond(opc, op->args[1], |
1297 | op->args[2], op->args[3]); | |
b336ceb6 | 1298 | if (tmp != 2) { |
dc84988a | 1299 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 | 1300 | continue; |
f8dd19e5 | 1301 | } |
b10f3833 | 1302 | break; |
6e14e91b | 1303 | |
fbeaa26c | 1304 | CASE_OP_32_64(brcond): |
acd93701 RH |
1305 | tmp = do_constant_folding_cond(opc, op->args[0], |
1306 | op->args[1], op->args[2]); | |
b10f3833 RH |
1307 | switch (tmp) { |
1308 | case 0: | |
1309 | tcg_op_remove(s, op); | |
1310 | continue; | |
1311 | case 1: | |
1312 | memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); | |
1313 | op->opc = opc = INDEX_op_br; | |
1314 | op->args[0] = op->args[3]; | |
6e14e91b | 1315 | break; |
fbeaa26c | 1316 | } |
b10f3833 | 1317 | break; |
6e14e91b | 1318 | |
fa01a208 | 1319 | CASE_OP_32_64(movcond): |
acd93701 RH |
1320 | tmp = do_constant_folding_cond(opc, op->args[1], |
1321 | op->args[2], op->args[5]); | |
b336ceb6 | 1322 | if (tmp != 2) { |
dc84988a | 1323 | tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4-tmp]); |
b10f3833 | 1324 | continue; |
fa01a208 | 1325 | } |
6349039d | 1326 | if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { |
54795544 RH |
1327 | uint64_t tv = arg_info(op->args[3])->val; |
1328 | uint64_t fv = arg_info(op->args[4])->val; | |
acd93701 | 1329 | TCGCond cond = op->args[5]; |
54795544 | 1330 | |
333b21b8 RH |
1331 | if (fv == 1 && tv == 0) { |
1332 | cond = tcg_invert_cond(cond); | |
1333 | } else if (!(tv == 1 && fv == 0)) { | |
b10f3833 | 1334 | break; |
333b21b8 | 1335 | } |
acd93701 | 1336 | op->args[3] = cond; |
333b21b8 RH |
1337 | op->opc = opc = (opc == INDEX_op_movcond_i32 |
1338 | ? INDEX_op_setcond_i32 | |
1339 | : INDEX_op_setcond_i64); | |
1340 | nb_iargs = 2; | |
1341 | } | |
b10f3833 | 1342 | break; |
212c328d RH |
1343 | |
1344 | case INDEX_op_add2_i32: | |
1345 | case INDEX_op_sub2_i32: | |
6349039d RH |
1346 | if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) |
1347 | && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) { | |
1348 | uint32_t al = arg_info(op->args[2])->val; | |
1349 | uint32_t ah = arg_info(op->args[3])->val; | |
1350 | uint32_t bl = arg_info(op->args[4])->val; | |
1351 | uint32_t bh = arg_info(op->args[5])->val; | |
212c328d RH |
1352 | uint64_t a = ((uint64_t)ah << 32) | al; |
1353 | uint64_t b = ((uint64_t)bh << 32) | bl; | |
1354 | TCGArg rl, rh; | |
8fe35e04 | 1355 | TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); |
212c328d | 1356 | |
c45cb8bb | 1357 | if (opc == INDEX_op_add2_i32) { |
212c328d RH |
1358 | a += b; |
1359 | } else { | |
1360 | a -= b; | |
1361 | } | |
1362 | ||
acd93701 RH |
1363 | rl = op->args[0]; |
1364 | rh = op->args[1]; | |
dc84988a RH |
1365 | tcg_opt_gen_movi(&ctx, op, rl, (int32_t)a); |
1366 | tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(a >> 32)); | |
b10f3833 | 1367 | continue; |
212c328d | 1368 | } |
b10f3833 | 1369 | break; |
1414968a RH |
1370 | |
1371 | case INDEX_op_mulu2_i32: | |
6349039d RH |
1372 | if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { |
1373 | uint32_t a = arg_info(op->args[2])->val; | |
1374 | uint32_t b = arg_info(op->args[3])->val; | |
1414968a RH |
1375 | uint64_t r = (uint64_t)a * b; |
1376 | TCGArg rl, rh; | |
8fe35e04 | 1377 | TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); |
1414968a | 1378 | |
acd93701 RH |
1379 | rl = op->args[0]; |
1380 | rh = op->args[1]; | |
dc84988a RH |
1381 | tcg_opt_gen_movi(&ctx, op, rl, (int32_t)r); |
1382 | tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(r >> 32)); | |
b10f3833 | 1383 | continue; |
1414968a | 1384 | } |
b10f3833 | 1385 | break; |
6e14e91b | 1386 | |
bc1473ef | 1387 | case INDEX_op_brcond2_i32: |
acd93701 RH |
1388 | tmp = do_constant_folding_cond2(&op->args[0], &op->args[2], |
1389 | op->args[4]); | |
b10f3833 | 1390 | if (tmp == 0) { |
a763551a | 1391 | do_brcond_false: |
b10f3833 RH |
1392 | tcg_op_remove(s, op); |
1393 | continue; | |
1394 | } | |
1395 | if (tmp == 1) { | |
1396 | do_brcond_true: | |
1397 | op->opc = opc = INDEX_op_br; | |
1398 | op->args[0] = op->args[5]; | |
1399 | break; | |
1400 | } | |
1401 | if ((op->args[4] == TCG_COND_LT || op->args[4] == TCG_COND_GE) | |
1402 | && arg_is_const(op->args[2]) | |
1403 | && arg_info(op->args[2])->val == 0 | |
1404 | && arg_is_const(op->args[3]) | |
1405 | && arg_info(op->args[3])->val == 0) { | |
6c4382f8 RH |
1406 | /* Simplify LT/GE comparisons vs zero to a single compare |
1407 | vs the high word of the input. */ | |
a763551a | 1408 | do_brcond_high: |
b10f3833 | 1409 | op->opc = opc = INDEX_op_brcond_i32; |
acd93701 RH |
1410 | op->args[0] = op->args[1]; |
1411 | op->args[1] = op->args[3]; | |
1412 | op->args[2] = op->args[4]; | |
1413 | op->args[3] = op->args[5]; | |
b10f3833 RH |
1414 | break; |
1415 | } | |
1416 | if (op->args[4] == TCG_COND_EQ) { | |
a763551a RH |
1417 | /* Simplify EQ comparisons where one of the pairs |
1418 | can be simplified. */ | |
1419 | tmp = do_constant_folding_cond(INDEX_op_brcond_i32, | |
acd93701 RH |
1420 | op->args[0], op->args[2], |
1421 | TCG_COND_EQ); | |
a763551a RH |
1422 | if (tmp == 0) { |
1423 | goto do_brcond_false; | |
1424 | } else if (tmp == 1) { | |
1425 | goto do_brcond_high; | |
1426 | } | |
1427 | tmp = do_constant_folding_cond(INDEX_op_brcond_i32, | |
acd93701 RH |
1428 | op->args[1], op->args[3], |
1429 | TCG_COND_EQ); | |
a763551a RH |
1430 | if (tmp == 0) { |
1431 | goto do_brcond_false; | |
1432 | } else if (tmp != 1) { | |
b10f3833 | 1433 | break; |
a763551a RH |
1434 | } |
1435 | do_brcond_low: | |
3b3f847d | 1436 | memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); |
c45cb8bb | 1437 | op->opc = INDEX_op_brcond_i32; |
acd93701 RH |
1438 | op->args[1] = op->args[2]; |
1439 | op->args[2] = op->args[4]; | |
1440 | op->args[3] = op->args[5]; | |
b10f3833 RH |
1441 | break; |
1442 | } | |
1443 | if (op->args[4] == TCG_COND_NE) { | |
a763551a RH |
1444 | /* Simplify NE comparisons where one of the pairs |
1445 | can be simplified. */ | |
1446 | tmp = do_constant_folding_cond(INDEX_op_brcond_i32, | |
acd93701 RH |
1447 | op->args[0], op->args[2], |
1448 | TCG_COND_NE); | |
a763551a RH |
1449 | if (tmp == 0) { |
1450 | goto do_brcond_high; | |
1451 | } else if (tmp == 1) { | |
1452 | goto do_brcond_true; | |
1453 | } | |
1454 | tmp = do_constant_folding_cond(INDEX_op_brcond_i32, | |
acd93701 RH |
1455 | op->args[1], op->args[3], |
1456 | TCG_COND_NE); | |
a763551a RH |
1457 | if (tmp == 0) { |
1458 | goto do_brcond_low; | |
1459 | } else if (tmp == 1) { | |
1460 | goto do_brcond_true; | |
1461 | } | |
bc1473ef | 1462 | } |
6c4382f8 | 1463 | break; |
bc1473ef RH |
1464 | |
1465 | case INDEX_op_setcond2_i32: | |
acd93701 RH |
1466 | tmp = do_constant_folding_cond2(&op->args[1], &op->args[3], |
1467 | op->args[5]); | |
6c4382f8 | 1468 | if (tmp != 2) { |
a763551a | 1469 | do_setcond_const: |
dc84988a | 1470 | tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); |
b10f3833 RH |
1471 | continue; |
1472 | } | |
1473 | if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) | |
1474 | && arg_is_const(op->args[3]) | |
1475 | && arg_info(op->args[3])->val == 0 | |
1476 | && arg_is_const(op->args[4]) | |
1477 | && arg_info(op->args[4])->val == 0) { | |
6c4382f8 RH |
1478 | /* Simplify LT/GE comparisons vs zero to a single compare |
1479 | vs the high word of the input. */ | |
a763551a | 1480 | do_setcond_high: |
acd93701 | 1481 | reset_temp(op->args[0]); |
b1fde411 | 1482 | arg_info(op->args[0])->z_mask = 1; |
c45cb8bb | 1483 | op->opc = INDEX_op_setcond_i32; |
acd93701 RH |
1484 | op->args[1] = op->args[2]; |
1485 | op->args[2] = op->args[4]; | |
1486 | op->args[3] = op->args[5]; | |
b10f3833 RH |
1487 | break; |
1488 | } | |
1489 | if (op->args[5] == TCG_COND_EQ) { | |
a763551a RH |
1490 | /* Simplify EQ comparisons where one of the pairs |
1491 | can be simplified. */ | |
1492 | tmp = do_constant_folding_cond(INDEX_op_setcond_i32, | |
acd93701 RH |
1493 | op->args[1], op->args[3], |
1494 | TCG_COND_EQ); | |
a763551a RH |
1495 | if (tmp == 0) { |
1496 | goto do_setcond_const; | |
1497 | } else if (tmp == 1) { | |
1498 | goto do_setcond_high; | |
1499 | } | |
1500 | tmp = do_constant_folding_cond(INDEX_op_setcond_i32, | |
acd93701 RH |
1501 | op->args[2], op->args[4], |
1502 | TCG_COND_EQ); | |
a763551a RH |
1503 | if (tmp == 0) { |
1504 | goto do_setcond_high; | |
1505 | } else if (tmp != 1) { | |
b10f3833 | 1506 | break; |
a763551a RH |
1507 | } |
1508 | do_setcond_low: | |
acd93701 | 1509 | reset_temp(op->args[0]); |
b1fde411 | 1510 | arg_info(op->args[0])->z_mask = 1; |
c45cb8bb | 1511 | op->opc = INDEX_op_setcond_i32; |
acd93701 RH |
1512 | op->args[2] = op->args[3]; |
1513 | op->args[3] = op->args[5]; | |
b10f3833 RH |
1514 | break; |
1515 | } | |
1516 | if (op->args[5] == TCG_COND_NE) { | |
a763551a RH |
1517 | /* Simplify NE comparisons where one of the pairs |
1518 | can be simplified. */ | |
1519 | tmp = do_constant_folding_cond(INDEX_op_setcond_i32, | |
acd93701 RH |
1520 | op->args[1], op->args[3], |
1521 | TCG_COND_NE); | |
a763551a RH |
1522 | if (tmp == 0) { |
1523 | goto do_setcond_high; | |
1524 | } else if (tmp == 1) { | |
1525 | goto do_setcond_const; | |
1526 | } | |
1527 | tmp = do_constant_folding_cond(INDEX_op_setcond_i32, | |
acd93701 RH |
1528 | op->args[2], op->args[4], |
1529 | TCG_COND_NE); | |
a763551a RH |
1530 | if (tmp == 0) { |
1531 | goto do_setcond_low; | |
1532 | } else if (tmp == 1) { | |
1533 | goto do_setcond_const; | |
1534 | } | |
bc1473ef | 1535 | } |
6c4382f8 | 1536 | break; |
bc1473ef | 1537 | |
b10f3833 RH |
1538 | default: |
1539 | break; | |
1540 | } | |
1541 | ||
1542 | /* Some of the folding above can change opc. */ | |
1543 | opc = op->opc; | |
1544 | def = &tcg_op_defs[opc]; | |
1545 | if (def->flags & TCG_OPF_BB_END) { | |
1546 | memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); | |
1547 | } else { | |
1548 | if (opc == INDEX_op_call && | |
1549 | !(tcg_call_flags(op) | |
cf066674 | 1550 | & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { |
22613af4 | 1551 | for (i = 0; i < nb_globals; i++) { |
3b3f847d | 1552 | if (test_bit(i, ctx.temps_used.l)) { |
6349039d | 1553 | reset_ts(&s->temps[i]); |
1208d7dd | 1554 | } |
22613af4 KB |
1555 | } |
1556 | } | |
6e14e91b | 1557 | |
b10f3833 RH |
1558 | for (i = 0; i < nb_oargs; i++) { |
1559 | reset_temp(op->args[i]); | |
1560 | /* Save the corresponding known-zero bits mask for the | |
1561 | first output argument (only one supported so far). */ | |
1562 | if (i == 0) { | |
1563 | arg_info(op->args[i])->z_mask = z_mask; | |
a2550660 | 1564 | } |
22613af4 | 1565 | } |
8f2e8c07 | 1566 | } |
34f93921 PK |
1567 | |
1568 | /* Eliminate duplicate and redundant fence instructions. */ | |
acd93701 | 1569 | if (prev_mb) { |
34f93921 PK |
1570 | switch (opc) { |
1571 | case INDEX_op_mb: | |
1572 | /* Merge two barriers of the same type into one, | |
1573 | * or a weaker barrier into a stronger one, | |
1574 | * or two weaker barriers into a stronger one. | |
1575 | * mb X; mb Y => mb X|Y | |
1576 | * mb; strl => mb; st | |
1577 | * ldaq; mb => ld; mb | |
1578 | * ldaq; strl => ld; mb; st | |
1579 | * Other combinations are also merged into a strong | |
1580 | * barrier. This is stricter than specified but for | |
1581 | * the purposes of TCG is better than not optimizing. | |
1582 | */ | |
acd93701 | 1583 | prev_mb->args[0] |= op->args[0]; |
34f93921 PK |
1584 | tcg_op_remove(s, op); |
1585 | break; | |
1586 | ||
1587 | default: | |
1588 | /* Opcodes that end the block stop the optimization. */ | |
1589 | if ((def->flags & TCG_OPF_BB_END) == 0) { | |
1590 | break; | |
1591 | } | |
1592 | /* fallthru */ | |
1593 | case INDEX_op_qemu_ld_i32: | |
1594 | case INDEX_op_qemu_ld_i64: | |
1595 | case INDEX_op_qemu_st_i32: | |
07ce0b05 | 1596 | case INDEX_op_qemu_st8_i32: |
34f93921 PK |
1597 | case INDEX_op_qemu_st_i64: |
1598 | case INDEX_op_call: | |
1599 | /* Opcodes that touch guest memory stop the optimization. */ | |
acd93701 | 1600 | prev_mb = NULL; |
34f93921 PK |
1601 | break; |
1602 | } | |
1603 | } else if (opc == INDEX_op_mb) { | |
acd93701 | 1604 | prev_mb = op; |
34f93921 | 1605 | } |
8f2e8c07 | 1606 | } |
8f2e8c07 | 1607 | } |