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tcg: fix build on 32-bit hppa, ppc and sparc hosts
[mirror_qemu.git] / tcg / ppc / tcg-target.c
CommitLineData
2662e13f
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25static uint8_t *tb_ret_addr;
26
6ec85236 27#ifdef _CALL_DARWIN
bf6bca52 28#define LINKAGE_AREA_SIZE 24
2946898b 29#define LR_OFFSET 8
6ec85236 30#elif defined _CALL_AIX
b29fe3ed 31#define LINKAGE_AREA_SIZE 52
32#define LR_OFFSET 8
f9bf2987 33#else
34#define LINKAGE_AREA_SIZE 8
2946898b 35#define LR_OFFSET 4
f9bf2987 36#endif
37
2662e13f
FB		 38#define FAST_PATH
39#if TARGET_PHYS_ADDR_BITS <= 32
40#define ADDEND_OFFSET 0
41#else
42#define ADDEND_OFFSET 4
43#endif
44
f6548c0a 45#ifndef GUEST_BASE
46#define GUEST_BASE 0
47#endif
48
49#ifdef CONFIG_USE_GUEST_BASE
50#define TCG_GUEST_BASE_REG 30
51#else
52#define TCG_GUEST_BASE_REG 0
53#endif
54
d4a9eb1f 55#ifndef NDEBUG
2662e13f
FB		 56static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
57 "r0",
58 "r1",
59 "rp",
60 "r3",
61 "r4",
62 "r5",
63 "r6",
64 "r7",
65 "r8",
66 "r9",
67 "r10",
68 "r11",
69 "r12",
70 "r13",
71 "r14",
72 "r15",
73 "r16",
74 "r17",
75 "r18",
76 "r19",
77 "r20",
78 "r21",
79 "r22",
80 "r23",
81 "r24",
82 "r25",
83 "r26",
84 "r27",
85 "r28",
86 "r29",
87 "r30",
88 "r31"
89};
d4a9eb1f 90#endif
2662e13f
FB		 91
92static const int tcg_target_reg_alloc_order[] = {
a35e86c5 93 TCG_REG_R14,
94 TCG_REG_R15,
95 TCG_REG_R16,
96 TCG_REG_R17,
97 TCG_REG_R18,
98 TCG_REG_R19,
99 TCG_REG_R20,
100 TCG_REG_R21,
101 TCG_REG_R22,
102 TCG_REG_R23,
103 TCG_REG_R28,
104 TCG_REG_R29,
105 TCG_REG_R30,
106 TCG_REG_R31,
6ec85236 107#ifdef _CALL_DARWIN
f9bf2987 108 TCG_REG_R2,
109#endif
2662e13f
FB		 110 TCG_REG_R3,
111 TCG_REG_R4,
112 TCG_REG_R5,
113 TCG_REG_R6,
114 TCG_REG_R7,
115 TCG_REG_R8,
116 TCG_REG_R9,
117 TCG_REG_R10,
6ec85236 118#ifndef _CALL_DARWIN
2662e13f 119 TCG_REG_R11,
f9bf2987 120#endif
2662e13f 121 TCG_REG_R12,
6ec85236 122#ifndef _CALL_SYSV
2662e13f 123 TCG_REG_R13,
5db3ee79 124#endif
2662e13f
FB		 125 TCG_REG_R24,
126 TCG_REG_R25,
127 TCG_REG_R26,
a35e86c5 128 TCG_REG_R27
2662e13f
FB		 129};
130
131static const int tcg_target_call_iarg_regs[] = {
132 TCG_REG_R3,
133 TCG_REG_R4,
134 TCG_REG_R5,
135 TCG_REG_R6,
136 TCG_REG_R7,
137 TCG_REG_R8,
138 TCG_REG_R9,
139 TCG_REG_R10
140};
141
142static const int tcg_target_call_oarg_regs[2] = {
143 TCG_REG_R3,
144 TCG_REG_R4
145};
146
147static const int tcg_target_callee_save_regs[] = {
6ec85236 148#ifdef _CALL_DARWIN
f9bf2987 149 TCG_REG_R11,
150 TCG_REG_R13,
b29fe3ed 151#endif
6ec85236 152#ifdef _CALL_AIX
b29fe3ed 153 TCG_REG_R13,
f9bf2987 154#endif
2662e13f
FB		 155 TCG_REG_R14,
156 TCG_REG_R15,
157 TCG_REG_R16,
158 TCG_REG_R17,
159 TCG_REG_R18,
160 TCG_REG_R19,
161 TCG_REG_R20,
162 TCG_REG_R21,
163 TCG_REG_R22,
164 TCG_REG_R23,
eb2eb1dc 165 TCG_REG_R24,
166 TCG_REG_R25,
167 TCG_REG_R26,
168 /* TCG_REG_R27, */ /* currently used for the global env, so no
169 need to save */
2662e13f
FB		 170 TCG_REG_R28,
171 TCG_REG_R29,
172 TCG_REG_R30,
173 TCG_REG_R31
174};
175
176static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
177{
932a6909
FB		 178 tcg_target_long disp;
179
180 disp = target - (tcg_target_long) pc;
181 if ((disp << 6) >> 6 != disp)
182 tcg_abort ();
183
184 return disp & 0x3fffffc;
2662e13f
FB		 185}
186
187static void reloc_pc24 (void *pc, tcg_target_long target)
188{
189 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
190 | reloc_pc24_val (pc, target);
191}
192
193static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
194{
932a6909
FB		 195 tcg_target_long disp;
196
197 disp = target - (tcg_target_long) pc;
198 if (disp != (int16_t) disp)
199 tcg_abort ();
200
201 return disp & 0xfffc;
2662e13f
FB		 202}
203
204static void reloc_pc14 (void *pc, tcg_target_long target)
205{
206 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
207 | reloc_pc14_val (pc, target);
208}
209
210static void patch_reloc(uint8_t *code_ptr, int type,
211 tcg_target_long value, tcg_target_long addend)
212{
213 value += addend;
214 switch (type) {
215 case R_PPC_REL14:
216 reloc_pc14 (code_ptr, value);
217 break;
218 case R_PPC_REL24:
219 reloc_pc24 (code_ptr, value);
220 break;
221 default:
222 tcg_abort();
223 }
224}
225
226/* maximum number of register used for input function arguments */
227static int tcg_target_get_call_iarg_regs_count(int flags)
228{
b1503cda 229 return ARRAY_SIZE (tcg_target_call_iarg_regs);
2662e13f
FB		 230}
231
232/* parse target specific constraints */
233static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
234{
235 const char *ct_str;
236
237 ct_str = *pct_str;
238 switch (ct_str[0]) {
398ce98e 239 case 'A': case 'B': case 'C': case 'D':
240 ct->ct |= TCG_CT_REG;
241 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
242 break;
2662e13f
FB		 243 case 'r':
244 ct->ct |= TCG_CT_REG;
245 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
246 break;
70fa887c 247#ifdef CONFIG_SOFTMMU
2662e13f
FB		 248 case 'L': /* qemu_ld constraint */
249 ct->ct |= TCG_CT_REG;
250 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 break;
254 case 'K': /* qemu_st[8..32] constraint */
255 ct->ct |= TCG_CT_REG;
256 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
257 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
258 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
259 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
260#if TARGET_LONG_BITS == 64
261 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
262#endif
263 break;
264 case 'M': /* qemu_st64 constraint */
265 ct->ct |= TCG_CT_REG;
266 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
267 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
268 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
269 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
270 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
271 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
272 break;
70fa887c 273#else
274 case 'L':
275 case 'K':
276 ct->ct |= TCG_CT_REG;
277 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
278 break;
279 case 'M':
280 ct->ct |= TCG_CT_REG;
281 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
282 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
283 break;
284#endif
2662e13f
FB		 285 default:
286 return -1;
287 }
288 ct_str++;
289 *pct_str = ct_str;
290 return 0;
291}
292
293/* test if a constant matches the constraint */
294static int tcg_target_const_match(tcg_target_long val,
295 const TCGArgConstraint *arg_ct)
296{
297 int ct;
298
299 ct = arg_ct->ct;
300 if (ct & TCG_CT_CONST)
301 return 1;
2662e13f
FB		 302 return 0;
303}
304
305#define OPCD(opc) ((opc)<<26)
306#define XO31(opc) (OPCD(31)|((opc)<<1))
307#define XO19(opc) (OPCD(19)|((opc)<<1))
308
309#define B OPCD(18)
310#define BC OPCD(16)
311#define LBZ OPCD(34)
312#define LHZ OPCD(40)
313#define LHA OPCD(42)
314#define LWZ OPCD(32)
315#define STB OPCD(38)
316#define STH OPCD(44)
317#define STW OPCD(36)
318
b0809bf7 319#define ADDIC OPCD(12)
2662e13f
FB		 320#define ADDI OPCD(14)
321#define ADDIS OPCD(15)
322#define ORI OPCD(24)
323#define ORIS OPCD(25)
324#define XORI OPCD(26)
325#define XORIS OPCD(27)
326#define ANDI OPCD(28)
327#define ANDIS OPCD(29)
328#define MULLI OPCD( 7)
329#define CMPLI OPCD(10)
330#define CMPI OPCD(11)
331
332#define LWZU OPCD(33)
333#define STWU OPCD(37)
334
335#define RLWINM OPCD(21)
336
c596defd 337#define BCLR XO19( 16)
2662e13f
FB		 338#define BCCTR XO19(528)
339#define CRAND XO19(257)
c596defd 340#define CRANDC XO19(129)
341#define CRNAND XO19(225)
342#define CROR XO19(449)
b0809bf7 343#define CRNOR XO19( 33)
2662e13f
FB		 344
345#define EXTSB XO31(954)
346#define EXTSH XO31(922)
347#define ADD XO31(266)
348#define ADDE XO31(138)
349#define ADDC XO31( 10)
350#define AND XO31( 28)
351#define SUBF XO31( 40)
352#define SUBFC XO31( 8)
353#define SUBFE XO31(136)
354#define OR XO31(444)
355#define XOR XO31(316)
356#define MULLW XO31(235)
357#define MULHWU XO31( 11)
358#define DIVW XO31(491)
359#define DIVWU XO31(459)
360#define CMP XO31( 0)
361#define CMPL XO31( 32)
362#define LHBRX XO31(790)
363#define LWBRX XO31(534)
364#define STHBRX XO31(918)
365#define STWBRX XO31(662)
366#define MFSPR XO31(339)
367#define MTSPR XO31(467)
368#define SRAWI XO31(824)
369#define NEG XO31(104)
b0809bf7 370#define MFCR XO31( 19)
371#define CNTLZW XO31( 26)
2662e13f
FB		 372
373#define LBZX XO31( 87)
4f4a67ae 374#define LHZX XO31(279)
2662e13f
FB		 375#define LHAX XO31(343)
376#define LWZX XO31( 23)
377#define STBX XO31(215)
378#define STHX XO31(407)
379#define STWX XO31(151)
380
381#define SPR(a,b) ((((a)<<5)|(b))<<11)
382#define LR SPR(8, 0)
383#define CTR SPR(9, 0)
384
385#define SLW XO31( 24)
386#define SRW XO31(536)
387#define SRAW XO31(792)
388
2662e13f
FB		 389#define TW XO31(4)
390#define TRAP (TW | TO (31))
391
392#define RT(r) ((r)<<21)
393#define RS(r) ((r)<<21)
394#define RA(r) ((r)<<16)
395#define RB(r) ((r)<<11)
396#define TO(t) ((t)<<21)
397#define SH(s) ((s)<<11)
398#define MB(b) ((b)<<6)
399#define ME(e) ((e)<<1)
400#define BO(o) ((o)<<21)
401
402#define LK 1
403
404#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
405#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
406
407#define BF(n) ((n)<<23)
408#define BI(n, c) (((c)+((n)*4))<<16)
409#define BT(n, c) (((c)+((n)*4))<<21)
410#define BA(n, c) (((c)+((n)*4))<<16)
411#define BB(n, c) (((c)+((n)*4))<<11)
412
413#define BO_COND_TRUE BO (12)
414#define BO_COND_FALSE BO (4)
415#define BO_ALWAYS BO (20)
416
417enum {
418 CR_LT,
419 CR_GT,
420 CR_EQ,
421 CR_SO
422};
423
424static const uint32_t tcg_to_bc[10] = {
425 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
426 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
427 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
428 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
429 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
430 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
431 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
432 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
433 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
434 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
435};
436
437static void tcg_out_mov(TCGContext *s, int ret, int arg)
438{
439 tcg_out32 (s, OR | SAB (arg, ret, arg));
440}
441
442static void tcg_out_movi(TCGContext *s, TCGType type,
443 int ret, tcg_target_long arg)
444{
445 if (arg == (int16_t) arg)
446 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
447 else {
448 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
449 if (arg & 0xffff)
0a878c47 450 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
2662e13f
FB		 451 }
452}
453
454static void tcg_out_ldst (TCGContext *s, int ret, int addr,
455 int offset, int op1, int op2)
456{
457 if (offset == (int16_t) offset)
458 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
459 else {
460 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
461 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
462 }
463}
464
932a6909
FB		 465static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
466{
467 tcg_target_long disp;
468
469 disp = target - (tcg_target_long) s->code_ptr;
470 if ((disp << 6) >> 6 == disp)
8c5e95d8 471 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
932a6909
FB		 472 else {
473 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
474 tcg_out32 (s, MTSPR | RS (0) | CTR);
475 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
476 }
477}
478
b29fe3ed 479static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
480{
6ec85236 481#ifdef _CALL_AIX
b29fe3ed 482 int reg;
483
484 if (const_arg) {
485 reg = 2;
486 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
487 }
488 else reg = arg;
489
490 tcg_out32 (s, LWZ | RT (0) | RA (reg));
491 tcg_out32 (s, MTSPR | RA (0) | CTR);
492 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
493 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
d9370327 494#else
495 if (const_arg) {
496 tcg_out_b (s, LK, arg);
497 }
498 else {
499 tcg_out32 (s, MTSPR | RS (arg) | LR);
500 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
501 }
b29fe3ed 502#endif
d9370327 503}
b29fe3ed 504
2662e13f 505#if defined(CONFIG_SOFTMMU)
79383c9c
BS		 506
507#include "../../softmmu_defs.h"
2662e13f
FB		 508
509static void *qemu_ld_helpers[4] = {
510 __ldb_mmu,
511 __ldw_mmu,
512 __ldl_mmu,
513 __ldq_mmu,
514};
515
516static void *qemu_st_helpers[4] = {
517 __stb_mmu,
518 __stw_mmu,
519 __stl_mmu,
520 __stq_mmu,
521};
522#endif
523
524static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
525{
f6548c0a 526 int addr_reg, data_reg, data_reg2, r0, r1, rbase, mem_index, s_bits, bswap;
2662e13f 527#ifdef CONFIG_SOFTMMU
f8edcbaa 528 int r2;
2662e13f
FB		 529 void *label1_ptr, *label2_ptr;
530#endif
531#if TARGET_LONG_BITS == 64
532 int addr_reg2;
533#endif
534
535 data_reg = *args++;
536 if (opc == 3)
537 data_reg2 = *args++;
538 else
539 data_reg2 = 0;
540 addr_reg = *args++;
541#if TARGET_LONG_BITS == 64
542 addr_reg2 = *args++;
543#endif
544 mem_index = *args;
545 s_bits = opc & 3;
546
547#ifdef CONFIG_SOFTMMU
548 r0 = 3;
549 r1 = 4;
550 r2 = 0;
f6548c0a 551 rbase = 0;
2662e13f
FB		 552
553 tcg_out32 (s, (RLWINM
554 | RA (r0)
555 | RS (addr_reg)
556 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
557 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
558 | ME (31 - CPU_TLB_ENTRY_BITS)
559 )
560 );
561 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
562 tcg_out32 (s, (LWZU
563 | RT (r1)
564 | RA (r0)
565 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
566 )
567 );
568 tcg_out32 (s, (RLWINM
569 | RA (r2)
570 | RS (addr_reg)
571 | SH (0)
572 | MB ((32 - s_bits) & 31)
573 | ME (31 - TARGET_PAGE_BITS)
574 )
575 );
576
577 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
578#if TARGET_LONG_BITS == 64
579 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
580 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
581 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
582#endif
583
584 label1_ptr = s->code_ptr;
585#ifdef FAST_PATH
586 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
587#endif
588
589 /* slow path */
590#if TARGET_LONG_BITS == 32
591 tcg_out_mov (s, 3, addr_reg);
592 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
593#else
594 tcg_out_mov (s, 3, addr_reg2);
595 tcg_out_mov (s, 4, addr_reg);
596 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
597#endif
598
b29fe3ed 599 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
2662e13f
FB		 600 switch (opc) {
601 case 0|4:
602 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
603 break;
604 case 1|4:
605 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
606 break;
607 case 0:
608 case 1:
609 case 2:
610 if (data_reg != 3)
611 tcg_out_mov (s, data_reg, 3);
612 break;
613 case 3:
614 if (data_reg == 3) {
615 if (data_reg2 == 4) {
616 tcg_out_mov (s, 0, 4);
617 tcg_out_mov (s, 4, 3);
618 tcg_out_mov (s, 3, 0);
619 }
620 else {
621 tcg_out_mov (s, data_reg2, 3);
622 tcg_out_mov (s, 3, 4);
623 }
624 }
625 else {
626 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
627 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
628 }
629 break;
630 }
631 label2_ptr = s->code_ptr;
632 tcg_out32 (s, B);
633
634 /* label1: fast path */
635#ifdef FAST_PATH
636 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
637#endif
638
639 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
640 tcg_out32 (s, (LWZ
641 | RT (r0)
642 | RA (r0)
643 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
644 - offsetof (CPUTLBEntry, addr_read))
645 ));
646 /* r0 = env->tlb_table[mem_index][index].addend */
647 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
648 /* r0 = env->tlb_table[mem_index][index].addend + addr */
649
650#else /* !CONFIG_SOFTMMU */
651 r0 = addr_reg;
f8edcbaa 652 r1 = 3;
f6548c0a 653 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
2662e13f
FB		 654#endif
655
656#ifdef TARGET_WORDS_BIGENDIAN
657 bswap = 0;
658#else
659 bswap = 1;
660#endif
f6548c0a 661
2662e13f
FB		 662 switch (opc) {
663 default:
664 case 0:
f6548c0a 665 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 666 break;
667 case 0|4:
f6548c0a 668 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 669 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
670 break;
671 case 1:
f6548c0a 672 if (bswap)
673 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
674 else
675 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 676 break;
677 case 1|4:
678 if (bswap) {
f6548c0a 679 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
2662e13f
FB		 680 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
681 }
f6548c0a 682 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
2662e13f
FB		 683 break;
684 case 2:
f6548c0a 685 if (bswap)
686 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
687 else
688 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 689 break;
690 case 3:
691 if (bswap) {
f6548c0a 692 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
693 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
694 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
2662e13f
FB		 695 }
696 else {
f6548c0a 697#ifdef CONFIG_USE_GUEST_BASE
698 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
699 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
700 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
701#else
2662e13f
FB		 702 if (r0 == data_reg2) {
703 tcg_out32 (s, LWZ | RT (0) | RA (r0));
704 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
705 tcg_out_mov (s, data_reg2, 0);
706 }
707 else {
708 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
709 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
710 }
f6548c0a 711#endif
2662e13f
FB		 712 }
713 break;
714 }
715
716#ifdef CONFIG_SOFTMMU
717 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
718#endif
719}
720
721static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
722{
f6548c0a 723 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap, rbase;
2662e13f
FB		 724#ifdef CONFIG_SOFTMMU
725 int r2, ir;
726 void *label1_ptr, *label2_ptr;
727#endif
728#if TARGET_LONG_BITS == 64
729 int addr_reg2;
730#endif
731
732 data_reg = *args++;
733 if (opc == 3)
734 data_reg2 = *args++;
735 else
736 data_reg2 = 0;
737 addr_reg = *args++;
738#if TARGET_LONG_BITS == 64
739 addr_reg2 = *args++;
740#endif
741 mem_index = *args;
742
743#ifdef CONFIG_SOFTMMU
744 r0 = 3;
745 r1 = 4;
746 r2 = 0;
f6548c0a 747 rbase = 0;
2662e13f
FB		 748
749 tcg_out32 (s, (RLWINM
750 | RA (r0)
751 | RS (addr_reg)
752 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
753 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
754 | ME (31 - CPU_TLB_ENTRY_BITS)
755 )
756 );
757 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
758 tcg_out32 (s, (LWZU
759 | RT (r1)
760 | RA (r0)
761 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
762 )
763 );
764 tcg_out32 (s, (RLWINM
765 | RA (r2)
766 | RS (addr_reg)
767 | SH (0)
768 | MB ((32 - opc) & 31)
769 | ME (31 - TARGET_PAGE_BITS)
770 )
771 );
772
773 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
774#if TARGET_LONG_BITS == 64
775 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
776 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
777 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
778#endif
779
780 label1_ptr = s->code_ptr;
781#ifdef FAST_PATH
782 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
783#endif
784
785 /* slow path */
786#if TARGET_LONG_BITS == 32
787 tcg_out_mov (s, 3, addr_reg);
788 ir = 4;
789#else
790 tcg_out_mov (s, 3, addr_reg2);
791 tcg_out_mov (s, 4, addr_reg);
f9bf2987 792#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2662e13f 793 ir = 5;
f9bf2987 794#else
795 ir = 4;
796#endif
2662e13f
FB		 797#endif
798
799 switch (opc) {
800 case 0:
801 tcg_out32 (s, (RLWINM
802 | RA (ir)
803 | RS (data_reg)
804 | SH (0)
805 | MB (24)
806 | ME (31)));
807 break;
808 case 1:
809 tcg_out32 (s, (RLWINM
810 | RA (ir)
811 | RS (data_reg)
812 | SH (0)
813 | MB (16)
814 | ME (31)));
815 break;
816 case 2:
817 tcg_out_mov (s, ir, data_reg);
818 break;
819 case 3:
f9bf2987 820#ifdef TCG_TARGET_CALL_ALIGN_ARGS
821 ir = 5;
822#endif
823 tcg_out_mov (s, ir++, data_reg2);
824 tcg_out_mov (s, ir, data_reg);
2662e13f
FB		 825 break;
826 }
827 ir++;
828
829 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
b29fe3ed 830 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
2662e13f
FB		 831 label2_ptr = s->code_ptr;
832 tcg_out32 (s, B);
833
834 /* label1: fast path */
835#ifdef FAST_PATH
836 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
837#endif
838
839 tcg_out32 (s, (LWZ
840 | RT (r0)
841 | RA (r0)
842 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
843 - offsetof (CPUTLBEntry, addr_write))
844 ));
845 /* r0 = env->tlb_table[mem_index][index].addend */
846 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
847 /* r0 = env->tlb_table[mem_index][index].addend + addr */
848
849#else /* !CONFIG_SOFTMMU */
2662e13f 850 r0 = addr_reg;
f6548c0a 851 r1 = 3;
a71836de 852 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
2662e13f
FB		 853#endif
854
855#ifdef TARGET_WORDS_BIGENDIAN
856 bswap = 0;
857#else
858 bswap = 1;
859#endif
860 switch (opc) {
861 case 0:
f6548c0a 862 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
2662e13f
FB		 863 break;
864 case 1:
f6548c0a 865 if (bswap)
866 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
867 else
868 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
2662e13f
FB		 869 break;
870 case 2:
f6548c0a 871 if (bswap)
872 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
873 else
874 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
2662e13f
FB		 875 break;
876 case 3:
877 if (bswap) {
878 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
f6548c0a 879 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
880 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
2662e13f
FB		 881 }
882 else {
f6548c0a 883#ifdef CONFIG_USE_GUEST_BASE
884 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
885 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
886 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
887#else
2662e13f
FB		 888 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
889 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
f6548c0a 890#endif
2662e13f
FB		 891 }
892 break;
893 }
894
895#ifdef CONFIG_SOFTMMU
896 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
897#endif
898}
899
900void tcg_target_qemu_prologue (TCGContext *s)
901{
0d5bd363 902 int i, frame_size;
2662e13f
FB		 903
904 frame_size = 0
f9bf2987 905 + LINKAGE_AREA_SIZE
2662e13f
FB		 906 + TCG_STATIC_CALL_ARGS_SIZE
907 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
908 ;
909 frame_size = (frame_size + 15) & ~15;
910
6ec85236 911#ifdef _CALL_AIX
b29fe3ed 912 {
913 uint32_t addr;
914
915 /* First emit adhoc function descriptor */
916 addr = (uint32_t) s->code_ptr + 12;
917 tcg_out32 (s, addr); /* entry point */
918 s->code_ptr += 8; /* skip TOC and environment pointer */
919 }
920#endif
2662e13f
FB		 921 tcg_out32 (s, MFSPR | RT (0) | LR);
922 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
923 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
924 tcg_out32 (s, (STW
925 | RS (tcg_target_callee_save_regs[i])
926 | RA (1)
f9bf2987 927 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
2662e13f
FB		 928 )
929 );
2946898b 930 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
2662e13f 931
f6548c0a 932#ifdef CONFIG_USE_GUEST_BASE
933 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
934#endif
935
2662e13f
FB		 936 tcg_out32 (s, MTSPR | RS (3) | CTR);
937 tcg_out32 (s, BCCTR | BO_ALWAYS);
938 tb_ret_addr = s->code_ptr;
939
940 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
941 tcg_out32 (s, (LWZ
942 | RT (tcg_target_callee_save_regs[i])
943 | RA (1)
f9bf2987 944 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
2662e13f
FB		 945 )
946 );
2946898b 947 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
2662e13f
FB		 948 tcg_out32 (s, MTSPR | RS (0) | LR);
949 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
950 tcg_out32 (s, BCLR | BO_ALWAYS);
951}
952
953static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
954 tcg_target_long arg2)
955{
956 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
957}
958
959static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
960 tcg_target_long arg2)
961{
962 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
963}
964
965static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
966{
967 if (!si && rt == ra)
968 return;
969
970 if (si == (int16_t) si)
971 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
972 else {
973 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
974 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
975 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
976 }
977}
978
979static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
980{
981 ppc_addi (s, reg, reg, val);
982}
983
c596defd 984static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
985 int const_arg2, int cr)
2662e13f 986{
2662e13f
FB		 987 int imm;
988 uint32_t op;
989
2662e13f 990 switch (cond) {
f3f478a7
FB		 991 case TCG_COND_EQ:
992 case TCG_COND_NE:
993 if (const_arg2) {
994 if ((int16_t) arg2 == arg2) {
995 op = CMPI;
996 imm = 1;
997 break;
998 }
999 else if ((uint16_t) arg2 == arg2) {
1000 op = CMPLI;
1001 imm = 1;
1002 break;
1003 }
1004 }
1005 op = CMPL;
1006 imm = 0;
1007 break;
1008
1009 case TCG_COND_LT:
1010 case TCG_COND_GE:
1011 case TCG_COND_LE:
1012 case TCG_COND_GT:
1013 if (const_arg2) {
1014 if ((int16_t) arg2 == arg2) {
1015 op = CMPI;
1016 imm = 1;
1017 break;
1018 }
1019 }
1020 op = CMP;
1021 imm = 0;
1022 break;
1023
1024 case TCG_COND_LTU:
1025 case TCG_COND_GEU:
1026 case TCG_COND_LEU:
1027 case TCG_COND_GTU:
1028 if (const_arg2) {
1029 if ((uint16_t) arg2 == arg2) {
1030 op = CMPLI;
1031 imm = 1;
1032 break;
1033 }
1034 }
1035 op = CMPL;
1036 imm = 0;
1037 break;
1038
2662e13f
FB		 1039 default:
1040 tcg_abort ();
1041 }
c596defd 1042 op |= BF (cr);
2662e13f
FB		 1043
1044 if (imm)
1045 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1046 else {
1047 if (const_arg2) {
1048 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1049 tcg_out32 (s, op | RA (arg1) | RB (0));
1050 }
1051 else
1052 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1053 }
1054
c596defd 1055}
1056
1057static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1058{
1059 TCGLabel *l = &s->labels[label_index];
1060
0a878c47 1061 if (l->has_value)
c596defd 1062 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
2662e13f 1063 else {
0a878c47 1064 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1065
1066 /* Thanks to Andrzej Zaborowski */
c596defd 1067 tcg_out32 (s, bc | (val & 0xfffc));
2662e13f
FB		 1068 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1069 }
1070}
1071
b0809bf7 1072static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
1073 const int *const_args)
c596defd 1074{
b0809bf7 1075 int cond = args[4], op;
c596defd 1076 struct { int bit1; int bit2; int cond2; } bits[] = {
1077 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1078 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1079 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1080 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1081 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1082 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1083 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1084 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1085 }, *b = &bits[cond];
1086
1087 switch (cond) {
2662e13f 1088 case TCG_COND_EQ:
2662e13f 1089 case TCG_COND_NE:
e924c485 1090 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1091 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1092 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1093 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
2662e13f
FB		 1094 break;
1095 case TCG_COND_LT:
2662e13f 1096 case TCG_COND_LE:
2662e13f 1097 case TCG_COND_GT:
2662e13f 1098 case TCG_COND_GE:
2662e13f 1099 case TCG_COND_LTU:
2662e13f 1100 case TCG_COND_LEU:
2662e13f 1101 case TCG_COND_GTU:
2662e13f 1102 case TCG_COND_GEU:
c596defd 1103 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1104 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1105 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1106 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1107 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1108 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
2662e13f
FB		 1109 break;
1110 default:
1111 tcg_abort();
1112 }
b0809bf7 1113}
1114
1115static void tcg_out_setcond (TCGContext *s, int cond, TCGArg arg0,
1116 TCGArg arg1, TCGArg arg2, int const_arg2)
1117{
1118 int crop, sh, arg;
1119
1120 switch (cond) {
1121 case TCG_COND_EQ:
1122 if (const_arg2) {
1123 if (!arg2) {
1124 arg = arg1;
1125 }
1126 else {
1127 arg = 0;
1128 if ((uint16_t) arg2 == arg2) {
1129 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1130 }
1131 else {
1132 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1133 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1134 }
1135 }
1136 }
1137 else {
1138 arg = 0;
1139 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1140 }
1141 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1142 tcg_out32 (s, (RLWINM
1143 | RA (arg0)
1144 | RS (0)
1145 | SH (27)
1146 | MB (5)
1147 | ME (31)
1148 )
1149 );
27a7797b 1150 break;
b0809bf7 1151
1152 case TCG_COND_NE:
1153 if (const_arg2) {
1154 if (!arg2) {
1155 arg = arg1;
1156 }
1157 else {
1158 arg = 0;
1159 if ((uint16_t) arg2 == arg2) {
1160 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1161 }
1162 else {
1163 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1164 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1165 }
1166 }
1167 }
1168 else {
1169 arg = 0;
1170 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1171 }
1172
1173 if (arg == arg1 && arg1 == arg0) {
1174 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1175 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1176 }
1177 else {
1178 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1179 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1180 }
27a7797b 1181 break;
1182
1183 case TCG_COND_GT:
1184 case TCG_COND_GTU:
1185 sh = 30;
1186 crop = 0;
1187 goto crtest;
b0809bf7 1188
b0809bf7 1189 case TCG_COND_LT:
27a7797b 1190 case TCG_COND_LTU:
b0809bf7 1191 sh = 29;
1192 crop = 0;
27a7797b 1193 goto crtest;
b0809bf7 1194
b0809bf7 1195 case TCG_COND_GE:
27a7797b 1196 case TCG_COND_GEU:
b0809bf7 1197 sh = 31;
1198 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
27a7797b 1199 goto crtest;
b0809bf7 1200
b0809bf7 1201 case TCG_COND_LE:
27a7797b 1202 case TCG_COND_LEU:
b0809bf7 1203 sh = 31;
1204 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
27a7797b 1205 crtest:
1206 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1207 if (crop) tcg_out32 (s, crop);
1208 tcg_out32 (s, MFCR | RT (0));
1209 tcg_out32 (s, (RLWINM
1210 | RA (arg0)
1211 | RS (0)
1212 | SH (sh)
1213 | MB (31)
1214 | ME (31)
1215 )
1216 );
b0809bf7 1217 break;
1218
1219 default:
1220 tcg_abort ();
1221 }
b0809bf7 1222}
1223
1224static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
1225 const int *const_args)
1226{
1227 tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
1228 tcg_out32 (s, MFCR | RT (0));
1229 tcg_out32 (s, (RLWINM
1230 | RA (args[0])
1231 | RS (0)
1232 | SH (31)
1233 | MB (31)
1234 | ME (31)
1235 )
1236 );
1237}
1238
1239static void tcg_out_brcond (TCGContext *s, int cond,
1240 TCGArg arg1, TCGArg arg2, int const_arg2,
1241 int label_index)
1242{
1243 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1244 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1245}
1246
1247/* XXX: we implement it at the target level to avoid having to
1248 handle cross basic blocks temporaries */
1249static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1250 const int *const_args)
1251{
1252 tcg_out_cr7eq_from_cond (s, args, const_args);
1253 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
2662e13f
FB		 1254}
1255
52781543 1256void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1257{
1258 uint32_t *ptr;
1259 long disp = addr - jmp_addr;
1260 unsigned long patch_size;
1261
1262 ptr = (uint32_t *)jmp_addr;
1263
1264 if ((disp << 6) >> 6 != disp) {
1265 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1266 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1267 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1268 ptr[3] = 0x4e800420; /* brctr */
1269 patch_size = 16;
1270 } else {
1271 /* patch the branch destination */
1272 if (disp != 16) {
1273 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1274 patch_size = 4;
1275 } else {
1276 ptr[0] = 0x60000000; /* nop */
1277 ptr[1] = 0x60000000;
1278 ptr[2] = 0x60000000;
1279 ptr[3] = 0x60000000;
1280 patch_size = 16;
1281 }
1282 }
1283 /* flush icache */
1284 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1285}
1286
2662e13f
FB		 1287static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1288 const int *const_args)
1289{
1290 switch (opc) {
1291 case INDEX_op_exit_tb:
1292 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
932a6909 1293 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
2662e13f
FB		 1294 break;
1295 case INDEX_op_goto_tb:
1296 if (s->tb_jmp_offset) {
1297 /* direct jump method */
932a6909 1298
2662e13f 1299 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
0a878c47 1300 s->code_ptr += 16;
932a6909
FB		 1301 }
1302 else {
2662e13f
FB		 1303 tcg_abort ();
1304 }
1305 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1306 break;
1307 case INDEX_op_br:
1308 {
1309 TCGLabel *l = &s->labels[args[0]];
1310
1311 if (l->has_value) {
932a6909 1312 tcg_out_b (s, 0, l->u.value);
2662e13f
FB		 1313 }
1314 else {
0a878c47 1315 uint32_t val = *(uint32_t *) s->code_ptr;
1316
1317 /* Thanks to Andrzej Zaborowski */
1318 tcg_out32 (s, B | (val & 0x3fffffc));
2662e13f
FB		 1319 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1320 }
1321 }
1322 break;
1323 case INDEX_op_call:
b29fe3ed 1324 tcg_out_call (s, args[0], const_args[0]);
2662e13f
FB		 1325 break;
1326 case INDEX_op_jmp:
1327 if (const_args[0]) {
932a6909 1328 tcg_out_b (s, 0, args[0]);
2662e13f
FB		 1329 }
1330 else {
1331 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1332 tcg_out32 (s, BCCTR | BO_ALWAYS);
1333 }
1334 break;
1335 case INDEX_op_movi_i32:
1336 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1337 break;
1338 case INDEX_op_ld8u_i32:
1339 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1340 break;
1341 case INDEX_op_ld8s_i32:
1342 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1343 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1344 break;
1345 case INDEX_op_ld16u_i32:
1346 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1347 break;
1348 case INDEX_op_ld16s_i32:
1349 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1350 break;
1351 case INDEX_op_ld_i32:
1352 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1353 break;
1354 case INDEX_op_st8_i32:
1355 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1356 break;
1357 case INDEX_op_st16_i32:
1358 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1359 break;
1360 case INDEX_op_st_i32:
1361 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1362 break;
1363
1364 case INDEX_op_add_i32:
1365 if (const_args[2])
1366 ppc_addi (s, args[0], args[1], args[2]);
1367 else
1368 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1369 break;
1370 case INDEX_op_sub_i32:
1371 if (const_args[2])
1372 ppc_addi (s, args[0], args[1], -args[2]);
1373 else
1374 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1375 break;
1376
1377 case INDEX_op_and_i32:
1378 if (const_args[2]) {
c45851c4 1379 uint32_t c;
1380
1381 c = args[2];
1382
1383 if (!c) {
1384 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1385 break;
1386 }
1387#ifdef __PPU__
1388 uint32_t t, n;
1389 int mb, me;
1390
1391 n = c ^ -(c & 1);
1392 t = n + (n & -n);
1393
1394 if ((t & (t - 1)) == 0) {
1395 int lzc, tzc;
1396
1397 if ((c & 0x80000001) == 0x80000001) {
1398 lzc = clz32 (n);
1399 tzc = ctz32 (n);
1400
1401 mb = 32 - tzc;
1402 me = lzc - 1;
1403 }
1404 else {
1405 lzc = clz32 (c);
1406 tzc = ctz32 (c);
1407
1408 mb = lzc;
1409 me = 31 - tzc;
1410 }
1411
1412 tcg_out32 (s, (RLWINM
1413 | RA (args[0])
1414 | RS (args[1])
1415 | SH (0)
1416 | MB (mb)
1417 | ME (me)
1418 )
1419 );
1420 }
1421 else
1422#endif /* !__PPU__ */
1423 {
1424 if ((c & 0xffff) == c)
1425 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1426 else if ((c & 0xffff0000) == c)
1427 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1428 | ((c >> 16) & 0xffff));
1429 else {
1430 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1431 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1432 }
2662e13f
FB		 1433 }
1434 }
1435 else
1436 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1437 break;
1438 case INDEX_op_or_i32:
1439 if (const_args[2]) {
000a2d86 1440 if (args[2] & 0xffff) {
1441 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1442 | (args[2] & 0xffff));
1443 if (args[2] >> 16)
1444 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
2662e13f 1445 | ((args[2] >> 16) & 0xffff));
2662e13f
FB		 1446 }
1447 else {
000a2d86 1448 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1449 | ((args[2] >> 16) & 0xffff));
2662e13f
FB		 1450 }
1451 }
1452 else
1453 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1454 break;
1455 case INDEX_op_xor_i32:
1456 if (const_args[2]) {
000a2d86 1457 if ((args[2] & 0xffff) == args[2])
1458 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1459 | (args[2] & 0xffff));
1460 else if ((args[2] & 0xffff0000) == args[2])
1461 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1462 | ((args[2] >> 16) & 0xffff));
2662e13f 1463 else {
000a2d86 1464 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1465 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
2662e13f
FB		 1466 }
1467 }
1468 else
1469 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1470 break;
1471
1472 case INDEX_op_mul_i32:
1473 if (const_args[2]) {
1474 if (args[2] == (int16_t) args[2])
1475 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1476 | (args[2] & 0xffff));
1477 else {
1478 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1479 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1480 }
1481 }
1482 else
1483 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1484 break;
77b73de6 1485
1486 case INDEX_op_div_i32:
1487 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1488 break;
1489
1490 case INDEX_op_divu_i32:
1491 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1492 break;
1493
1494 case INDEX_op_rem_i32:
1495 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1496 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1497 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1498 break;
1499
1500 case INDEX_op_remu_i32:
1501 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1502 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1503 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1504 break;
1505
2662e13f
FB		 1506 case INDEX_op_mulu2_i32:
1507 if (args[0] == args[2] || args[0] == args[3]) {
1508 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1509 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1510 tcg_out_mov (s, args[0], 0);
1511 }
1512 else {
1513 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1514 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1515 }
1516 break;
2662e13f
FB		 1517
1518 case INDEX_op_shl_i32:
1519 if (const_args[2]) {
000a2d86 1520 tcg_out32 (s, (RLWINM
1521 | RA (args[0])
1522 | RS (args[1])
1523 | SH (args[2])
1524 | MB (0)
1525 | ME (31 - args[2])
1526 )
1527 );
2662e13f
FB		 1528 }
1529 else
1530 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1531 break;
1532 case INDEX_op_shr_i32:
1533 if (const_args[2]) {
000a2d86 1534 tcg_out32 (s, (RLWINM
1535 | RA (args[0])
1536 | RS (args[1])
1537 | SH (32 - args[2])
1538 | MB (args[2])
1539 | ME (31)
1540 )
1541 );
2662e13f
FB		 1542 }
1543 else
1544 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1545 break;
1546 case INDEX_op_sar_i32:
1547 if (const_args[2])
1548 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1549 else
1550 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1551 break;
1552
1553 case INDEX_op_add2_i32:
1554 if (args[0] == args[3] || args[0] == args[5]) {
1555 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1556 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1557 tcg_out_mov (s, args[0], 0);
1558 }
1559 else {
1560 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1561 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1562 }
1563 break;
1564 case INDEX_op_sub2_i32:
1565 if (args[0] == args[3] || args[0] == args[5]) {
1566 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1567 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1568 tcg_out_mov (s, args[0], 0);
1569 }
1570 else {
1571 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1572 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1573 }
1574 break;
1575
1576 case INDEX_op_brcond_i32:
1577 /*
1578 args[0] = r0
1579 args[1] = r1
1580 args[2] = cond
1581 args[3] = r1 is const
1582 args[4] = label_index
1583 */
1584 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1585 break;
1586 case INDEX_op_brcond2_i32:
1587 tcg_out_brcond2(s, args, const_args);
1588 break;
1589
1590 case INDEX_op_neg_i32:
1591 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1592 break;
1593
1594 case INDEX_op_qemu_ld8u:
1595 tcg_out_qemu_ld(s, args, 0);
1596 break;
1597 case INDEX_op_qemu_ld8s:
1598 tcg_out_qemu_ld(s, args, 0 | 4);
1599 break;
1600 case INDEX_op_qemu_ld16u:
1601 tcg_out_qemu_ld(s, args, 1);
1602 break;
1603 case INDEX_op_qemu_ld16s:
1604 tcg_out_qemu_ld(s, args, 1 | 4);
1605 break;
1606 case INDEX_op_qemu_ld32u:
1607 tcg_out_qemu_ld(s, args, 2);
1608 break;
1609 case INDEX_op_qemu_ld64:
1610 tcg_out_qemu_ld(s, args, 3);
1611 break;
1612 case INDEX_op_qemu_st8:
1613 tcg_out_qemu_st(s, args, 0);
1614 break;
1615 case INDEX_op_qemu_st16:
1616 tcg_out_qemu_st(s, args, 1);
1617 break;
1618 case INDEX_op_qemu_st32:
1619 tcg_out_qemu_st(s, args, 2);
1620 break;
1621 case INDEX_op_qemu_st64:
1622 tcg_out_qemu_st(s, args, 3);
1623 break;
1624
e46b9681 1625 case INDEX_op_ext8s_i32:
1626 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1627 break;
1628 case INDEX_op_ext16s_i32:
1629 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1630 break;
1631
b0809bf7 1632 case INDEX_op_setcond_i32:
1633 tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
1634 break;
1635 case INDEX_op_setcond2_i32:
1636 tcg_out_setcond2 (s, args, const_args);
1637 break;
1638
2662e13f
FB		 1639 default:
1640 tcg_dump_ops (s, stderr);
1641 tcg_abort ();
1642 }
1643}
1644
1645static const TCGTargetOpDef ppc_op_defs[] = {
1646 { INDEX_op_exit_tb, { } },
1647 { INDEX_op_goto_tb, { } },
932a6909
FB		 1648 { INDEX_op_call, { "ri" } },
1649 { INDEX_op_jmp, { "ri" } },
2662e13f
FB		 1650 { INDEX_op_br, { } },
1651
1652 { INDEX_op_mov_i32, { "r", "r" } },
1653 { INDEX_op_movi_i32, { "r" } },
1654 { INDEX_op_ld8u_i32, { "r", "r" } },
1655 { INDEX_op_ld8s_i32, { "r", "r" } },
1656 { INDEX_op_ld16u_i32, { "r", "r" } },
1657 { INDEX_op_ld16s_i32, { "r", "r" } },
1658 { INDEX_op_ld_i32, { "r", "r" } },
1659 { INDEX_op_st8_i32, { "r", "r" } },
1660 { INDEX_op_st16_i32, { "r", "r" } },
1661 { INDEX_op_st_i32, { "r", "r" } },
1662
1663 { INDEX_op_add_i32, { "r", "r", "ri" } },
1664 { INDEX_op_mul_i32, { "r", "r", "ri" } },
77b73de6 1665 { INDEX_op_div_i32, { "r", "r", "r" } },
1666 { INDEX_op_divu_i32, { "r", "r", "r" } },
1667 { INDEX_op_rem_i32, { "r", "r", "r" } },
1668 { INDEX_op_remu_i32, { "r", "r", "r" } },
2662e13f 1669 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
2662e13f
FB		 1670 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1671 { INDEX_op_and_i32, { "r", "r", "ri" } },
1672 { INDEX_op_or_i32, { "r", "r", "ri" } },
1673 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1674
1675 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1676 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1677 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1678
1679 { INDEX_op_brcond_i32, { "r", "ri" } },
1680
1681 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1682 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1683 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1684
1685 { INDEX_op_neg_i32, { "r", "r" } },
1686
b0809bf7 1687 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1688 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
1689
2662e13f
FB		 1690#if TARGET_LONG_BITS == 32
1691 { INDEX_op_qemu_ld8u, { "r", "L" } },
1692 { INDEX_op_qemu_ld8s, { "r", "L" } },
1693 { INDEX_op_qemu_ld16u, { "r", "L" } },
1694 { INDEX_op_qemu_ld16s, { "r", "L" } },
1695 { INDEX_op_qemu_ld32u, { "r", "L" } },
2662e13f
FB		 1696 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1697
1698 { INDEX_op_qemu_st8, { "K", "K" } },
1699 { INDEX_op_qemu_st16, { "K", "K" } },
1700 { INDEX_op_qemu_st32, { "K", "K" } },
1701 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1702#else
1703 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1704 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1705 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1706 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1707 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
2662e13f
FB		 1708 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1709
1710 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1711 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1712 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1713 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1714#endif
1715
e46b9681 1716 { INDEX_op_ext8s_i32, { "r", "r" } },
1717 { INDEX_op_ext16s_i32, { "r", "r" } },
1718
2662e13f
FB		 1719 { -1 },
1720};
1721
1722void tcg_target_init(TCGContext *s)
1723{
1724 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1725 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1726 (1 << TCG_REG_R0) |
6ec85236 1727#ifdef _CALL_DARWIN
f9bf2987 1728 (1 << TCG_REG_R2) |
1729#endif
2662e13f
FB		 1730 (1 << TCG_REG_R3) |
1731 (1 << TCG_REG_R4) |
1732 (1 << TCG_REG_R5) |
1733 (1 << TCG_REG_R6) |
1734 (1 << TCG_REG_R7) |
1735 (1 << TCG_REG_R8) |
1736 (1 << TCG_REG_R9) |
1737 (1 << TCG_REG_R10) |
1738 (1 << TCG_REG_R11) |
1739 (1 << TCG_REG_R12)
1740 );
1741
1742 tcg_regset_clear(s->reserved_regs);
1743 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1744 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
6ec85236 1745#ifndef _CALL_DARWIN
2662e13f 1746 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
f9bf2987 1747#endif
6ec85236 1748#ifdef _CALL_SYSV
5db3ee79 1749 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1750#endif
f6548c0a 1751#ifdef CONFIG_USE_GUEST_BASE
1752 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1753#endif
2662e13f
FB		 1754
1755 tcg_add_target_add_op_defs(ppc_op_defs);
1756}
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