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tcg: implement real ext_i32_i64 and extu_i32_i64 ops
[mirror_qemu.git] / tcg / ppc / tcg-target.c
CommitLineData
810260a8 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
9ecefc84
RH		 25#include "tcg-be-ldst.h"
26
ffcfbece
RH		 27#if defined _CALL_DARWIN || defined __APPLE__
28#define TCG_TARGET_CALL_DARWIN
29#endif
7f25c469
RH		 30#ifdef _CALL_SYSV
31# define TCG_TARGET_CALL_ALIGN_ARGS 1
32#endif
ffcfbece 33
dfca1778
RH		 34/* For some memory operations, we need a scratch that isn't R0. For the AIX
35 calling convention, we can re-use the TOC register since we'll be reloading
36 it at every call. Otherwise R12 will do nicely as neither a call-saved
37 register nor a parameter register. */
38#ifdef _CALL_AIX
39# define TCG_REG_TMP1 TCG_REG_R2
40#else
41# define TCG_REG_TMP1 TCG_REG_R12
42#endif
43
a84ac4cb
RH		 44/* For the 64-bit target, we don't like the 5 insn sequence needed to build
45 full 64-bit addresses. Better to have a base register to which we can
46 apply a 32-bit displacement.
47
48 There are generally three items of interest:
49 (1) helper functions in the main executable,
50 (2) TranslationBlock data structures,
51 (3) the return address in the epilogue.
52
53 For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer
54 will be inside the main executable, and thus near enough to make a
55 pointer to the epilogue be within 2GB of all helper functions.
56
57 For softmmu, we'll let the kernel choose the address of code_gen_buffer,
58 and odds are it'll be somewhere close to the main malloc arena, and so
59 a pointer to the epilogue will be within 2GB of the TranslationBlocks.
60
61 For --enable-pie, everything will be kinda near everything else,
62 somewhere in high memory.
63
64 Thus we choose to keep the return address in a call-saved register. */
65#define TCG_REG_RA TCG_REG_R31
66#define USE_REG_RA (TCG_TARGET_REG_BITS == 64)
67
de3d636d
RH		 68/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
69#define SZP ((int)sizeof(void *))
70
4c3831a0
RH		 71/* Shorthand for size of a register. */
72#define SZR (TCG_TARGET_REG_BITS / 8)
73
3d582c61
RH		 74#define TCG_CT_CONST_S16 0x100
75#define TCG_CT_CONST_U16 0x200
76#define TCG_CT_CONST_S32 0x400
77#define TCG_CT_CONST_U32 0x800
78#define TCG_CT_CONST_ZERO 0x1000
6c858762 79#define TCG_CT_CONST_MONE 0x2000
fe6f943f 80
e083c4a2 81static tcg_insn_unit *tb_ret_addr;
810260a8 82
f6548c0a 83#ifndef GUEST_BASE
84#define GUEST_BASE 0
85#endif
86
cd629de1 87#include "elf.h"
1e6e9aca
RH		 88static bool have_isa_2_06;
89#define HAVE_ISA_2_06 have_isa_2_06
90#define HAVE_ISEL have_isa_2_06
49d9870a 91
f6548c0a 92#ifdef CONFIG_USE_GUEST_BASE
93#define TCG_GUEST_BASE_REG 30
94#else
95#define TCG_GUEST_BASE_REG 0
96#endif
97
d4a9eb1f 98#ifndef NDEBUG
810260a8 99static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
100 "r0",
101 "r1",
98926b0a 102 "r2",
810260a8 103 "r3",
104 "r4",
105 "r5",
106 "r6",
107 "r7",
108 "r8",
109 "r9",
110 "r10",
111 "r11",
112 "r12",
113 "r13",
114 "r14",
115 "r15",
116 "r16",
117 "r17",
118 "r18",
119 "r19",
120 "r20",
121 "r21",
122 "r22",
123 "r23",
124 "r24",
125 "r25",
126 "r26",
127 "r27",
128 "r28",
129 "r29",
130 "r30",
131 "r31"
132};
d4a9eb1f 133#endif
810260a8 134
135static const int tcg_target_reg_alloc_order[] = {
5e1702b0 136 TCG_REG_R14, /* call saved registers */
810260a8 137 TCG_REG_R15,
138 TCG_REG_R16,
139 TCG_REG_R17,
140 TCG_REG_R18,
141 TCG_REG_R19,
142 TCG_REG_R20,
143 TCG_REG_R21,
144 TCG_REG_R22,
145 TCG_REG_R23,
5e1702b0
RH		 146 TCG_REG_R24,
147 TCG_REG_R25,
148 TCG_REG_R26,
149 TCG_REG_R27,
810260a8 150 TCG_REG_R28,
151 TCG_REG_R29,
152 TCG_REG_R30,
153 TCG_REG_R31,
5e1702b0
RH		 154 TCG_REG_R12, /* call clobbered, non-arguments */
155 TCG_REG_R11,
dfca1778
RH		 156 TCG_REG_R2,
157 TCG_REG_R13,
5e1702b0 158 TCG_REG_R10, /* call clobbered, arguments */
810260a8 159 TCG_REG_R9,
5e1702b0
RH		 160 TCG_REG_R8,
161 TCG_REG_R7,
162 TCG_REG_R6,
163 TCG_REG_R5,
164 TCG_REG_R4,
165 TCG_REG_R3,
810260a8 166};
167
168static const int tcg_target_call_iarg_regs[] = {
169 TCG_REG_R3,
170 TCG_REG_R4,
171 TCG_REG_R5,
172 TCG_REG_R6,
173 TCG_REG_R7,
174 TCG_REG_R8,
175 TCG_REG_R9,
176 TCG_REG_R10
177};
178
be9c4183 179static const int tcg_target_call_oarg_regs[] = {
dfca1778
RH		 180 TCG_REG_R3,
181 TCG_REG_R4
810260a8 182};
183
184static const int tcg_target_callee_save_regs[] = {
dfca1778 185#ifdef TCG_TARGET_CALL_DARWIN
5d7ff5bb
AF		 186 TCG_REG_R11,
187#endif
810260a8 188 TCG_REG_R14,
189 TCG_REG_R15,
190 TCG_REG_R16,
191 TCG_REG_R17,
192 TCG_REG_R18,
193 TCG_REG_R19,
194 TCG_REG_R20,
195 TCG_REG_R21,
196 TCG_REG_R22,
197 TCG_REG_R23,
095271d4 198 TCG_REG_R24,
199 TCG_REG_R25,
200 TCG_REG_R26,
cea5f9a2 201 TCG_REG_R27, /* currently used for the global env */
810260a8 202 TCG_REG_R28,
203 TCG_REG_R29,
204 TCG_REG_R30,
205 TCG_REG_R31
206};
207
b0940da0
RH		 208static inline bool in_range_b(tcg_target_long target)
209{
210 return target == sextract64(target, 0, 26);
211}
212
e083c4a2 213static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 214{
e083c4a2 215 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
b0940da0 216 assert(in_range_b(disp));
810260a8 217 return disp & 0x3fffffc;
218}
219
e083c4a2 220static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 221{
e083c4a2 222 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
810260a8 223}
224
e083c4a2 225static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 226{
e083c4a2
RH		 227 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
228 assert(disp == (int16_t) disp);
810260a8 229 return disp & 0xfffc;
230}
231
e083c4a2 232static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 233{
e083c4a2 234 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
810260a8 235}
236
c7ca6a2b
RH		 237static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
238{
e083c4a2 239 unsigned retrans = *s->code_ptr & 0x3fffffc;
c7ca6a2b
RH		 240 tcg_out32(s, insn | retrans);
241}
242
243static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
244{
e083c4a2 245 unsigned retrans = *s->code_ptr & 0xfffc;
c7ca6a2b
RH		 246 tcg_out32(s, insn | retrans);
247}
248
e083c4a2 249static void patch_reloc(tcg_insn_unit *code_ptr, int type,
541dd4ce 250 intptr_t value, intptr_t addend)
810260a8 251{
e083c4a2
RH		 252 tcg_insn_unit *target = (tcg_insn_unit *)value;
253
254 assert(addend == 0);
810260a8 255 switch (type) {
256 case R_PPC_REL14:
e083c4a2 257 reloc_pc14(code_ptr, target);
810260a8 258 break;
259 case R_PPC_REL24:
e083c4a2 260 reloc_pc24(code_ptr, target);
810260a8 261 break;
262 default:
541dd4ce 263 tcg_abort();
810260a8 264 }
265}
266
810260a8 267/* parse target specific constraints */
541dd4ce 268static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
810260a8 269{
270 const char *ct_str;
271
272 ct_str = *pct_str;
273 switch (ct_str[0]) {
274 case 'A': case 'B': case 'C': case 'D':
275 ct->ct |= TCG_CT_REG;
541dd4ce 276 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
810260a8 277 break;
278 case 'r':
279 ct->ct |= TCG_CT_REG;
541dd4ce 280 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
810260a8 281 break;
282 case 'L': /* qemu_ld constraint */
283 ct->ct |= TCG_CT_REG;
541dd4ce
RH		 284 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
285 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 286#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 287 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
288 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
735ee40d 289#endif
810260a8 290 break;
c070355d 291 case 'S': /* qemu_st constraint */
810260a8 292 ct->ct |= TCG_CT_REG;
541dd4ce
RH		 293 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
294 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 295#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 296 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
297 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
298 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
735ee40d 299#endif
810260a8 300 break;
3d582c61
RH		 301 case 'I':
302 ct->ct |= TCG_CT_CONST_S16;
303 break;
304 case 'J':
305 ct->ct |= TCG_CT_CONST_U16;
306 break;
6c858762
RH		 307 case 'M':
308 ct->ct |= TCG_CT_CONST_MONE;
309 break;
3d582c61
RH		 310 case 'T':
311 ct->ct |= TCG_CT_CONST_S32;
312 break;
313 case 'U':
fe6f943f 314 ct->ct |= TCG_CT_CONST_U32;
315 break;
3d582c61
RH		 316 case 'Z':
317 ct->ct |= TCG_CT_CONST_ZERO;
318 break;
810260a8 319 default:
320 return -1;
321 }
322 ct_str++;
323 *pct_str = ct_str;
324 return 0;
325}
326
327/* test if a constant matches the constraint */
f6c6afc1 328static int tcg_target_const_match(tcg_target_long val, TCGType type,
541dd4ce 329 const TCGArgConstraint *arg_ct)
810260a8 330{
3d582c61
RH		 331 int ct = arg_ct->ct;
332 if (ct & TCG_CT_CONST) {
333 return 1;
1194dcba
RH		 334 }
335
336 /* The only 32-bit constraint we use aside from
337 TCG_CT_CONST is TCG_CT_CONST_S16. */
338 if (type == TCG_TYPE_I32) {
339 val = (int32_t)val;
340 }
341
342 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
3d582c61
RH		 343 return 1;
344 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
810260a8 345 return 1;
3d582c61 346 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
fe6f943f 347 return 1;
3d582c61
RH		 348 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
349 return 1;
350 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
351 return 1;
6c858762
RH		 352 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
353 return 1;
3d582c61 354 }
810260a8 355 return 0;
356}
357
358#define OPCD(opc) ((opc)<<26)
359#define XO19(opc) (OPCD(19)|((opc)<<1))
8a94cfb0
AB		 360#define MD30(opc) (OPCD(30)|((opc)<<2))
361#define MDS30(opc) (OPCD(30)|((opc)<<1))
810260a8 362#define XO31(opc) (OPCD(31)|((opc)<<1))
363#define XO58(opc) (OPCD(58)|(opc))
364#define XO62(opc) (OPCD(62)|(opc))
365
366#define B OPCD( 18)
367#define BC OPCD( 16)
368#define LBZ OPCD( 34)
369#define LHZ OPCD( 40)
370#define LHA OPCD( 42)
371#define LWZ OPCD( 32)
372#define STB OPCD( 38)
373#define STH OPCD( 44)
374#define STW OPCD( 36)
375
376#define STD XO62( 0)
377#define STDU XO62( 1)
378#define STDX XO31(149)
379
380#define LD XO58( 0)
381#define LDX XO31( 21)
382#define LDU XO58( 1)
301f6d90 383#define LWA XO58( 2)
810260a8 384#define LWAX XO31(341)
385
1cd62ae9 386#define ADDIC OPCD( 12)
810260a8 387#define ADDI OPCD( 14)
388#define ADDIS OPCD( 15)
389#define ORI OPCD( 24)
390#define ORIS OPCD( 25)
391#define XORI OPCD( 26)
392#define XORIS OPCD( 27)
393#define ANDI OPCD( 28)
394#define ANDIS OPCD( 29)
395#define MULLI OPCD( 7)
396#define CMPLI OPCD( 10)
397#define CMPI OPCD( 11)
148bdd23 398#define SUBFIC OPCD( 8)
810260a8 399
400#define LWZU OPCD( 33)
401#define STWU OPCD( 37)
402
313d91c7 403#define RLWIMI OPCD( 20)
810260a8 404#define RLWINM OPCD( 21)
313d91c7 405#define RLWNM OPCD( 23)
810260a8 406
8a94cfb0
AB		 407#define RLDICL MD30( 0)
408#define RLDICR MD30( 1)
409#define RLDIMI MD30( 3)
410#define RLDCL MDS30( 8)
810260a8 411
412#define BCLR XO19( 16)
413#define BCCTR XO19(528)
414#define CRAND XO19(257)
415#define CRANDC XO19(129)
416#define CRNAND XO19(225)
417#define CROR XO19(449)
1cd62ae9 418#define CRNOR XO19( 33)
810260a8 419
420#define EXTSB XO31(954)
421#define EXTSH XO31(922)
422#define EXTSW XO31(986)
423#define ADD XO31(266)
424#define ADDE XO31(138)
6c858762
RH		 425#define ADDME XO31(234)
426#define ADDZE XO31(202)
810260a8 427#define ADDC XO31( 10)
428#define AND XO31( 28)
429#define SUBF XO31( 40)
430#define SUBFC XO31( 8)
431#define SUBFE XO31(136)
6c858762
RH		 432#define SUBFME XO31(232)
433#define SUBFZE XO31(200)
810260a8 434#define OR XO31(444)
435#define XOR XO31(316)
436#define MULLW XO31(235)
8fa391a0 437#define MULHW XO31( 75)
810260a8 438#define MULHWU XO31( 11)
439#define DIVW XO31(491)
440#define DIVWU XO31(459)
441#define CMP XO31( 0)
442#define CMPL XO31( 32)
443#define LHBRX XO31(790)
444#define LWBRX XO31(534)
49d9870a 445#define LDBRX XO31(532)
810260a8 446#define STHBRX XO31(918)
447#define STWBRX XO31(662)
49d9870a 448#define STDBRX XO31(660)
810260a8 449#define MFSPR XO31(339)
450#define MTSPR XO31(467)
451#define SRAWI XO31(824)
452#define NEG XO31(104)
1cd62ae9 453#define MFCR XO31( 19)
6995a4a0 454#define MFOCRF (MFCR | (1u << 20))
157f2662 455#define NOR XO31(124)
1cd62ae9 456#define CNTLZW XO31( 26)
457#define CNTLZD XO31( 58)
ce1010d6
RH		 458#define ANDC XO31( 60)
459#define ORC XO31(412)
460#define EQV XO31(284)
461#define NAND XO31(476)
70fac59a 462#define ISEL XO31( 15)
810260a8 463
464#define MULLD XO31(233)
465#define MULHD XO31( 73)
466#define MULHDU XO31( 9)
467#define DIVD XO31(489)
468#define DIVDU XO31(457)
469
470#define LBZX XO31( 87)
4f4a67ae 471#define LHZX XO31(279)
810260a8 472#define LHAX XO31(343)
473#define LWZX XO31( 23)
474#define STBX XO31(215)
475#define STHX XO31(407)
476#define STWX XO31(151)
477
541dd4ce 478#define SPR(a, b) ((((a)<<5)|(b))<<11)
810260a8 479#define LR SPR(8, 0)
480#define CTR SPR(9, 0)
481
482#define SLW XO31( 24)
483#define SRW XO31(536)
484#define SRAW XO31(792)
485
486#define SLD XO31( 27)
487#define SRD XO31(539)
488#define SRAD XO31(794)
fe6f943f 489#define SRADI XO31(413<<1)
810260a8 490
810260a8 491#define TW XO31( 4)
541dd4ce 492#define TRAP (TW | TO(31))
810260a8 493
a84ac4cb
RH		 494#define NOP ORI /* ori 0,0,0 */
495
810260a8 496#define RT(r) ((r)<<21)
497#define RS(r) ((r)<<21)
498#define RA(r) ((r)<<16)
499#define RB(r) ((r)<<11)
500#define TO(t) ((t)<<21)
501#define SH(s) ((s)<<11)
502#define MB(b) ((b)<<6)
503#define ME(e) ((e)<<1)
504#define BO(o) ((o)<<21)
505#define MB64(b) ((b)<<5)
6995a4a0 506#define FXM(b) (1 << (19 - (b)))
810260a8 507
508#define LK 1
509
2fd8eddc
RH		 510#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
511#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
512#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
513#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
810260a8 514
515#define BF(n) ((n)<<23)
516#define BI(n, c) (((c)+((n)*4))<<16)
517#define BT(n, c) (((c)+((n)*4))<<21)
518#define BA(n, c) (((c)+((n)*4))<<16)
519#define BB(n, c) (((c)+((n)*4))<<11)
70fac59a 520#define BC_(n, c) (((c)+((n)*4))<<6)
810260a8 521
541dd4ce
RH		 522#define BO_COND_TRUE BO(12)
523#define BO_COND_FALSE BO( 4)
524#define BO_ALWAYS BO(20)
810260a8 525
526enum {
527 CR_LT,
528 CR_GT,
529 CR_EQ,
530 CR_SO
531};
532
0aed257f 533static const uint32_t tcg_to_bc[] = {
541dd4ce
RH		 534 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
535 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
536 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
537 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
538 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
539 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
540 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
541 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
542 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
543 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
810260a8 544};
545
70fac59a
RH		 546/* The low bit here is set if the RA and RB fields must be inverted. */
547static const uint32_t tcg_to_isel[] = {
548 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
549 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
550 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
551 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
552 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
553 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
554 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
555 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
556 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
557 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
558};
559
a84ac4cb
RH		 560static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
561 TCGReg base, tcg_target_long offset);
562
796f1a68 563static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
810260a8 564{
796f1a68 565 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
f8b84129
RH		 566 if (ret != arg) {
567 tcg_out32(s, OR | SAB(arg, ret, arg));
568 }
810260a8 569}
570
aceac8d6
RH		 571static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
572 int sh, int mb)
810260a8 573{
a757e1ee 574 assert(TCG_TARGET_REG_BITS == 64);
541dd4ce
RH		 575 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
576 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
577 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
810260a8 578}
579
9e555b73
RH		 580static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
581 int sh, int mb, int me)
582{
583 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
584}
585
6e5e0602
RH		 586static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
587{
588 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
589}
590
a757e1ee
RH		 591static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
592{
593 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
594}
595
0a9564b9
RH		 596static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
597{
598 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
599}
600
a757e1ee
RH		 601static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
602{
603 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
604}
605
5e916c28
RH		 606static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
607{
608 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
609}
610
aceac8d6 611static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
810260a8 612{
2fd8eddc
RH		 613 if (arg == (int16_t) arg) {
614 tcg_out32(s, ADDI | TAI(ret, 0, arg));
615 } else {
616 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
617 if (arg & 0xffff) {
618 tcg_out32(s, ORI | SAI(ret, ret, arg));
619 }
810260a8 620 }
621}
622
421233a1
RH		 623static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
624 tcg_target_long arg)
810260a8 625{
796f1a68 626 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
421233a1
RH		 627 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
628 tcg_out_movi32(s, ret, arg);
629 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
630 tcg_out32(s, ADDI | TAI(ret, 0, arg));
631 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
632 } else {
a84ac4cb
RH		 633 int32_t high;
634
635 if (USE_REG_RA) {
636 intptr_t diff = arg - (intptr_t)tb_ret_addr;
637 if (diff == (int32_t)diff) {
638 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff);
639 return;
640 }
641 }
642
643 high = arg >> 31 >> 1;
421233a1
RH		 644 tcg_out_movi32(s, ret, high);
645 if (high) {
0a9564b9 646 tcg_out_shli64(s, ret, ret, 32);
421233a1
RH		 647 }
648 if (arg & 0xffff0000) {
649 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
650 }
651 if (arg & 0xffff) {
652 tcg_out32(s, ORI | SAI(ret, ret, arg));
810260a8 653 }
654 }
655}
656
637af30c 657static bool mask_operand(uint32_t c, int *mb, int *me)
a9249dff
RH		 658{
659 uint32_t lsb, test;
660
661 /* Accept a bit pattern like:
662 0....01....1
663 1....10....0
664 0..01..10..0
665 Keep track of the transitions. */
666 if (c == 0 || c == -1) {
667 return false;
668 }
669 test = c;
670 lsb = test & -test;
671 test += lsb;
672 if (test & (test - 1)) {
673 return false;
674 }
675
676 *me = clz32(lsb);
677 *mb = test ? clz32(test & -test) + 1 : 0;
678 return true;
679}
680
637af30c
RH		 681static bool mask64_operand(uint64_t c, int *mb, int *me)
682{
683 uint64_t lsb;
684
685 if (c == 0) {
686 return false;
687 }
688
689 lsb = c & -c;
690 /* Accept 1..10..0. */
691 if (c == -lsb) {
692 *mb = 0;
693 *me = clz64(lsb);
694 return true;
695 }
696 /* Accept 0..01..1. */
697 if (lsb == 1 && (c & (c + 1)) == 0) {
698 *mb = clz64(c + 1) + 1;
699 *me = 63;
700 return true;
701 }
702 return false;
703}
704
a9249dff
RH		 705static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
706{
707 int mb, me;
708
709 if ((c & 0xffff) == c) {
710 tcg_out32(s, ANDI | SAI(src, dst, c));
711 return;
712 } else if ((c & 0xffff0000) == c) {
713 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
714 return;
715 } else if (mask_operand(c, &mb, &me)) {
716 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
717 } else {
8327a470
RH		 718 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
719 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
a9249dff
RH		 720 }
721}
722
637af30c
RH		 723static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
724{
725 int mb, me;
726
a757e1ee 727 assert(TCG_TARGET_REG_BITS == 64);
637af30c
RH		 728 if ((c & 0xffff) == c) {
729 tcg_out32(s, ANDI | SAI(src, dst, c));
730 return;
731 } else if ((c & 0xffff0000) == c) {
732 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
733 return;
734 } else if (mask64_operand(c, &mb, &me)) {
735 if (mb == 0) {
736 tcg_out_rld(s, RLDICR, dst, src, 0, me);
737 } else {
738 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
739 }
740 } else {
8327a470
RH		 741 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
742 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
637af30c
RH		 743 }
744}
745
dce74c57
RH		 746static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
747 int op_lo, int op_hi)
748{
749 if (c >> 16) {
750 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
751 src = dst;
752 }
753 if (c & 0xffff) {
754 tcg_out32(s, op_lo | SAI(src, dst, c));
755 src = dst;
756 }
757}
758
759static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
760{
761 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
762}
763
764static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
765{
766 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
767}
768
e083c4a2 769static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
5d7ff5bb 770{
e083c4a2 771 ptrdiff_t disp = tcg_pcrel_diff(s, target);
b0940da0 772 if (in_range_b(disp)) {
541dd4ce
RH		 773 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
774 } else {
de3d636d 775 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
8327a470 776 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
541dd4ce 777 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
5d7ff5bb
AF		 778 }
779}
780
b18d5d2b
RH		 781static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
782 TCGReg base, tcg_target_long offset)
810260a8 783{
b18d5d2b 784 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
de7761a3 785 bool is_store = false;
dfca1778 786 TCGReg rs = TCG_REG_TMP1;
b18d5d2b 787
b18d5d2b
RH		 788 switch (opi) {
789 case LD: case LWA:
790 align = 3;
791 /* FALLTHRU */
792 default:
793 if (rt != TCG_REG_R0) {
794 rs = rt;
de7761a3 795 break;
b18d5d2b
RH		 796 }
797 break;
798 case STD:
799 align = 3;
de7761a3 800 /* FALLTHRU */
b18d5d2b 801 case STB: case STH: case STW:
de7761a3 802 is_store = true;
b18d5d2b 803 break;
810260a8 804 }
810260a8 805
b18d5d2b
RH		 806 /* For unaligned, or very large offsets, use the indexed form. */
807 if (offset & align || offset != (int32_t)offset) {
d4cba13b
RH		 808 if (rs == base) {
809 rs = TCG_REG_R0;
810 }
811 tcg_debug_assert(!is_store || rs != rt);
de7761a3
RH		 812 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
813 tcg_out32(s, opx | TAB(rt, base, rs));
b18d5d2b
RH		 814 return;
815 }
816
817 l0 = (int16_t)offset;
818 offset = (offset - l0) >> 16;
819 l1 = (int16_t)offset;
820
821 if (l1 < 0 && orig >= 0) {
822 extra = 0x4000;
823 l1 = (int16_t)(offset - 0x4000);
824 }
825 if (l1) {
826 tcg_out32(s, ADDIS | TAI(rs, base, l1));
827 base = rs;
828 }
829 if (extra) {
830 tcg_out32(s, ADDIS | TAI(rs, base, extra));
831 base = rs;
832 }
833 if (opi != ADDI || base != rt || l0 != 0) {
834 tcg_out32(s, opi | TAI(rt, base, l0));
828808f5 835 }
836}
837
d604f1a9
RH		 838static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
839 TCGReg arg1, intptr_t arg2)
840{
841 int opi, opx;
810260a8 842
a757e1ee 843 assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
d604f1a9
RH		 844 if (type == TCG_TYPE_I32) {
845 opi = LWZ, opx = LWZX;
846 } else {
847 opi = LD, opx = LDX;
848 }
849 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
850}
fedee3e7 851
d604f1a9
RH		 852static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
853 TCGReg arg1, intptr_t arg2)
810260a8 854{
d604f1a9 855 int opi, opx;
fedee3e7 856
a757e1ee 857 assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
d604f1a9
RH		 858 if (type == TCG_TYPE_I32) {
859 opi = STW, opx = STWX;
fedee3e7 860 } else {
d604f1a9 861 opi = STD, opx = STDX;
fedee3e7 862 }
d604f1a9
RH		 863 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
864}
810260a8 865
d604f1a9
RH		 866static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
867 int const_arg2, int cr, TCGType type)
868{
869 int imm;
870 uint32_t op;
810260a8 871
abcf61c4
RH		 872 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
873
d604f1a9
RH		 874 /* Simplify the comparisons below wrt CMPI. */
875 if (type == TCG_TYPE_I32) {
876 arg2 = (int32_t)arg2;
4a40e231 877 }
fedee3e7 878
d604f1a9
RH		 879 switch (cond) {
880 case TCG_COND_EQ:
881 case TCG_COND_NE:
882 if (const_arg2) {
883 if ((int16_t) arg2 == arg2) {
884 op = CMPI;
885 imm = 1;
886 break;
887 } else if ((uint16_t) arg2 == arg2) {
888 op = CMPLI;
889 imm = 1;
890 break;
891 }
892 }
893 op = CMPL;
894 imm = 0;
895 break;
fedee3e7 896
d604f1a9
RH		 897 case TCG_COND_LT:
898 case TCG_COND_GE:
899 case TCG_COND_LE:
900 case TCG_COND_GT:
901 if (const_arg2) {
902 if ((int16_t) arg2 == arg2) {
903 op = CMPI;
904 imm = 1;
905 break;
906 }
907 }
908 op = CMP;
909 imm = 0;
910 break;
fedee3e7 911
d604f1a9
RH		 912 case TCG_COND_LTU:
913 case TCG_COND_GEU:
914 case TCG_COND_LEU:
915 case TCG_COND_GTU:
916 if (const_arg2) {
917 if ((uint16_t) arg2 == arg2) {
918 op = CMPLI;
919 imm = 1;
920 break;
921 }
922 }
923 op = CMPL;
924 imm = 0;
925 break;
fedee3e7 926
d604f1a9
RH		 927 default:
928 tcg_abort();
fedee3e7 929 }
d604f1a9 930 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
fedee3e7 931
d604f1a9
RH		 932 if (imm) {
933 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
934 } else {
935 if (const_arg2) {
936 tcg_out_movi(s, type, TCG_REG_R0, arg2);
937 arg2 = TCG_REG_R0;
938 }
939 tcg_out32(s, op | RA(arg1) | RB(arg2));
940 }
810260a8 941}
942
d604f1a9
RH		 943static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
944 TCGReg dst, TCGReg src)
7f12d649 945{
a757e1ee
RH		 946 if (type == TCG_TYPE_I32) {
947 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
948 tcg_out_shri32(s, dst, dst, 5);
949 } else {
950 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
951 tcg_out_shri64(s, dst, dst, 6);
952 }
7f12d649
RH		 953}
954
d604f1a9 955static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
7f12d649 956{
d604f1a9
RH		 957 /* X != 0 implies X + -1 generates a carry. Extra addition
958 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
959 if (dst != src) {
960 tcg_out32(s, ADDIC | TAI(dst, src, -1));
961 tcg_out32(s, SUBFE | TAB(dst, dst, src));
7f12d649 962 } else {
d604f1a9
RH		 963 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
964 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
7f12d649 965 }
d604f1a9 966}
7f12d649 967
d604f1a9
RH		 968static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
969 bool const_arg2)
970{
971 if (const_arg2) {
972 if ((uint32_t)arg2 == arg2) {
973 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
974 } else {
975 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
976 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
977 }
978 } else {
979 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
980 }
981 return TCG_REG_R0;
7f12d649
RH		 982}
983
d604f1a9
RH		 984static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
985 TCGArg arg0, TCGArg arg1, TCGArg arg2,
986 int const_arg2)
7f12d649 987{
d604f1a9 988 int crop, sh;
7f12d649 989
a757e1ee
RH		 990 assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
991
d604f1a9
RH		 992 /* Ignore high bits of a potential constant arg2. */
993 if (type == TCG_TYPE_I32) {
994 arg2 = (uint32_t)arg2;
995 }
7f12d649 996
d604f1a9
RH		 997 /* Handle common and trivial cases before handling anything else. */
998 if (arg2 == 0) {
999 switch (cond) {
1000 case TCG_COND_EQ:
1001 tcg_out_setcond_eq0(s, type, arg0, arg1);
1002 return;
1003 case TCG_COND_NE:
a757e1ee 1004 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1005 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1006 arg1 = TCG_REG_R0;
1007 }
1008 tcg_out_setcond_ne0(s, arg0, arg1);
1009 return;
1010 case TCG_COND_GE:
1011 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1012 arg1 = arg0;
1013 /* FALLTHRU */
1014 case TCG_COND_LT:
1015 /* Extract the sign bit. */
a757e1ee
RH		 1016 if (type == TCG_TYPE_I32) {
1017 tcg_out_shri32(s, arg0, arg1, 31);
1018 } else {
1019 tcg_out_shri64(s, arg0, arg1, 63);
1020 }
d604f1a9
RH		 1021 return;
1022 default:
1023 break;
1024 }
1025 }
7f12d649 1026
d604f1a9
RH		 1027 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1028 All other cases below are also at least 3 insns, so speed up the
1029 code generator by not considering them and always using ISEL. */
1030 if (HAVE_ISEL) {
1031 int isel, tab;
7f12d649 1032
d604f1a9 1033 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
7f12d649 1034
d604f1a9 1035 isel = tcg_to_isel[cond];
7f12d649 1036
d604f1a9
RH		 1037 tcg_out_movi(s, type, arg0, 1);
1038 if (isel & 1) {
1039 /* arg0 = (bc ? 0 : 1) */
1040 tab = TAB(arg0, 0, arg0);
1041 isel &= ~1;
1042 } else {
1043 /* arg0 = (bc ? 1 : 0) */
1044 tcg_out_movi(s, type, TCG_REG_R0, 0);
1045 tab = TAB(arg0, arg0, TCG_REG_R0);
1046 }
1047 tcg_out32(s, isel | tab);
1048 return;
1049 }
49d9870a 1050
d604f1a9
RH		 1051 switch (cond) {
1052 case TCG_COND_EQ:
1053 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1054 tcg_out_setcond_eq0(s, type, arg0, arg1);
1055 return;
810260a8 1056
d604f1a9
RH		 1057 case TCG_COND_NE:
1058 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1059 /* Discard the high bits only once, rather than both inputs. */
a757e1ee 1060 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1061 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1062 arg1 = TCG_REG_R0;
1063 }
1064 tcg_out_setcond_ne0(s, arg0, arg1);
1065 return;
810260a8 1066
d604f1a9
RH		 1067 case TCG_COND_GT:
1068 case TCG_COND_GTU:
1069 sh = 30;
1070 crop = 0;
1071 goto crtest;
810260a8 1072
d604f1a9
RH		 1073 case TCG_COND_LT:
1074 case TCG_COND_LTU:
1075 sh = 29;
1076 crop = 0;
1077 goto crtest;
810260a8 1078
d604f1a9
RH		 1079 case TCG_COND_GE:
1080 case TCG_COND_GEU:
1081 sh = 31;
1082 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1083 goto crtest;
810260a8 1084
d604f1a9
RH		 1085 case TCG_COND_LE:
1086 case TCG_COND_LEU:
1087 sh = 31;
1088 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1089 crtest:
1090 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1091 if (crop) {
1092 tcg_out32(s, crop);
1093 }
1094 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1095 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1096 break;
1097
1098 default:
1099 tcg_abort();
1100 }
810260a8 1101}
1102
bec16311 1103static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
810260a8 1104{
d604f1a9
RH		 1105 if (l->has_value) {
1106 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
49d9870a 1107 } else {
bec16311 1108 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
d604f1a9 1109 tcg_out_bc_noaddr(s, bc);
810260a8 1110 }
810260a8 1111}
1112
d604f1a9
RH		 1113static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1114 TCGArg arg1, TCGArg arg2, int const_arg2,
bec16311 1115 TCGLabel *l, TCGType type)
810260a8 1116{
d604f1a9 1117 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
bec16311 1118 tcg_out_bc(s, tcg_to_bc[cond], l);
d604f1a9 1119}
fa94c3be 1120
d604f1a9
RH		 1121static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1122 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1123 TCGArg v2, bool const_c2)
1124{
1125 /* If for some reason both inputs are zero, don't produce bad code. */
1126 if (v1 == 0 && v2 == 0) {
1127 tcg_out_movi(s, type, dest, 0);
1128 return;
b9e946c7 1129 }
f6548c0a 1130
d604f1a9 1131 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
a69abbe0 1132
d604f1a9
RH		 1133 if (HAVE_ISEL) {
1134 int isel = tcg_to_isel[cond];
810260a8 1135
d604f1a9
RH		 1136 /* Swap the V operands if the operation indicates inversion. */
1137 if (isel & 1) {
1138 int t = v1;
1139 v1 = v2;
1140 v2 = t;
1141 isel &= ~1;
1142 }
1143 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1144 if (v2 == 0) {
1145 tcg_out_movi(s, type, TCG_REG_R0, 0);
1146 }
1147 tcg_out32(s, isel | TAB(dest, v1, v2));
1148 } else {
1149 if (dest == v2) {
1150 cond = tcg_invert_cond(cond);
1151 v2 = v1;
1152 } else if (dest != v1) {
1153 if (v1 == 0) {
1154 tcg_out_movi(s, type, dest, 0);
1155 } else {
1156 tcg_out_mov(s, type, dest, v1);
1157 }
1158 }
1159 /* Branch forward over one insn */
1160 tcg_out32(s, tcg_to_bc[cond] | 8);
1161 if (v2 == 0) {
1162 tcg_out_movi(s, type, dest, 0);
1163 } else {
1164 tcg_out_mov(s, type, dest, v2);
1165 }
29b69198 1166 }
810260a8 1167}
1168
abcf61c4
RH		 1169static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1170 const int *const_args)
1171{
1172 static const struct { uint8_t bit1, bit2; } bits[] = {
1173 [TCG_COND_LT ] = { CR_LT, CR_LT },
1174 [TCG_COND_LE ] = { CR_LT, CR_GT },
1175 [TCG_COND_GT ] = { CR_GT, CR_GT },
1176 [TCG_COND_GE ] = { CR_GT, CR_LT },
1177 [TCG_COND_LTU] = { CR_LT, CR_LT },
1178 [TCG_COND_LEU] = { CR_LT, CR_GT },
1179 [TCG_COND_GTU] = { CR_GT, CR_GT },
1180 [TCG_COND_GEU] = { CR_GT, CR_LT },
1181 };
1182
1183 TCGCond cond = args[4], cond2;
1184 TCGArg al, ah, bl, bh;
1185 int blconst, bhconst;
1186 int op, bit1, bit2;
1187
1188 al = args[0];
1189 ah = args[1];
1190 bl = args[2];
1191 bh = args[3];
1192 blconst = const_args[2];
1193 bhconst = const_args[3];
1194
1195 switch (cond) {
1196 case TCG_COND_EQ:
1197 op = CRAND;
1198 goto do_equality;
1199 case TCG_COND_NE:
1200 op = CRNAND;
1201 do_equality:
1202 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1203 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1204 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1205 break;
1206
1207 case TCG_COND_LT:
1208 case TCG_COND_LE:
1209 case TCG_COND_GT:
1210 case TCG_COND_GE:
1211 case TCG_COND_LTU:
1212 case TCG_COND_LEU:
1213 case TCG_COND_GTU:
1214 case TCG_COND_GEU:
1215 bit1 = bits[cond].bit1;
1216 bit2 = bits[cond].bit2;
1217 op = (bit1 != bit2 ? CRANDC : CRAND);
1218 cond2 = tcg_unsigned_cond(cond);
1219
1220 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1221 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1222 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1223 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1224 break;
1225
1226 default:
1227 tcg_abort();
1228 }
1229}
1230
1231static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1232 const int *const_args)
1233{
1234 tcg_out_cmp2(s, args + 1, const_args + 1);
1235 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1236 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1237}
1238
1239static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1240 const int *const_args)
1241{
1242 tcg_out_cmp2(s, args, const_args);
bec16311 1243 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
abcf61c4
RH		 1244}
1245
d604f1a9 1246void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
810260a8 1247{
d604f1a9 1248 TCGContext s;
b18d5d2b 1249
d604f1a9
RH		 1250 s.code_buf = s.code_ptr = (tcg_insn_unit *)jmp_addr;
1251 tcg_out_b(&s, 0, (tcg_insn_unit *)addr);
1252 flush_icache_range(jmp_addr, jmp_addr + tcg_current_code_size(&s));
810260a8 1253}
1254
d604f1a9 1255static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
810260a8 1256{
eaf7d1cf 1257#ifdef _CALL_AIX
d604f1a9
RH		 1258 /* Look through the descriptor. If the branch is in range, and we
1259 don't have to spend too much effort on building the toc. */
1260 void *tgt = ((void **)target)[0];
1261 uintptr_t toc = ((uintptr_t *)target)[1];
1262 intptr_t diff = tcg_pcrel_diff(s, tgt);
b18d5d2b 1263
d604f1a9 1264 if (in_range_b(diff) && toc == (uint32_t)toc) {
dfca1778 1265 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
d604f1a9 1266 tcg_out_b(s, LK, tgt);
541dd4ce 1267 } else {
d604f1a9
RH		 1268 /* Fold the low bits of the constant into the addresses below. */
1269 intptr_t arg = (intptr_t)target;
1270 int ofs = (int16_t)arg;
1271
1272 if (ofs + 8 < 0x8000) {
1273 arg -= ofs;
1274 } else {
1275 ofs = 0;
1276 }
dfca1778
RH		 1277 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1278 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
d604f1a9 1279 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
dfca1778 1280 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
d604f1a9 1281 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
541dd4ce 1282 }
77e58d0d
UW		 1283#elif defined(_CALL_ELF) && _CALL_ELF == 2
1284 intptr_t diff;
1285
1286 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1287 address, which the callee uses to compute its TOC address. */
1288 /* FIXME: when the branch is in range, we could avoid r12 load if we
1289 knew that the destination uses the same TOC, and what its local
1290 entry point offset is. */
1291 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1292
1293 diff = tcg_pcrel_diff(s, target);
1294 if (in_range_b(diff)) {
1295 tcg_out_b(s, LK, target);
1296 } else {
1297 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1298 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1299 }
eaf7d1cf
RH		 1300#else
1301 tcg_out_b(s, LK, target);
d604f1a9 1302#endif
810260a8 1303}
1304
d604f1a9
RH		 1305static const uint32_t qemu_ldx_opc[16] = {
1306 [MO_UB] = LBZX,
1307 [MO_UW] = LHZX,
1308 [MO_UL] = LWZX,
1309 [MO_Q] = LDX,
1310 [MO_SW] = LHAX,
1311 [MO_SL] = LWAX,
1312 [MO_BSWAP | MO_UB] = LBZX,
1313 [MO_BSWAP | MO_UW] = LHBRX,
1314 [MO_BSWAP | MO_UL] = LWBRX,
1315 [MO_BSWAP | MO_Q] = LDBRX,
1316};
810260a8 1317
d604f1a9
RH		 1318static const uint32_t qemu_stx_opc[16] = {
1319 [MO_UB] = STBX,
1320 [MO_UW] = STHX,
1321 [MO_UL] = STWX,
1322 [MO_Q] = STDX,
1323 [MO_BSWAP | MO_UB] = STBX,
1324 [MO_BSWAP | MO_UW] = STHBRX,
1325 [MO_BSWAP | MO_UL] = STWBRX,
1326 [MO_BSWAP | MO_Q] = STDBRX,
1327};
991041a4 1328
d604f1a9
RH		 1329static const uint32_t qemu_exts_opc[4] = {
1330 EXTSB, EXTSH, EXTSW, 0
1331};
810260a8 1332
d604f1a9
RH		 1333#if defined (CONFIG_SOFTMMU)
1334/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1335 * int mmu_idx, uintptr_t ra)
1336 */
1337static void * const qemu_ld_helpers[16] = {
1338 [MO_UB] = helper_ret_ldub_mmu,
1339 [MO_LEUW] = helper_le_lduw_mmu,
1340 [MO_LEUL] = helper_le_ldul_mmu,
1341 [MO_LEQ] = helper_le_ldq_mmu,
1342 [MO_BEUW] = helper_be_lduw_mmu,
1343 [MO_BEUL] = helper_be_ldul_mmu,
1344 [MO_BEQ] = helper_be_ldq_mmu,
1345};
810260a8 1346
d604f1a9
RH		 1347/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1348 * uintxx_t val, int mmu_idx, uintptr_t ra)
1349 */
1350static void * const qemu_st_helpers[16] = {
1351 [MO_UB] = helper_ret_stb_mmu,
1352 [MO_LEUW] = helper_le_stw_mmu,
1353 [MO_LEUL] = helper_le_stl_mmu,
1354 [MO_LEQ] = helper_le_stq_mmu,
1355 [MO_BEUW] = helper_be_stw_mmu,
1356 [MO_BEUL] = helper_be_stl_mmu,
1357 [MO_BEQ] = helper_be_stq_mmu,
1358};
810260a8 1359
d604f1a9
RH		 1360/* Perform the TLB load and compare. Places the result of the comparison
1361 in CR7, loads the addend of the TLB into R3, and returns the register
1362 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1363
7f25c469
RH		 1364static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits,
1365 TCGReg addrlo, TCGReg addrhi,
d604f1a9
RH		 1366 int mem_index, bool is_read)
1367{
1368 int cmp_off
1369 = (is_read
1370 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1371 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1372 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1373 TCGReg base = TCG_AREG0;
1374
1375 /* Extract the page index, shifted into place for tlb index. */
7f25c469
RH		 1376 if (TCG_TARGET_REG_BITS == 64) {
1377 if (TARGET_LONG_BITS == 32) {
1378 /* Zero-extend the address into a place helpful for further use. */
1379 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1380 addrlo = TCG_REG_R4;
1381 } else {
1382 tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo,
1383 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
1384 }
810260a8 1385 }
810260a8 1386
d604f1a9
RH		 1387 /* Compensate for very large offsets. */
1388 if (add_off >= 0x8000) {
1389 /* Most target env are smaller than 32k; none are larger than 64k.
1390 Simplify the logic here merely to offset by 0x7ff0, giving us a
1391 range just shy of 64k. Check this assumption. */
1392 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
1393 tlb_table[NB_MMU_MODES - 1][1])
1394 > 0x7ff0 + 0x7fff);
dfca1778
RH		 1395 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0));
1396 base = TCG_REG_TMP1;
d604f1a9
RH		 1397 cmp_off -= 0x7ff0;
1398 add_off -= 0x7ff0;
1399 }
1400
1401 /* Extraction and shifting, part 2. */
7f25c469
RH		 1402 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1403 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo,
d604f1a9
RH		 1404 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
1405 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
1406 31 - CPU_TLB_ENTRY_BITS);
4c314da6 1407 } else {
d604f1a9 1408 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
810260a8 1409 }
810260a8 1410
d604f1a9 1411 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
1cd62ae9 1412
d604f1a9 1413 /* Load the tlb comparator. */
7f25c469
RH		 1414 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1415 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
dfca1778 1416 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
7f25c469 1417 } else {
dfca1778 1418 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
7f25c469 1419 }
d604f1a9
RH		 1420
1421 /* Load the TLB addend for use on the fast path. Do this asap
1422 to minimize any load use delay. */
4c3831a0 1423 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
d604f1a9
RH		 1424
1425 /* Clear the non-page, non-alignment bits from the address. */
7f25c469
RH		 1426 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1427 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
d604f1a9
RH		 1428 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
1429 } else if (!s_bits) {
7f25c469
RH		 1430 tcg_out_rld(s, RLDICR, TCG_REG_R0, addrlo,
1431 0, 63 - TARGET_PAGE_BITS);
70fac59a 1432 } else {
7f25c469 1433 tcg_out_rld(s, RLDICL, TCG_REG_R0, addrlo,
d604f1a9
RH		 1434 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
1435 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
70fac59a 1436 }
d604f1a9 1437
7f25c469 1438 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
dfca1778
RH		 1439 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1440 0, 7, TCG_TYPE_I32);
7f25c469
RH		 1441 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1442 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1443 } else {
dfca1778
RH		 1444 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1445 0, 7, TCG_TYPE_TL);
7f25c469 1446 }
d604f1a9 1447
7f25c469 1448 return addrlo;
70fac59a 1449}
1cd62ae9 1450
d604f1a9
RH		 1451/* Record the context of a call to the out of line helper code for the slow
1452 path for a load or store, so that we can later generate the correct
1453 helper code. */
3972ef6f 1454static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
7f25c469
RH		 1455 TCGReg datalo_reg, TCGReg datahi_reg,
1456 TCGReg addrlo_reg, TCGReg addrhi_reg,
3972ef6f 1457 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
70fac59a 1458{
d604f1a9
RH		 1459 TCGLabelQemuLdst *label = new_ldst_label(s);
1460
1461 label->is_ld = is_ld;
3972ef6f 1462 label->oi = oi;
7f25c469
RH		 1463 label->datalo_reg = datalo_reg;
1464 label->datahi_reg = datahi_reg;
1465 label->addrlo_reg = addrlo_reg;
1466 label->addrhi_reg = addrhi_reg;
d604f1a9 1467 label->raddr = raddr;
7f25c469 1468 label->label_ptr[0] = lptr;
70fac59a 1469}
1cd62ae9 1470
d604f1a9 1471static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
70fac59a 1472{
3972ef6f
RH		 1473 TCGMemOpIdx oi = lb->oi;
1474 TCGMemOp opc = get_memop(oi);
7f25c469 1475 TCGReg hi, lo, arg = TCG_REG_R3;
70fac59a 1476
d604f1a9 1477 reloc_pc14(lb->label_ptr[0], s->code_ptr);
70fac59a 1478
7f25c469 1479 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1cd62ae9 1480
7f25c469
RH		 1481 lo = lb->addrlo_reg;
1482 hi = lb->addrhi_reg;
1483 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1484#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1485 arg |= 1;
1486#endif
1487 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1488 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1489 } else {
1490 /* If the address needed to be zero-extended, we'll have already
1491 placed it in R4. The only remaining case is 64-bit guest. */
1492 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1493 }
752c1fdb 1494
3972ef6f 1495 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 1496 tcg_out32(s, MFSPR | RT(arg) | LR);
70fac59a 1497
2b7ec66f 1498 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
70fac59a 1499
7f25c469
RH		 1500 lo = lb->datalo_reg;
1501 hi = lb->datahi_reg;
1502 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1503 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
1504 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
1505 } else if (opc & MO_SIGN) {
d604f1a9 1506 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
7f25c469 1507 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
d604f1a9 1508 } else {
7f25c469 1509 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
70fac59a
RH		 1510 }
1511
d604f1a9
RH		 1512 tcg_out_b(s, 0, lb->raddr);
1513}
70fac59a 1514
d604f1a9
RH		 1515static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1516{
3972ef6f
RH		 1517 TCGMemOpIdx oi = lb->oi;
1518 TCGMemOp opc = get_memop(oi);
d604f1a9 1519 TCGMemOp s_bits = opc & MO_SIZE;
7f25c469 1520 TCGReg hi, lo, arg = TCG_REG_R3;
1cd62ae9 1521
d604f1a9 1522 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1cd62ae9 1523
7f25c469
RH		 1524 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1525
1526 lo = lb->addrlo_reg;
1527 hi = lb->addrhi_reg;
1528 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1529#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1530 arg |= 1;
1531#endif
1532 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1533 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1534 } else {
1535 /* If the address needed to be zero-extended, we'll have already
1536 placed it in R4. The only remaining case is 64-bit guest. */
1537 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1538 }
1cd62ae9 1539
7f25c469
RH		 1540 lo = lb->datalo_reg;
1541 hi = lb->datahi_reg;
1542 if (TCG_TARGET_REG_BITS == 32) {
1543 switch (s_bits) {
1544 case MO_64:
1545#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1546 arg |= 1;
1547#endif
1548 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1549 /* FALLTHRU */
1550 case MO_32:
1551 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1552 break;
1553 default:
1554 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
1555 break;
1556 }
1557 } else {
1558 if (s_bits == MO_64) {
1559 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
1560 } else {
1561 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
1562 }
1563 }
1cd62ae9 1564
3972ef6f 1565 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 1566 tcg_out32(s, MFSPR | RT(arg) | LR);
1cd62ae9 1567
2b7ec66f 1568 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
d604f1a9
RH		 1569
1570 tcg_out_b(s, 0, lb->raddr);
1cd62ae9 1571}
d604f1a9 1572#endif /* SOFTMMU */
1cd62ae9 1573
7f25c469 1574static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
810260a8 1575{
7f25c469
RH		 1576 TCGReg datalo, datahi, addrlo, rbase;
1577 TCGReg addrhi __attribute__((unused));
59227d5d 1578 TCGMemOpIdx oi;
7f25c469 1579 TCGMemOp opc, s_bits;
d604f1a9 1580#ifdef CONFIG_SOFTMMU
7f25c469 1581 int mem_index;
d604f1a9
RH		 1582 tcg_insn_unit *label_ptr;
1583#endif
810260a8 1584
7f25c469
RH		 1585 datalo = *args++;
1586 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1587 addrlo = *args++;
1588 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1589 oi = *args++;
1590 opc = get_memop(oi);
7f25c469
RH		 1591 s_bits = opc & MO_SIZE;
1592
d604f1a9 1593#ifdef CONFIG_SOFTMMU
59227d5d 1594 mem_index = get_mmuidx(oi);
7f25c469 1595 addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, true);
d604f1a9
RH		 1596
1597 /* Load a pointer into the current opcode w/conditional branch-link. */
1598 label_ptr = s->code_ptr;
1599 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1600
1601 rbase = TCG_REG_R3;
1602#else /* !CONFIG_SOFTMMU */
1603 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
7f25c469 1604 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 1605 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1606 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 1607 }
1608#endif
1609
7f25c469
RH		 1610 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1611 if (opc & MO_BSWAP) {
1612 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1613 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1614 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
1615 } else if (rbase != 0) {
1616 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1617 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
1618 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
1619 } else if (addrlo == datahi) {
1620 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1621 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1622 } else {
1623 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1624 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1625 }
541dd4ce 1626 } else {
2b7ec66f 1627 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
7f25c469
RH		 1628 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1629 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1630 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1631 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1632 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
1633 } else if (insn) {
1634 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1635 } else {
1636 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1637 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1638 insn = qemu_exts_opc[s_bits];
1639 tcg_out32(s, insn | RA(datalo) | RS(datalo));
1640 }
810260a8 1641 }
810260a8 1642
d604f1a9 1643#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 1644 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1645 s->code_ptr, label_ptr);
d604f1a9 1646#endif
810260a8 1647}
1648
7f25c469 1649static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
027ffea9 1650{
7f25c469
RH		 1651 TCGReg datalo, datahi, addrlo, rbase;
1652 TCGReg addrhi __attribute__((unused));
59227d5d 1653 TCGMemOpIdx oi;
7f25c469 1654 TCGMemOp opc, s_bits;
d604f1a9 1655#ifdef CONFIG_SOFTMMU
7f25c469 1656 int mem_index;
d604f1a9
RH		 1657 tcg_insn_unit *label_ptr;
1658#endif
027ffea9 1659
7f25c469
RH		 1660 datalo = *args++;
1661 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1662 addrlo = *args++;
1663 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1664 oi = *args++;
1665 opc = get_memop(oi);
7f25c469
RH		 1666 s_bits = opc & MO_SIZE;
1667
d604f1a9 1668#ifdef CONFIG_SOFTMMU
59227d5d 1669 mem_index = get_mmuidx(oi);
7f25c469 1670 addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, false);
027ffea9 1671
d604f1a9
RH		 1672 /* Load a pointer into the current opcode w/conditional branch-link. */
1673 label_ptr = s->code_ptr;
1674 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
027ffea9 1675
d604f1a9
RH		 1676 rbase = TCG_REG_R3;
1677#else /* !CONFIG_SOFTMMU */
1678 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
7f25c469 1679 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 1680 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1681 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 1682 }
1683#endif
1684
7f25c469
RH		 1685 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1686 if (opc & MO_BSWAP) {
1687 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1688 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1689 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
1690 } else if (rbase != 0) {
1691 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1692 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
1693 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
1694 } else {
1695 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
1696 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
1697 }
027ffea9 1698 } else {
2b7ec66f 1699 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
7f25c469
RH		 1700 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1701 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
dfca1778 1702 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
7f25c469 1703 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
dfca1778 1704 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
7f25c469
RH		 1705 } else {
1706 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
1707 }
027ffea9 1708 }
d604f1a9
RH		 1709
1710#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 1711 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1712 s->code_ptr, label_ptr);
d604f1a9 1713#endif
027ffea9
RH		 1714}
1715
a921fddc
RH		 1716/* Parameters for function call generation, used in tcg.c. */
1717#define TCG_TARGET_STACK_ALIGN 16
a921fddc
RH		 1718#define TCG_TARGET_EXTEND_ARGS 1
1719
802ca56e
RH		 1720#ifdef _CALL_AIX
1721# define LINK_AREA_SIZE (6 * SZR)
1722# define LR_OFFSET (1 * SZR)
1723# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1045fc04
PM		 1724#elif defined(TCG_TARGET_CALL_DARWIN)
1725# define LINK_AREA_SIZE (6 * SZR)
1726# define LR_OFFSET (2 * SZR)
ffcfbece
RH		 1727#elif TCG_TARGET_REG_BITS == 64
1728# if defined(_CALL_ELF) && _CALL_ELF == 2
1729# define LINK_AREA_SIZE (4 * SZR)
1730# define LR_OFFSET (1 * SZR)
1731# endif
1732#else /* TCG_TARGET_REG_BITS == 32 */
1733# if defined(_CALL_SYSV)
ffcfbece
RH		 1734# define LINK_AREA_SIZE (2 * SZR)
1735# define LR_OFFSET (1 * SZR)
ffcfbece
RH		 1736# endif
1737#endif
1738#ifndef LR_OFFSET
1739# error "Unhandled abi"
1740#endif
1741#ifndef TCG_TARGET_CALL_STACK_OFFSET
a2a98f80 1742# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
802ca56e
RH		 1743#endif
1744
1745#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1746#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
d604f1a9 1747
802ca56e
RH		 1748#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1749 + TCG_STATIC_CALL_ARGS_SIZE \
1750 + CPU_TEMP_BUF_SIZE \
1751 + REG_SAVE_SIZE \
1752 + TCG_TARGET_STACK_ALIGN - 1) \
1753 & -TCG_TARGET_STACK_ALIGN)
1754
1755#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
d604f1a9
RH		 1756
1757static void tcg_target_qemu_prologue(TCGContext *s)
810260a8 1758{
d604f1a9 1759 int i;
810260a8 1760
802ca56e 1761#ifdef _CALL_AIX
a84ac4cb
RH		 1762 void **desc = (void **)s->code_ptr;
1763 desc[0] = desc + 2; /* entry point */
1764 desc[1] = 0; /* environment pointer */
1765 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
d604f1a9
RH		 1766#endif
1767
a84ac4cb
RH		 1768 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1769 CPU_TEMP_BUF_SIZE);
1770
d604f1a9
RH		 1771 /* Prologue */
1772 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
ffcfbece
RH		 1773 tcg_out32(s, (SZR == 8 ? STDU : STWU)
1774 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
802ca56e 1775
d604f1a9 1776 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 1777 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1778 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 1779 }
802ca56e 1780 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9
RH		 1781
1782#ifdef CONFIG_USE_GUEST_BASE
1783 if (GUEST_BASE) {
1784 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
1785 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1786 }
1787#endif
1788
1789 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1790 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
a84ac4cb
RH		 1791
1792 if (USE_REG_RA) {
1793#ifdef _CALL_AIX
1794 /* Make the caller load the value as the TOC into R2. */
1795 tb_ret_addr = s->code_ptr + 2;
1796 desc[1] = tb_ret_addr;
1797 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2);
1798 tcg_out32(s, BCCTR | BO_ALWAYS);
1799#elif defined(_CALL_ELF) && _CALL_ELF == 2
1800 /* Compute from the incoming R12 value. */
1801 tb_ret_addr = s->code_ptr + 2;
1802 tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12,
1803 tcg_ptr_byte_diff(tb_ret_addr, s->code_buf)));
1804 tcg_out32(s, BCCTR | BO_ALWAYS);
1805#else
1806 /* Reserve max 5 insns for the constant load. */
1807 tb_ret_addr = s->code_ptr + 6;
1808 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr);
1809 tcg_out32(s, BCCTR | BO_ALWAYS);
1810 while (s->code_ptr < tb_ret_addr) {
1811 tcg_out32(s, NOP);
1812 }
1813#endif
1814 } else {
1815 tcg_out32(s, BCCTR | BO_ALWAYS);
1816 tb_ret_addr = s->code_ptr;
1817 }
d604f1a9
RH		 1818
1819 /* Epilogue */
a84ac4cb 1820 assert(tb_ret_addr == s->code_ptr);
d604f1a9 1821
802ca56e 1822 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 1823 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 1824 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1825 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 1826 }
d604f1a9
RH		 1827 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1828 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1829 tcg_out32(s, BCLR | BO_ALWAYS);
810260a8 1830}
1831
541dd4ce
RH		 1832static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1833 const int *const_args)
810260a8 1834{
ee924fa6 1835 TCGArg a0, a1, a2;
e46b9681 1836 int c;
1837
810260a8 1838 switch (opc) {
1839 case INDEX_op_exit_tb:
a84ac4cb
RH		 1840 if (USE_REG_RA) {
1841 ptrdiff_t disp = tcg_pcrel_diff(s, tb_ret_addr);
1842
1843 /* If we can use a direct branch, otherwise use the value in RA.
1844 Note that the direct branch is always forward. If it's in
1845 range now, it'll still be in range after the movi. Don't
1846 bother about the 20 bytes where the test here fails but it
1847 would succeed below. */
1848 if (!in_range_b(disp)) {
1849 tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR);
1850 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1851 tcg_out32(s, BCCTR | BO_ALWAYS);
1852 break;
1853 }
1854 }
de3d636d 1855 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
e083c4a2 1856 tcg_out_b(s, 0, tb_ret_addr);
810260a8 1857 break;
1858 case INDEX_op_goto_tb:
1859 if (s->tb_jmp_offset) {
541dd4ce 1860 /* Direct jump method. */
e083c4a2
RH		 1861 s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
1862 s->code_ptr += 7;
541dd4ce
RH		 1863 } else {
1864 /* Indirect jump method. */
1865 tcg_abort();
810260a8 1866 }
e083c4a2 1867 s->tb_next_offset[args[0]] = tcg_current_code_size(s);
810260a8 1868 break;
1869 case INDEX_op_br:
1870 {
bec16311 1871 TCGLabel *l = arg_label(args[0]);
810260a8 1872
1873 if (l->has_value) {
e083c4a2 1874 tcg_out_b(s, 0, l->u.value_ptr);
541dd4ce 1875 } else {
bec16311 1876 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
c7ca6a2b 1877 tcg_out_b_noaddr(s, B);
810260a8 1878 }
1879 }
1880 break;
810260a8 1881 case INDEX_op_ld8u_i32:
1882 case INDEX_op_ld8u_i64:
b18d5d2b 1883 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
810260a8 1884 break;
1885 case INDEX_op_ld8s_i32:
1886 case INDEX_op_ld8s_i64:
b18d5d2b 1887 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
541dd4ce 1888 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
810260a8 1889 break;
1890 case INDEX_op_ld16u_i32:
1891 case INDEX_op_ld16u_i64:
b18d5d2b 1892 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
810260a8 1893 break;
1894 case INDEX_op_ld16s_i32:
1895 case INDEX_op_ld16s_i64:
b18d5d2b 1896 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
810260a8 1897 break;
1898 case INDEX_op_ld_i32:
1899 case INDEX_op_ld32u_i64:
b18d5d2b 1900 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
810260a8 1901 break;
1902 case INDEX_op_ld32s_i64:
b18d5d2b 1903 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
810260a8 1904 break;
1905 case INDEX_op_ld_i64:
b18d5d2b 1906 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
810260a8 1907 break;
1908 case INDEX_op_st8_i32:
1909 case INDEX_op_st8_i64:
b18d5d2b 1910 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
810260a8 1911 break;
1912 case INDEX_op_st16_i32:
1913 case INDEX_op_st16_i64:
b18d5d2b 1914 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
810260a8 1915 break;
1916 case INDEX_op_st_i32:
1917 case INDEX_op_st32_i64:
b18d5d2b 1918 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
810260a8 1919 break;
1920 case INDEX_op_st_i64:
b18d5d2b 1921 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
810260a8 1922 break;
1923
1924 case INDEX_op_add_i32:
ee924fa6
RH		 1925 a0 = args[0], a1 = args[1], a2 = args[2];
1926 if (const_args[2]) {
ee924fa6 1927 do_addi_32:
b18d5d2b 1928 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
ee924fa6
RH		 1929 } else {
1930 tcg_out32(s, ADD | TAB(a0, a1, a2));
1931 }
810260a8 1932 break;
1933 case INDEX_op_sub_i32:
ee924fa6 1934 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 1935 if (const_args[1]) {
1936 if (const_args[2]) {
1937 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1938 } else {
1939 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1940 }
1941 } else if (const_args[2]) {
ee924fa6
RH		 1942 a2 = -a2;
1943 goto do_addi_32;
1944 } else {
1945 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1946 }
810260a8 1947 break;
1948
1949 case INDEX_op_and_i32:
37251b98 1950 a0 = args[0], a1 = args[1], a2 = args[2];
a9249dff 1951 if (const_args[2]) {
37251b98 1952 tcg_out_andi32(s, a0, a1, a2);
a9249dff 1953 } else {
37251b98 1954 tcg_out32(s, AND | SAB(a1, a0, a2));
a9249dff
RH		 1955 }
1956 break;
1957 case INDEX_op_and_i64:
37251b98 1958 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1959 if (const_args[2]) {
37251b98 1960 tcg_out_andi64(s, a0, a1, a2);
637af30c 1961 } else {
37251b98 1962 tcg_out32(s, AND | SAB(a1, a0, a2));
810260a8 1963 }
810260a8 1964 break;
fe6f943f 1965 case INDEX_op_or_i64:
810260a8 1966 case INDEX_op_or_i32:
dce74c57 1967 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1968 if (const_args[2]) {
dce74c57
RH		 1969 tcg_out_ori32(s, a0, a1, a2);
1970 } else {
1971 tcg_out32(s, OR | SAB(a1, a0, a2));
810260a8 1972 }
810260a8 1973 break;
fe6f943f 1974 case INDEX_op_xor_i64:
810260a8 1975 case INDEX_op_xor_i32:
dce74c57 1976 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1977 if (const_args[2]) {
dce74c57
RH		 1978 tcg_out_xori32(s, a0, a1, a2);
1979 } else {
1980 tcg_out32(s, XOR | SAB(a1, a0, a2));
810260a8 1981 }
810260a8 1982 break;
ce1010d6 1983 case INDEX_op_andc_i32:
37251b98
RH		 1984 a0 = args[0], a1 = args[1], a2 = args[2];
1985 if (const_args[2]) {
1986 tcg_out_andi32(s, a0, a1, ~a2);
1987 } else {
1988 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1989 }
1990 break;
ce1010d6 1991 case INDEX_op_andc_i64:
37251b98
RH		 1992 a0 = args[0], a1 = args[1], a2 = args[2];
1993 if (const_args[2]) {
1994 tcg_out_andi64(s, a0, a1, ~a2);
1995 } else {
1996 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1997 }
ce1010d6
RH		 1998 break;
1999 case INDEX_op_orc_i32:
37251b98
RH		 2000 if (const_args[2]) {
2001 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2002 break;
2003 }
2004 /* FALLTHRU */
ce1010d6
RH		 2005 case INDEX_op_orc_i64:
2006 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2007 break;
2008 case INDEX_op_eqv_i32:
37251b98
RH		 2009 if (const_args[2]) {
2010 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2011 break;
2012 }
2013 /* FALLTHRU */
ce1010d6
RH		 2014 case INDEX_op_eqv_i64:
2015 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2016 break;
2017 case INDEX_op_nand_i32:
2018 case INDEX_op_nand_i64:
2019 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2020 break;
2021 case INDEX_op_nor_i32:
2022 case INDEX_op_nor_i64:
2023 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2024 break;
810260a8 2025
2026 case INDEX_op_mul_i32:
ef809300 2027 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2028 if (const_args[2]) {
ef809300
RH		 2029 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2030 } else {
2031 tcg_out32(s, MULLW | TAB(a0, a1, a2));
810260a8 2032 }
810260a8 2033 break;
2034
2035 case INDEX_op_div_i32:
541dd4ce 2036 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
810260a8 2037 break;
2038
2039 case INDEX_op_divu_i32:
541dd4ce 2040 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
810260a8 2041 break;
2042
810260a8 2043 case INDEX_op_shl_i32:
2044 if (const_args[2]) {
a757e1ee 2045 tcg_out_shli32(s, args[0], args[1], args[2]);
9e555b73 2046 } else {
541dd4ce 2047 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
9e555b73 2048 }
810260a8 2049 break;
2050 case INDEX_op_shr_i32:
2051 if (const_args[2]) {
a757e1ee 2052 tcg_out_shri32(s, args[0], args[1], args[2]);
9e555b73 2053 } else {
541dd4ce 2054 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
9e555b73 2055 }
810260a8 2056 break;
2057 case INDEX_op_sar_i32:
541dd4ce
RH		 2058 if (const_args[2]) {
2059 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
2060 } else {
2061 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2062 }
810260a8 2063 break;
313d91c7
RH		 2064 case INDEX_op_rotl_i32:
2065 if (const_args[2]) {
2066 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2067 } else {
2068 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2069 | MB(0) | ME(31));
2070 }
2071 break;
2072 case INDEX_op_rotr_i32:
2073 if (const_args[2]) {
2074 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2075 } else {
8327a470
RH		 2076 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2077 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
313d91c7
RH		 2078 | MB(0) | ME(31));
2079 }
2080 break;
810260a8 2081
2082 case INDEX_op_brcond_i32:
4c314da6 2083 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2084 arg_label(args[3]), TCG_TYPE_I32);
e924bbec 2085 break;
810260a8 2086 case INDEX_op_brcond_i64:
4c314da6 2087 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2088 arg_label(args[3]), TCG_TYPE_I64);
810260a8 2089 break;
abcf61c4
RH		 2090 case INDEX_op_brcond2_i32:
2091 tcg_out_brcond2(s, args, const_args);
2092 break;
810260a8 2093
2094 case INDEX_op_neg_i32:
810260a8 2095 case INDEX_op_neg_i64:
541dd4ce 2096 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
810260a8 2097 break;
2098
157f2662 2099 case INDEX_op_not_i32:
2100 case INDEX_op_not_i64:
541dd4ce 2101 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
157f2662 2102 break;
2103
810260a8 2104 case INDEX_op_add_i64:
ee924fa6
RH		 2105 a0 = args[0], a1 = args[1], a2 = args[2];
2106 if (const_args[2]) {
ee924fa6 2107 do_addi_64:
b18d5d2b 2108 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
ee924fa6
RH		 2109 } else {
2110 tcg_out32(s, ADD | TAB(a0, a1, a2));
2111 }
810260a8 2112 break;
2113 case INDEX_op_sub_i64:
ee924fa6 2114 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2115 if (const_args[1]) {
2116 if (const_args[2]) {
2117 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2118 } else {
2119 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2120 }
2121 } else if (const_args[2]) {
ee924fa6
RH		 2122 a2 = -a2;
2123 goto do_addi_64;
2124 } else {
2125 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2126 }
810260a8 2127 break;
2128
2129 case INDEX_op_shl_i64:
541dd4ce 2130 if (const_args[2]) {
0a9564b9 2131 tcg_out_shli64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2132 } else {
2133 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2134 }
810260a8 2135 break;
2136 case INDEX_op_shr_i64:
541dd4ce 2137 if (const_args[2]) {
5e916c28 2138 tcg_out_shri64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2139 } else {
2140 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2141 }
810260a8 2142 break;
2143 case INDEX_op_sar_i64:
fe6f943f 2144 if (const_args[2]) {
541dd4ce
RH		 2145 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2146 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2147 } else {
2148 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
fe6f943f 2149 }
810260a8 2150 break;
313d91c7
RH		 2151 case INDEX_op_rotl_i64:
2152 if (const_args[2]) {
2153 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2154 } else {
2155 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2156 }
2157 break;
2158 case INDEX_op_rotr_i64:
2159 if (const_args[2]) {
2160 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2161 } else {
8327a470
RH		 2162 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2163 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
313d91c7
RH		 2164 }
2165 break;
810260a8 2166
2167 case INDEX_op_mul_i64:
ef809300
RH		 2168 a0 = args[0], a1 = args[1], a2 = args[2];
2169 if (const_args[2]) {
2170 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2171 } else {
2172 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2173 }
810260a8 2174 break;
2175 case INDEX_op_div_i64:
541dd4ce 2176 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
810260a8 2177 break;
2178 case INDEX_op_divu_i64:
541dd4ce 2179 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
810260a8 2180 break;
810260a8 2181
1768ec06 2182 case INDEX_op_qemu_ld_i32:
7f25c469
RH		 2183 tcg_out_qemu_ld(s, args, false);
2184 break;
1768ec06 2185 case INDEX_op_qemu_ld_i64:
7f25c469 2186 tcg_out_qemu_ld(s, args, true);
810260a8 2187 break;
1768ec06 2188 case INDEX_op_qemu_st_i32:
7f25c469
RH		 2189 tcg_out_qemu_st(s, args, false);
2190 break;
1768ec06 2191 case INDEX_op_qemu_st_i64:
7f25c469 2192 tcg_out_qemu_st(s, args, true);
810260a8 2193 break;
2194
e46b9681 2195 case INDEX_op_ext8s_i32:
2196 case INDEX_op_ext8s_i64:
2197 c = EXTSB;
2198 goto gen_ext;
2199 case INDEX_op_ext16s_i32:
2200 case INDEX_op_ext16s_i64:
2201 c = EXTSH;
2202 goto gen_ext;
4f2331e5 2203 case INDEX_op_ext_i32_i64:
e46b9681 2204 case INDEX_op_ext32s_i64:
2205 c = EXTSW;
2206 goto gen_ext;
2207 gen_ext:
541dd4ce 2208 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
e46b9681 2209 break;
4f2331e5
AJ		 2210 case INDEX_op_extu_i32_i64:
2211 tcg_out_ext32u(s, args[0], args[1]);
2212 break;
e46b9681 2213
1cd62ae9 2214 case INDEX_op_setcond_i32:
541dd4ce
RH		 2215 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2216 const_args[2]);
1cd62ae9 2217 break;
2218 case INDEX_op_setcond_i64:
541dd4ce
RH		 2219 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2220 const_args[2]);
1cd62ae9 2221 break;
abcf61c4
RH		 2222 case INDEX_op_setcond2_i32:
2223 tcg_out_setcond2(s, args, const_args);
2224 break;
1cd62ae9 2225
5d221582
RH		 2226 case INDEX_op_bswap16_i32:
2227 case INDEX_op_bswap16_i64:
2228 a0 = args[0], a1 = args[1];
2229 /* a1 = abcd */
2230 if (a0 != a1) {
2231 /* a0 = (a1 r<< 24) & 0xff # 000c */
2232 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2233 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2234 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2235 } else {
2236 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2237 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2238 /* a0 = (a1 r<< 24) & 0xff # 000c */
2239 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2240 /* a0 = a0 | r0 # 00dc */
2241 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2242 }
2243 break;
2244
2245 case INDEX_op_bswap32_i32:
2246 case INDEX_op_bswap32_i64:
2247 /* Stolen from gcc's builtin_bswap32 */
2248 a1 = args[1];
2249 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2250
2251 /* a1 = args[1] # abcd */
2252 /* a0 = rotate_left (a1, 8) # bcda */
2253 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2254 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2255 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2256 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2257 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2258
2259 if (a0 == TCG_REG_R0) {
de3d636d 2260 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
5d221582
RH		 2261 }
2262 break;
2263
68aebd45 2264 case INDEX_op_bswap64_i64:
8327a470 2265 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
68aebd45 2266 if (a0 == a1) {
8327a470 2267 a0 = TCG_REG_R0;
68aebd45
RH		 2268 a2 = a1;
2269 }
2270
2271 /* a1 = # abcd efgh */
2272 /* a0 = rl32(a1, 8) # 0000 fghe */
2273 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2274 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2275 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2276 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2277 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2278
2279 /* a0 = rl64(a0, 32) # hgfe 0000 */
2280 /* a2 = rl64(a1, 32) # efgh abcd */
2281 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2282 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2283
2284 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2285 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2286 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2287 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2288 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2289 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2290
2291 if (a0 == 0) {
de3d636d 2292 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
68aebd45
RH		 2293 }
2294 break;
2295
33de9ed2 2296 case INDEX_op_deposit_i32:
39dc85b9
RH		 2297 if (const_args[2]) {
2298 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2299 tcg_out_andi32(s, args[0], args[0], ~mask);
2300 } else {
2301 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2302 32 - args[3] - args[4], 31 - args[3]);
2303 }
33de9ed2
RH		 2304 break;
2305 case INDEX_op_deposit_i64:
39dc85b9
RH		 2306 if (const_args[2]) {
2307 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2308 tcg_out_andi64(s, args[0], args[0], ~mask);
2309 } else {
2310 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2311 64 - args[3] - args[4]);
2312 }
33de9ed2
RH		 2313 break;
2314
027ffea9
RH		 2315 case INDEX_op_movcond_i32:
2316 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2317 args[3], args[4], const_args[2]);
2318 break;
2319 case INDEX_op_movcond_i64:
2320 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2321 args[3], args[4], const_args[2]);
2322 break;
2323
796f1a68 2324#if TCG_TARGET_REG_BITS == 64
6c858762 2325 case INDEX_op_add2_i64:
796f1a68
RH		 2326#else
2327 case INDEX_op_add2_i32:
2328#endif
6c858762
RH		 2329 /* Note that the CA bit is defined based on the word size of the
2330 environment. So in 64-bit mode it's always carry-out of bit 63.
2331 The fallback code using deposit works just as well for 32-bit. */
2332 a0 = args[0], a1 = args[1];
84247357 2333 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
6c858762
RH		 2334 a0 = TCG_REG_R0;
2335 }
84247357
AB		 2336 if (const_args[4]) {
2337 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
6c858762 2338 } else {
84247357 2339 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
6c858762
RH		 2340 }
2341 if (const_args[5]) {
84247357 2342 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
6c858762 2343 } else {
84247357 2344 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
6c858762
RH		 2345 }
2346 if (a0 != args[0]) {
de3d636d 2347 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2348 }
2349 break;
2350
796f1a68 2351#if TCG_TARGET_REG_BITS == 64
6c858762 2352 case INDEX_op_sub2_i64:
796f1a68
RH		 2353#else
2354 case INDEX_op_sub2_i32:
2355#endif
6c858762 2356 a0 = args[0], a1 = args[1];
b31284ce 2357 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
6c858762
RH		 2358 a0 = TCG_REG_R0;
2359 }
2360 if (const_args[2]) {
b31284ce 2361 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
6c858762 2362 } else {
b31284ce 2363 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
6c858762 2364 }
b31284ce
RH		 2365 if (const_args[3]) {
2366 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
6c858762 2367 } else {
b31284ce 2368 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
6c858762
RH		 2369 }
2370 if (a0 != args[0]) {
de3d636d 2371 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2372 }
2373 break;
2374
abcf61c4
RH		 2375 case INDEX_op_muluh_i32:
2376 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2377 break;
8fa391a0
RH		 2378 case INDEX_op_mulsh_i32:
2379 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2380 break;
32f5717f
RH		 2381 case INDEX_op_muluh_i64:
2382 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2383 break;
2384 case INDEX_op_mulsh_i64:
2385 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
6645c147
RH		 2386 break;
2387
96d0ee7f
RH		 2388 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2389 case INDEX_op_mov_i64:
2390 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2391 case INDEX_op_movi_i64:
2392 case INDEX_op_call: /* Always emitted via tcg_out_call. */
810260a8 2393 default:
541dd4ce 2394 tcg_abort();
810260a8 2395 }
2396}
2397
2398static const TCGTargetOpDef ppc_op_defs[] = {
2399 { INDEX_op_exit_tb, { } },
2400 { INDEX_op_goto_tb, { } },
810260a8 2401 { INDEX_op_br, { } },
2402
810260a8 2403 { INDEX_op_ld8u_i32, { "r", "r" } },
2404 { INDEX_op_ld8s_i32, { "r", "r" } },
2405 { INDEX_op_ld16u_i32, { "r", "r" } },
2406 { INDEX_op_ld16s_i32, { "r", "r" } },
2407 { INDEX_op_ld_i32, { "r", "r" } },
796f1a68 2408
810260a8 2409 { INDEX_op_st8_i32, { "r", "r" } },
810260a8 2410 { INDEX_op_st16_i32, { "r", "r" } },
810260a8 2411 { INDEX_op_st_i32, { "r", "r" } },
810260a8 2412
2413 { INDEX_op_add_i32, { "r", "r", "ri" } },
ef809300 2414 { INDEX_op_mul_i32, { "r", "r", "rI" } },
810260a8 2415 { INDEX_op_div_i32, { "r", "r", "r" } },
2416 { INDEX_op_divu_i32, { "r", "r", "r" } },
148bdd23 2417 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
810260a8 2418 { INDEX_op_and_i32, { "r", "r", "ri" } },
2419 { INDEX_op_or_i32, { "r", "r", "ri" } },
2420 { INDEX_op_xor_i32, { "r", "r", "ri" } },
37251b98
RH		 2421 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2422 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2423 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
ce1010d6
RH		 2424 { INDEX_op_nand_i32, { "r", "r", "r" } },
2425 { INDEX_op_nor_i32, { "r", "r", "r" } },
810260a8 2426
2427 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2428 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2429 { INDEX_op_sar_i32, { "r", "r", "ri" } },
313d91c7
RH		 2430 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2431 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
810260a8 2432
810260a8 2433 { INDEX_op_neg_i32, { "r", "r" } },
157f2662 2434 { INDEX_op_not_i32, { "r", "r" } },
796f1a68
RH		 2435 { INDEX_op_ext8s_i32, { "r", "r" } },
2436 { INDEX_op_ext16s_i32, { "r", "r" } },
2437 { INDEX_op_bswap16_i32, { "r", "r" } },
2438 { INDEX_op_bswap32_i32, { "r", "r" } },
2439
2440 { INDEX_op_brcond_i32, { "r", "ri" } },
2441 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2442 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2443
2444 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2445
abcf61c4 2446 { INDEX_op_muluh_i32, { "r", "r", "r" } },
8fa391a0 2447 { INDEX_op_mulsh_i32, { "r", "r", "r" } },
abcf61c4 2448
796f1a68
RH		 2449#if TCG_TARGET_REG_BITS == 64
2450 { INDEX_op_ld8u_i64, { "r", "r" } },
2451 { INDEX_op_ld8s_i64, { "r", "r" } },
2452 { INDEX_op_ld16u_i64, { "r", "r" } },
2453 { INDEX_op_ld16s_i64, { "r", "r" } },
2454 { INDEX_op_ld32u_i64, { "r", "r" } },
2455 { INDEX_op_ld32s_i64, { "r", "r" } },
2456 { INDEX_op_ld_i64, { "r", "r" } },
2457
2458 { INDEX_op_st8_i64, { "r", "r" } },
2459 { INDEX_op_st16_i64, { "r", "r" } },
2460 { INDEX_op_st32_i64, { "r", "r" } },
2461 { INDEX_op_st_i64, { "r", "r" } },
810260a8 2462
ee924fa6 2463 { INDEX_op_add_i64, { "r", "r", "rT" } },
148bdd23 2464 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
37251b98 2465 { INDEX_op_and_i64, { "r", "r", "ri" } },
3d582c61
RH		 2466 { INDEX_op_or_i64, { "r", "r", "rU" } },
2467 { INDEX_op_xor_i64, { "r", "r", "rU" } },
37251b98 2468 { INDEX_op_andc_i64, { "r", "r", "ri" } },
ce1010d6
RH		 2469 { INDEX_op_orc_i64, { "r", "r", "r" } },
2470 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2471 { INDEX_op_nand_i64, { "r", "r", "r" } },
2472 { INDEX_op_nor_i64, { "r", "r", "r" } },
810260a8 2473
fe6f943f 2474 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2475 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2476 { INDEX_op_sar_i64, { "r", "r", "ri" } },
313d91c7
RH		 2477 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2478 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
810260a8 2479
ef809300 2480 { INDEX_op_mul_i64, { "r", "r", "rI" } },
810260a8 2481 { INDEX_op_div_i64, { "r", "r", "r" } },
2482 { INDEX_op_divu_i64, { "r", "r", "r" } },
810260a8 2483
2484 { INDEX_op_neg_i64, { "r", "r" } },
157f2662 2485 { INDEX_op_not_i64, { "r", "r" } },
e46b9681 2486 { INDEX_op_ext8s_i64, { "r", "r" } },
2487 { INDEX_op_ext16s_i64, { "r", "r" } },
2488 { INDEX_op_ext32s_i64, { "r", "r" } },
4f2331e5
AJ		 2489 { INDEX_op_ext_i32_i64, { "r", "r" } },
2490 { INDEX_op_extu_i32_i64, { "r", "r" } },
5d221582 2491 { INDEX_op_bswap16_i64, { "r", "r" } },
5d221582 2492 { INDEX_op_bswap32_i64, { "r", "r" } },
68aebd45 2493 { INDEX_op_bswap64_i64, { "r", "r" } },
5d221582 2494
796f1a68
RH		 2495 { INDEX_op_brcond_i64, { "r", "ri" } },
2496 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2497 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2498
39dc85b9 2499 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
33de9ed2 2500
32f5717f
RH		 2501 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2502 { INDEX_op_muluh_i64, { "r", "r", "r" } },
796f1a68
RH		 2503#endif
2504
abcf61c4
RH		 2505#if TCG_TARGET_REG_BITS == 32
2506 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
2507 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
2508#endif
2509
796f1a68
RH		 2510#if TCG_TARGET_REG_BITS == 64
2511 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2512 { INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } },
2513#else
2514 { INDEX_op_add2_i32, { "r", "r", "r", "r", "rI", "rZM" } },
2515 { INDEX_op_sub2_i32, { "r", "r", "rI", "rZM", "r", "r" } },
2516#endif
2517
2518#if TCG_TARGET_REG_BITS == 64
2519 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2520 { INDEX_op_qemu_st_i32, { "S", "S" } },
2521 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2522 { INDEX_op_qemu_st_i64, { "S", "S" } },
2523#elif TARGET_LONG_BITS == 32
2524 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2525 { INDEX_op_qemu_st_i32, { "S", "S" } },
7f25c469 2526 { INDEX_op_qemu_ld_i64, { "L", "L", "L" } },
796f1a68
RH		 2527 { INDEX_op_qemu_st_i64, { "S", "S", "S" } },
2528#else
2529 { INDEX_op_qemu_ld_i32, { "r", "L", "L" } },
2530 { INDEX_op_qemu_st_i32, { "S", "S", "S" } },
7f25c469 2531 { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } },
796f1a68
RH		 2532 { INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
2533#endif
6c858762 2534
810260a8 2535 { -1 },
2536};
2537
541dd4ce 2538static void tcg_target_init(TCGContext *s)
810260a8 2539{
cd629de1 2540 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
1e6e9aca
RH		 2541 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2542 have_isa_2_06 = true;
2543 }
1e6e9aca 2544
541dd4ce
RH		 2545 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2546 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2547 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
810260a8 2548 (1 << TCG_REG_R0) |
5d7ff5bb 2549 (1 << TCG_REG_R2) |
810260a8 2550 (1 << TCG_REG_R3) |
2551 (1 << TCG_REG_R4) |
2552 (1 << TCG_REG_R5) |
2553 (1 << TCG_REG_R6) |
2554 (1 << TCG_REG_R7) |
2555 (1 << TCG_REG_R8) |
2556 (1 << TCG_REG_R9) |
2557 (1 << TCG_REG_R10) |
2558 (1 << TCG_REG_R11) |
5e1702b0 2559 (1 << TCG_REG_R12));
810260a8 2560
541dd4ce 2561 tcg_regset_clear(s->reserved_regs);
5e1702b0
RH		 2562 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2563 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
dfca1778
RH		 2564#if defined(_CALL_SYSV)
2565 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
5d7ff5bb 2566#endif
dfca1778 2567#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
5e1702b0 2568 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
dfca1778
RH		 2569#endif
2570 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
a84ac4cb
RH		 2571 if (USE_REG_RA) {
2572 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */
2573 }
810260a8 2574
541dd4ce 2575 tcg_add_target_add_op_defs(ppc_op_defs);
810260a8 2576}
fa94c3be 2577
ffcfbece 2578#ifdef __ELF__
fa94c3be
RH		 2579typedef struct {
2580 DebugFrameCIE cie;
2581 DebugFrameFDEHeader fde;
2582 uint8_t fde_def_cfa[4];
2583 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2584} DebugFrame;
2585
2586/* We're expecting a 2 byte uleb128 encoded value. */
2587QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2588
ffcfbece
RH		 2589#if TCG_TARGET_REG_BITS == 64
2590# define ELF_HOST_MACHINE EM_PPC64
2591#else
2592# define ELF_HOST_MACHINE EM_PPC
2593#endif
fa94c3be
RH		 2594
2595static DebugFrame debug_frame = {
2596 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2597 .cie.id = -1,
2598 .cie.version = 1,
2599 .cie.code_align = 1,
802ca56e 2600 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
fa94c3be
RH		 2601 .cie.return_column = 65,
2602
2603 /* Total FDE size does not include the "len" member. */
2604 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2605
2606 .fde_def_cfa = {
802ca56e 2607 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
fa94c3be
RH		 2608 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2609 (FRAME_SIZE >> 7)
2610 },
2611 .fde_reg_ofs = {
802ca56e
RH		 2612 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2613 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
fa94c3be
RH		 2614 }
2615};
2616
2617void tcg_register_jit(void *buf, size_t buf_size)
2618{
2619 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2620 int i;
2621
2622 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2623 p[0] = 0x80 + tcg_target_callee_save_regs[i];
802ca56e 2624 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
fa94c3be
RH		 2625 }
2626
802ca56e 2627 debug_frame.fde.func_start = (uintptr_t)buf;
fa94c3be
RH		 2628 debug_frame.fde.func_len = buf_size;
2629
2630 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2631}
ffcfbece 2632#endif /* __ELF__ */
224f9fd4
RH		 2633
2634static size_t dcache_bsize = 16;
2635static size_t icache_bsize = 16;
2636
2637void flush_icache_range(uintptr_t start, uintptr_t stop)
2638{
2639 uintptr_t p, start1, stop1;
2640 size_t dsize = dcache_bsize;
2641 size_t isize = icache_bsize;
2642
2643 start1 = start & ~(dsize - 1);
2644 stop1 = (stop + dsize - 1) & ~(dsize - 1);
2645 for (p = start1; p < stop1; p += dsize) {
2646 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
2647 }
2648 asm volatile ("sync" : : : "memory");
2649
2650 start &= start & ~(isize - 1);
2651 stop1 = (stop + isize - 1) & ~(isize - 1);
2652 for (p = start1; p < stop1; p += isize) {
2653 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
2654 }
2655 asm volatile ("sync" : : : "memory");
2656 asm volatile ("isync" : : : "memory");
2657}
2658
2659#if defined _AIX
2660#include <sys/systemcfg.h>
2661
2662static void __attribute__((constructor)) tcg_cache_init(void)
2663{
2664 icache_bsize = _system_configuration.icache_line;
2665 dcache_bsize = _system_configuration.dcache_line;
2666}
2667
2668#elif defined __linux__
2669static void __attribute__((constructor)) tcg_cache_init(void)
2670{
2671 unsigned long dsize = qemu_getauxval(AT_DCACHEBSIZE);
2672 unsigned long isize = qemu_getauxval(AT_ICACHEBSIZE);
2673
2674 if (dsize == 0 || isize == 0) {
2675 if (dsize == 0) {
2676 fprintf(stderr, "getauxval AT_DCACHEBSIZE failed\n");
2677 }
2678 if (isize == 0) {
2679 fprintf(stderr, "getauxval AT_ICACHEBSIZE failed\n");
2680 }
2681 exit(1);
2682 }
2683 dcache_bsize = dsize;
2684 icache_bsize = isize;
2685}
2686
2687#elif defined __APPLE__
2688#include <stdio.h>
2689#include <sys/types.h>
2690#include <sys/sysctl.h>
2691
2692static void __attribute__((constructor)) tcg_cache_init(void)
2693{
2694 size_t len;
2695 unsigned cacheline;
2696 int name[2] = { CTL_HW, HW_CACHELINE };
2697
2698 len = sizeof(cacheline);
2699 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) {
2700 perror("sysctl CTL_HW HW_CACHELINE failed");
2701 exit(1);
2702 }
2703 dcache_bsize = cacheline;
2704 icache_bsize = cacheline;
2705}
2706
2707#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
2708#include <errno.h>
2709#include <stdio.h>
2710#include <stdlib.h>
2711#include <string.h>
2712#include <sys/types.h>
2713#include <sys/sysctl.h>
2714
2715static void __attribute__((constructor)) tcg_cache_init(void)
2716{
2717 size_t len = 4;
2718 unsigned cacheline;
2719
2720 if (sysctlbyname ("machdep.cacheline_size", &cacheline, &len, NULL, 0)) {
2721 fprintf(stderr, "sysctlbyname machdep.cacheline_size failed: %s\n",
2722 strerror(errno));
2723 exit(1);
2724 }
2725 dcache_bsize = cacheline;
2726 icache_bsize = cacheline;
2727}
2728#endif
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