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target-sparc: fix --enable-debug build for 64 bit host
[mirror_qemu.git] / tcg / ppc / tcg-target.c
CommitLineData
2662e13f
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25static uint8_t *tb_ret_addr;
26
6ec85236 27#ifdef _CALL_DARWIN
bf6bca52 28#define LINKAGE_AREA_SIZE 24
2946898b 29#define LR_OFFSET 8
6ec85236 30#elif defined _CALL_AIX
b29fe3ed 31#define LINKAGE_AREA_SIZE 52
32#define LR_OFFSET 8
f9bf2987 33#else
34#define LINKAGE_AREA_SIZE 8
2946898b 35#define LR_OFFSET 4
f9bf2987 36#endif
37
2662e13f
FB		 38#define FAST_PATH
39#if TARGET_PHYS_ADDR_BITS <= 32
40#define ADDEND_OFFSET 0
41#else
42#define ADDEND_OFFSET 4
43#endif
44
f6548c0a 45#ifndef GUEST_BASE
46#define GUEST_BASE 0
47#endif
48
49#ifdef CONFIG_USE_GUEST_BASE
50#define TCG_GUEST_BASE_REG 30
51#else
52#define TCG_GUEST_BASE_REG 0
53#endif
54
d4a9eb1f 55#ifndef NDEBUG
2662e13f
FB		 56static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
57 "r0",
58 "r1",
59 "rp",
60 "r3",
61 "r4",
62 "r5",
63 "r6",
64 "r7",
65 "r8",
66 "r9",
67 "r10",
68 "r11",
69 "r12",
70 "r13",
71 "r14",
72 "r15",
73 "r16",
74 "r17",
75 "r18",
76 "r19",
77 "r20",
78 "r21",
79 "r22",
80 "r23",
81 "r24",
82 "r25",
83 "r26",
84 "r27",
85 "r28",
86 "r29",
87 "r30",
88 "r31"
89};
d4a9eb1f 90#endif
2662e13f
FB		 91
92static const int tcg_target_reg_alloc_order[] = {
a35e86c5 93 TCG_REG_R14,
94 TCG_REG_R15,
95 TCG_REG_R16,
96 TCG_REG_R17,
97 TCG_REG_R18,
98 TCG_REG_R19,
99 TCG_REG_R20,
100 TCG_REG_R21,
101 TCG_REG_R22,
102 TCG_REG_R23,
103 TCG_REG_R28,
104 TCG_REG_R29,
105 TCG_REG_R30,
106 TCG_REG_R31,
6ec85236 107#ifdef _CALL_DARWIN
f9bf2987 108 TCG_REG_R2,
109#endif
2662e13f
FB		 110 TCG_REG_R3,
111 TCG_REG_R4,
112 TCG_REG_R5,
113 TCG_REG_R6,
114 TCG_REG_R7,
115 TCG_REG_R8,
116 TCG_REG_R9,
117 TCG_REG_R10,
6ec85236 118#ifndef _CALL_DARWIN
2662e13f 119 TCG_REG_R11,
f9bf2987 120#endif
2662e13f 121 TCG_REG_R12,
6ec85236 122#ifndef _CALL_SYSV
2662e13f 123 TCG_REG_R13,
5db3ee79 124#endif
2662e13f
FB		 125 TCG_REG_R24,
126 TCG_REG_R25,
127 TCG_REG_R26,
a35e86c5 128 TCG_REG_R27
2662e13f
FB		 129};
130
131static const int tcg_target_call_iarg_regs[] = {
132 TCG_REG_R3,
133 TCG_REG_R4,
134 TCG_REG_R5,
135 TCG_REG_R6,
136 TCG_REG_R7,
137 TCG_REG_R8,
138 TCG_REG_R9,
139 TCG_REG_R10
140};
141
142static const int tcg_target_call_oarg_regs[2] = {
143 TCG_REG_R3,
144 TCG_REG_R4
145};
146
147static const int tcg_target_callee_save_regs[] = {
6ec85236 148#ifdef _CALL_DARWIN
f9bf2987 149 TCG_REG_R11,
150 TCG_REG_R13,
b29fe3ed 151#endif
6ec85236 152#ifdef _CALL_AIX
b29fe3ed 153 TCG_REG_R13,
f9bf2987 154#endif
2662e13f
FB		 155 TCG_REG_R14,
156 TCG_REG_R15,
157 TCG_REG_R16,
158 TCG_REG_R17,
159 TCG_REG_R18,
160 TCG_REG_R19,
161 TCG_REG_R20,
162 TCG_REG_R21,
163 TCG_REG_R22,
164 TCG_REG_R23,
eb2eb1dc 165 TCG_REG_R24,
166 TCG_REG_R25,
167 TCG_REG_R26,
168 /* TCG_REG_R27, */ /* currently used for the global env, so no
169 need to save */
2662e13f
FB		 170 TCG_REG_R28,
171 TCG_REG_R29,
172 TCG_REG_R30,
173 TCG_REG_R31
174};
175
176static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
177{
932a6909
FB		 178 tcg_target_long disp;
179
180 disp = target - (tcg_target_long) pc;
181 if ((disp << 6) >> 6 != disp)
182 tcg_abort ();
183
184 return disp & 0x3fffffc;
2662e13f
FB		 185}
186
187static void reloc_pc24 (void *pc, tcg_target_long target)
188{
189 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
190 | reloc_pc24_val (pc, target);
191}
192
193static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
194{
932a6909
FB		 195 tcg_target_long disp;
196
197 disp = target - (tcg_target_long) pc;
198 if (disp != (int16_t) disp)
199 tcg_abort ();
200
201 return disp & 0xfffc;
2662e13f
FB		 202}
203
204static void reloc_pc14 (void *pc, tcg_target_long target)
205{
206 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
207 | reloc_pc14_val (pc, target);
208}
209
210static void patch_reloc(uint8_t *code_ptr, int type,
211 tcg_target_long value, tcg_target_long addend)
212{
213 value += addend;
214 switch (type) {
215 case R_PPC_REL14:
216 reloc_pc14 (code_ptr, value);
217 break;
218 case R_PPC_REL24:
219 reloc_pc24 (code_ptr, value);
220 break;
221 default:
222 tcg_abort();
223 }
224}
225
226/* maximum number of register used for input function arguments */
227static int tcg_target_get_call_iarg_regs_count(int flags)
228{
b1503cda 229 return ARRAY_SIZE (tcg_target_call_iarg_regs);
2662e13f
FB		 230}
231
232/* parse target specific constraints */
233static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
234{
235 const char *ct_str;
236
237 ct_str = *pct_str;
238 switch (ct_str[0]) {
398ce98e 239 case 'A': case 'B': case 'C': case 'D':
240 ct->ct |= TCG_CT_REG;
241 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
242 break;
2662e13f
FB		 243 case 'r':
244 ct->ct |= TCG_CT_REG;
245 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
246 break;
70fa887c 247#ifdef CONFIG_SOFTMMU
2662e13f
FB		 248 case 'L': /* qemu_ld constraint */
249 ct->ct |= TCG_CT_REG;
250 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 break;
254 case 'K': /* qemu_st[8..32] constraint */
255 ct->ct |= TCG_CT_REG;
256 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
257 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
258 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
259 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
260#if TARGET_LONG_BITS == 64
261 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
262#endif
263 break;
264 case 'M': /* qemu_st64 constraint */
265 ct->ct |= TCG_CT_REG;
266 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
267 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
268 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
269 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
270 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
271 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
272 break;
70fa887c 273#else
274 case 'L':
275 case 'K':
276 ct->ct |= TCG_CT_REG;
277 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
278 break;
279 case 'M':
280 ct->ct |= TCG_CT_REG;
281 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
282 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
283 break;
284#endif
2662e13f
FB		 285 default:
286 return -1;
287 }
288 ct_str++;
289 *pct_str = ct_str;
290 return 0;
291}
292
293/* test if a constant matches the constraint */
294static int tcg_target_const_match(tcg_target_long val,
295 const TCGArgConstraint *arg_ct)
296{
297 int ct;
298
299 ct = arg_ct->ct;
300 if (ct & TCG_CT_CONST)
301 return 1;
2662e13f
FB		 302 return 0;
303}
304
305#define OPCD(opc) ((opc)<<26)
306#define XO31(opc) (OPCD(31)|((opc)<<1))
307#define XO19(opc) (OPCD(19)|((opc)<<1))
308
309#define B OPCD(18)
310#define BC OPCD(16)
311#define LBZ OPCD(34)
312#define LHZ OPCD(40)
313#define LHA OPCD(42)
314#define LWZ OPCD(32)
315#define STB OPCD(38)
316#define STH OPCD(44)
317#define STW OPCD(36)
318
b0809bf7 319#define ADDIC OPCD(12)
2662e13f
FB		 320#define ADDI OPCD(14)
321#define ADDIS OPCD(15)
322#define ORI OPCD(24)
323#define ORIS OPCD(25)
324#define XORI OPCD(26)
325#define XORIS OPCD(27)
326#define ANDI OPCD(28)
327#define ANDIS OPCD(29)
328#define MULLI OPCD( 7)
329#define CMPLI OPCD(10)
330#define CMPI OPCD(11)
331
332#define LWZU OPCD(33)
333#define STWU OPCD(37)
334
335#define RLWINM OPCD(21)
65fe043e 336#define RLWNM OPCD(23)
2662e13f 337
c596defd 338#define BCLR XO19( 16)
2662e13f
FB		 339#define BCCTR XO19(528)
340#define CRAND XO19(257)
c596defd 341#define CRANDC XO19(129)
342#define CRNAND XO19(225)
343#define CROR XO19(449)
b0809bf7 344#define CRNOR XO19( 33)
2662e13f
FB		 345
346#define EXTSB XO31(954)
347#define EXTSH XO31(922)
348#define ADD XO31(266)
349#define ADDE XO31(138)
350#define ADDC XO31( 10)
351#define AND XO31( 28)
352#define SUBF XO31( 40)
353#define SUBFC XO31( 8)
354#define SUBFE XO31(136)
355#define OR XO31(444)
356#define XOR XO31(316)
357#define MULLW XO31(235)
358#define MULHWU XO31( 11)
359#define DIVW XO31(491)
360#define DIVWU XO31(459)
361#define CMP XO31( 0)
362#define CMPL XO31( 32)
363#define LHBRX XO31(790)
364#define LWBRX XO31(534)
365#define STHBRX XO31(918)
366#define STWBRX XO31(662)
367#define MFSPR XO31(339)
368#define MTSPR XO31(467)
369#define SRAWI XO31(824)
370#define NEG XO31(104)
b0809bf7 371#define MFCR XO31( 19)
372#define CNTLZW XO31( 26)
65fe043e 373#define NOR XO31(124)
374#define ANDC XO31( 60)
375#define ORC XO31(412)
2662e13f
FB		 376
377#define LBZX XO31( 87)
4f4a67ae 378#define LHZX XO31(279)
2662e13f
FB		 379#define LHAX XO31(343)
380#define LWZX XO31( 23)
381#define STBX XO31(215)
382#define STHX XO31(407)
383#define STWX XO31(151)
384
385#define SPR(a,b) ((((a)<<5)|(b))<<11)
386#define LR SPR(8, 0)
387#define CTR SPR(9, 0)
388
389#define SLW XO31( 24)
390#define SRW XO31(536)
391#define SRAW XO31(792)
392
2662e13f
FB		 393#define TW XO31(4)
394#define TRAP (TW | TO (31))
395
396#define RT(r) ((r)<<21)
397#define RS(r) ((r)<<21)
398#define RA(r) ((r)<<16)
399#define RB(r) ((r)<<11)
400#define TO(t) ((t)<<21)
401#define SH(s) ((s)<<11)
402#define MB(b) ((b)<<6)
403#define ME(e) ((e)<<1)
404#define BO(o) ((o)<<21)
405
406#define LK 1
407
408#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
409#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
410
411#define BF(n) ((n)<<23)
412#define BI(n, c) (((c)+((n)*4))<<16)
413#define BT(n, c) (((c)+((n)*4))<<21)
414#define BA(n, c) (((c)+((n)*4))<<16)
415#define BB(n, c) (((c)+((n)*4))<<11)
416
417#define BO_COND_TRUE BO (12)
418#define BO_COND_FALSE BO (4)
419#define BO_ALWAYS BO (20)
420
421enum {
422 CR_LT,
423 CR_GT,
424 CR_EQ,
425 CR_SO
426};
427
428static const uint32_t tcg_to_bc[10] = {
429 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
430 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
431 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
432 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
433 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
434 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
435 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
436 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
437 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
438 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
439};
440
441static void tcg_out_mov(TCGContext *s, int ret, int arg)
442{
443 tcg_out32 (s, OR | SAB (arg, ret, arg));
444}
445
446static void tcg_out_movi(TCGContext *s, TCGType type,
447 int ret, tcg_target_long arg)
448{
449 if (arg == (int16_t) arg)
450 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
451 else {
452 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
453 if (arg & 0xffff)
0a878c47 454 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
2662e13f
FB		 455 }
456}
457
458static void tcg_out_ldst (TCGContext *s, int ret, int addr,
459 int offset, int op1, int op2)
460{
461 if (offset == (int16_t) offset)
462 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
463 else {
464 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
465 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
466 }
467}
468
932a6909
FB		 469static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
470{
471 tcg_target_long disp;
472
473 disp = target - (tcg_target_long) s->code_ptr;
474 if ((disp << 6) >> 6 == disp)
8c5e95d8 475 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
932a6909
FB		 476 else {
477 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
478 tcg_out32 (s, MTSPR | RS (0) | CTR);
479 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
480 }
481}
482
b29fe3ed 483static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
484{
6ec85236 485#ifdef _CALL_AIX
b29fe3ed 486 int reg;
487
488 if (const_arg) {
489 reg = 2;
490 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
491 }
492 else reg = arg;
493
494 tcg_out32 (s, LWZ | RT (0) | RA (reg));
495 tcg_out32 (s, MTSPR | RA (0) | CTR);
496 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
497 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
d9370327 498#else
499 if (const_arg) {
500 tcg_out_b (s, LK, arg);
501 }
502 else {
503 tcg_out32 (s, MTSPR | RS (arg) | LR);
504 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
505 }
b29fe3ed 506#endif
d9370327 507}
b29fe3ed 508
2662e13f 509#if defined(CONFIG_SOFTMMU)
79383c9c
BS		 510
511#include "../../softmmu_defs.h"
2662e13f
FB		 512
513static void *qemu_ld_helpers[4] = {
514 __ldb_mmu,
515 __ldw_mmu,
516 __ldl_mmu,
517 __ldq_mmu,
518};
519
520static void *qemu_st_helpers[4] = {
521 __stb_mmu,
522 __stw_mmu,
523 __stl_mmu,
524 __stq_mmu,
525};
526#endif
527
528static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
529{
f6548c0a 530 int addr_reg, data_reg, data_reg2, r0, r1, rbase, mem_index, s_bits, bswap;
2662e13f 531#ifdef CONFIG_SOFTMMU
f8edcbaa 532 int r2;
2662e13f
FB		 533 void *label1_ptr, *label2_ptr;
534#endif
535#if TARGET_LONG_BITS == 64
536 int addr_reg2;
537#endif
538
539 data_reg = *args++;
540 if (opc == 3)
541 data_reg2 = *args++;
542 else
543 data_reg2 = 0;
544 addr_reg = *args++;
545#if TARGET_LONG_BITS == 64
546 addr_reg2 = *args++;
547#endif
548 mem_index = *args;
549 s_bits = opc & 3;
550
551#ifdef CONFIG_SOFTMMU
552 r0 = 3;
553 r1 = 4;
554 r2 = 0;
f6548c0a 555 rbase = 0;
2662e13f
FB		 556
557 tcg_out32 (s, (RLWINM
558 | RA (r0)
559 | RS (addr_reg)
560 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
561 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
562 | ME (31 - CPU_TLB_ENTRY_BITS)
563 )
564 );
565 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
566 tcg_out32 (s, (LWZU
567 | RT (r1)
568 | RA (r0)
569 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
570 )
571 );
572 tcg_out32 (s, (RLWINM
573 | RA (r2)
574 | RS (addr_reg)
575 | SH (0)
576 | MB ((32 - s_bits) & 31)
577 | ME (31 - TARGET_PAGE_BITS)
578 )
579 );
580
581 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
582#if TARGET_LONG_BITS == 64
583 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
584 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
585 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
586#endif
587
588 label1_ptr = s->code_ptr;
589#ifdef FAST_PATH
590 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
591#endif
592
593 /* slow path */
594#if TARGET_LONG_BITS == 32
595 tcg_out_mov (s, 3, addr_reg);
596 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
597#else
598 tcg_out_mov (s, 3, addr_reg2);
599 tcg_out_mov (s, 4, addr_reg);
600 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
601#endif
602
b29fe3ed 603 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
2662e13f
FB		 604 switch (opc) {
605 case 0|4:
606 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
607 break;
608 case 1|4:
609 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
610 break;
611 case 0:
612 case 1:
613 case 2:
614 if (data_reg != 3)
615 tcg_out_mov (s, data_reg, 3);
616 break;
617 case 3:
618 if (data_reg == 3) {
619 if (data_reg2 == 4) {
620 tcg_out_mov (s, 0, 4);
621 tcg_out_mov (s, 4, 3);
622 tcg_out_mov (s, 3, 0);
623 }
624 else {
625 tcg_out_mov (s, data_reg2, 3);
626 tcg_out_mov (s, 3, 4);
627 }
628 }
629 else {
630 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
631 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
632 }
633 break;
634 }
635 label2_ptr = s->code_ptr;
636 tcg_out32 (s, B);
637
638 /* label1: fast path */
639#ifdef FAST_PATH
640 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
641#endif
642
643 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
644 tcg_out32 (s, (LWZ
645 | RT (r0)
646 | RA (r0)
647 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
648 - offsetof (CPUTLBEntry, addr_read))
649 ));
650 /* r0 = env->tlb_table[mem_index][index].addend */
651 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
652 /* r0 = env->tlb_table[mem_index][index].addend + addr */
653
654#else /* !CONFIG_SOFTMMU */
655 r0 = addr_reg;
f8edcbaa 656 r1 = 3;
f6548c0a 657 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
2662e13f
FB		 658#endif
659
660#ifdef TARGET_WORDS_BIGENDIAN
661 bswap = 0;
662#else
663 bswap = 1;
664#endif
f6548c0a 665
2662e13f
FB		 666 switch (opc) {
667 default:
668 case 0:
f6548c0a 669 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 670 break;
671 case 0|4:
f6548c0a 672 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 673 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
674 break;
675 case 1:
f6548c0a 676 if (bswap)
677 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
678 else
679 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 680 break;
681 case 1|4:
682 if (bswap) {
f6548c0a 683 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
2662e13f
FB		 684 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
685 }
f6548c0a 686 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
2662e13f
FB		 687 break;
688 case 2:
f6548c0a 689 if (bswap)
690 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
691 else
692 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 693 break;
694 case 3:
695 if (bswap) {
f6548c0a 696 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
697 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
698 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
2662e13f
FB		 699 }
700 else {
f6548c0a 701#ifdef CONFIG_USE_GUEST_BASE
702 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
703 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
704 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
705#else
2662e13f
FB		 706 if (r0 == data_reg2) {
707 tcg_out32 (s, LWZ | RT (0) | RA (r0));
708 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
709 tcg_out_mov (s, data_reg2, 0);
710 }
711 else {
712 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
713 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
714 }
f6548c0a 715#endif
2662e13f
FB		 716 }
717 break;
718 }
719
720#ifdef CONFIG_SOFTMMU
721 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
722#endif
723}
724
725static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
726{
f6548c0a 727 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap, rbase;
2662e13f
FB		 728#ifdef CONFIG_SOFTMMU
729 int r2, ir;
730 void *label1_ptr, *label2_ptr;
731#endif
732#if TARGET_LONG_BITS == 64
733 int addr_reg2;
734#endif
735
736 data_reg = *args++;
737 if (opc == 3)
738 data_reg2 = *args++;
739 else
740 data_reg2 = 0;
741 addr_reg = *args++;
742#if TARGET_LONG_BITS == 64
743 addr_reg2 = *args++;
744#endif
745 mem_index = *args;
746
747#ifdef CONFIG_SOFTMMU
748 r0 = 3;
749 r1 = 4;
750 r2 = 0;
f6548c0a 751 rbase = 0;
2662e13f
FB		 752
753 tcg_out32 (s, (RLWINM
754 | RA (r0)
755 | RS (addr_reg)
756 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
757 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
758 | ME (31 - CPU_TLB_ENTRY_BITS)
759 )
760 );
761 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
762 tcg_out32 (s, (LWZU
763 | RT (r1)
764 | RA (r0)
765 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
766 )
767 );
768 tcg_out32 (s, (RLWINM
769 | RA (r2)
770 | RS (addr_reg)
771 | SH (0)
772 | MB ((32 - opc) & 31)
773 | ME (31 - TARGET_PAGE_BITS)
774 )
775 );
776
777 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
778#if TARGET_LONG_BITS == 64
779 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
780 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
781 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
782#endif
783
784 label1_ptr = s->code_ptr;
785#ifdef FAST_PATH
786 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
787#endif
788
789 /* slow path */
790#if TARGET_LONG_BITS == 32
791 tcg_out_mov (s, 3, addr_reg);
792 ir = 4;
793#else
794 tcg_out_mov (s, 3, addr_reg2);
795 tcg_out_mov (s, 4, addr_reg);
f9bf2987 796#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2662e13f 797 ir = 5;
f9bf2987 798#else
799 ir = 4;
800#endif
2662e13f
FB		 801#endif
802
803 switch (opc) {
804 case 0:
805 tcg_out32 (s, (RLWINM
806 | RA (ir)
807 | RS (data_reg)
808 | SH (0)
809 | MB (24)
810 | ME (31)));
811 break;
812 case 1:
813 tcg_out32 (s, (RLWINM
814 | RA (ir)
815 | RS (data_reg)
816 | SH (0)
817 | MB (16)
818 | ME (31)));
819 break;
820 case 2:
821 tcg_out_mov (s, ir, data_reg);
822 break;
823 case 3:
f9bf2987 824#ifdef TCG_TARGET_CALL_ALIGN_ARGS
825 ir = 5;
826#endif
827 tcg_out_mov (s, ir++, data_reg2);
828 tcg_out_mov (s, ir, data_reg);
2662e13f
FB		 829 break;
830 }
831 ir++;
832
833 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
b29fe3ed 834 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
2662e13f
FB		 835 label2_ptr = s->code_ptr;
836 tcg_out32 (s, B);
837
838 /* label1: fast path */
839#ifdef FAST_PATH
840 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
841#endif
842
843 tcg_out32 (s, (LWZ
844 | RT (r0)
845 | RA (r0)
846 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
847 - offsetof (CPUTLBEntry, addr_write))
848 ));
849 /* r0 = env->tlb_table[mem_index][index].addend */
850 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
851 /* r0 = env->tlb_table[mem_index][index].addend + addr */
852
853#else /* !CONFIG_SOFTMMU */
2662e13f 854 r0 = addr_reg;
f6548c0a 855 r1 = 3;
a71836de 856 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
2662e13f
FB		 857#endif
858
859#ifdef TARGET_WORDS_BIGENDIAN
860 bswap = 0;
861#else
862 bswap = 1;
863#endif
864 switch (opc) {
865 case 0:
f6548c0a 866 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
2662e13f
FB		 867 break;
868 case 1:
f6548c0a 869 if (bswap)
870 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
871 else
872 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
2662e13f
FB		 873 break;
874 case 2:
f6548c0a 875 if (bswap)
876 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
877 else
878 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
2662e13f
FB		 879 break;
880 case 3:
881 if (bswap) {
882 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
f6548c0a 883 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
884 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
2662e13f
FB		 885 }
886 else {
f6548c0a 887#ifdef CONFIG_USE_GUEST_BASE
888 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
889 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
890 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
891#else
2662e13f
FB		 892 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
893 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
f6548c0a 894#endif
2662e13f
FB		 895 }
896 break;
897 }
898
899#ifdef CONFIG_SOFTMMU
900 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
901#endif
902}
903
904void tcg_target_qemu_prologue (TCGContext *s)
905{
0d5bd363 906 int i, frame_size;
2662e13f
FB		 907
908 frame_size = 0
f9bf2987 909 + LINKAGE_AREA_SIZE
2662e13f
FB		 910 + TCG_STATIC_CALL_ARGS_SIZE
911 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
912 ;
913 frame_size = (frame_size + 15) & ~15;
914
6ec85236 915#ifdef _CALL_AIX
b29fe3ed 916 {
917 uint32_t addr;
918
919 /* First emit adhoc function descriptor */
920 addr = (uint32_t) s->code_ptr + 12;
921 tcg_out32 (s, addr); /* entry point */
922 s->code_ptr += 8; /* skip TOC and environment pointer */
923 }
924#endif
2662e13f
FB		 925 tcg_out32 (s, MFSPR | RT (0) | LR);
926 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
927 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
928 tcg_out32 (s, (STW
929 | RS (tcg_target_callee_save_regs[i])
930 | RA (1)
f9bf2987 931 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
2662e13f
FB		 932 )
933 );
2946898b 934 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
2662e13f 935
f6548c0a 936#ifdef CONFIG_USE_GUEST_BASE
937 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
938#endif
939
2662e13f
FB		 940 tcg_out32 (s, MTSPR | RS (3) | CTR);
941 tcg_out32 (s, BCCTR | BO_ALWAYS);
942 tb_ret_addr = s->code_ptr;
943
944 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
945 tcg_out32 (s, (LWZ
946 | RT (tcg_target_callee_save_regs[i])
947 | RA (1)
f9bf2987 948 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
2662e13f
FB		 949 )
950 );
2946898b 951 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
2662e13f
FB		 952 tcg_out32 (s, MTSPR | RS (0) | LR);
953 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
954 tcg_out32 (s, BCLR | BO_ALWAYS);
955}
956
957static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
958 tcg_target_long arg2)
959{
960 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
961}
962
963static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
964 tcg_target_long arg2)
965{
966 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
967}
968
969static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
970{
971 if (!si && rt == ra)
972 return;
973
974 if (si == (int16_t) si)
975 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
976 else {
977 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
978 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
979 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
980 }
981}
982
983static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
984{
985 ppc_addi (s, reg, reg, val);
986}
987
c596defd 988static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
989 int const_arg2, int cr)
2662e13f 990{
2662e13f
FB		 991 int imm;
992 uint32_t op;
993
2662e13f 994 switch (cond) {
f3f478a7
FB		 995 case TCG_COND_EQ:
996 case TCG_COND_NE:
997 if (const_arg2) {
998 if ((int16_t) arg2 == arg2) {
999 op = CMPI;
1000 imm = 1;
1001 break;
1002 }
1003 else if ((uint16_t) arg2 == arg2) {
1004 op = CMPLI;
1005 imm = 1;
1006 break;
1007 }
1008 }
1009 op = CMPL;
1010 imm = 0;
1011 break;
1012
1013 case TCG_COND_LT:
1014 case TCG_COND_GE:
1015 case TCG_COND_LE:
1016 case TCG_COND_GT:
1017 if (const_arg2) {
1018 if ((int16_t) arg2 == arg2) {
1019 op = CMPI;
1020 imm = 1;
1021 break;
1022 }
1023 }
1024 op = CMP;
1025 imm = 0;
1026 break;
1027
1028 case TCG_COND_LTU:
1029 case TCG_COND_GEU:
1030 case TCG_COND_LEU:
1031 case TCG_COND_GTU:
1032 if (const_arg2) {
1033 if ((uint16_t) arg2 == arg2) {
1034 op = CMPLI;
1035 imm = 1;
1036 break;
1037 }
1038 }
1039 op = CMPL;
1040 imm = 0;
1041 break;
1042
2662e13f
FB		 1043 default:
1044 tcg_abort ();
1045 }
c596defd 1046 op |= BF (cr);
2662e13f
FB		 1047
1048 if (imm)
1049 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1050 else {
1051 if (const_arg2) {
1052 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1053 tcg_out32 (s, op | RA (arg1) | RB (0));
1054 }
1055 else
1056 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1057 }
1058
c596defd 1059}
1060
1061static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1062{
1063 TCGLabel *l = &s->labels[label_index];
1064
0a878c47 1065 if (l->has_value)
c596defd 1066 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
2662e13f 1067 else {
0a878c47 1068 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1069
1070 /* Thanks to Andrzej Zaborowski */
c596defd 1071 tcg_out32 (s, bc | (val & 0xfffc));
2662e13f
FB		 1072 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1073 }
1074}
1075
b0809bf7 1076static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
1077 const int *const_args)
c596defd 1078{
b0809bf7 1079 int cond = args[4], op;
c596defd 1080 struct { int bit1; int bit2; int cond2; } bits[] = {
1081 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1082 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1083 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1084 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1085 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1086 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1087 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1088 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1089 }, *b = &bits[cond];
1090
1091 switch (cond) {
2662e13f 1092 case TCG_COND_EQ:
2662e13f 1093 case TCG_COND_NE:
e924c485 1094 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1095 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1096 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1097 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
2662e13f
FB		 1098 break;
1099 case TCG_COND_LT:
2662e13f 1100 case TCG_COND_LE:
2662e13f 1101 case TCG_COND_GT:
2662e13f 1102 case TCG_COND_GE:
2662e13f 1103 case TCG_COND_LTU:
2662e13f 1104 case TCG_COND_LEU:
2662e13f 1105 case TCG_COND_GTU:
2662e13f 1106 case TCG_COND_GEU:
c596defd 1107 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1108 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1109 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1110 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1111 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1112 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
2662e13f
FB		 1113 break;
1114 default:
1115 tcg_abort();
1116 }
b0809bf7 1117}
1118
1119static void tcg_out_setcond (TCGContext *s, int cond, TCGArg arg0,
1120 TCGArg arg1, TCGArg arg2, int const_arg2)
1121{
1122 int crop, sh, arg;
1123
1124 switch (cond) {
1125 case TCG_COND_EQ:
1126 if (const_arg2) {
1127 if (!arg2) {
1128 arg = arg1;
1129 }
1130 else {
1131 arg = 0;
1132 if ((uint16_t) arg2 == arg2) {
1133 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1134 }
1135 else {
1136 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1137 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1138 }
1139 }
1140 }
1141 else {
1142 arg = 0;
1143 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1144 }
1145 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1146 tcg_out32 (s, (RLWINM
1147 | RA (arg0)
1148 | RS (0)
1149 | SH (27)
1150 | MB (5)
1151 | ME (31)
1152 )
1153 );
27a7797b 1154 break;
b0809bf7 1155
1156 case TCG_COND_NE:
1157 if (const_arg2) {
1158 if (!arg2) {
1159 arg = arg1;
1160 }
1161 else {
1162 arg = 0;
1163 if ((uint16_t) arg2 == arg2) {
1164 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1165 }
1166 else {
1167 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1168 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1169 }
1170 }
1171 }
1172 else {
1173 arg = 0;
1174 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1175 }
1176
1177 if (arg == arg1 && arg1 == arg0) {
1178 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1179 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1180 }
1181 else {
1182 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1183 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1184 }
27a7797b 1185 break;
1186
1187 case TCG_COND_GT:
1188 case TCG_COND_GTU:
1189 sh = 30;
1190 crop = 0;
1191 goto crtest;
b0809bf7 1192
b0809bf7 1193 case TCG_COND_LT:
27a7797b 1194 case TCG_COND_LTU:
b0809bf7 1195 sh = 29;
1196 crop = 0;
27a7797b 1197 goto crtest;
b0809bf7 1198
b0809bf7 1199 case TCG_COND_GE:
27a7797b 1200 case TCG_COND_GEU:
b0809bf7 1201 sh = 31;
1202 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
27a7797b 1203 goto crtest;
b0809bf7 1204
b0809bf7 1205 case TCG_COND_LE:
27a7797b 1206 case TCG_COND_LEU:
b0809bf7 1207 sh = 31;
1208 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
27a7797b 1209 crtest:
1210 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1211 if (crop) tcg_out32 (s, crop);
1212 tcg_out32 (s, MFCR | RT (0));
1213 tcg_out32 (s, (RLWINM
1214 | RA (arg0)
1215 | RS (0)
1216 | SH (sh)
1217 | MB (31)
1218 | ME (31)
1219 )
1220 );
b0809bf7 1221 break;
1222
1223 default:
1224 tcg_abort ();
1225 }
b0809bf7 1226}
1227
1228static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
1229 const int *const_args)
1230{
1231 tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
1232 tcg_out32 (s, MFCR | RT (0));
1233 tcg_out32 (s, (RLWINM
1234 | RA (args[0])
1235 | RS (0)
1236 | SH (31)
1237 | MB (31)
1238 | ME (31)
1239 )
1240 );
1241}
1242
1243static void tcg_out_brcond (TCGContext *s, int cond,
1244 TCGArg arg1, TCGArg arg2, int const_arg2,
1245 int label_index)
1246{
1247 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1248 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1249}
1250
1251/* XXX: we implement it at the target level to avoid having to
1252 handle cross basic blocks temporaries */
1253static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1254 const int *const_args)
1255{
1256 tcg_out_cr7eq_from_cond (s, args, const_args);
1257 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
2662e13f
FB		 1258}
1259
52781543 1260void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1261{
1262 uint32_t *ptr;
1263 long disp = addr - jmp_addr;
1264 unsigned long patch_size;
1265
1266 ptr = (uint32_t *)jmp_addr;
1267
1268 if ((disp << 6) >> 6 != disp) {
1269 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1270 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1271 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1272 ptr[3] = 0x4e800420; /* brctr */
1273 patch_size = 16;
1274 } else {
1275 /* patch the branch destination */
1276 if (disp != 16) {
1277 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1278 patch_size = 4;
1279 } else {
1280 ptr[0] = 0x60000000; /* nop */
1281 ptr[1] = 0x60000000;
1282 ptr[2] = 0x60000000;
1283 ptr[3] = 0x60000000;
1284 patch_size = 16;
1285 }
1286 }
1287 /* flush icache */
1288 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1289}
1290
2662e13f
FB		 1291static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1292 const int *const_args)
1293{
1294 switch (opc) {
1295 case INDEX_op_exit_tb:
1296 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
932a6909 1297 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
2662e13f
FB		 1298 break;
1299 case INDEX_op_goto_tb:
1300 if (s->tb_jmp_offset) {
1301 /* direct jump method */
932a6909 1302
2662e13f 1303 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
0a878c47 1304 s->code_ptr += 16;
932a6909
FB		 1305 }
1306 else {
2662e13f
FB		 1307 tcg_abort ();
1308 }
1309 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1310 break;
1311 case INDEX_op_br:
1312 {
1313 TCGLabel *l = &s->labels[args[0]];
1314
1315 if (l->has_value) {
932a6909 1316 tcg_out_b (s, 0, l->u.value);
2662e13f
FB		 1317 }
1318 else {
0a878c47 1319 uint32_t val = *(uint32_t *) s->code_ptr;
1320
1321 /* Thanks to Andrzej Zaborowski */
1322 tcg_out32 (s, B | (val & 0x3fffffc));
2662e13f
FB		 1323 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1324 }
1325 }
1326 break;
1327 case INDEX_op_call:
b29fe3ed 1328 tcg_out_call (s, args[0], const_args[0]);
2662e13f
FB		 1329 break;
1330 case INDEX_op_jmp:
1331 if (const_args[0]) {
932a6909 1332 tcg_out_b (s, 0, args[0]);
2662e13f
FB		 1333 }
1334 else {
1335 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1336 tcg_out32 (s, BCCTR | BO_ALWAYS);
1337 }
1338 break;
1339 case INDEX_op_movi_i32:
1340 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1341 break;
1342 case INDEX_op_ld8u_i32:
1343 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1344 break;
1345 case INDEX_op_ld8s_i32:
1346 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1347 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1348 break;
1349 case INDEX_op_ld16u_i32:
1350 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1351 break;
1352 case INDEX_op_ld16s_i32:
1353 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1354 break;
1355 case INDEX_op_ld_i32:
1356 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1357 break;
1358 case INDEX_op_st8_i32:
1359 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1360 break;
1361 case INDEX_op_st16_i32:
1362 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1363 break;
1364 case INDEX_op_st_i32:
1365 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1366 break;
1367
1368 case INDEX_op_add_i32:
1369 if (const_args[2])
1370 ppc_addi (s, args[0], args[1], args[2]);
1371 else
1372 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1373 break;
1374 case INDEX_op_sub_i32:
1375 if (const_args[2])
1376 ppc_addi (s, args[0], args[1], -args[2]);
1377 else
1378 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1379 break;
1380
1381 case INDEX_op_and_i32:
1382 if (const_args[2]) {
c45851c4 1383 uint32_t c;
1384
1385 c = args[2];
1386
1387 if (!c) {
1388 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1389 break;
1390 }
1391#ifdef __PPU__
1392 uint32_t t, n;
1393 int mb, me;
1394
1395 n = c ^ -(c & 1);
1396 t = n + (n & -n);
1397
1398 if ((t & (t - 1)) == 0) {
1399 int lzc, tzc;
1400
1401 if ((c & 0x80000001) == 0x80000001) {
1402 lzc = clz32 (n);
1403 tzc = ctz32 (n);
1404
1405 mb = 32 - tzc;
1406 me = lzc - 1;
1407 }
1408 else {
1409 lzc = clz32 (c);
1410 tzc = ctz32 (c);
1411
1412 mb = lzc;
1413 me = 31 - tzc;
1414 }
1415
1416 tcg_out32 (s, (RLWINM
1417 | RA (args[0])
1418 | RS (args[1])
1419 | SH (0)
1420 | MB (mb)
1421 | ME (me)
1422 )
1423 );
1424 }
1425 else
1426#endif /* !__PPU__ */
1427 {
1428 if ((c & 0xffff) == c)
1429 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1430 else if ((c & 0xffff0000) == c)
1431 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1432 | ((c >> 16) & 0xffff));
1433 else {
1434 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1435 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1436 }
2662e13f
FB		 1437 }
1438 }
1439 else
1440 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1441 break;
1442 case INDEX_op_or_i32:
1443 if (const_args[2]) {
000a2d86 1444 if (args[2] & 0xffff) {
1445 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1446 | (args[2] & 0xffff));
1447 if (args[2] >> 16)
1448 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
2662e13f 1449 | ((args[2] >> 16) & 0xffff));
2662e13f
FB		 1450 }
1451 else {
000a2d86 1452 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1453 | ((args[2] >> 16) & 0xffff));
2662e13f
FB		 1454 }
1455 }
1456 else
1457 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1458 break;
1459 case INDEX_op_xor_i32:
1460 if (const_args[2]) {
000a2d86 1461 if ((args[2] & 0xffff) == args[2])
1462 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1463 | (args[2] & 0xffff));
1464 else if ((args[2] & 0xffff0000) == args[2])
1465 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1466 | ((args[2] >> 16) & 0xffff));
2662e13f 1467 else {
000a2d86 1468 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1469 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
2662e13f
FB		 1470 }
1471 }
1472 else
1473 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1474 break;
65fe043e 1475 case INDEX_op_andc_i32:
1476 tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2]));
1477 break;
1478 case INDEX_op_orc_i32:
1479 tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
1480 break;
2662e13f
FB		 1481
1482 case INDEX_op_mul_i32:
1483 if (const_args[2]) {
1484 if (args[2] == (int16_t) args[2])
1485 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1486 | (args[2] & 0xffff));
1487 else {
1488 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1489 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1490 }
1491 }
1492 else
1493 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1494 break;
77b73de6 1495
1496 case INDEX_op_div_i32:
1497 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1498 break;
1499
1500 case INDEX_op_divu_i32:
1501 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1502 break;
1503
1504 case INDEX_op_rem_i32:
1505 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1506 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1507 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1508 break;
1509
1510 case INDEX_op_remu_i32:
1511 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1512 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1513 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1514 break;
1515
2662e13f
FB		 1516 case INDEX_op_mulu2_i32:
1517 if (args[0] == args[2] || args[0] == args[3]) {
1518 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1519 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1520 tcg_out_mov (s, args[0], 0);
1521 }
1522 else {
1523 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1524 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1525 }
1526 break;
2662e13f
FB		 1527
1528 case INDEX_op_shl_i32:
1529 if (const_args[2]) {
000a2d86 1530 tcg_out32 (s, (RLWINM
1531 | RA (args[0])
1532 | RS (args[1])
1533 | SH (args[2])
1534 | MB (0)
1535 | ME (31 - args[2])
1536 )
1537 );
2662e13f
FB		 1538 }
1539 else
1540 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1541 break;
1542 case INDEX_op_shr_i32:
1543 if (const_args[2]) {
000a2d86 1544 tcg_out32 (s, (RLWINM
1545 | RA (args[0])
1546 | RS (args[1])
1547 | SH (32 - args[2])
1548 | MB (args[2])
1549 | ME (31)
1550 )
1551 );
2662e13f
FB		 1552 }
1553 else
1554 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1555 break;
1556 case INDEX_op_sar_i32:
1557 if (const_args[2])
1558 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1559 else
1560 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1561 break;
65fe043e 1562 case INDEX_op_rotl_i32:
1563 {
1564 int op = 0
1565 | RA (args[0])
1566 | RS (args[1])
1567 | MB (0)
1568 | ME (31)
1569 | (const_args[2] ? RLWINM | SH (args[2])
1570 : RLWNM | RB (args[2]))
1571 ;
1572 tcg_out32 (s, op);
1573 }
1574 break;
1575 case INDEX_op_rotr_i32:
1576 if (const_args[2]) {
1577 if (!args[2]) {
98b8d951 1578 tcg_out_mov (s, args[0], args[1]);
65fe043e 1579 }
1580 else {
1581 tcg_out32 (s, RLWINM
1582 | RA (args[0])
1583 | RS (args[1])
1584 | SH (32 - args[2])
1585 | MB (0)
1586 | ME (31)
1587 );
1588 }
1589 }
1590 else {
1591 tcg_out32 (s, ADDI | RT (0) | RA (args[2]) | 0xffe0);
1592 tcg_out32 (s, RLWNM
1593 | RA (args[0])
1594 | RS (args[1])
1595 | RB (0)
1596 | MB (0)
1597 | ME (31)
1598 );
1599 }
1600 break;
2662e13f
FB		 1601
1602 case INDEX_op_add2_i32:
1603 if (args[0] == args[3] || args[0] == args[5]) {
1604 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1605 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1606 tcg_out_mov (s, args[0], 0);
1607 }
1608 else {
1609 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1610 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1611 }
1612 break;
1613 case INDEX_op_sub2_i32:
1614 if (args[0] == args[3] || args[0] == args[5]) {
1615 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1616 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1617 tcg_out_mov (s, args[0], 0);
1618 }
1619 else {
1620 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1621 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1622 }
1623 break;
1624
1625 case INDEX_op_brcond_i32:
1626 /*
1627 args[0] = r0
1628 args[1] = r1
1629 args[2] = cond
1630 args[3] = r1 is const
1631 args[4] = label_index
1632 */
1633 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1634 break;
1635 case INDEX_op_brcond2_i32:
1636 tcg_out_brcond2(s, args, const_args);
1637 break;
1638
1639 case INDEX_op_neg_i32:
1640 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1641 break;
1642
65fe043e 1643 case INDEX_op_not_i32:
1644 tcg_out32 (s, NOR | SAB (args[1], args[0], args[0]));
1645 break;
1646
2662e13f
FB		 1647 case INDEX_op_qemu_ld8u:
1648 tcg_out_qemu_ld(s, args, 0);
1649 break;
1650 case INDEX_op_qemu_ld8s:
1651 tcg_out_qemu_ld(s, args, 0 | 4);
1652 break;
1653 case INDEX_op_qemu_ld16u:
1654 tcg_out_qemu_ld(s, args, 1);
1655 break;
1656 case INDEX_op_qemu_ld16s:
1657 tcg_out_qemu_ld(s, args, 1 | 4);
1658 break;
1659 case INDEX_op_qemu_ld32u:
1660 tcg_out_qemu_ld(s, args, 2);
1661 break;
1662 case INDEX_op_qemu_ld64:
1663 tcg_out_qemu_ld(s, args, 3);
1664 break;
1665 case INDEX_op_qemu_st8:
1666 tcg_out_qemu_st(s, args, 0);
1667 break;
1668 case INDEX_op_qemu_st16:
1669 tcg_out_qemu_st(s, args, 1);
1670 break;
1671 case INDEX_op_qemu_st32:
1672 tcg_out_qemu_st(s, args, 2);
1673 break;
1674 case INDEX_op_qemu_st64:
1675 tcg_out_qemu_st(s, args, 3);
1676 break;
1677
e46b9681 1678 case INDEX_op_ext8s_i32:
1679 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1680 break;
65fe043e 1681 case INDEX_op_ext8u_i32:
1682 tcg_out32 (s, RLWINM
1683 | RA (args[0])
1684 | RS (args[1])
1685 | SH (0)
1686 | MB (24)
1687 | ME (31)
1688 );
1689 break;
e46b9681 1690 case INDEX_op_ext16s_i32:
1691 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1692 break;
65fe043e 1693 case INDEX_op_ext16u_i32:
1694 tcg_out32 (s, RLWINM
1695 | RA (args[0])
1696 | RS (args[1])
1697 | SH (0)
1698 | MB (16)
1699 | ME (31)
1700 );
1701 break;
e46b9681 1702
b0809bf7 1703 case INDEX_op_setcond_i32:
1704 tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
1705 break;
1706 case INDEX_op_setcond2_i32:
1707 tcg_out_setcond2 (s, args, const_args);
1708 break;
1709
2662e13f
FB		 1710 default:
1711 tcg_dump_ops (s, stderr);
1712 tcg_abort ();
1713 }
1714}
1715
1716static const TCGTargetOpDef ppc_op_defs[] = {
1717 { INDEX_op_exit_tb, { } },
1718 { INDEX_op_goto_tb, { } },
932a6909
FB		 1719 { INDEX_op_call, { "ri" } },
1720 { INDEX_op_jmp, { "ri" } },
2662e13f
FB		 1721 { INDEX_op_br, { } },
1722
1723 { INDEX_op_mov_i32, { "r", "r" } },
1724 { INDEX_op_movi_i32, { "r" } },
1725 { INDEX_op_ld8u_i32, { "r", "r" } },
1726 { INDEX_op_ld8s_i32, { "r", "r" } },
1727 { INDEX_op_ld16u_i32, { "r", "r" } },
1728 { INDEX_op_ld16s_i32, { "r", "r" } },
1729 { INDEX_op_ld_i32, { "r", "r" } },
1730 { INDEX_op_st8_i32, { "r", "r" } },
1731 { INDEX_op_st16_i32, { "r", "r" } },
1732 { INDEX_op_st_i32, { "r", "r" } },
1733
1734 { INDEX_op_add_i32, { "r", "r", "ri" } },
1735 { INDEX_op_mul_i32, { "r", "r", "ri" } },
77b73de6 1736 { INDEX_op_div_i32, { "r", "r", "r" } },
1737 { INDEX_op_divu_i32, { "r", "r", "r" } },
1738 { INDEX_op_rem_i32, { "r", "r", "r" } },
1739 { INDEX_op_remu_i32, { "r", "r", "r" } },
2662e13f 1740 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
2662e13f
FB		 1741 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1742 { INDEX_op_and_i32, { "r", "r", "ri" } },
1743 { INDEX_op_or_i32, { "r", "r", "ri" } },
1744 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1745
1746 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1747 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1748 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1749
65fe043e 1750 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1751 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1752
2662e13f
FB		 1753 { INDEX_op_brcond_i32, { "r", "ri" } },
1754
1755 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1756 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1757 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1758
1759 { INDEX_op_neg_i32, { "r", "r" } },
65fe043e 1760 { INDEX_op_not_i32, { "r", "r" } },
1761
1762 { INDEX_op_andc_i32, { "r", "r", "r" } },
1763 { INDEX_op_orc_i32, { "r", "r", "r" } },
2662e13f 1764
b0809bf7 1765 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1766 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
1767
2662e13f
FB		 1768#if TARGET_LONG_BITS == 32
1769 { INDEX_op_qemu_ld8u, { "r", "L" } },
1770 { INDEX_op_qemu_ld8s, { "r", "L" } },
1771 { INDEX_op_qemu_ld16u, { "r", "L" } },
1772 { INDEX_op_qemu_ld16s, { "r", "L" } },
1773 { INDEX_op_qemu_ld32u, { "r", "L" } },
2662e13f
FB		 1774 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1775
1776 { INDEX_op_qemu_st8, { "K", "K" } },
1777 { INDEX_op_qemu_st16, { "K", "K" } },
1778 { INDEX_op_qemu_st32, { "K", "K" } },
1779 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1780#else
1781 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1782 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1783 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1784 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1785 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
2662e13f
FB		 1786 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1787
1788 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1789 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1790 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1791 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1792#endif
1793
e46b9681 1794 { INDEX_op_ext8s_i32, { "r", "r" } },
65fe043e 1795 { INDEX_op_ext8u_i32, { "r", "r" } },
e46b9681 1796 { INDEX_op_ext16s_i32, { "r", "r" } },
65fe043e 1797 { INDEX_op_ext16u_i32, { "r", "r" } },
e46b9681 1798
2662e13f
FB		 1799 { -1 },
1800};
1801
1802void tcg_target_init(TCGContext *s)
1803{
1804 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1805 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1806 (1 << TCG_REG_R0) |
6ec85236 1807#ifdef _CALL_DARWIN
f9bf2987 1808 (1 << TCG_REG_R2) |
1809#endif
2662e13f
FB		 1810 (1 << TCG_REG_R3) |
1811 (1 << TCG_REG_R4) |
1812 (1 << TCG_REG_R5) |
1813 (1 << TCG_REG_R6) |
1814 (1 << TCG_REG_R7) |
1815 (1 << TCG_REG_R8) |
1816 (1 << TCG_REG_R9) |
1817 (1 << TCG_REG_R10) |
1818 (1 << TCG_REG_R11) |
1819 (1 << TCG_REG_R12)
1820 );
1821
1822 tcg_regset_clear(s->reserved_regs);
1823 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1824 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
6ec85236 1825#ifndef _CALL_DARWIN
2662e13f 1826 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
f9bf2987 1827#endif
6ec85236 1828#ifdef _CALL_SYSV
5db3ee79 1829 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1830#endif
f6548c0a 1831#ifdef CONFIG_USE_GUEST_BASE
1832 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1833#endif
2662e13f
FB		 1834
1835 tcg_add_target_add_op_defs(ppc_op_defs);
1836}
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