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tcg: Add TCG_CALL_{RET,ARG}_BY_REF
[mirror_qemu.git] / tcg / ppc / tcg-target.c.inc
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810260a8 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
53c89efd 25#include "elf.h"
139c1837 26#include "../tcg-pool.c.inc"
8605cbcd 27#include "../tcg-ldst.c.inc"
53c89efd 28
d2168985
RH		 29/*
30 * Standardize on the _CALL_FOO symbols used by GCC:
31 * Apple XCode does not define _CALL_DARWIN.
32 * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit).
33 */
34#if !defined(_CALL_SYSV) && \
35 !defined(_CALL_DARWIN) && \
36 !defined(_CALL_AIX) && \
37 !defined(_CALL_ELF)
38# if defined(__APPLE__)
39# define _CALL_DARWIN
40# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32
41# define _CALL_SYSV
42# else
43# error "Unknown ABI"
44# endif
a813e36f 45#endif
d2168985 46
eb8b0224
RH		 47#if TCG_TARGET_REG_BITS == 64
48# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND
49#else
50# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
51#endif
7f25c469 52#ifdef _CALL_SYSV
c8eef960
RH		 53# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN
54#else
55# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
7f25c469 56#endif
ffcfbece 57
dfca1778
RH		 58/* For some memory operations, we need a scratch that isn't R0. For the AIX
59 calling convention, we can re-use the TOC register since we'll be reloading
60 it at every call. Otherwise R12 will do nicely as neither a call-saved
61 register nor a parameter register. */
62#ifdef _CALL_AIX
63# define TCG_REG_TMP1 TCG_REG_R2
64#else
65# define TCG_REG_TMP1 TCG_REG_R12
66#endif
67
42281ec6
RH		 68#define TCG_VEC_TMP1 TCG_REG_V0
69#define TCG_VEC_TMP2 TCG_REG_V1
70
5964fca8
RH		 71#define TCG_REG_TB TCG_REG_R31
72#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
a84ac4cb 73
de3d636d
RH		 74/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
75#define SZP ((int)sizeof(void *))
76
4c3831a0
RH		 77/* Shorthand for size of a register. */
78#define SZR (TCG_TARGET_REG_BITS / 8)
79
3d582c61
RH		 80#define TCG_CT_CONST_S16 0x100
81#define TCG_CT_CONST_U16 0x200
82#define TCG_CT_CONST_S32 0x400
83#define TCG_CT_CONST_U32 0x800
84#define TCG_CT_CONST_ZERO 0x1000
6c858762 85#define TCG_CT_CONST_MONE 0x2000
d0b07481 86#define TCG_CT_CONST_WSZ 0x4000
fe6f943f 87
85d251d7
RH		 88#define ALL_GENERAL_REGS 0xffffffffu
89#define ALL_VECTOR_REGS 0xffffffff00000000ull
90
91#ifdef CONFIG_SOFTMMU
92#define ALL_QLOAD_REGS \
93 (ALL_GENERAL_REGS & \
94 ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
95#define ALL_QSTORE_REGS \
96 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
97 (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
98#else
99#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
100#define ALL_QSTORE_REGS ALL_QLOAD_REGS
101#endif
102
7d9dae0a 103TCGPowerISA have_isa;
63922f46 104static bool have_isel;
4b06c216 105bool have_altivec;
47c906ae 106bool have_vsx;
49d9870a 107
4cbea598 108#ifndef CONFIG_SOFTMMU
f6548c0a 109#define TCG_GUEST_BASE_REG 30
f6548c0a 110#endif
111
8d8fdbae 112#ifdef CONFIG_DEBUG_TCG
42281ec6
RH		 113static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
114 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
115 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
116 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
117 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
118 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
119 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
120 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
121 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
810260a8 122};
d4a9eb1f 123#endif
810260a8 124
125static const int tcg_target_reg_alloc_order[] = {
5e1702b0 126 TCG_REG_R14, /* call saved registers */
810260a8 127 TCG_REG_R15,
128 TCG_REG_R16,
129 TCG_REG_R17,
130 TCG_REG_R18,
131 TCG_REG_R19,
132 TCG_REG_R20,
133 TCG_REG_R21,
134 TCG_REG_R22,
135 TCG_REG_R23,
5e1702b0
RH		 136 TCG_REG_R24,
137 TCG_REG_R25,
138 TCG_REG_R26,
139 TCG_REG_R27,
810260a8 140 TCG_REG_R28,
141 TCG_REG_R29,
142 TCG_REG_R30,
143 TCG_REG_R31,
5e1702b0
RH		 144 TCG_REG_R12, /* call clobbered, non-arguments */
145 TCG_REG_R11,
dfca1778
RH		 146 TCG_REG_R2,
147 TCG_REG_R13,
5e1702b0 148 TCG_REG_R10, /* call clobbered, arguments */
810260a8 149 TCG_REG_R9,
5e1702b0
RH		 150 TCG_REG_R8,
151 TCG_REG_R7,
152 TCG_REG_R6,
153 TCG_REG_R5,
154 TCG_REG_R4,
155 TCG_REG_R3,
42281ec6
RH		 156
157 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
158 TCG_REG_V2, /* call clobbered, vectors */
159 TCG_REG_V3,
160 TCG_REG_V4,
161 TCG_REG_V5,
162 TCG_REG_V6,
163 TCG_REG_V7,
164 TCG_REG_V8,
165 TCG_REG_V9,
166 TCG_REG_V10,
167 TCG_REG_V11,
168 TCG_REG_V12,
169 TCG_REG_V13,
170 TCG_REG_V14,
171 TCG_REG_V15,
172 TCG_REG_V16,
173 TCG_REG_V17,
174 TCG_REG_V18,
175 TCG_REG_V19,
810260a8 176};
177
178static const int tcg_target_call_iarg_regs[] = {
179 TCG_REG_R3,
180 TCG_REG_R4,
181 TCG_REG_R5,
182 TCG_REG_R6,
183 TCG_REG_R7,
184 TCG_REG_R8,
185 TCG_REG_R9,
186 TCG_REG_R10
187};
188
be9c4183 189static const int tcg_target_call_oarg_regs[] = {
dfca1778
RH		 190 TCG_REG_R3,
191 TCG_REG_R4
810260a8 192};
193
194static const int tcg_target_callee_save_regs[] = {
2fa169ba 195#ifdef _CALL_DARWIN
5d7ff5bb
AF		 196 TCG_REG_R11,
197#endif
810260a8 198 TCG_REG_R14,
199 TCG_REG_R15,
200 TCG_REG_R16,
201 TCG_REG_R17,
202 TCG_REG_R18,
203 TCG_REG_R19,
204 TCG_REG_R20,
205 TCG_REG_R21,
206 TCG_REG_R22,
207 TCG_REG_R23,
095271d4 208 TCG_REG_R24,
209 TCG_REG_R25,
210 TCG_REG_R26,
cea5f9a2 211 TCG_REG_R27, /* currently used for the global env */
810260a8 212 TCG_REG_R28,
213 TCG_REG_R29,
214 TCG_REG_R30,
215 TCG_REG_R31
216};
217
b0940da0
RH		 218static inline bool in_range_b(tcg_target_long target)
219{
220 return target == sextract64(target, 0, 26);
221}
222
d54401df
RH		 223static uint32_t reloc_pc24_val(const tcg_insn_unit *pc,
224 const tcg_insn_unit *target)
810260a8 225{
e083c4a2 226 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 227 tcg_debug_assert(in_range_b(disp));
810260a8 228 return disp & 0x3fffffc;
229}
230
d54401df 231static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
810260a8 232{
d54401df
RH		 233 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
234 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx);
235
d5132903 236 if (in_range_b(disp)) {
d54401df 237 *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc);
d5132903
RH		 238 return true;
239 }
240 return false;
810260a8 241}
242
d54401df
RH		 243static uint16_t reloc_pc14_val(const tcg_insn_unit *pc,
244 const tcg_insn_unit *target)
810260a8 245{
e083c4a2 246 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 247 tcg_debug_assert(disp == (int16_t) disp);
810260a8 248 return disp & 0xfffc;
249}
250
d54401df 251static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
810260a8 252{
d54401df
RH		 253 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
254 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx);
255
d5132903 256 if (disp == (int16_t) disp) {
d54401df 257 *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc);
d5132903
RH		 258 return true;
259 }
260 return false;
810260a8 261}
262
810260a8 263/* test if a constant matches the constraint */
a4fbbd77 264static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
810260a8 265{
3d582c61
RH		 266 if (ct & TCG_CT_CONST) {
267 return 1;
1194dcba
RH		 268 }
269
270 /* The only 32-bit constraint we use aside from
271 TCG_CT_CONST is TCG_CT_CONST_S16. */
272 if (type == TCG_TYPE_I32) {
273 val = (int32_t)val;
274 }
275
276 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
3d582c61
RH		 277 return 1;
278 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
810260a8 279 return 1;
3d582c61 280 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
fe6f943f 281 return 1;
3d582c61
RH		 282 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
283 return 1;
284 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
285 return 1;
6c858762
RH		 286 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
287 return 1;
d0b07481
RH		 288 } else if ((ct & TCG_CT_CONST_WSZ)
289 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
290 return 1;
3d582c61 291 }
810260a8 292 return 0;
293}
294
295#define OPCD(opc) ((opc)<<26)
296#define XO19(opc) (OPCD(19)|((opc)<<1))
8a94cfb0
AB		 297#define MD30(opc) (OPCD(30)|((opc)<<2))
298#define MDS30(opc) (OPCD(30)|((opc)<<1))
810260a8 299#define XO31(opc) (OPCD(31)|((opc)<<1))
300#define XO58(opc) (OPCD(58)|(opc))
301#define XO62(opc) (OPCD(62)|(opc))
1838905e 302#define VX4(opc) (OPCD(4)|(opc))
810260a8 303
304#define B OPCD( 18)
305#define BC OPCD( 16)
306#define LBZ OPCD( 34)
307#define LHZ OPCD( 40)
308#define LHA OPCD( 42)
309#define LWZ OPCD( 32)
644f591a 310#define LWZUX XO31( 55)
810260a8 311#define STB OPCD( 38)
312#define STH OPCD( 44)
313#define STW OPCD( 36)
314
315#define STD XO62( 0)
316#define STDU XO62( 1)
317#define STDX XO31(149)
318
319#define LD XO58( 0)
320#define LDX XO31( 21)
321#define LDU XO58( 1)
644f591a 322#define LDUX XO31( 53)
301f6d90 323#define LWA XO58( 2)
810260a8 324#define LWAX XO31(341)
325
1cd62ae9 326#define ADDIC OPCD( 12)
810260a8 327#define ADDI OPCD( 14)
328#define ADDIS OPCD( 15)
329#define ORI OPCD( 24)
330#define ORIS OPCD( 25)
331#define XORI OPCD( 26)
332#define XORIS OPCD( 27)
333#define ANDI OPCD( 28)
334#define ANDIS OPCD( 29)
335#define MULLI OPCD( 7)
336#define CMPLI OPCD( 10)
337#define CMPI OPCD( 11)
148bdd23 338#define SUBFIC OPCD( 8)
810260a8 339
340#define LWZU OPCD( 33)
341#define STWU OPCD( 37)
342
313d91c7 343#define RLWIMI OPCD( 20)
810260a8 344#define RLWINM OPCD( 21)
313d91c7 345#define RLWNM OPCD( 23)
810260a8 346
8a94cfb0
AB		 347#define RLDICL MD30( 0)
348#define RLDICR MD30( 1)
349#define RLDIMI MD30( 3)
350#define RLDCL MDS30( 8)
810260a8 351
352#define BCLR XO19( 16)
353#define BCCTR XO19(528)
354#define CRAND XO19(257)
355#define CRANDC XO19(129)
356#define CRNAND XO19(225)
357#define CROR XO19(449)
1cd62ae9 358#define CRNOR XO19( 33)
810260a8 359
360#define EXTSB XO31(954)
361#define EXTSH XO31(922)
362#define EXTSW XO31(986)
363#define ADD XO31(266)
364#define ADDE XO31(138)
6c858762
RH		 365#define ADDME XO31(234)
366#define ADDZE XO31(202)
810260a8 367#define ADDC XO31( 10)
368#define AND XO31( 28)
369#define SUBF XO31( 40)
370#define SUBFC XO31( 8)
371#define SUBFE XO31(136)
6c858762
RH		 372#define SUBFME XO31(232)
373#define SUBFZE XO31(200)
810260a8 374#define OR XO31(444)
375#define XOR XO31(316)
376#define MULLW XO31(235)
8fa391a0 377#define MULHW XO31( 75)
810260a8 378#define MULHWU XO31( 11)
379#define DIVW XO31(491)
380#define DIVWU XO31(459)
4d573822
MKF		 381#define MODSW XO31(779)
382#define MODUW XO31(267)
810260a8 383#define CMP XO31( 0)
384#define CMPL XO31( 32)
385#define LHBRX XO31(790)
386#define LWBRX XO31(534)
49d9870a 387#define LDBRX XO31(532)
810260a8 388#define STHBRX XO31(918)
389#define STWBRX XO31(662)
49d9870a 390#define STDBRX XO31(660)
810260a8 391#define MFSPR XO31(339)
392#define MTSPR XO31(467)
393#define SRAWI XO31(824)
394#define NEG XO31(104)
1cd62ae9 395#define MFCR XO31( 19)
6995a4a0 396#define MFOCRF (MFCR | (1u << 20))
157f2662 397#define NOR XO31(124)
1cd62ae9 398#define CNTLZW XO31( 26)
399#define CNTLZD XO31( 58)
d0b07481
RH		 400#define CNTTZW XO31(538)
401#define CNTTZD XO31(570)
33e75fb9
RH		 402#define CNTPOPW XO31(378)
403#define CNTPOPD XO31(506)
ce1010d6
RH		 404#define ANDC XO31( 60)
405#define ORC XO31(412)
406#define EQV XO31(284)
407#define NAND XO31(476)
70fac59a 408#define ISEL XO31( 15)
810260a8 409
410#define MULLD XO31(233)
411#define MULHD XO31( 73)
412#define MULHDU XO31( 9)
413#define DIVD XO31(489)
414#define DIVDU XO31(457)
4d573822
MKF		 415#define MODSD XO31(777)
416#define MODUD XO31(265)
810260a8 417
418#define LBZX XO31( 87)
4f4a67ae 419#define LHZX XO31(279)
810260a8 420#define LHAX XO31(343)
421#define LWZX XO31( 23)
422#define STBX XO31(215)
423#define STHX XO31(407)
424#define STWX XO31(151)
425
7b4af5ee
PK		 426#define EIEIO XO31(854)
427#define HWSYNC XO31(598)
428#define LWSYNC (HWSYNC | (1u << 21))
429
541dd4ce 430#define SPR(a, b) ((((a)<<5)|(b))<<11)
810260a8 431#define LR SPR(8, 0)
432#define CTR SPR(9, 0)
433
434#define SLW XO31( 24)
435#define SRW XO31(536)
436#define SRAW XO31(792)
437
438#define SLD XO31( 27)
439#define SRD XO31(539)
440#define SRAD XO31(794)
fe6f943f 441#define SRADI XO31(413<<1)
810260a8 442
780b573f
RH		 443#define BRH XO31(219)
444#define BRW XO31(155)
445#define BRD XO31(187)
446
810260a8 447#define TW XO31( 4)
541dd4ce 448#define TRAP (TW | TO(31))
810260a8 449
a84ac4cb
RH		 450#define NOP ORI /* ori 0,0,0 */
451
6ef14d7e
RH		 452#define LVX XO31(103)
453#define LVEBX XO31(7)
454#define LVEHX XO31(39)
455#define LVEWX XO31(71)
47c906ae
RH		 456#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */
457#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */
b2dda640 458#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */
6e11cde1
RH		 459#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */
460#define LXSD (OPCD(57) | 2) /* v3.00 */
461#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */
6ef14d7e
RH		 462
463#define STVX XO31(231)
464#define STVEWX XO31(199)
47c906ae 465#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */
b2dda640 466#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */
6e11cde1
RH		 467#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */
468#define STXSD (OPCD(61) | 2) /* v3.00 */
6ef14d7e 469
e9d1a53a
RH		 470#define VADDSBS VX4(768)
471#define VADDUBS VX4(512)
d6750811 472#define VADDUBM VX4(0)
e9d1a53a
RH		 473#define VADDSHS VX4(832)
474#define VADDUHS VX4(576)
d6750811 475#define VADDUHM VX4(64)
e9d1a53a
RH		 476#define VADDSWS VX4(896)
477#define VADDUWS VX4(640)
d6750811 478#define VADDUWM VX4(128)
64ff1c6d 479#define VADDUDM VX4(192) /* v2.07 */
d6750811 480
e9d1a53a
RH		 481#define VSUBSBS VX4(1792)
482#define VSUBUBS VX4(1536)
d6750811 483#define VSUBUBM VX4(1024)
e9d1a53a
RH		 484#define VSUBSHS VX4(1856)
485#define VSUBUHS VX4(1600)
d6750811 486#define VSUBUHM VX4(1088)
e9d1a53a
RH		 487#define VSUBSWS VX4(1920)
488#define VSUBUWS VX4(1664)
d6750811 489#define VSUBUWM VX4(1152)
64ff1c6d 490#define VSUBUDM VX4(1216) /* v2.07 */
d6750811 491
d7cd6a2f
RH		 492#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
493#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
494
e2382972
RH		 495#define VMAXSB VX4(258)
496#define VMAXSH VX4(322)
497#define VMAXSW VX4(386)
64ff1c6d 498#define VMAXSD VX4(450) /* v2.07 */
e2382972
RH		 499#define VMAXUB VX4(2)
500#define VMAXUH VX4(66)
501#define VMAXUW VX4(130)
64ff1c6d 502#define VMAXUD VX4(194) /* v2.07 */
e2382972
RH		 503#define VMINSB VX4(770)
504#define VMINSH VX4(834)
505#define VMINSW VX4(898)
64ff1c6d 506#define VMINSD VX4(962) /* v2.07 */
e2382972
RH		 507#define VMINUB VX4(514)
508#define VMINUH VX4(578)
509#define VMINUW VX4(642)
64ff1c6d 510#define VMINUD VX4(706) /* v2.07 */
e2382972 511
6ef14d7e
RH		 512#define VCMPEQUB VX4(6)
513#define VCMPEQUH VX4(70)
514#define VCMPEQUW VX4(134)
64ff1c6d 515#define VCMPEQUD VX4(199) /* v2.07 */
6ef14d7e
RH		 516#define VCMPGTSB VX4(774)
517#define VCMPGTSH VX4(838)
518#define VCMPGTSW VX4(902)
64ff1c6d 519#define VCMPGTSD VX4(967) /* v2.07 */
6ef14d7e
RH		 520#define VCMPGTUB VX4(518)
521#define VCMPGTUH VX4(582)
522#define VCMPGTUW VX4(646)
64ff1c6d 523#define VCMPGTUD VX4(711) /* v2.07 */
d7cd6a2f
RH		 524#define VCMPNEB VX4(7) /* v3.00 */
525#define VCMPNEH VX4(71) /* v3.00 */
526#define VCMPNEW VX4(135) /* v3.00 */
6ef14d7e 527
dabae097
RH		 528#define VSLB VX4(260)
529#define VSLH VX4(324)
530#define VSLW VX4(388)
64ff1c6d 531#define VSLD VX4(1476) /* v2.07 */
dabae097
RH		 532#define VSRB VX4(516)
533#define VSRH VX4(580)
534#define VSRW VX4(644)
64ff1c6d 535#define VSRD VX4(1732) /* v2.07 */
dabae097
RH		 536#define VSRAB VX4(772)
537#define VSRAH VX4(836)
538#define VSRAW VX4(900)
64ff1c6d 539#define VSRAD VX4(964) /* v2.07 */
d9897efa
RH		 540#define VRLB VX4(4)
541#define VRLH VX4(68)
542#define VRLW VX4(132)
64ff1c6d 543#define VRLD VX4(196) /* v2.07 */
d9897efa
RH		 544
545#define VMULEUB VX4(520)
546#define VMULEUH VX4(584)
64ff1c6d 547#define VMULEUW VX4(648) /* v2.07 */
d9897efa
RH		 548#define VMULOUB VX4(8)
549#define VMULOUH VX4(72)
64ff1c6d
RH		 550#define VMULOUW VX4(136) /* v2.07 */
551#define VMULUWM VX4(137) /* v2.07 */
73ebe95e 552#define VMULLD VX4(457) /* v3.10 */
d9897efa
RH		 553#define VMSUMUHM VX4(38)
554
555#define VMRGHB VX4(12)
556#define VMRGHH VX4(76)
557#define VMRGHW VX4(140)
558#define VMRGLB VX4(268)
559#define VMRGLH VX4(332)
560#define VMRGLW VX4(396)
561
562#define VPKUHUM VX4(14)
563#define VPKUWUM VX4(78)
dabae097 564
6ef14d7e
RH		 565#define VAND VX4(1028)
566#define VANDC VX4(1092)
567#define VNOR VX4(1284)
568#define VOR VX4(1156)
569#define VXOR VX4(1220)
64ff1c6d
RH		 570#define VEQV VX4(1668) /* v2.07 */
571#define VNAND VX4(1412) /* v2.07 */
572#define VORC VX4(1348) /* v2.07 */
6ef14d7e
RH		 573
574#define VSPLTB VX4(524)
575#define VSPLTH VX4(588)
576#define VSPLTW VX4(652)
577#define VSPLTISB VX4(780)
578#define VSPLTISH VX4(844)
579#define VSPLTISW VX4(908)
580
581#define VSLDOI VX4(44)
582
47c906ae
RH		 583#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */
584#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */
b7ce3cff 585#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */
47c906ae 586
7097312d
RH		 587#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */
588#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */
589#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */
590#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */
b7ce3cff
RH		 591#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */
592#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */
7097312d 593
810260a8 594#define RT(r) ((r)<<21)
595#define RS(r) ((r)<<21)
596#define RA(r) ((r)<<16)
597#define RB(r) ((r)<<11)
598#define TO(t) ((t)<<21)
599#define SH(s) ((s)<<11)
600#define MB(b) ((b)<<6)
601#define ME(e) ((e)<<1)
602#define BO(o) ((o)<<21)
603#define MB64(b) ((b)<<5)
6995a4a0 604#define FXM(b) (1 << (19 - (b)))
810260a8 605
b82f769c
RH		 606#define VRT(r) (((r) & 31) << 21)
607#define VRA(r) (((r) & 31) << 16)
608#define VRB(r) (((r) & 31) << 11)
609#define VRC(r) (((r) & 31) << 6)
610
810260a8 611#define LK 1
612
2fd8eddc
RH		 613#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
614#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
615#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
616#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
810260a8 617
618#define BF(n) ((n)<<23)
619#define BI(n, c) (((c)+((n)*4))<<16)
620#define BT(n, c) (((c)+((n)*4))<<21)
621#define BA(n, c) (((c)+((n)*4))<<16)
622#define BB(n, c) (((c)+((n)*4))<<11)
70fac59a 623#define BC_(n, c) (((c)+((n)*4))<<6)
810260a8 624
541dd4ce
RH		 625#define BO_COND_TRUE BO(12)
626#define BO_COND_FALSE BO( 4)
627#define BO_ALWAYS BO(20)
810260a8 628
629enum {
630 CR_LT,
631 CR_GT,
632 CR_EQ,
633 CR_SO
634};
635
0aed257f 636static const uint32_t tcg_to_bc[] = {
541dd4ce
RH		 637 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
638 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
639 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
640 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
641 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
642 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
643 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
644 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
645 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
646 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
810260a8 647};
648
70fac59a
RH		 649/* The low bit here is set if the RA and RB fields must be inverted. */
650static const uint32_t tcg_to_isel[] = {
651 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
652 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
653 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
654 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
655 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
656 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
657 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
658 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
659 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
660 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
661};
662
6ac17786 663static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
030ffe39
RH		 664 intptr_t value, intptr_t addend)
665{
d54401df 666 const tcg_insn_unit *target;
6ef14d7e
RH		 667 int16_t lo;
668 int32_t hi;
030ffe39
RH		 669
670 value += addend;
d54401df 671 target = (const tcg_insn_unit *)value;
030ffe39
RH		 672
673 switch (type) {
674 case R_PPC_REL14:
d5132903 675 return reloc_pc14(code_ptr, target);
030ffe39 676 case R_PPC_REL24:
d5132903 677 return reloc_pc24(code_ptr, target);
030ffe39 678 case R_PPC_ADDR16:
a7cdaf71
RH		 679 /*
680 * We are (slightly) abusing this relocation type. In particular,
681 * assert that the low 2 bits are zero, and do not modify them.
682 * That way we can use this with LD et al that have opcode bits
683 * in the low 2 bits of the insn.
684 */
685 if ((value & 3) || value != (int16_t)value) {
686 return false;
030ffe39 687 }
a7cdaf71 688 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
030ffe39 689 break;
6ef14d7e
RH		 690 case R_PPC_ADDR32:
691 /*
692 * We are abusing this relocation type. Again, this points to
693 * a pair of insns, lis + load. This is an absolute address
694 * relocation for PPC32 so the lis cannot be removed.
695 */
696 lo = value;
697 hi = value - lo;
698 if (hi + lo != value) {
699 return false;
700 }
701 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
702 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
703 break;
030ffe39
RH		 704 default:
705 g_assert_not_reached();
706 }
6ac17786 707 return true;
030ffe39
RH		 708}
709
a84ac4cb
RH		 710static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
711 TCGReg base, tcg_target_long offset);
712
78113e83 713static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
810260a8 714{
6ef14d7e
RH		 715 if (ret == arg) {
716 return true;
717 }
718 switch (type) {
719 case TCG_TYPE_I64:
720 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
721 /* fallthru */
722 case TCG_TYPE_I32:
7097312d
RH		 723 if (ret < TCG_REG_V0) {
724 if (arg < TCG_REG_V0) {
725 tcg_out32(s, OR | SAB(arg, ret, arg));
726 break;
727 } else if (have_isa_2_07) {
728 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)
729 | VRT(arg) | RA(ret));
730 break;
731 } else {
732 /* Altivec does not support vector->integer moves. */
733 return false;
734 }
735 } else if (arg < TCG_REG_V0) {
736 if (have_isa_2_07) {
737 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)
738 | VRT(ret) | RA(arg));
739 break;
740 } else {
741 /* Altivec does not support integer->vector moves. */
742 return false;
743 }
6ef14d7e
RH		 744 }
745 /* fallthru */
746 case TCG_TYPE_V64:
747 case TCG_TYPE_V128:
748 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
749 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
750 break;
751 default:
752 g_assert_not_reached();
f8b84129 753 }
78113e83 754 return true;
810260a8 755}
756
aceac8d6
RH		 757static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
758 int sh, int mb)
810260a8 759{
eabb7b91 760 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
541dd4ce
RH		 761 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
762 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
763 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
810260a8 764}
765
9e555b73
RH		 766static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
767 int sh, int mb, int me)
768{
769 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
770}
771
f4bf14f4
RH		 772static inline void tcg_out_ext8s(TCGContext *s, TCGReg dst, TCGReg src)
773{
774 tcg_out32(s, EXTSB | RA(dst) | RS(src));
775}
776
777static inline void tcg_out_ext16s(TCGContext *s, TCGReg dst, TCGReg src)
778{
779 tcg_out32(s, EXTSH | RA(dst) | RS(src));
780}
781
780b573f
RH		 782static inline void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src)
783{
784 tcg_out32(s, ANDI | SAI(src, dst, 0xffff));
785}
786
f4bf14f4
RH		 787static inline void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src)
788{
789 tcg_out32(s, EXTSW | RA(dst) | RS(src));
790}
791
6e5e0602
RH		 792static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
793{
794 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
795}
796
a757e1ee
RH		 797static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
798{
799 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
800}
801
0a9564b9
RH		 802static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
803{
804 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
805}
806
05dd01fa
RH		 807static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c)
808{
809 /* Limit immediate shift count lest we create an illegal insn. */
810 tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31));
811}
812
a757e1ee
RH		 813static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
814{
815 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
816}
817
5e916c28
RH		 818static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
819{
820 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
821}
822
05dd01fa
RH		 823static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c)
824{
825 tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2));
826}
827
26ce7005 828static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags)
783d3ecd
RH		 829{
830 TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
831
780b573f
RH		 832 if (have_isa_3_10) {
833 tcg_out32(s, BRH | RA(dst) | RS(src));
834 if (flags & TCG_BSWAP_OS) {
835 tcg_out_ext16s(s, dst, dst);
836 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
837 tcg_out_ext16u(s, dst, dst);
838 }
839 return;
840 }
841
783d3ecd
RH		 842 /*
843 * In the following,
844 * dep(a, b, m) -> (a & ~m) | (b & m)
845 *
846 * Begin with: src = xxxxabcd
847 */
848 /* tmp = rol32(src, 24) & 0x000000ff = 0000000c */
849 tcg_out_rlw(s, RLWINM, tmp, src, 24, 24, 31);
850 /* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */
851 tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23);
852
26ce7005
RH		 853 if (flags & TCG_BSWAP_OS) {
854 tcg_out_ext16s(s, dst, tmp);
855 } else {
856 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
857 }
783d3ecd
RH		 858}
859
26ce7005 860static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags)
8a611d86
RH		 861{
862 TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
863
780b573f
RH		 864 if (have_isa_3_10) {
865 tcg_out32(s, BRW | RA(dst) | RS(src));
866 if (flags & TCG_BSWAP_OS) {
867 tcg_out_ext32s(s, dst, dst);
868 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
869 tcg_out_ext32u(s, dst, dst);
870 }
871 return;
872 }
873
8a611d86
RH		 874 /*
875 * Stolen from gcc's builtin_bswap32.
876 * In the following,
877 * dep(a, b, m) -> (a & ~m) | (b & m)
878 *
879 * Begin with: src = xxxxabcd
880 */
881 /* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */
882 tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31);
883 /* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */
884 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7);
885 /* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */
886 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23);
887
26ce7005
RH		 888 if (flags & TCG_BSWAP_OS) {
889 tcg_out_ext32s(s, dst, tmp);
890 } else {
891 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
892 }
8a611d86
RH		 893}
894
674ba588
RH		 895static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src)
896{
897 TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
898 TCGReg t1 = dst == src ? dst : TCG_REG_R0;
899
780b573f
RH		 900 if (have_isa_3_10) {
901 tcg_out32(s, BRD | RA(dst) | RS(src));
902 return;
903 }
904
674ba588
RH		 905 /*
906 * In the following,
907 * dep(a, b, m) -> (a & ~m) | (b & m)
908 *
909 * Begin with: src = abcdefgh
910 */
911 /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */
912 tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31);
913 /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */
914 tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7);
915 /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */
916 tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23);
917
918 /* t0 = rol64(t0, 32) = hgfe0000 */
919 tcg_out_rld(s, RLDICL, t0, t0, 32, 0);
920 /* t1 = rol64(src, 32) = efghabcd */
921 tcg_out_rld(s, RLDICL, t1, src, 32, 0);
922
923 /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */
924 tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31);
925 /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */
926 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7);
927 /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */
928 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23);
929
930 tcg_out_mov(s, TCG_TYPE_REG, dst, t0);
931}
932
77bfc7c0
RH		 933/* Emit a move into ret of arg, if it can be done in one insn. */
934static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
935{
936 if (arg == (int16_t)arg) {
937 tcg_out32(s, ADDI | TAI(ret, 0, arg));
938 return true;
939 }
940 if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
941 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
942 return true;
943 }
944 return false;
945}
946
5964fca8
RH		 947static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
948 tcg_target_long arg, bool in_prologue)
810260a8 949{
5964fca8 950 intptr_t tb_diff;
77bfc7c0
RH		 951 tcg_target_long tmp;
952 int shift;
5964fca8
RH		 953
954 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
955
956 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
957 arg = (int32_t)arg;
958 }
959
960 /* Load 16-bit immediates with one insn. */
77bfc7c0 961 if (tcg_out_movi_one(s, ret, arg)) {
5964fca8
RH		 962 return;
963 }
964
965 /* Load addresses within the TB with one insn. */
e6dc7f81 966 tb_diff = tcg_tbrel_diff(s, (void *)arg);
5964fca8
RH		 967 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
968 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
969 return;
970 }
971
77bfc7c0
RH		 972 /* Load 32-bit immediates with two insns. Note that we've already
973 eliminated bare ADDIS, so we know both insns are required. */
5964fca8 974 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
2fd8eddc 975 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
77bfc7c0 976 tcg_out32(s, ORI | SAI(ret, ret, arg));
5964fca8 977 return;
810260a8 978 }
5964fca8 979 if (arg == (uint32_t)arg && !(arg & 0x8000)) {
421233a1
RH		 980 tcg_out32(s, ADDI | TAI(ret, 0, arg));
981 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
5964fca8
RH		 982 return;
983 }
a84ac4cb 984
77bfc7c0
RH		 985 /* Load masked 16-bit value. */
986 if (arg > 0 && (arg & 0x8000)) {
987 tmp = arg | 0x7fff;
988 if ((tmp & (tmp + 1)) == 0) {
989 int mb = clz64(tmp + 1) + 1;
990 tcg_out32(s, ADDI | TAI(ret, 0, arg));
991 tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
992 return;
993 }
994 }
995
996 /* Load common masks with 2 insns. */
997 shift = ctz64(arg);
998 tmp = arg >> shift;
999 if (tmp == (int16_t)tmp) {
1000 tcg_out32(s, ADDI | TAI(ret, 0, tmp));
1001 tcg_out_shli64(s, ret, ret, shift);
1002 return;
1003 }
1004 shift = clz64(arg);
1005 if (tcg_out_movi_one(s, ret, arg << shift)) {
1006 tcg_out_shri64(s, ret, ret, shift);
1007 return;
1008 }
1009
5964fca8
RH		 1010 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
1011 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
1012 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
1013 return;
1014 }
a84ac4cb 1015
53c89efd
RH		 1016 /* Use the constant pool, if possible. */
1017 if (!in_prologue && USE_REG_TB) {
1018 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
e6dc7f81 1019 tcg_tbrel_diff(s, NULL));
a7cdaf71 1020 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
53c89efd
RH		 1021 return;
1022 }
1023
77bfc7c0
RH		 1024 tmp = arg >> 31 >> 1;
1025 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
1026 if (tmp) {
5964fca8 1027 tcg_out_shli64(s, ret, ret, 32);
810260a8 1028 }
5964fca8
RH		 1029 if (arg & 0xffff0000) {
1030 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
1031 }
1032 if (arg & 0xffff) {
1033 tcg_out32(s, ORI | SAI(ret, ret, arg));
1034 }
1035}
1036
4e186175
RH		 1037static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
1038 TCGReg ret, int64_t val)
5964fca8 1039{
6ef14d7e
RH		 1040 uint32_t load_insn;
1041 int rel, low;
1042 intptr_t add;
1043
4e186175
RH		 1044 switch (vece) {
1045 case MO_8:
1046 low = (int8_t)val;
1047 if (low >= -16 && low < 16) {
6ef14d7e
RH		 1048 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16));
1049 return;
1050 }
4e186175
RH		 1051 if (have_isa_3_00) {
1052 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
1053 return;
1054 }
1055 break;
1056
1057 case MO_16:
1058 low = (int16_t)val;
1059 if (low >= -16 && low < 16) {
6ef14d7e
RH		 1060 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16));
1061 return;
1062 }
4e186175
RH		 1063 break;
1064
1065 case MO_32:
1066 low = (int32_t)val;
1067 if (low >= -16 && low < 16) {
6ef14d7e
RH		 1068 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16));
1069 return;
1070 }
4e186175 1071 break;
b7ce3cff 1072 }
6ef14d7e
RH		 1073
1074 /*
1075 * Otherwise we must load the value from the constant pool.
1076 */
1077 if (USE_REG_TB) {
1078 rel = R_PPC_ADDR16;
e6dc7f81 1079 add = tcg_tbrel_diff(s, NULL);
6ef14d7e
RH		 1080 } else {
1081 rel = R_PPC_ADDR32;
1082 add = 0;
1083 }
1084
47c906ae
RH		 1085 if (have_vsx) {
1086 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
1087 load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
1088 if (TCG_TARGET_REG_BITS == 64) {
1089 new_pool_label(s, val, rel, s->code_ptr, add);
1090 } else {
4e186175 1091 new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val);
47c906ae 1092 }
6ef14d7e 1093 } else {
47c906ae
RH		 1094 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
1095 if (TCG_TARGET_REG_BITS == 64) {
1096 new_pool_l2(s, rel, s->code_ptr, add, val, val);
1097 } else {
4e186175
RH		 1098 new_pool_l4(s, rel, s->code_ptr, add,
1099 val >> 32, val, val >> 32, val);
47c906ae 1100 }
6ef14d7e
RH		 1101 }
1102
1103 if (USE_REG_TB) {
1104 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0));
1105 load_insn |= RA(TCG_REG_TB);
1106 } else {
1107 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0));
1108 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
1109 }
1110 tcg_out32(s, load_insn);
4b06c216
RH		 1111}
1112
1113static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
1114 tcg_target_long arg)
1115{
1116 switch (type) {
1117 case TCG_TYPE_I32:
1118 case TCG_TYPE_I64:
1119 tcg_debug_assert(ret < TCG_REG_V0);
1120 tcg_out_movi_int(s, type, ret, arg, false);
1121 break;
1122
4b06c216
RH		 1123 default:
1124 g_assert_not_reached();
1125 }
810260a8 1126}
1127
6a6d772e
RH		 1128static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
1129 tcg_target_long imm)
1130{
1131 /* This function is only used for passing structs by reference. */
1132 g_assert_not_reached();
1133}
1134
637af30c 1135static bool mask_operand(uint32_t c, int *mb, int *me)
a9249dff
RH		 1136{
1137 uint32_t lsb, test;
1138
1139 /* Accept a bit pattern like:
1140 0....01....1
1141 1....10....0
1142 0..01..10..0
1143 Keep track of the transitions. */
1144 if (c == 0 || c == -1) {
1145 return false;
1146 }
1147 test = c;
1148 lsb = test & -test;
1149 test += lsb;
1150 if (test & (test - 1)) {
1151 return false;
1152 }
1153
1154 *me = clz32(lsb);
1155 *mb = test ? clz32(test & -test) + 1 : 0;
1156 return true;
1157}
1158
637af30c
RH		 1159static bool mask64_operand(uint64_t c, int *mb, int *me)
1160{
1161 uint64_t lsb;
1162
1163 if (c == 0) {
1164 return false;
1165 }
1166
1167 lsb = c & -c;
1168 /* Accept 1..10..0. */
1169 if (c == -lsb) {
1170 *mb = 0;
1171 *me = clz64(lsb);
1172 return true;
1173 }
1174 /* Accept 0..01..1. */
1175 if (lsb == 1 && (c & (c + 1)) == 0) {
1176 *mb = clz64(c + 1) + 1;
1177 *me = 63;
1178 return true;
1179 }
1180 return false;
1181}
1182
a9249dff
RH		 1183static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1184{
1185 int mb, me;
1186
1e1df962
RH		 1187 if (mask_operand(c, &mb, &me)) {
1188 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
1189 } else if ((c & 0xffff) == c) {
a9249dff
RH		 1190 tcg_out32(s, ANDI | SAI(src, dst, c));
1191 return;
1192 } else if ((c & 0xffff0000) == c) {
1193 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
1194 return;
a9249dff 1195 } else {
8327a470
RH		 1196 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
1197 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
a9249dff
RH		 1198 }
1199}
1200
637af30c
RH		 1201static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
1202{
1203 int mb, me;
1204
eabb7b91 1205 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1e1df962 1206 if (mask64_operand(c, &mb, &me)) {
637af30c
RH		 1207 if (mb == 0) {
1208 tcg_out_rld(s, RLDICR, dst, src, 0, me);
1209 } else {
1210 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
1211 }
1e1df962
RH		 1212 } else if ((c & 0xffff) == c) {
1213 tcg_out32(s, ANDI | SAI(src, dst, c));
1214 return;
1215 } else if ((c & 0xffff0000) == c) {
1216 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
1217 return;
637af30c 1218 } else {
8327a470
RH		 1219 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
1220 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
637af30c
RH		 1221 }
1222}
1223
dce74c57
RH		 1224static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
1225 int op_lo, int op_hi)
1226{
1227 if (c >> 16) {
1228 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
1229 src = dst;
1230 }
1231 if (c & 0xffff) {
1232 tcg_out32(s, op_lo | SAI(src, dst, c));
1233 src = dst;
1234 }
1235}
1236
1237static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1238{
1239 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
1240}
1241
1242static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
1243{
1244 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
1245}
1246
2be7d76b 1247static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target)
5d7ff5bb 1248{
e083c4a2 1249 ptrdiff_t disp = tcg_pcrel_diff(s, target);
b0940da0 1250 if (in_range_b(disp)) {
541dd4ce
RH		 1251 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
1252 } else {
de3d636d 1253 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
8327a470 1254 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
541dd4ce 1255 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
5d7ff5bb
AF		 1256 }
1257}
1258
b18d5d2b
RH		 1259static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
1260 TCGReg base, tcg_target_long offset)
810260a8 1261{
b18d5d2b 1262 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
6e11cde1 1263 bool is_int_store = false;
dfca1778 1264 TCGReg rs = TCG_REG_TMP1;
b18d5d2b 1265
b18d5d2b
RH		 1266 switch (opi) {
1267 case LD: case LWA:
1268 align = 3;
1269 /* FALLTHRU */
1270 default:
6ef14d7e 1271 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) {
b18d5d2b 1272 rs = rt;
de7761a3 1273 break;
b18d5d2b
RH		 1274 }
1275 break;
6e11cde1
RH		 1276 case LXSD:
1277 case STXSD:
1278 align = 3;
1279 break;
1280 case LXV:
1281 case STXV:
1282 align = 15;
1283 break;
b18d5d2b
RH		 1284 case STD:
1285 align = 3;
de7761a3 1286 /* FALLTHRU */
b18d5d2b 1287 case STB: case STH: case STW:
6e11cde1 1288 is_int_store = true;
b18d5d2b 1289 break;
810260a8 1290 }
810260a8 1291
b18d5d2b 1292 /* For unaligned, or very large offsets, use the indexed form. */
6ef14d7e 1293 if (offset & align || offset != (int32_t)offset || opi == 0) {
d4cba13b
RH		 1294 if (rs == base) {
1295 rs = TCG_REG_R0;
1296 }
6e11cde1 1297 tcg_debug_assert(!is_int_store || rs != rt);
de7761a3 1298 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
6ef14d7e 1299 tcg_out32(s, opx | TAB(rt & 31, base, rs));
b18d5d2b
RH		 1300 return;
1301 }
1302
1303 l0 = (int16_t)offset;
1304 offset = (offset - l0) >> 16;
1305 l1 = (int16_t)offset;
1306
1307 if (l1 < 0 && orig >= 0) {
1308 extra = 0x4000;
1309 l1 = (int16_t)(offset - 0x4000);
1310 }
1311 if (l1) {
1312 tcg_out32(s, ADDIS | TAI(rs, base, l1));
1313 base = rs;
1314 }
1315 if (extra) {
1316 tcg_out32(s, ADDIS | TAI(rs, base, extra));
1317 base = rs;
1318 }
1319 if (opi != ADDI || base != rt || l0 != 0) {
6ef14d7e 1320 tcg_out32(s, opi | TAI(rt & 31, base, l0));
828808f5 1321 }
1322}
1323
6ef14d7e
RH		 1324static void tcg_out_vsldoi(TCGContext *s, TCGReg ret,
1325 TCGReg va, TCGReg vb, int shb)
d604f1a9 1326{
6ef14d7e
RH		 1327 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6));
1328}
810260a8 1329
6ef14d7e
RH		 1330static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1331 TCGReg base, intptr_t offset)
1332{
1333 int shift;
1334
1335 switch (type) {
1336 case TCG_TYPE_I32:
1337 if (ret < TCG_REG_V0) {
1338 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
1339 break;
1340 }
b2dda640
RH		 1341 if (have_isa_2_07 && have_vsx) {
1342 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset);
1343 break;
1344 }
6ef14d7e
RH		 1345 tcg_debug_assert((offset & 3) == 0);
1346 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset);
1347 shift = (offset - 4) & 0xc;
1348 if (shift) {
1349 tcg_out_vsldoi(s, ret, ret, ret, shift);
1350 }
1351 break;
1352 case TCG_TYPE_I64:
1353 if (ret < TCG_REG_V0) {
1354 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1355 tcg_out_mem_long(s, LD, LDX, ret, base, offset);
1356 break;
1357 }
1358 /* fallthru */
1359 case TCG_TYPE_V64:
1360 tcg_debug_assert(ret >= TCG_REG_V0);
47c906ae 1361 if (have_vsx) {
6e11cde1
RH		 1362 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX,
1363 ret, base, offset);
47c906ae
RH		 1364 break;
1365 }
6ef14d7e
RH		 1366 tcg_debug_assert((offset & 7) == 0);
1367 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16);
1368 if (offset & 8) {
1369 tcg_out_vsldoi(s, ret, ret, ret, 8);
1370 }
1371 break;
1372 case TCG_TYPE_V128:
1373 tcg_debug_assert(ret >= TCG_REG_V0);
1374 tcg_debug_assert((offset & 15) == 0);
6e11cde1
RH		 1375 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0,
1376 LVX, ret, base, offset);
6ef14d7e
RH		 1377 break;
1378 default:
1379 g_assert_not_reached();
d604f1a9 1380 }
d604f1a9 1381}
fedee3e7 1382
6ef14d7e
RH		 1383static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1384 TCGReg base, intptr_t offset)
810260a8 1385{
6ef14d7e 1386 int shift;
fedee3e7 1387
6ef14d7e
RH		 1388 switch (type) {
1389 case TCG_TYPE_I32:
1390 if (arg < TCG_REG_V0) {
1391 tcg_out_mem_long(s, STW, STWX, arg, base, offset);
1392 break;
1393 }
b2dda640
RH		 1394 if (have_isa_2_07 && have_vsx) {
1395 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset);
1396 break;
1397 }
1398 assert((offset & 3) == 0);
6ef14d7e
RH		 1399 tcg_debug_assert((offset & 3) == 0);
1400 shift = (offset - 4) & 0xc;
1401 if (shift) {
1402 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift);
1403 arg = TCG_VEC_TMP1;
1404 }
1405 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
1406 break;
1407 case TCG_TYPE_I64:
1408 if (arg < TCG_REG_V0) {
1409 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1410 tcg_out_mem_long(s, STD, STDX, arg, base, offset);
1411 break;
1412 }
1413 /* fallthru */
1414 case TCG_TYPE_V64:
1415 tcg_debug_assert(arg >= TCG_REG_V0);
47c906ae 1416 if (have_vsx) {
6e11cde1
RH		 1417 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0,
1418 STXSDX, arg, base, offset);
47c906ae
RH		 1419 break;
1420 }
6ef14d7e
RH		 1421 tcg_debug_assert((offset & 7) == 0);
1422 if (offset & 8) {
1423 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
1424 arg = TCG_VEC_TMP1;
1425 }
1426 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
1427 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4);
1428 break;
1429 case TCG_TYPE_V128:
1430 tcg_debug_assert(arg >= TCG_REG_V0);
6e11cde1
RH		 1431 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0,
1432 STVX, arg, base, offset);
6ef14d7e
RH		 1433 break;
1434 default:
1435 g_assert_not_reached();
fedee3e7 1436 }
d604f1a9 1437}
810260a8 1438
59d7c14e
RH		 1439static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
1440 TCGReg base, intptr_t ofs)
1441{
1442 return false;
1443}
1444
d604f1a9
RH		 1445static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1446 int const_arg2, int cr, TCGType type)
1447{
1448 int imm;
1449 uint32_t op;
810260a8 1450
abcf61c4
RH		 1451 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
1452
d604f1a9
RH		 1453 /* Simplify the comparisons below wrt CMPI. */
1454 if (type == TCG_TYPE_I32) {
1455 arg2 = (int32_t)arg2;
4a40e231 1456 }
fedee3e7 1457
d604f1a9
RH		 1458 switch (cond) {
1459 case TCG_COND_EQ:
1460 case TCG_COND_NE:
1461 if (const_arg2) {
1462 if ((int16_t) arg2 == arg2) {
1463 op = CMPI;
1464 imm = 1;
1465 break;
1466 } else if ((uint16_t) arg2 == arg2) {
1467 op = CMPLI;
1468 imm = 1;
1469 break;
1470 }
1471 }
1472 op = CMPL;
1473 imm = 0;
1474 break;
fedee3e7 1475
d604f1a9
RH		 1476 case TCG_COND_LT:
1477 case TCG_COND_GE:
1478 case TCG_COND_LE:
1479 case TCG_COND_GT:
1480 if (const_arg2) {
1481 if ((int16_t) arg2 == arg2) {
1482 op = CMPI;
1483 imm = 1;
1484 break;
1485 }
1486 }
1487 op = CMP;
1488 imm = 0;
1489 break;
fedee3e7 1490
d604f1a9
RH		 1491 case TCG_COND_LTU:
1492 case TCG_COND_GEU:
1493 case TCG_COND_LEU:
1494 case TCG_COND_GTU:
1495 if (const_arg2) {
1496 if ((uint16_t) arg2 == arg2) {
1497 op = CMPLI;
1498 imm = 1;
1499 break;
1500 }
1501 }
1502 op = CMPL;
1503 imm = 0;
1504 break;
fedee3e7 1505
d604f1a9
RH		 1506 default:
1507 tcg_abort();
fedee3e7 1508 }
d604f1a9 1509 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
fedee3e7 1510
d604f1a9
RH		 1511 if (imm) {
1512 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1513 } else {
1514 if (const_arg2) {
1515 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1516 arg2 = TCG_REG_R0;
1517 }
1518 tcg_out32(s, op | RA(arg1) | RB(arg2));
1519 }
810260a8 1520}
1521
d604f1a9
RH		 1522static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1523 TCGReg dst, TCGReg src)
7f12d649 1524{
a757e1ee
RH		 1525 if (type == TCG_TYPE_I32) {
1526 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
1527 tcg_out_shri32(s, dst, dst, 5);
1528 } else {
1529 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
1530 tcg_out_shri64(s, dst, dst, 6);
1531 }
7f12d649
RH		 1532}
1533
d604f1a9 1534static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
7f12d649 1535{
d604f1a9
RH		 1536 /* X != 0 implies X + -1 generates a carry. Extra addition
1537 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1538 if (dst != src) {
1539 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1540 tcg_out32(s, SUBFE | TAB(dst, dst, src));
7f12d649 1541 } else {
d604f1a9
RH		 1542 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1543 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
7f12d649 1544 }
d604f1a9 1545}
7f12d649 1546
d604f1a9
RH		 1547static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1548 bool const_arg2)
1549{
1550 if (const_arg2) {
1551 if ((uint32_t)arg2 == arg2) {
1552 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1553 } else {
1554 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1555 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1556 }
1557 } else {
1558 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1559 }
1560 return TCG_REG_R0;
7f12d649
RH		 1561}
1562
d604f1a9
RH		 1563static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1564 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1565 int const_arg2)
7f12d649 1566{
d604f1a9 1567 int crop, sh;
7f12d649 1568
eabb7b91 1569 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
a757e1ee 1570
d604f1a9
RH		 1571 /* Ignore high bits of a potential constant arg2. */
1572 if (type == TCG_TYPE_I32) {
1573 arg2 = (uint32_t)arg2;
1574 }
7f12d649 1575
d604f1a9
RH		 1576 /* Handle common and trivial cases before handling anything else. */
1577 if (arg2 == 0) {
1578 switch (cond) {
1579 case TCG_COND_EQ:
1580 tcg_out_setcond_eq0(s, type, arg0, arg1);
1581 return;
1582 case TCG_COND_NE:
a757e1ee 1583 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1584 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1585 arg1 = TCG_REG_R0;
1586 }
1587 tcg_out_setcond_ne0(s, arg0, arg1);
1588 return;
1589 case TCG_COND_GE:
1590 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1591 arg1 = arg0;
1592 /* FALLTHRU */
1593 case TCG_COND_LT:
1594 /* Extract the sign bit. */
a757e1ee
RH		 1595 if (type == TCG_TYPE_I32) {
1596 tcg_out_shri32(s, arg0, arg1, 31);
1597 } else {
1598 tcg_out_shri64(s, arg0, arg1, 63);
1599 }
d604f1a9
RH		 1600 return;
1601 default:
1602 break;
1603 }
1604 }
7f12d649 1605
d604f1a9
RH		 1606 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1607 All other cases below are also at least 3 insns, so speed up the
1608 code generator by not considering them and always using ISEL. */
63922f46 1609 if (have_isel) {
d604f1a9 1610 int isel, tab;
7f12d649 1611
d604f1a9 1612 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
7f12d649 1613
d604f1a9 1614 isel = tcg_to_isel[cond];
7f12d649 1615
d604f1a9
RH		 1616 tcg_out_movi(s, type, arg0, 1);
1617 if (isel & 1) {
1618 /* arg0 = (bc ? 0 : 1) */
1619 tab = TAB(arg0, 0, arg0);
1620 isel &= ~1;
1621 } else {
1622 /* arg0 = (bc ? 1 : 0) */
1623 tcg_out_movi(s, type, TCG_REG_R0, 0);
1624 tab = TAB(arg0, arg0, TCG_REG_R0);
1625 }
1626 tcg_out32(s, isel | tab);
1627 return;
1628 }
49d9870a 1629
d604f1a9
RH		 1630 switch (cond) {
1631 case TCG_COND_EQ:
1632 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1633 tcg_out_setcond_eq0(s, type, arg0, arg1);
1634 return;
810260a8 1635
d604f1a9
RH		 1636 case TCG_COND_NE:
1637 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1638 /* Discard the high bits only once, rather than both inputs. */
a757e1ee 1639 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1640 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1641 arg1 = TCG_REG_R0;
1642 }
1643 tcg_out_setcond_ne0(s, arg0, arg1);
1644 return;
810260a8 1645
d604f1a9
RH		 1646 case TCG_COND_GT:
1647 case TCG_COND_GTU:
1648 sh = 30;
1649 crop = 0;
1650 goto crtest;
810260a8 1651
d604f1a9
RH		 1652 case TCG_COND_LT:
1653 case TCG_COND_LTU:
1654 sh = 29;
1655 crop = 0;
1656 goto crtest;
810260a8 1657
d604f1a9
RH		 1658 case TCG_COND_GE:
1659 case TCG_COND_GEU:
1660 sh = 31;
1661 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1662 goto crtest;
810260a8 1663
d604f1a9
RH		 1664 case TCG_COND_LE:
1665 case TCG_COND_LEU:
1666 sh = 31;
1667 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1668 crtest:
1669 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1670 if (crop) {
1671 tcg_out32(s, crop);
1672 }
1673 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1674 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1675 break;
1676
1677 default:
1678 tcg_abort();
1679 }
810260a8 1680}
1681
bec16311 1682static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
810260a8 1683{
d604f1a9 1684 if (l->has_value) {
d54401df 1685 bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr);
49d9870a 1686 } else {
bec16311 1687 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
810260a8 1688 }
f9c7246f 1689 tcg_out32(s, bc);
810260a8 1690}
1691
d604f1a9
RH		 1692static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1693 TCGArg arg1, TCGArg arg2, int const_arg2,
bec16311 1694 TCGLabel *l, TCGType type)
810260a8 1695{
d604f1a9 1696 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
bec16311 1697 tcg_out_bc(s, tcg_to_bc[cond], l);
d604f1a9 1698}
fa94c3be 1699
d604f1a9
RH		 1700static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1701 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1702 TCGArg v2, bool const_c2)
1703{
1704 /* If for some reason both inputs are zero, don't produce bad code. */
1705 if (v1 == 0 && v2 == 0) {
1706 tcg_out_movi(s, type, dest, 0);
1707 return;
b9e946c7 1708 }
f6548c0a 1709
d604f1a9 1710 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
a69abbe0 1711
63922f46 1712 if (have_isel) {
d604f1a9 1713 int isel = tcg_to_isel[cond];
810260a8 1714
d604f1a9
RH		 1715 /* Swap the V operands if the operation indicates inversion. */
1716 if (isel & 1) {
1717 int t = v1;
1718 v1 = v2;
1719 v2 = t;
1720 isel &= ~1;
1721 }
1722 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1723 if (v2 == 0) {
1724 tcg_out_movi(s, type, TCG_REG_R0, 0);
1725 }
1726 tcg_out32(s, isel | TAB(dest, v1, v2));
1727 } else {
1728 if (dest == v2) {
1729 cond = tcg_invert_cond(cond);
1730 v2 = v1;
1731 } else if (dest != v1) {
1732 if (v1 == 0) {
1733 tcg_out_movi(s, type, dest, 0);
1734 } else {
1735 tcg_out_mov(s, type, dest, v1);
1736 }
1737 }
1738 /* Branch forward over one insn */
1739 tcg_out32(s, tcg_to_bc[cond] | 8);
1740 if (v2 == 0) {
1741 tcg_out_movi(s, type, dest, 0);
1742 } else {
1743 tcg_out_mov(s, type, dest, v2);
1744 }
29b69198 1745 }
810260a8 1746}
1747
d0b07481
RH		 1748static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
1749 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
1750{
1751 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
1752 tcg_out32(s, opc | RA(a0) | RS(a1));
1753 } else {
1754 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
1755 /* Note that the only other valid constant for a2 is 0. */
63922f46 1756 if (have_isel) {
d0b07481
RH		 1757 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
1758 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
1759 } else if (!const_a2 && a0 == a2) {
1760 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
1761 tcg_out32(s, opc | RA(a0) | RS(a1));
1762 } else {
1763 tcg_out32(s, opc | RA(a0) | RS(a1));
1764 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
1765 if (const_a2) {
1766 tcg_out_movi(s, type, a0, 0);
1767 } else {
1768 tcg_out_mov(s, type, a0, a2);
1769 }
1770 }
1771 }
1772}
1773
abcf61c4
RH		 1774static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1775 const int *const_args)
1776{
1777 static const struct { uint8_t bit1, bit2; } bits[] = {
1778 [TCG_COND_LT ] = { CR_LT, CR_LT },
1779 [TCG_COND_LE ] = { CR_LT, CR_GT },
1780 [TCG_COND_GT ] = { CR_GT, CR_GT },
1781 [TCG_COND_GE ] = { CR_GT, CR_LT },
1782 [TCG_COND_LTU] = { CR_LT, CR_LT },
1783 [TCG_COND_LEU] = { CR_LT, CR_GT },
1784 [TCG_COND_GTU] = { CR_GT, CR_GT },
1785 [TCG_COND_GEU] = { CR_GT, CR_LT },
1786 };
1787
1788 TCGCond cond = args[4], cond2;
1789 TCGArg al, ah, bl, bh;
1790 int blconst, bhconst;
1791 int op, bit1, bit2;
1792
1793 al = args[0];
1794 ah = args[1];
1795 bl = args[2];
1796 bh = args[3];
1797 blconst = const_args[2];
1798 bhconst = const_args[3];
1799
1800 switch (cond) {
1801 case TCG_COND_EQ:
1802 op = CRAND;
1803 goto do_equality;
1804 case TCG_COND_NE:
1805 op = CRNAND;
1806 do_equality:
1807 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1808 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1809 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1810 break;
1811
1812 case TCG_COND_LT:
1813 case TCG_COND_LE:
1814 case TCG_COND_GT:
1815 case TCG_COND_GE:
1816 case TCG_COND_LTU:
1817 case TCG_COND_LEU:
1818 case TCG_COND_GTU:
1819 case TCG_COND_GEU:
1820 bit1 = bits[cond].bit1;
1821 bit2 = bits[cond].bit2;
1822 op = (bit1 != bit2 ? CRANDC : CRAND);
1823 cond2 = tcg_unsigned_cond(cond);
1824
1825 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1826 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1827 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1828 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1829 break;
1830
1831 default:
1832 tcg_abort();
1833 }
1834}
1835
1836static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1837 const int *const_args)
1838{
1839 tcg_out_cmp2(s, args + 1, const_args + 1);
1840 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1841 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1842}
1843
1844static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1845 const int *const_args)
1846{
1847 tcg_out_cmp2(s, args, const_args);
bec16311 1848 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
abcf61c4
RH		 1849}
1850
7b4af5ee
PK		 1851static void tcg_out_mb(TCGContext *s, TCGArg a0)
1852{
fc879703
NP		 1853 uint32_t insn;
1854
1855 if (a0 & TCG_MO_ST_LD) {
1856 insn = HWSYNC;
1857 } else {
7b4af5ee 1858 insn = LWSYNC;
7b4af5ee 1859 }
fc879703 1860
7b4af5ee
PK		 1861 tcg_out32(s, insn);
1862}
1863
8605cbcd
RH		 1864static void tcg_out_call_int(TCGContext *s, int lk,
1865 const tcg_insn_unit *target)
810260a8 1866{
eaf7d1cf 1867#ifdef _CALL_AIX
d604f1a9
RH		 1868 /* Look through the descriptor. If the branch is in range, and we
1869 don't have to spend too much effort on building the toc. */
2be7d76b
RH		 1870 const void *tgt = ((const void * const *)target)[0];
1871 uintptr_t toc = ((const uintptr_t *)target)[1];
d604f1a9 1872 intptr_t diff = tcg_pcrel_diff(s, tgt);
b18d5d2b 1873
d604f1a9 1874 if (in_range_b(diff) && toc == (uint32_t)toc) {
dfca1778 1875 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
8605cbcd 1876 tcg_out_b(s, lk, tgt);
541dd4ce 1877 } else {
d604f1a9
RH		 1878 /* Fold the low bits of the constant into the addresses below. */
1879 intptr_t arg = (intptr_t)target;
1880 int ofs = (int16_t)arg;
1881
1882 if (ofs + 8 < 0x8000) {
1883 arg -= ofs;
1884 } else {
1885 ofs = 0;
1886 }
dfca1778
RH		 1887 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1888 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
d604f1a9 1889 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
dfca1778 1890 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
8605cbcd 1891 tcg_out32(s, BCCTR | BO_ALWAYS | lk);
541dd4ce 1892 }
77e58d0d
UW		 1893#elif defined(_CALL_ELF) && _CALL_ELF == 2
1894 intptr_t diff;
1895
1896 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1897 address, which the callee uses to compute its TOC address. */
1898 /* FIXME: when the branch is in range, we could avoid r12 load if we
1899 knew that the destination uses the same TOC, and what its local
1900 entry point offset is. */
1901 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1902
1903 diff = tcg_pcrel_diff(s, target);
1904 if (in_range_b(diff)) {
8605cbcd 1905 tcg_out_b(s, lk, target);
77e58d0d
UW		 1906 } else {
1907 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
8605cbcd 1908 tcg_out32(s, BCCTR | BO_ALWAYS | lk);
77e58d0d 1909 }
eaf7d1cf 1910#else
8605cbcd 1911 tcg_out_b(s, lk, target);
d604f1a9 1912#endif
810260a8 1913}
1914
cee44b03
RH		 1915static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target,
1916 const TCGHelperInfo *info)
8605cbcd
RH		 1917{
1918 tcg_out_call_int(s, LK, target);
1919}
1920
4b473e0c 1921static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = {
d604f1a9
RH		 1922 [MO_UB] = LBZX,
1923 [MO_UW] = LHZX,
1924 [MO_UL] = LWZX,
fc313c64 1925 [MO_UQ] = LDX,
d604f1a9
RH		 1926 [MO_SW] = LHAX,
1927 [MO_SL] = LWAX,
1928 [MO_BSWAP | MO_UB] = LBZX,
1929 [MO_BSWAP | MO_UW] = LHBRX,
1930 [MO_BSWAP | MO_UL] = LWBRX,
fc313c64 1931 [MO_BSWAP | MO_UQ] = LDBRX,
d604f1a9 1932};
810260a8 1933
4b473e0c 1934static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = {
d604f1a9
RH		 1935 [MO_UB] = STBX,
1936 [MO_UW] = STHX,
1937 [MO_UL] = STWX,
fc313c64 1938 [MO_UQ] = STDX,
d604f1a9
RH		 1939 [MO_BSWAP | MO_UB] = STBX,
1940 [MO_BSWAP | MO_UW] = STHBRX,
1941 [MO_BSWAP | MO_UL] = STWBRX,
fc313c64 1942 [MO_BSWAP | MO_UQ] = STDBRX,
d604f1a9 1943};
991041a4 1944
d604f1a9
RH		 1945static const uint32_t qemu_exts_opc[4] = {
1946 EXTSB, EXTSH, EXTSW, 0
1947};
810260a8 1948
d604f1a9
RH		 1949#if defined (CONFIG_SOFTMMU)
1950/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1951 * int mmu_idx, uintptr_t ra)
1952 */
4b473e0c 1953static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
d604f1a9
RH		 1954 [MO_UB] = helper_ret_ldub_mmu,
1955 [MO_LEUW] = helper_le_lduw_mmu,
1956 [MO_LEUL] = helper_le_ldul_mmu,
fc313c64 1957 [MO_LEUQ] = helper_le_ldq_mmu,
d604f1a9
RH		 1958 [MO_BEUW] = helper_be_lduw_mmu,
1959 [MO_BEUL] = helper_be_ldul_mmu,
fc313c64 1960 [MO_BEUQ] = helper_be_ldq_mmu,
d604f1a9 1961};
810260a8 1962
d604f1a9
RH		 1963/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1964 * uintxx_t val, int mmu_idx, uintptr_t ra)
1965 */
4b473e0c 1966static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
d604f1a9
RH		 1967 [MO_UB] = helper_ret_stb_mmu,
1968 [MO_LEUW] = helper_le_stw_mmu,
1969 [MO_LEUL] = helper_le_stl_mmu,
fc313c64 1970 [MO_LEUQ] = helper_le_stq_mmu,
d604f1a9
RH		 1971 [MO_BEUW] = helper_be_stw_mmu,
1972 [MO_BEUL] = helper_be_stl_mmu,
fc313c64 1973 [MO_BEUQ] = helper_be_stq_mmu,
d604f1a9 1974};
810260a8 1975
269bd5d8
RH		 1976/* We expect to use a 16-bit negative offset from ENV. */
1977QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1978QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1979
d604f1a9
RH		 1980/* Perform the TLB load and compare. Places the result of the comparison
1981 in CR7, loads the addend of the TLB into R3, and returns the register
1982 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1983
14776ab5 1984static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
7f25c469 1985 TCGReg addrlo, TCGReg addrhi,
d604f1a9
RH		 1986 int mem_index, bool is_read)
1987{
1988 int cmp_off
1989 = (is_read
644f591a
RH		 1990 ? offsetof(CPUTLBEntry, addr_read)
1991 : offsetof(CPUTLBEntry, addr_write));
269bd5d8
RH		 1992 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1993 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1994 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
85aa8081
RH		 1995 unsigned s_bits = opc & MO_SIZE;
1996 unsigned a_bits = get_alignment_bits(opc);
d604f1a9 1997
644f591a 1998 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
269bd5d8
RH		 1999 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
2000 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
644f591a
RH		 2001
2002 /* Extract the page index, shifted into place for tlb index. */
2003 if (TCG_TARGET_REG_BITS == 32) {
2004 tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
2005 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
4c314da6 2006 } else {
644f591a
RH		 2007 tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
2008 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
810260a8 2009 }
644f591a 2010 tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
810260a8 2011
644f591a
RH		 2012 /* Load the TLB comparator. */
2013 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
2014 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
2015 ? LWZUX : LDUX);
2016 tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
7f25c469 2017 } else {
644f591a
RH		 2018 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
2019 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2020 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
2021 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
2022 } else {
2023 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
2024 }
7f25c469 2025 }
d604f1a9
RH		 2026
2027 /* Load the TLB addend for use on the fast path. Do this asap
2028 to minimize any load use delay. */
644f591a
RH		 2029 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3,
2030 offsetof(CPUTLBEntry, addend));
d604f1a9 2031
68d45bb6 2032 /* Clear the non-page, non-alignment bits from the address */
85aa8081
RH		 2033 if (TCG_TARGET_REG_BITS == 32) {
2034 /* We don't support unaligned accesses on 32-bits.
2035 * Preserve the bottom bits and thus trigger a comparison
2036 * failure on unaligned accesses.
68d45bb6 2037 */
85aa8081 2038 if (a_bits < s_bits) {
1f00b27f
SS		 2039 a_bits = s_bits;
2040 }
7f25c469 2041 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
1f00b27f 2042 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
85aa8081
RH		 2043 } else {
2044 TCGReg t = addrlo;
2045
2046 /* If the access is unaligned, we need to make sure we fail if we
2047 * cross a page boundary. The trick is to add the access size-1
2048 * to the address before masking the low bits. That will make the
2049 * address overflow to the next page if we cross a page boundary,
2050 * which will then force a mismatch of the TLB compare.
2051 */
2052 if (a_bits < s_bits) {
2053 unsigned a_mask = (1 << a_bits) - 1;
2054 unsigned s_mask = (1 << s_bits) - 1;
2055 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
2056 t = TCG_REG_R0;
2057 }
2058
2059 /* Mask the address for the requested alignment. */
2060 if (TARGET_LONG_BITS == 32) {
2061 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
2062 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
644f591a
RH		 2063 /* Zero-extend the address for use in the final address. */
2064 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
2065 addrlo = TCG_REG_R4;
85aa8081
RH		 2066 } else if (a_bits == 0) {
2067 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
2068 } else {
2069 tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
1f00b27f 2070 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
68d45bb6 2071 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
68d45bb6 2072 }
70fac59a 2073 }
d604f1a9 2074
7f25c469 2075 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
dfca1778
RH		 2076 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
2077 0, 7, TCG_TYPE_I32);
7f25c469
RH		 2078 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
2079 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
2080 } else {
dfca1778
RH		 2081 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
2082 0, 7, TCG_TYPE_TL);
7f25c469 2083 }
d604f1a9 2084
7f25c469 2085 return addrlo;
70fac59a 2086}
1cd62ae9 2087
d604f1a9
RH		 2088/* Record the context of a call to the out of line helper code for the slow
2089 path for a load or store, so that we can later generate the correct
2090 helper code. */
9002ffcb 2091static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
7f25c469
RH		 2092 TCGReg datalo_reg, TCGReg datahi_reg,
2093 TCGReg addrlo_reg, TCGReg addrhi_reg,
3972ef6f 2094 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
70fac59a 2095{
d604f1a9
RH		 2096 TCGLabelQemuLdst *label = new_ldst_label(s);
2097
2098 label->is_ld = is_ld;
3972ef6f 2099 label->oi = oi;
7f25c469
RH		 2100 label->datalo_reg = datalo_reg;
2101 label->datahi_reg = datahi_reg;
2102 label->addrlo_reg = addrlo_reg;
2103 label->addrhi_reg = addrhi_reg;
e5e2e4c7 2104 label->raddr = tcg_splitwx_to_rx(raddr);
7f25c469 2105 label->label_ptr[0] = lptr;
70fac59a 2106}
1cd62ae9 2107
aeee05f5 2108static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
70fac59a 2109{
9002ffcb 2110 MemOpIdx oi = lb->oi;
14776ab5 2111 MemOp opc = get_memop(oi);
7f25c469 2112 TCGReg hi, lo, arg = TCG_REG_R3;
70fac59a 2113
d54401df 2114 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
aeee05f5
RH		 2115 return false;
2116 }
70fac59a 2117
7f25c469 2118 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1cd62ae9 2119
7f25c469
RH		 2120 lo = lb->addrlo_reg;
2121 hi = lb->addrhi_reg;
2122 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
c8eef960 2123 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
7f25c469
RH		 2124 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2125 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2126 } else {
2127 /* If the address needed to be zero-extended, we'll have already
2128 placed it in R4. The only remaining case is 64-bit guest. */
2129 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
2130 }
752c1fdb 2131
3972ef6f 2132 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 2133 tcg_out32(s, MFSPR | RT(arg) | LR);
70fac59a 2134
cee44b03 2135 tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
70fac59a 2136
7f25c469
RH		 2137 lo = lb->datalo_reg;
2138 hi = lb->datahi_reg;
2139 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
2140 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
2141 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
2142 } else if (opc & MO_SIGN) {
d604f1a9 2143 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
7f25c469 2144 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
d604f1a9 2145 } else {
7f25c469 2146 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
70fac59a
RH		 2147 }
2148
d604f1a9 2149 tcg_out_b(s, 0, lb->raddr);
aeee05f5 2150 return true;
d604f1a9 2151}
70fac59a 2152
aeee05f5 2153static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
d604f1a9 2154{
9002ffcb 2155 MemOpIdx oi = lb->oi;
14776ab5
TN		 2156 MemOp opc = get_memop(oi);
2157 MemOp s_bits = opc & MO_SIZE;
7f25c469 2158 TCGReg hi, lo, arg = TCG_REG_R3;
1cd62ae9 2159
d54401df 2160 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
aeee05f5
RH		 2161 return false;
2162 }
1cd62ae9 2163
7f25c469
RH		 2164 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
2165
2166 lo = lb->addrlo_reg;
2167 hi = lb->addrhi_reg;
2168 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
c8eef960 2169 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
7f25c469
RH		 2170 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2171 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2172 } else {
2173 /* If the address needed to be zero-extended, we'll have already
2174 placed it in R4. The only remaining case is 64-bit guest. */
2175 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
2176 }
1cd62ae9 2177
7f25c469
RH		 2178 lo = lb->datalo_reg;
2179 hi = lb->datahi_reg;
2180 if (TCG_TARGET_REG_BITS == 32) {
2181 switch (s_bits) {
2182 case MO_64:
c8eef960 2183 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
7f25c469
RH		 2184 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
2185 /* FALLTHRU */
2186 case MO_32:
2187 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
2188 break;
2189 default:
2190 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
2191 break;
2192 }
2193 } else {
2194 if (s_bits == MO_64) {
2195 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
2196 } else {
2197 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
2198 }
2199 }
1cd62ae9 2200
3972ef6f 2201 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 2202 tcg_out32(s, MFSPR | RT(arg) | LR);
1cd62ae9 2203
cee44b03 2204 tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
d604f1a9
RH		 2205
2206 tcg_out_b(s, 0, lb->raddr);
aeee05f5 2207 return true;
1cd62ae9 2208}
8605cbcd
RH		 2209#else
2210
2211static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
2212 TCGReg addrhi, unsigned a_bits)
2213{
2214 unsigned a_mask = (1 << a_bits) - 1;
2215 TCGLabelQemuLdst *label = new_ldst_label(s);
2216
2217 label->is_ld = is_ld;
2218 label->addrlo_reg = addrlo;
2219 label->addrhi_reg = addrhi;
2220
2221 /* We are expecting a_bits to max out at 7, much lower than ANDI. */
2222 tcg_debug_assert(a_bits < 16);
2223 tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask));
2224
2225 label->label_ptr[0] = s->code_ptr;
2226 tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
2227
2228 label->raddr = tcg_splitwx_to_rx(s->code_ptr);
2229}
2230
2231static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
2232{
2233 if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
2234 return false;
2235 }
2236
2237 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
2238 TCGReg arg = TCG_REG_R4;
c8eef960
RH		 2239
2240 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
8605cbcd
RH		 2241 if (l->addrlo_reg != arg) {
2242 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg);
2243 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg);
2244 } else if (l->addrhi_reg != arg + 1) {
2245 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg);
2246 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg);
2247 } else {
2248 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg);
2249 tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1);
2250 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0);
2251 }
2252 } else {
2253 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg);
2254 }
2255 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0);
2256
2257 /* "Tail call" to the helper, with the return address back inline. */
2258 tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld
2259 : helper_unaligned_st));
2260 return true;
2261}
2262
2263static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
2264{
2265 return tcg_out_fail_alignment(s, l);
2266}
2267
2268static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
2269{
2270 return tcg_out_fail_alignment(s, l);
2271}
2272
d604f1a9 2273#endif /* SOFTMMU */
1cd62ae9 2274
7f25c469 2275static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
810260a8 2276{
7f25c469
RH		 2277 TCGReg datalo, datahi, addrlo, rbase;
2278 TCGReg addrhi __attribute__((unused));
9002ffcb 2279 MemOpIdx oi;
14776ab5 2280 MemOp opc, s_bits;
d604f1a9 2281#ifdef CONFIG_SOFTMMU
7f25c469 2282 int mem_index;
d604f1a9 2283 tcg_insn_unit *label_ptr;
8605cbcd
RH		 2284#else
2285 unsigned a_bits;
d604f1a9 2286#endif
810260a8 2287
7f25c469
RH		 2288 datalo = *args++;
2289 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
2290 addrlo = *args++;
2291 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 2292 oi = *args++;
2293 opc = get_memop(oi);
7f25c469
RH		 2294 s_bits = opc & MO_SIZE;
2295
d604f1a9 2296#ifdef CONFIG_SOFTMMU
59227d5d 2297 mem_index = get_mmuidx(oi);
68d45bb6 2298 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
d604f1a9
RH		 2299
2300 /* Load a pointer into the current opcode w/conditional branch-link. */
2301 label_ptr = s->code_ptr;
f9c7246f 2302 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
d604f1a9
RH		 2303
2304 rbase = TCG_REG_R3;
2305#else /* !CONFIG_SOFTMMU */
8605cbcd
RH		 2306 a_bits = get_alignment_bits(opc);
2307 if (a_bits) {
2308 tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
2309 }
b76f21a7 2310 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 2311 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 2312 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
2313 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 2314 }
2315#endif
2316
7f25c469
RH		 2317 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
2318 if (opc & MO_BSWAP) {
2319 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2320 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
2321 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
2322 } else if (rbase != 0) {
2323 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2324 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
2325 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
2326 } else if (addrlo == datahi) {
2327 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
2328 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
2329 } else {
2330 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
2331 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
2332 }
541dd4ce 2333 } else {
2b7ec66f 2334 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
4e33fe01 2335 if (!have_isa_2_06 && insn == LDBRX) {
7f25c469
RH		 2336 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2337 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
2338 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
2339 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
2340 } else if (insn) {
2341 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
2342 } else {
2343 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
2344 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
2345 insn = qemu_exts_opc[s_bits];
2346 tcg_out32(s, insn | RA(datalo) | RS(datalo));
2347 }
810260a8 2348 }
810260a8 2349
d604f1a9 2350#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 2351 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
2352 s->code_ptr, label_ptr);
d604f1a9 2353#endif
810260a8 2354}
2355
7f25c469 2356static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
027ffea9 2357{
7f25c469
RH		 2358 TCGReg datalo, datahi, addrlo, rbase;
2359 TCGReg addrhi __attribute__((unused));
9002ffcb 2360 MemOpIdx oi;
14776ab5 2361 MemOp opc, s_bits;
d604f1a9 2362#ifdef CONFIG_SOFTMMU
7f25c469 2363 int mem_index;
d604f1a9 2364 tcg_insn_unit *label_ptr;
8605cbcd
RH		 2365#else
2366 unsigned a_bits;
d604f1a9 2367#endif
027ffea9 2368
7f25c469
RH		 2369 datalo = *args++;
2370 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
2371 addrlo = *args++;
2372 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 2373 oi = *args++;
2374 opc = get_memop(oi);
7f25c469
RH		 2375 s_bits = opc & MO_SIZE;
2376
d604f1a9 2377#ifdef CONFIG_SOFTMMU
59227d5d 2378 mem_index = get_mmuidx(oi);
68d45bb6 2379 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
027ffea9 2380
d604f1a9
RH		 2381 /* Load a pointer into the current opcode w/conditional branch-link. */
2382 label_ptr = s->code_ptr;
f9c7246f 2383 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
027ffea9 2384
d604f1a9
RH		 2385 rbase = TCG_REG_R3;
2386#else /* !CONFIG_SOFTMMU */
8605cbcd
RH		 2387 a_bits = get_alignment_bits(opc);
2388 if (a_bits) {
2389 tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
2390 }
b76f21a7 2391 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 2392 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 2393 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
2394 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 2395 }
2396#endif
2397
7f25c469
RH		 2398 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
2399 if (opc & MO_BSWAP) {
2400 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2401 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
2402 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
2403 } else if (rbase != 0) {
2404 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
2405 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
2406 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
2407 } else {
2408 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
2409 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
2410 }
027ffea9 2411 } else {
2b7ec66f 2412 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
4e33fe01 2413 if (!have_isa_2_06 && insn == STDBRX) {
7f25c469 2414 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
dfca1778 2415 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
7f25c469 2416 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
dfca1778 2417 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
7f25c469
RH		 2418 } else {
2419 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
2420 }
027ffea9 2421 }
d604f1a9
RH		 2422
2423#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 2424 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
2425 s->code_ptr, label_ptr);
d604f1a9 2426#endif
027ffea9
RH		 2427}
2428
53c89efd
RH		 2429static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
2430{
2431 int i;
2432 for (i = 0; i < count; ++i) {
2433 p[i] = NOP;
2434 }
2435}
2436
a921fddc
RH		 2437/* Parameters for function call generation, used in tcg.c. */
2438#define TCG_TARGET_STACK_ALIGN 16
a921fddc 2439
802ca56e
RH		 2440#ifdef _CALL_AIX
2441# define LINK_AREA_SIZE (6 * SZR)
2442# define LR_OFFSET (1 * SZR)
2443# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
2fa169ba 2444#elif defined(_CALL_DARWIN)
1045fc04
PM		 2445# define LINK_AREA_SIZE (6 * SZR)
2446# define LR_OFFSET (2 * SZR)
ffcfbece
RH		 2447#elif TCG_TARGET_REG_BITS == 64
2448# if defined(_CALL_ELF) && _CALL_ELF == 2
2449# define LINK_AREA_SIZE (4 * SZR)
2450# define LR_OFFSET (1 * SZR)
2451# endif
2452#else /* TCG_TARGET_REG_BITS == 32 */
2453# if defined(_CALL_SYSV)
ffcfbece
RH		 2454# define LINK_AREA_SIZE (2 * SZR)
2455# define LR_OFFSET (1 * SZR)
ffcfbece
RH		 2456# endif
2457#endif
2458#ifndef LR_OFFSET
2459# error "Unhandled abi"
2460#endif
2461#ifndef TCG_TARGET_CALL_STACK_OFFSET
a2a98f80 2462# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
802ca56e
RH		 2463#endif
2464
2465#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2466#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
d604f1a9 2467
802ca56e
RH		 2468#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
2469 + TCG_STATIC_CALL_ARGS_SIZE \
2470 + CPU_TEMP_BUF_SIZE \
2471 + REG_SAVE_SIZE \
2472 + TCG_TARGET_STACK_ALIGN - 1) \
2473 & -TCG_TARGET_STACK_ALIGN)
2474
2475#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
d604f1a9
RH		 2476
2477static void tcg_target_qemu_prologue(TCGContext *s)
810260a8 2478{
d604f1a9 2479 int i;
810260a8 2480
802ca56e 2481#ifdef _CALL_AIX
d54401df
RH		 2482 const void **desc = (const void **)s->code_ptr;
2483 desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */
2484 desc[1] = 0; /* environment pointer */
2485 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
d604f1a9
RH		 2486#endif
2487
a84ac4cb
RH		 2488 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
2489 CPU_TEMP_BUF_SIZE);
2490
d604f1a9
RH		 2491 /* Prologue */
2492 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
ffcfbece
RH		 2493 tcg_out32(s, (SZR == 8 ? STDU : STWU)
2494 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
802ca56e 2495
d604f1a9 2496 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 2497 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2498 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 2499 }
802ca56e 2500 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 2501
4cbea598 2502#ifndef CONFIG_SOFTMMU
b76f21a7 2503 if (guest_base) {
5964fca8 2504 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
d604f1a9
RH		 2505 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2506 }
2507#endif
2508
2509 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2510 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
5964fca8
RH		 2511 if (USE_REG_TB) {
2512 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
a84ac4cb 2513 }
5964fca8 2514 tcg_out32(s, BCCTR | BO_ALWAYS);
d604f1a9
RH		 2515
2516 /* Epilogue */
c8bc1168 2517 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
d604f1a9 2518
802ca56e 2519 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 2520 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 2521 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2522 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 2523 }
d604f1a9
RH		 2524 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
2525 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
2526 tcg_out32(s, BCLR | BO_ALWAYS);
810260a8 2527}
2528
b55a8d9d
RH		 2529static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg)
2530{
2531 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg);
2532 tcg_out_b(s, 0, tcg_code_gen_epilogue);
2533}
2534
cf7d6b8e 2535static void tcg_out_goto_tb(TCGContext *s, int which)
810260a8 2536{
20b66433
RH		 2537 uintptr_t ptr = get_jmp_target_addr(s, which);
2538
2539 if (USE_REG_TB) {
2540 ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr);
2541 tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset);
2542
2543 /* Direct branch will be patched by tb_target_set_jmp_target. */
cf7d6b8e 2544 set_jmp_insn_offset(s, which);
5964fca8 2545 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
20b66433
RH		 2546
2547 /* When branch is out of range, fall through to indirect. */
5bfd75a3 2548 tcg_out32(s, BCCTR | BO_ALWAYS);
20b66433
RH		 2549
2550 /* For the unlinked case, need to reset TCG_REG_TB. */
cf7d6b8e 2551 set_jmp_reset_offset(s, which);
20b66433
RH		 2552 tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB,
2553 -tcg_current_code_size(s));
cf7d6b8e 2554 } else {
20b66433 2555 /* Direct branch will be patched by tb_target_set_jmp_target. */
cf7d6b8e 2556 set_jmp_insn_offset(s, which);
20b66433
RH		 2557 tcg_out32(s, NOP);
2558
2559 /* When branch is out of range, fall through to indirect. */
2560 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr);
2561 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)ptr);
2562 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR);
2563 tcg_out32(s, BCCTR | BO_ALWAYS);
cf7d6b8e
RH		 2564 set_jmp_reset_offset(s, which);
2565 }
2566}
2567
20b66433
RH		 2568void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
2569 uintptr_t jmp_rx, uintptr_t jmp_rw)
2570{
2571 uintptr_t addr = tb->jmp_target_addr[n];
2572 intptr_t diff = addr - jmp_rx;
2573 tcg_insn_unit insn;
2574
2575 if (in_range_b(diff)) {
2576 insn = B | (diff & 0x3fffffc);
2577 } else if (USE_REG_TB) {
2578 insn = MTSPR | RS(TCG_REG_TB) | CTR;
2579 } else {
2580 insn = NOP;
2581 }
2582
2583 qatomic_set((uint32_t *)jmp_rw, insn);
2584 flush_idcache_range(jmp_rx, jmp_rw, 4);
2585}
2586
cf7d6b8e
RH		 2587static void tcg_out_op(TCGContext *s, TCGOpcode opc,
2588 const TCGArg args[TCG_MAX_OP_ARGS],
2589 const int const_args[TCG_MAX_OP_ARGS])
2590{
2591 TCGArg a0, a1, a2;
2592
2593 switch (opc) {
0c240785
RH		 2594 case INDEX_op_goto_ptr:
2595 tcg_out32(s, MTSPR | RS(args[0]) | CTR);
5964fca8
RH		 2596 if (USE_REG_TB) {
2597 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
2598 }
2599 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
0c240785
RH		 2600 tcg_out32(s, BCCTR | BO_ALWAYS);
2601 break;
810260a8 2602 case INDEX_op_br:
2603 {
bec16311 2604 TCGLabel *l = arg_label(args[0]);
f9c7246f 2605 uint32_t insn = B;
810260a8 2606
2607 if (l->has_value) {
d54401df
RH		 2608 insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr),
2609 l->u.value_ptr);
541dd4ce 2610 } else {
bec16311 2611 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
810260a8 2612 }
f9c7246f 2613 tcg_out32(s, insn);
810260a8 2614 }
2615 break;
810260a8 2616 case INDEX_op_ld8u_i32:
2617 case INDEX_op_ld8u_i64:
b18d5d2b 2618 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
810260a8 2619 break;
2620 case INDEX_op_ld8s_i32:
2621 case INDEX_op_ld8s_i64:
b18d5d2b 2622 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
f4bf14f4 2623 tcg_out_ext8s(s, args[0], args[0]);
810260a8 2624 break;
2625 case INDEX_op_ld16u_i32:
2626 case INDEX_op_ld16u_i64:
b18d5d2b 2627 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
810260a8 2628 break;
2629 case INDEX_op_ld16s_i32:
2630 case INDEX_op_ld16s_i64:
b18d5d2b 2631 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
810260a8 2632 break;
2633 case INDEX_op_ld_i32:
2634 case INDEX_op_ld32u_i64:
b18d5d2b 2635 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
810260a8 2636 break;
2637 case INDEX_op_ld32s_i64:
b18d5d2b 2638 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
810260a8 2639 break;
2640 case INDEX_op_ld_i64:
b18d5d2b 2641 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
810260a8 2642 break;
2643 case INDEX_op_st8_i32:
2644 case INDEX_op_st8_i64:
b18d5d2b 2645 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
810260a8 2646 break;
2647 case INDEX_op_st16_i32:
2648 case INDEX_op_st16_i64:
b18d5d2b 2649 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
810260a8 2650 break;
2651 case INDEX_op_st_i32:
2652 case INDEX_op_st32_i64:
b18d5d2b 2653 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
810260a8 2654 break;
2655 case INDEX_op_st_i64:
b18d5d2b 2656 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
810260a8 2657 break;
2658
2659 case INDEX_op_add_i32:
ee924fa6
RH		 2660 a0 = args[0], a1 = args[1], a2 = args[2];
2661 if (const_args[2]) {
ee924fa6 2662 do_addi_32:
b18d5d2b 2663 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
ee924fa6
RH		 2664 } else {
2665 tcg_out32(s, ADD | TAB(a0, a1, a2));
2666 }
810260a8 2667 break;
2668 case INDEX_op_sub_i32:
ee924fa6 2669 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2670 if (const_args[1]) {
2671 if (const_args[2]) {
2672 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
2673 } else {
2674 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2675 }
2676 } else if (const_args[2]) {
ee924fa6
RH		 2677 a2 = -a2;
2678 goto do_addi_32;
2679 } else {
2680 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2681 }
810260a8 2682 break;
2683
2684 case INDEX_op_and_i32:
37251b98 2685 a0 = args[0], a1 = args[1], a2 = args[2];
a9249dff 2686 if (const_args[2]) {
37251b98 2687 tcg_out_andi32(s, a0, a1, a2);
a9249dff 2688 } else {
37251b98 2689 tcg_out32(s, AND | SAB(a1, a0, a2));
a9249dff
RH		 2690 }
2691 break;
2692 case INDEX_op_and_i64:
37251b98 2693 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2694 if (const_args[2]) {
37251b98 2695 tcg_out_andi64(s, a0, a1, a2);
637af30c 2696 } else {
37251b98 2697 tcg_out32(s, AND | SAB(a1, a0, a2));
810260a8 2698 }
810260a8 2699 break;
fe6f943f 2700 case INDEX_op_or_i64:
810260a8 2701 case INDEX_op_or_i32:
dce74c57 2702 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2703 if (const_args[2]) {
dce74c57
RH		 2704 tcg_out_ori32(s, a0, a1, a2);
2705 } else {
2706 tcg_out32(s, OR | SAB(a1, a0, a2));
810260a8 2707 }
810260a8 2708 break;
fe6f943f 2709 case INDEX_op_xor_i64:
810260a8 2710 case INDEX_op_xor_i32:
dce74c57 2711 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2712 if (const_args[2]) {
dce74c57
RH		 2713 tcg_out_xori32(s, a0, a1, a2);
2714 } else {
2715 tcg_out32(s, XOR | SAB(a1, a0, a2));
810260a8 2716 }
810260a8 2717 break;
ce1010d6 2718 case INDEX_op_andc_i32:
37251b98
RH		 2719 a0 = args[0], a1 = args[1], a2 = args[2];
2720 if (const_args[2]) {
2721 tcg_out_andi32(s, a0, a1, ~a2);
2722 } else {
2723 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2724 }
2725 break;
ce1010d6 2726 case INDEX_op_andc_i64:
37251b98
RH		 2727 a0 = args[0], a1 = args[1], a2 = args[2];
2728 if (const_args[2]) {
2729 tcg_out_andi64(s, a0, a1, ~a2);
2730 } else {
2731 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2732 }
ce1010d6
RH		 2733 break;
2734 case INDEX_op_orc_i32:
37251b98
RH		 2735 if (const_args[2]) {
2736 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2737 break;
2738 }
2739 /* FALLTHRU */
ce1010d6
RH		 2740 case INDEX_op_orc_i64:
2741 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2742 break;
2743 case INDEX_op_eqv_i32:
37251b98
RH		 2744 if (const_args[2]) {
2745 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2746 break;
2747 }
2748 /* FALLTHRU */
ce1010d6
RH		 2749 case INDEX_op_eqv_i64:
2750 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2751 break;
2752 case INDEX_op_nand_i32:
2753 case INDEX_op_nand_i64:
2754 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2755 break;
2756 case INDEX_op_nor_i32:
2757 case INDEX_op_nor_i64:
2758 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2759 break;
810260a8 2760
d0b07481
RH		 2761 case INDEX_op_clz_i32:
2762 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
2763 args[2], const_args[2]);
2764 break;
2765 case INDEX_op_ctz_i32:
2766 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
2767 args[2], const_args[2]);
2768 break;
33e75fb9
RH		 2769 case INDEX_op_ctpop_i32:
2770 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
2771 break;
d0b07481
RH		 2772
2773 case INDEX_op_clz_i64:
2774 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
2775 args[2], const_args[2]);
2776 break;
2777 case INDEX_op_ctz_i64:
2778 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
2779 args[2], const_args[2]);
2780 break;
33e75fb9
RH		 2781 case INDEX_op_ctpop_i64:
2782 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
2783 break;
d0b07481 2784
810260a8 2785 case INDEX_op_mul_i32:
ef809300 2786 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2787 if (const_args[2]) {
ef809300
RH		 2788 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2789 } else {
2790 tcg_out32(s, MULLW | TAB(a0, a1, a2));
810260a8 2791 }
810260a8 2792 break;
2793
2794 case INDEX_op_div_i32:
541dd4ce 2795 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
810260a8 2796 break;
2797
2798 case INDEX_op_divu_i32:
541dd4ce 2799 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
810260a8 2800 break;
2801
4d573822
MKF		 2802 case INDEX_op_rem_i32:
2803 tcg_out32(s, MODSW | TAB(args[0], args[1], args[2]));
2804 break;
2805
2806 case INDEX_op_remu_i32:
2807 tcg_out32(s, MODUW | TAB(args[0], args[1], args[2]));
2808 break;
2809
810260a8 2810 case INDEX_op_shl_i32:
2811 if (const_args[2]) {
94248cfc
CF		 2812 /* Limit immediate shift count lest we create an illegal insn. */
2813 tcg_out_shli32(s, args[0], args[1], args[2] & 31);
9e555b73 2814 } else {
541dd4ce 2815 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
9e555b73 2816 }
810260a8 2817 break;
2818 case INDEX_op_shr_i32:
2819 if (const_args[2]) {
94248cfc
CF		 2820 /* Limit immediate shift count lest we create an illegal insn. */
2821 tcg_out_shri32(s, args[0], args[1], args[2] & 31);
9e555b73 2822 } else {
541dd4ce 2823 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
9e555b73 2824 }
810260a8 2825 break;
2826 case INDEX_op_sar_i32:
541dd4ce 2827 if (const_args[2]) {
05dd01fa 2828 tcg_out_sari32(s, args[0], args[1], args[2]);
541dd4ce
RH		 2829 } else {
2830 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2831 }
810260a8 2832 break;
313d91c7
RH		 2833 case INDEX_op_rotl_i32:
2834 if (const_args[2]) {
2835 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2836 } else {
2837 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2838 | MB(0) | ME(31));
2839 }
2840 break;
2841 case INDEX_op_rotr_i32:
2842 if (const_args[2]) {
2843 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2844 } else {
8327a470
RH		 2845 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2846 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
313d91c7
RH		 2847 | MB(0) | ME(31));
2848 }
2849 break;
810260a8 2850
2851 case INDEX_op_brcond_i32:
4c314da6 2852 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2853 arg_label(args[3]), TCG_TYPE_I32);
e924bbec 2854 break;
810260a8 2855 case INDEX_op_brcond_i64:
4c314da6 2856 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2857 arg_label(args[3]), TCG_TYPE_I64);
810260a8 2858 break;
abcf61c4
RH		 2859 case INDEX_op_brcond2_i32:
2860 tcg_out_brcond2(s, args, const_args);
2861 break;
810260a8 2862
2863 case INDEX_op_neg_i32:
810260a8 2864 case INDEX_op_neg_i64:
541dd4ce 2865 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
810260a8 2866 break;
2867
157f2662 2868 case INDEX_op_not_i32:
2869 case INDEX_op_not_i64:
541dd4ce 2870 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
157f2662 2871 break;
2872
810260a8 2873 case INDEX_op_add_i64:
ee924fa6
RH		 2874 a0 = args[0], a1 = args[1], a2 = args[2];
2875 if (const_args[2]) {
ee924fa6 2876 do_addi_64:
b18d5d2b 2877 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
ee924fa6
RH		 2878 } else {
2879 tcg_out32(s, ADD | TAB(a0, a1, a2));
2880 }
810260a8 2881 break;
2882 case INDEX_op_sub_i64:
ee924fa6 2883 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2884 if (const_args[1]) {
2885 if (const_args[2]) {
2886 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2887 } else {
2888 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2889 }
2890 } else if (const_args[2]) {
ee924fa6
RH		 2891 a2 = -a2;
2892 goto do_addi_64;
2893 } else {
2894 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2895 }
810260a8 2896 break;
2897
2898 case INDEX_op_shl_i64:
541dd4ce 2899 if (const_args[2]) {
94248cfc
CF		 2900 /* Limit immediate shift count lest we create an illegal insn. */
2901 tcg_out_shli64(s, args[0], args[1], args[2] & 63);
541dd4ce
RH		 2902 } else {
2903 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2904 }
810260a8 2905 break;
2906 case INDEX_op_shr_i64:
541dd4ce 2907 if (const_args[2]) {
94248cfc
CF		 2908 /* Limit immediate shift count lest we create an illegal insn. */
2909 tcg_out_shri64(s, args[0], args[1], args[2] & 63);
541dd4ce
RH		 2910 } else {
2911 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2912 }
810260a8 2913 break;
2914 case INDEX_op_sar_i64:
fe6f943f 2915 if (const_args[2]) {
05dd01fa 2916 tcg_out_sari64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2917 } else {
2918 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
fe6f943f 2919 }
810260a8 2920 break;
313d91c7
RH		 2921 case INDEX_op_rotl_i64:
2922 if (const_args[2]) {
2923 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2924 } else {
2925 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2926 }
2927 break;
2928 case INDEX_op_rotr_i64:
2929 if (const_args[2]) {
2930 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2931 } else {
8327a470
RH		 2932 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2933 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
313d91c7
RH		 2934 }
2935 break;
810260a8 2936
2937 case INDEX_op_mul_i64:
ef809300
RH		 2938 a0 = args[0], a1 = args[1], a2 = args[2];
2939 if (const_args[2]) {
2940 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2941 } else {
2942 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2943 }
810260a8 2944 break;
2945 case INDEX_op_div_i64:
541dd4ce 2946 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
810260a8 2947 break;
2948 case INDEX_op_divu_i64:
541dd4ce 2949 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
810260a8 2950 break;
4d573822
MKF		 2951 case INDEX_op_rem_i64:
2952 tcg_out32(s, MODSD | TAB(args[0], args[1], args[2]));
2953 break;
2954 case INDEX_op_remu_i64:
2955 tcg_out32(s, MODUD | TAB(args[0], args[1], args[2]));
2956 break;
810260a8 2957
1768ec06 2958 case INDEX_op_qemu_ld_i32:
7f25c469
RH		 2959 tcg_out_qemu_ld(s, args, false);
2960 break;
1768ec06 2961 case INDEX_op_qemu_ld_i64:
7f25c469 2962 tcg_out_qemu_ld(s, args, true);
810260a8 2963 break;
1768ec06 2964 case INDEX_op_qemu_st_i32:
7f25c469
RH		 2965 tcg_out_qemu_st(s, args, false);
2966 break;
1768ec06 2967 case INDEX_op_qemu_st_i64:
7f25c469 2968 tcg_out_qemu_st(s, args, true);
810260a8 2969 break;
2970
e46b9681 2971 case INDEX_op_ext8s_i32:
2972 case INDEX_op_ext8s_i64:
f4bf14f4
RH		 2973 tcg_out_ext8s(s, args[0], args[1]);
2974 break;
e46b9681 2975 case INDEX_op_ext16s_i32:
2976 case INDEX_op_ext16s_i64:
f4bf14f4
RH		 2977 tcg_out_ext16s(s, args[0], args[1]);
2978 break;
4f2331e5 2979 case INDEX_op_ext_i32_i64:
e46b9681 2980 case INDEX_op_ext32s_i64:
f4bf14f4 2981 tcg_out_ext32s(s, args[0], args[1]);
e46b9681 2982 break;
4f2331e5
AJ		 2983 case INDEX_op_extu_i32_i64:
2984 tcg_out_ext32u(s, args[0], args[1]);
2985 break;
e46b9681 2986
1cd62ae9 2987 case INDEX_op_setcond_i32:
541dd4ce
RH		 2988 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2989 const_args[2]);
1cd62ae9 2990 break;
2991 case INDEX_op_setcond_i64:
541dd4ce
RH		 2992 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2993 const_args[2]);
1cd62ae9 2994 break;
abcf61c4
RH		 2995 case INDEX_op_setcond2_i32:
2996 tcg_out_setcond2(s, args, const_args);
2997 break;
1cd62ae9 2998
5d221582
RH		 2999 case INDEX_op_bswap16_i32:
3000 case INDEX_op_bswap16_i64:
26ce7005 3001 tcg_out_bswap16(s, args[0], args[1], args[2]);
5d221582 3002 break;
5d221582 3003 case INDEX_op_bswap32_i32:
26ce7005
RH		 3004 tcg_out_bswap32(s, args[0], args[1], 0);
3005 break;
5d221582 3006 case INDEX_op_bswap32_i64:
26ce7005 3007 tcg_out_bswap32(s, args[0], args[1], args[2]);
5d221582 3008 break;
68aebd45 3009 case INDEX_op_bswap64_i64:
674ba588 3010 tcg_out_bswap64(s, args[0], args[1]);
68aebd45
RH		 3011 break;
3012
33de9ed2 3013 case INDEX_op_deposit_i32:
39dc85b9
RH		 3014 if (const_args[2]) {
3015 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
3016 tcg_out_andi32(s, args[0], args[0], ~mask);
3017 } else {
3018 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
3019 32 - args[3] - args[4], 31 - args[3]);
3020 }
33de9ed2
RH		 3021 break;
3022 case INDEX_op_deposit_i64:
39dc85b9
RH		 3023 if (const_args[2]) {
3024 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
3025 tcg_out_andi64(s, args[0], args[0], ~mask);
3026 } else {
3027 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
3028 64 - args[3] - args[4]);
3029 }
33de9ed2
RH		 3030 break;
3031
c05021c3
RH		 3032 case INDEX_op_extract_i32:
3033 tcg_out_rlw(s, RLWINM, args[0], args[1],
3034 32 - args[2], 32 - args[3], 31);
3035 break;
3036 case INDEX_op_extract_i64:
3037 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
3038 break;
3039
027ffea9
RH		 3040 case INDEX_op_movcond_i32:
3041 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
3042 args[3], args[4], const_args[2]);
3043 break;
3044 case INDEX_op_movcond_i64:
3045 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
3046 args[3], args[4], const_args[2]);
3047 break;
3048
796f1a68 3049#if TCG_TARGET_REG_BITS == 64
6c858762 3050 case INDEX_op_add2_i64:
796f1a68
RH		 3051#else
3052 case INDEX_op_add2_i32:
3053#endif
6c858762
RH		 3054 /* Note that the CA bit is defined based on the word size of the
3055 environment. So in 64-bit mode it's always carry-out of bit 63.
3056 The fallback code using deposit works just as well for 32-bit. */
3057 a0 = args[0], a1 = args[1];
84247357 3058 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
6c858762
RH		 3059 a0 = TCG_REG_R0;
3060 }
84247357
AB		 3061 if (const_args[4]) {
3062 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
6c858762 3063 } else {
84247357 3064 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
6c858762
RH		 3065 }
3066 if (const_args[5]) {
84247357 3067 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
6c858762 3068 } else {
84247357 3069 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
6c858762
RH		 3070 }
3071 if (a0 != args[0]) {
de3d636d 3072 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 3073 }
3074 break;
3075
796f1a68 3076#if TCG_TARGET_REG_BITS == 64
6c858762 3077 case INDEX_op_sub2_i64:
796f1a68
RH		 3078#else
3079 case INDEX_op_sub2_i32:
3080#endif
6c858762 3081 a0 = args[0], a1 = args[1];
b31284ce 3082 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
6c858762
RH		 3083 a0 = TCG_REG_R0;
3084 }
3085 if (const_args[2]) {
b31284ce 3086 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
6c858762 3087 } else {
b31284ce 3088 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
6c858762 3089 }
b31284ce
RH		 3090 if (const_args[3]) {
3091 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
6c858762 3092 } else {
b31284ce 3093 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
6c858762
RH		 3094 }
3095 if (a0 != args[0]) {
de3d636d 3096 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 3097 }
3098 break;
3099
abcf61c4
RH		 3100 case INDEX_op_muluh_i32:
3101 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
3102 break;
8fa391a0
RH		 3103 case INDEX_op_mulsh_i32:
3104 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
3105 break;
32f5717f
RH		 3106 case INDEX_op_muluh_i64:
3107 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
3108 break;
3109 case INDEX_op_mulsh_i64:
3110 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
6645c147
RH		 3111 break;
3112
7b4af5ee
PK		 3113 case INDEX_op_mb:
3114 tcg_out_mb(s, args[0]);
3115 break;
3116
96d0ee7f
RH		 3117 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
3118 case INDEX_op_mov_i64:
96d0ee7f 3119 case INDEX_op_call: /* Always emitted via tcg_out_call. */
b55a8d9d 3120 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
cf7d6b8e 3121 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
810260a8 3122 default:
541dd4ce 3123 tcg_abort();
810260a8 3124 }
3125}
3126
4b06c216
RH		 3127int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
3128{
6ef14d7e
RH		 3129 switch (opc) {
3130 case INDEX_op_and_vec:
3131 case INDEX_op_or_vec:
3132 case INDEX_op_xor_vec:
3133 case INDEX_op_andc_vec:
3134 case INDEX_op_not_vec:
fa8e90d6
RH		 3135 case INDEX_op_nor_vec:
3136 case INDEX_op_eqv_vec:
3137 case INDEX_op_nand_vec:
6ef14d7e 3138 return 1;
64ff1c6d
RH		 3139 case INDEX_op_orc_vec:
3140 return have_isa_2_07;
d6750811
RH		 3141 case INDEX_op_add_vec:
3142 case INDEX_op_sub_vec:
e2382972
RH		 3143 case INDEX_op_smax_vec:
3144 case INDEX_op_smin_vec:
3145 case INDEX_op_umax_vec:
3146 case INDEX_op_umin_vec:
64ff1c6d
RH		 3147 case INDEX_op_shlv_vec:
3148 case INDEX_op_shrv_vec:
3149 case INDEX_op_sarv_vec:
ab87a66f 3150 case INDEX_op_rotlv_vec:
64ff1c6d 3151 return vece <= MO_32 || have_isa_2_07;
e9d1a53a
RH		 3152 case INDEX_op_ssadd_vec:
3153 case INDEX_op_sssub_vec:
3154 case INDEX_op_usadd_vec:
3155 case INDEX_op_ussub_vec:
e2382972 3156 return vece <= MO_32;
6ef14d7e 3157 case INDEX_op_cmp_vec:
dabae097
RH		 3158 case INDEX_op_shli_vec:
3159 case INDEX_op_shri_vec:
3160 case INDEX_op_sari_vec:
ab87a66f 3161 case INDEX_op_rotli_vec:
64ff1c6d 3162 return vece <= MO_32 || have_isa_2_07 ? -1 : 0;
d7cd6a2f
RH		 3163 case INDEX_op_neg_vec:
3164 return vece >= MO_32 && have_isa_3_00;
64ff1c6d
RH		 3165 case INDEX_op_mul_vec:
3166 switch (vece) {
3167 case MO_8:
3168 case MO_16:
3169 return -1;
3170 case MO_32:
3171 return have_isa_2_07 ? 1 : -1;
73ebe95e
LP		 3172 case MO_64:
3173 return have_isa_3_10;
64ff1c6d
RH		 3174 }
3175 return 0;
47c906ae
RH		 3176 case INDEX_op_bitsel_vec:
3177 return have_vsx;
ab87a66f
RH		 3178 case INDEX_op_rotrv_vec:
3179 return -1;
6ef14d7e
RH		 3180 default:
3181 return 0;
3182 }
4b06c216
RH		 3183}
3184
3185static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
3186 TCGReg dst, TCGReg src)
3187{
6ef14d7e 3188 tcg_debug_assert(dst >= TCG_REG_V0);
b7ce3cff
RH		 3189
3190 /* Splat from integer reg allowed via constraints for v3.00. */
3191 if (src < TCG_REG_V0) {
3192 tcg_debug_assert(have_isa_3_00);
3193 switch (vece) {
3194 case MO_64:
3195 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src));
3196 return true;
3197 case MO_32:
3198 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src));
3199 return true;
3200 default:
3201 /* Fail, so that we fall back on either dupm or mov+dup. */
3202 return false;
3203 }
3204 }
6ef14d7e
RH		 3205
3206 /*
3207 * Recall we use (or emulate) VSX integer loads, so the integer is
3208 * right justified within the left (zero-index) double-word.
3209 */
3210 switch (vece) {
3211 case MO_8:
3212 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16));
3213 break;
3214 case MO_16:
3215 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16));
3216 break;
3217 case MO_32:
3218 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
3219 break;
3220 case MO_64:
47c906ae
RH		 3221 if (have_vsx) {
3222 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src));
3223 break;
3224 }
6ef14d7e
RH		 3225 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8);
3226 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8);
3227 break;
3228 default:
3229 g_assert_not_reached();
3230 }
3231 return true;
4b06c216
RH		 3232}
3233
3234static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
3235 TCGReg out, TCGReg base, intptr_t offset)
3236{
6ef14d7e
RH		 3237 int elt;
3238
3239 tcg_debug_assert(out >= TCG_REG_V0);
3240 switch (vece) {
3241 case MO_8:
6e11cde1
RH		 3242 if (have_isa_3_00) {
3243 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16);
3244 } else {
3245 tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
3246 }
6ef14d7e 3247 elt = extract32(offset, 0, 4);
e03b5686 3248#if !HOST_BIG_ENDIAN
6ef14d7e
RH		 3249 elt ^= 15;
3250#endif
3251 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16));
3252 break;
3253 case MO_16:
3254 tcg_debug_assert((offset & 1) == 0);
6e11cde1
RH		 3255 if (have_isa_3_00) {
3256 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16);
3257 } else {
3258 tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
3259 }
6ef14d7e 3260 elt = extract32(offset, 1, 3);
e03b5686 3261#if !HOST_BIG_ENDIAN
6ef14d7e
RH		 3262 elt ^= 7;
3263#endif
3264 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16));
3265 break;
3266 case MO_32:
6e11cde1
RH		 3267 if (have_isa_3_00) {
3268 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset);
3269 break;
3270 }
6ef14d7e
RH		 3271 tcg_debug_assert((offset & 3) == 0);
3272 tcg_out_mem_long(s, 0, LVEWX, out, base, offset);
3273 elt = extract32(offset, 2, 2);
e03b5686 3274#if !HOST_BIG_ENDIAN
6ef14d7e
RH		 3275 elt ^= 3;
3276#endif
3277 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16));
3278 break;
3279 case MO_64:
47c906ae
RH		 3280 if (have_vsx) {
3281 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset);
3282 break;
3283 }
6ef14d7e
RH		 3284 tcg_debug_assert((offset & 7) == 0);
3285 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16);
3286 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8);
3287 elt = extract32(offset, 3, 1);
e03b5686 3288#if !HOST_BIG_ENDIAN
6ef14d7e
RH		 3289 elt = !elt;
3290#endif
3291 if (elt) {
3292 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8);
3293 } else {
3294 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8);
3295 }
3296 break;
3297 default:
3298 g_assert_not_reached();
3299 }
3300 return true;
4b06c216
RH		 3301}
3302
3303static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3304 unsigned vecl, unsigned vece,
5e8892db
MR		 3305 const TCGArg args[TCG_MAX_OP_ARGS],
3306 const int const_args[TCG_MAX_OP_ARGS])
4b06c216 3307{
6ef14d7e 3308 static const uint32_t
64ff1c6d
RH		 3309 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
3310 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
73ebe95e 3311 mul_op[4] = { 0, 0, VMULUWM, VMULLD },
d7cd6a2f 3312 neg_op[4] = { 0, 0, VNEGW, VNEGD },
64ff1c6d 3313 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
d7cd6a2f 3314 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
64ff1c6d
RH		 3315 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD },
3316 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD },
e9d1a53a
RH		 3317 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
3318 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
3319 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
3320 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
64ff1c6d
RH		 3321 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD },
3322 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD },
3323 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD },
3324 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD },
3325 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD },
3326 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD },
3327 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD },
d9897efa
RH		 3328 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
3329 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
64ff1c6d
RH		 3330 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 },
3331 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 },
d9897efa 3332 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
64ff1c6d 3333 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD };
6ef14d7e
RH		 3334
3335 TCGType type = vecl + TCG_TYPE_V64;
3336 TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
3337 uint32_t insn;
3338
3339 switch (opc) {
3340 case INDEX_op_ld_vec:
3341 tcg_out_ld(s, type, a0, a1, a2);
3342 return;
3343 case INDEX_op_st_vec:
3344 tcg_out_st(s, type, a0, a1, a2);
3345 return;
3346 case INDEX_op_dupm_vec:
3347 tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
3348 return;
3349
d6750811
RH		 3350 case INDEX_op_add_vec:
3351 insn = add_op[vece];
3352 break;
3353 case INDEX_op_sub_vec:
3354 insn = sub_op[vece];
3355 break;
d7cd6a2f
RH		 3356 case INDEX_op_neg_vec:
3357 insn = neg_op[vece];
3358 a2 = a1;
3359 a1 = 0;
3360 break;
64ff1c6d 3361 case INDEX_op_mul_vec:
73ebe95e 3362 insn = mul_op[vece];
64ff1c6d 3363 break;
e9d1a53a
RH		 3364 case INDEX_op_ssadd_vec:
3365 insn = ssadd_op[vece];
3366 break;
3367 case INDEX_op_sssub_vec:
3368 insn = sssub_op[vece];
3369 break;
3370 case INDEX_op_usadd_vec:
3371 insn = usadd_op[vece];
3372 break;
3373 case INDEX_op_ussub_vec:
3374 insn = ussub_op[vece];
3375 break;
e2382972
RH		 3376 case INDEX_op_smin_vec:
3377 insn = smin_op[vece];
3378 break;
3379 case INDEX_op_umin_vec:
3380 insn = umin_op[vece];
3381 break;
3382 case INDEX_op_smax_vec:
3383 insn = smax_op[vece];
3384 break;
3385 case INDEX_op_umax_vec:
3386 insn = umax_op[vece];
3387 break;
dabae097
RH		 3388 case INDEX_op_shlv_vec:
3389 insn = shlv_op[vece];
3390 break;
3391 case INDEX_op_shrv_vec:
3392 insn = shrv_op[vece];
3393 break;
3394 case INDEX_op_sarv_vec:
3395 insn = sarv_op[vece];
3396 break;
6ef14d7e
RH		 3397 case INDEX_op_and_vec:
3398 insn = VAND;
3399 break;
3400 case INDEX_op_or_vec:
3401 insn = VOR;
3402 break;
3403 case INDEX_op_xor_vec:
3404 insn = VXOR;
3405 break;
3406 case INDEX_op_andc_vec:
3407 insn = VANDC;
3408 break;
3409 case INDEX_op_not_vec:
3410 insn = VNOR;
3411 a2 = a1;
3412 break;
64ff1c6d
RH		 3413 case INDEX_op_orc_vec:
3414 insn = VORC;
3415 break;
fa8e90d6
RH		 3416 case INDEX_op_nand_vec:
3417 insn = VNAND;
3418 break;
3419 case INDEX_op_nor_vec:
3420 insn = VNOR;
3421 break;
3422 case INDEX_op_eqv_vec:
3423 insn = VEQV;
3424 break;
6ef14d7e
RH		 3425
3426 case INDEX_op_cmp_vec:
3427 switch (args[3]) {
3428 case TCG_COND_EQ:
3429 insn = eq_op[vece];
3430 break;
d7cd6a2f
RH		 3431 case TCG_COND_NE:
3432 insn = ne_op[vece];
3433 break;
6ef14d7e
RH		 3434 case TCG_COND_GT:
3435 insn = gts_op[vece];
3436 break;
3437 case TCG_COND_GTU:
3438 insn = gtu_op[vece];
3439 break;
3440 default:
3441 g_assert_not_reached();
3442 }
3443 break;
3444
47c906ae
RH		 3445 case INDEX_op_bitsel_vec:
3446 tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3]));
3447 return;
3448
597cf978
RH		 3449 case INDEX_op_dup2_vec:
3450 assert(TCG_TARGET_REG_BITS == 32);
3451 /* With inputs a1 = xLxx, a2 = xHxx */
3452 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */
3453 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */
3454 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */
3455 return;
3456
d9897efa
RH		 3457 case INDEX_op_ppc_mrgh_vec:
3458 insn = mrgh_op[vece];
3459 break;
3460 case INDEX_op_ppc_mrgl_vec:
3461 insn = mrgl_op[vece];
3462 break;
3463 case INDEX_op_ppc_muleu_vec:
3464 insn = muleu_op[vece];
3465 break;
3466 case INDEX_op_ppc_mulou_vec:
3467 insn = mulou_op[vece];
3468 break;
3469 case INDEX_op_ppc_pkum_vec:
3470 insn = pkum_op[vece];
3471 break;
ab87a66f 3472 case INDEX_op_rotlv_vec:
d9897efa
RH		 3473 insn = rotl_op[vece];
3474 break;
3475 case INDEX_op_ppc_msum_vec:
3476 tcg_debug_assert(vece == MO_16);
3477 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
3478 return;
3479
6ef14d7e 3480 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
6ef14d7e
RH		 3481 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
3482 default:
3483 g_assert_not_reached();
3484 }
3485
3486 tcg_debug_assert(insn != 0);
3487 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
3488}
3489
dabae097
RH		 3490static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
3491 TCGv_vec v1, TCGArg imm, TCGOpcode opci)
3492{
44aa59a0
RH		 3493 TCGv_vec t1;
3494
3495 if (vece == MO_32) {
3496 /*
3497 * Only 5 bits are significant, and VSPLTISB can represent -16..15.
3498 * So using negative numbers gets us the 4th bit easily.
3499 */
3500 imm = sextract32(imm, 0, 5);
3501 } else {
3502 imm &= (8 << vece) - 1;
3503 }
dabae097 3504
44aa59a0
RH		 3505 /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */
3506 t1 = tcg_constant_vec(type, MO_8, imm);
dabae097
RH		 3507 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
3508 tcgv_vec_arg(v1), tcgv_vec_arg(t1));
dabae097
RH		 3509}
3510
6ef14d7e
RH		 3511static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
3512 TCGv_vec v1, TCGv_vec v2, TCGCond cond)
3513{
3514 bool need_swap = false, need_inv = false;
3515
64ff1c6d 3516 tcg_debug_assert(vece <= MO_32 || have_isa_2_07);
6ef14d7e
RH		 3517
3518 switch (cond) {
3519 case TCG_COND_EQ:
3520 case TCG_COND_GT:
3521 case TCG_COND_GTU:
3522 break;
3523 case TCG_COND_NE:
d7cd6a2f
RH		 3524 if (have_isa_3_00 && vece <= MO_32) {
3525 break;
3526 }
3527 /* fall through */
6ef14d7e
RH		 3528 case TCG_COND_LE:
3529 case TCG_COND_LEU:
3530 need_inv = true;
3531 break;
3532 case TCG_COND_LT:
3533 case TCG_COND_LTU:
3534 need_swap = true;
3535 break;
3536 case TCG_COND_GE:
3537 case TCG_COND_GEU:
3538 need_swap = need_inv = true;
3539 break;
3540 default:
3541 g_assert_not_reached();
3542 }
3543
3544 if (need_inv) {
3545 cond = tcg_invert_cond(cond);
3546 }
3547 if (need_swap) {
3548 TCGv_vec t1;
3549 t1 = v1, v1 = v2, v2 = t1;
3550 cond = tcg_swap_cond(cond);
3551 }
3552
3553 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
3554 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
3555
3556 if (need_inv) {
3557 tcg_gen_not_vec(vece, v0, v0);
3558 }
4b06c216
RH		 3559}
3560
d9897efa
RH		 3561static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
3562 TCGv_vec v1, TCGv_vec v2)
3563{
3564 TCGv_vec t1 = tcg_temp_new_vec(type);
3565 TCGv_vec t2 = tcg_temp_new_vec(type);
44aa59a0 3566 TCGv_vec c0, c16;
d9897efa
RH		 3567
3568 switch (vece) {
3569 case MO_8:
3570 case MO_16:
3571 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
3572 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3573 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
3574 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
3575 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0),
3576 tcgv_vec_arg(t1), tcgv_vec_arg(t2));
3577 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1),
3578 tcgv_vec_arg(t1), tcgv_vec_arg(t2));
3579 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0),
3580 tcgv_vec_arg(v0), tcgv_vec_arg(t1));
3581 break;
3582
3583 case MO_32:
64ff1c6d 3584 tcg_debug_assert(!have_isa_2_07);
44aa59a0
RH		 3585 /*
3586 * Only 5 bits are significant, and VSPLTISB can represent -16..15.
3587 * So using -16 is a quick way to represent 16.
3588 */
3589 c16 = tcg_constant_vec(type, MO_8, -16);
3590 c0 = tcg_constant_vec(type, MO_8, 0);
3591
ab87a66f 3592 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1),
44aa59a0 3593 tcgv_vec_arg(v2), tcgv_vec_arg(c16));
d9897efa
RH		 3594 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
3595 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
44aa59a0
RH		 3596 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1),
3597 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0));
3598 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1),
3599 tcgv_vec_arg(t1), tcgv_vec_arg(c16));
3600 tcg_gen_add_vec(MO_32, v0, t1, t2);
d9897efa
RH		 3601 break;
3602
3603 default:
3604 g_assert_not_reached();
3605 }
3606 tcg_temp_free_vec(t1);
3607 tcg_temp_free_vec(t2);
3608}
3609
4b06c216
RH		 3610void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
3611 TCGArg a0, ...)
3612{
6ef14d7e 3613 va_list va;
ab87a66f 3614 TCGv_vec v0, v1, v2, t0;
dabae097 3615 TCGArg a2;
6ef14d7e
RH		 3616
3617 va_start(va, a0);
3618 v0 = temp_tcgv_vec(arg_temp(a0));
3619 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
dabae097 3620 a2 = va_arg(va, TCGArg);
6ef14d7e
RH		 3621
3622 switch (opc) {
dabae097
RH		 3623 case INDEX_op_shli_vec:
3624 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
3625 break;
3626 case INDEX_op_shri_vec:
3627 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec);
3628 break;
3629 case INDEX_op_sari_vec:
3630 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
3631 break;
ab87a66f
RH		 3632 case INDEX_op_rotli_vec:
3633 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec);
3634 break;
6ef14d7e 3635 case INDEX_op_cmp_vec:
dabae097 3636 v2 = temp_tcgv_vec(arg_temp(a2));
6ef14d7e
RH		 3637 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
3638 break;
d9897efa
RH		 3639 case INDEX_op_mul_vec:
3640 v2 = temp_tcgv_vec(arg_temp(a2));
3641 expand_vec_mul(type, vece, v0, v1, v2);
3642 break;
ab87a66f
RH		 3643 case INDEX_op_rotlv_vec:
3644 v2 = temp_tcgv_vec(arg_temp(a2));
3645 t0 = tcg_temp_new_vec(type);
3646 tcg_gen_neg_vec(vece, t0, v2);
3647 tcg_gen_rotlv_vec(vece, v0, v1, t0);
3648 tcg_temp_free_vec(t0);
3649 break;
6ef14d7e
RH		 3650 default:
3651 g_assert_not_reached();
3652 }
3653 va_end(va);
4b06c216
RH		 3654}
3655
6893016b
RH		 3656static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
3657{
6cb3658a
RH		 3658 switch (op) {
3659 case INDEX_op_goto_ptr:
6893016b 3660 return C_O0_I1(r);
796f1a68 3661
6cb3658a
RH		 3662 case INDEX_op_ld8u_i32:
3663 case INDEX_op_ld8s_i32:
3664 case INDEX_op_ld16u_i32:
3665 case INDEX_op_ld16s_i32:
3666 case INDEX_op_ld_i32:
6cb3658a
RH		 3667 case INDEX_op_ctpop_i32:
3668 case INDEX_op_neg_i32:
3669 case INDEX_op_not_i32:
3670 case INDEX_op_ext8s_i32:
3671 case INDEX_op_ext16s_i32:
3672 case INDEX_op_bswap16_i32:
3673 case INDEX_op_bswap32_i32:
3674 case INDEX_op_extract_i32:
3675 case INDEX_op_ld8u_i64:
3676 case INDEX_op_ld8s_i64:
3677 case INDEX_op_ld16u_i64:
3678 case INDEX_op_ld16s_i64:
3679 case INDEX_op_ld32u_i64:
3680 case INDEX_op_ld32s_i64:
3681 case INDEX_op_ld_i64:
6cb3658a
RH		 3682 case INDEX_op_ctpop_i64:
3683 case INDEX_op_neg_i64:
3684 case INDEX_op_not_i64:
3685 case INDEX_op_ext8s_i64:
3686 case INDEX_op_ext16s_i64:
3687 case INDEX_op_ext32s_i64:
3688 case INDEX_op_ext_i32_i64:
3689 case INDEX_op_extu_i32_i64:
3690 case INDEX_op_bswap16_i64:
3691 case INDEX_op_bswap32_i64:
3692 case INDEX_op_bswap64_i64:
3693 case INDEX_op_extract_i64:
6893016b
RH		 3694 return C_O1_I1(r, r);
3695
3696 case INDEX_op_st8_i32:
3697 case INDEX_op_st16_i32:
3698 case INDEX_op_st_i32:
3699 case INDEX_op_st8_i64:
3700 case INDEX_op_st16_i64:
3701 case INDEX_op_st32_i64:
3702 case INDEX_op_st_i64:
3703 return C_O0_I2(r, r);
abcf61c4 3704
6cb3658a
RH		 3705 case INDEX_op_add_i32:
3706 case INDEX_op_and_i32:
3707 case INDEX_op_or_i32:
3708 case INDEX_op_xor_i32:
3709 case INDEX_op_andc_i32:
3710 case INDEX_op_orc_i32:
3711 case INDEX_op_eqv_i32:
3712 case INDEX_op_shl_i32:
3713 case INDEX_op_shr_i32:
3714 case INDEX_op_sar_i32:
3715 case INDEX_op_rotl_i32:
3716 case INDEX_op_rotr_i32:
3717 case INDEX_op_setcond_i32:
3718 case INDEX_op_and_i64:
3719 case INDEX_op_andc_i64:
3720 case INDEX_op_shl_i64:
3721 case INDEX_op_shr_i64:
3722 case INDEX_op_sar_i64:
3723 case INDEX_op_rotl_i64:
3724 case INDEX_op_rotr_i64:
3725 case INDEX_op_setcond_i64:
6893016b
RH		 3726 return C_O1_I2(r, r, ri);
3727
6cb3658a
RH		 3728 case INDEX_op_mul_i32:
3729 case INDEX_op_mul_i64:
6893016b
RH		 3730 return C_O1_I2(r, r, rI);
3731
6cb3658a
RH		 3732 case INDEX_op_div_i32:
3733 case INDEX_op_divu_i32:
4d573822
MKF		 3734 case INDEX_op_rem_i32:
3735 case INDEX_op_remu_i32:
6cb3658a
RH		 3736 case INDEX_op_nand_i32:
3737 case INDEX_op_nor_i32:
3738 case INDEX_op_muluh_i32:
3739 case INDEX_op_mulsh_i32:
3740 case INDEX_op_orc_i64:
3741 case INDEX_op_eqv_i64:
3742 case INDEX_op_nand_i64:
3743 case INDEX_op_nor_i64:
3744 case INDEX_op_div_i64:
3745 case INDEX_op_divu_i64:
4d573822
MKF		 3746 case INDEX_op_rem_i64:
3747 case INDEX_op_remu_i64:
6cb3658a
RH		 3748 case INDEX_op_mulsh_i64:
3749 case INDEX_op_muluh_i64:
6893016b
RH		 3750 return C_O1_I2(r, r, r);
3751
6cb3658a 3752 case INDEX_op_sub_i32:
6893016b 3753 return C_O1_I2(r, rI, ri);
6cb3658a 3754 case INDEX_op_add_i64:
6893016b 3755 return C_O1_I2(r, r, rT);
6cb3658a
RH		 3756 case INDEX_op_or_i64:
3757 case INDEX_op_xor_i64:
6893016b 3758 return C_O1_I2(r, r, rU);
6cb3658a 3759 case INDEX_op_sub_i64:
6893016b 3760 return C_O1_I2(r, rI, rT);
6cb3658a
RH		 3761 case INDEX_op_clz_i32:
3762 case INDEX_op_ctz_i32:
3763 case INDEX_op_clz_i64:
3764 case INDEX_op_ctz_i64:
6893016b 3765 return C_O1_I2(r, r, rZW);
796f1a68 3766
6cb3658a
RH		 3767 case INDEX_op_brcond_i32:
3768 case INDEX_op_brcond_i64:
6893016b 3769 return C_O0_I2(r, ri);
6c858762 3770
6cb3658a
RH		 3771 case INDEX_op_movcond_i32:
3772 case INDEX_op_movcond_i64:
6893016b 3773 return C_O1_I4(r, r, ri, rZ, rZ);
6cb3658a
RH		 3774 case INDEX_op_deposit_i32:
3775 case INDEX_op_deposit_i64:
6893016b 3776 return C_O1_I2(r, 0, rZ);
6cb3658a 3777 case INDEX_op_brcond2_i32:
6893016b 3778 return C_O0_I4(r, r, ri, ri);
6cb3658a 3779 case INDEX_op_setcond2_i32:
6893016b 3780 return C_O1_I4(r, r, r, ri, ri);
6cb3658a
RH		 3781 case INDEX_op_add2_i64:
3782 case INDEX_op_add2_i32:
6893016b 3783 return C_O2_I4(r, r, r, r, rI, rZM);
6cb3658a
RH		 3784 case INDEX_op_sub2_i64:
3785 case INDEX_op_sub2_i32:
6893016b 3786 return C_O2_I4(r, r, rI, rZM, r, r);
810260a8 3787
6cb3658a
RH		 3788 case INDEX_op_qemu_ld_i32:
3789 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
6893016b
RH		 3790 ? C_O1_I1(r, L)
3791 : C_O1_I2(r, L, L));
3792
6cb3658a
RH		 3793 case INDEX_op_qemu_st_i32:
3794 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
6893016b
RH		 3795 ? C_O0_I2(S, S)
3796 : C_O0_I3(S, S, S));
3797
6cb3658a 3798 case INDEX_op_qemu_ld_i64:
6893016b
RH		 3799 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
3800 : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
3801 : C_O2_I2(L, L, L, L));
3802
6cb3658a 3803 case INDEX_op_qemu_st_i64:
6893016b
RH		 3804 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
3805 : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
3806 : C_O0_I4(S, S, S, S));
f69d277e 3807
d6750811
RH		 3808 case INDEX_op_add_vec:
3809 case INDEX_op_sub_vec:
d9897efa 3810 case INDEX_op_mul_vec:
6ef14d7e
RH		 3811 case INDEX_op_and_vec:
3812 case INDEX_op_or_vec:
3813 case INDEX_op_xor_vec:
3814 case INDEX_op_andc_vec:
3815 case INDEX_op_orc_vec:
fa8e90d6
RH		 3816 case INDEX_op_nor_vec:
3817 case INDEX_op_eqv_vec:
3818 case INDEX_op_nand_vec:
6ef14d7e 3819 case INDEX_op_cmp_vec:
e9d1a53a
RH		 3820 case INDEX_op_ssadd_vec:
3821 case INDEX_op_sssub_vec:
3822 case INDEX_op_usadd_vec:
3823 case INDEX_op_ussub_vec:
e2382972
RH		 3824 case INDEX_op_smax_vec:
3825 case INDEX_op_smin_vec:
3826 case INDEX_op_umax_vec:
3827 case INDEX_op_umin_vec:
dabae097
RH		 3828 case INDEX_op_shlv_vec:
3829 case INDEX_op_shrv_vec:
3830 case INDEX_op_sarv_vec:
ab87a66f
RH		 3831 case INDEX_op_rotlv_vec:
3832 case INDEX_op_rotrv_vec:
d9897efa
RH		 3833 case INDEX_op_ppc_mrgh_vec:
3834 case INDEX_op_ppc_mrgl_vec:
3835 case INDEX_op_ppc_muleu_vec:
3836 case INDEX_op_ppc_mulou_vec:
3837 case INDEX_op_ppc_pkum_vec:
597cf978 3838 case INDEX_op_dup2_vec:
6893016b
RH		 3839 return C_O1_I2(v, v, v);
3840
6ef14d7e 3841 case INDEX_op_not_vec:
d7cd6a2f 3842 case INDEX_op_neg_vec:
6893016b
RH		 3843 return C_O1_I1(v, v);
3844
b7ce3cff 3845 case INDEX_op_dup_vec:
6893016b
RH		 3846 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
3847
6ef14d7e 3848 case INDEX_op_ld_vec:
6ef14d7e 3849 case INDEX_op_dupm_vec:
6893016b
RH		 3850 return C_O1_I1(v, r);
3851
3852 case INDEX_op_st_vec:
3853 return C_O0_I2(v, r);
3854
47c906ae 3855 case INDEX_op_bitsel_vec:
d9897efa 3856 case INDEX_op_ppc_msum_vec:
6893016b 3857 return C_O1_I3(v, v, v, v);
6ef14d7e 3858
6cb3658a 3859 default:
6893016b 3860 g_assert_not_reached();
f69d277e 3861 }
f69d277e
RH		 3862}
3863
541dd4ce 3864static void tcg_target_init(TCGContext *s)
810260a8 3865{
cd629de1 3866 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
d0b07481
RH		 3867 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
3868
7d9dae0a 3869 have_isa = tcg_isa_base;
1e6e9aca 3870 if (hwcap & PPC_FEATURE_ARCH_2_06) {
7d9dae0a 3871 have_isa = tcg_isa_2_06;
1e6e9aca 3872 }
64ff1c6d
RH		 3873#ifdef PPC_FEATURE2_ARCH_2_07
3874 if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
3875 have_isa = tcg_isa_2_07;
3876 }
3877#endif
d0b07481
RH		 3878#ifdef PPC_FEATURE2_ARCH_3_00
3879 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
7d9dae0a 3880 have_isa = tcg_isa_3_00;
d0b07481
RH		 3881 }
3882#endif
73ebe95e
LP		 3883#ifdef PPC_FEATURE2_ARCH_3_10
3884 if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
3885 have_isa = tcg_isa_3_10;
3886 }
3887#endif
1e6e9aca 3888
63922f46
RH		 3889#ifdef PPC_FEATURE2_HAS_ISEL
3890 /* Prefer explicit instruction from the kernel. */
3891 have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0;
3892#else
3893 /* Fall back to knowing Power7 (2.06) has ISEL. */
3894 have_isel = have_isa_2_06;
3895#endif
3896
68f340d4
RH		 3897 if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
3898 have_altivec = true;
47c906ae
RH		 3899 /* We only care about the portion of VSX that overlaps Altivec. */
3900 if (hwcap & PPC_FEATURE_HAS_VSX) {
3901 have_vsx = true;
3902 }
68f340d4
RH		 3903 }
3904
f46934df
RH		 3905 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
3906 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
4b06c216
RH		 3907 if (have_altivec) {
3908 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3909 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
3910 }
f46934df
RH		 3911
3912 tcg_target_call_clobber_regs = 0;
3913 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
3914 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
3915 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
3916 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
3917 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
3918 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
3919 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
3920 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
3921 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
3922 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
3923 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
3924 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
810260a8 3925
42281ec6
RH		 3926 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
3927 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
3928 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
3929 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
3930 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
3931 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
3932 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
3933 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
3934 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
3935 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
3936 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
3937 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
3938 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
3939 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
3940 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
3941 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
3942 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
3943 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
3944 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
3945 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
3946
ccb1bb66 3947 s->reserved_regs = 0;
5e1702b0
RH		 3948 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
3949 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
dfca1778
RH		 3950#if defined(_CALL_SYSV)
3951 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
5d7ff5bb 3952#endif
dfca1778 3953#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
5e1702b0 3954 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
dfca1778
RH		 3955#endif
3956 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
42281ec6
RH		 3957 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
3958 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2);
5964fca8
RH		 3959 if (USE_REG_TB) {
3960 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
a84ac4cb 3961 }
810260a8 3962}
fa94c3be 3963
ffcfbece 3964#ifdef __ELF__
fa94c3be
RH		 3965typedef struct {
3966 DebugFrameCIE cie;
3967 DebugFrameFDEHeader fde;
3968 uint8_t fde_def_cfa[4];
3969 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
3970} DebugFrame;
3971
3972/* We're expecting a 2 byte uleb128 encoded value. */
3973QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
3974
ffcfbece
RH		 3975#if TCG_TARGET_REG_BITS == 64
3976# define ELF_HOST_MACHINE EM_PPC64
3977#else
3978# define ELF_HOST_MACHINE EM_PPC
3979#endif
fa94c3be
RH		 3980
3981static DebugFrame debug_frame = {
3982 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
3983 .cie.id = -1,
3984 .cie.version = 1,
3985 .cie.code_align = 1,
802ca56e 3986 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
fa94c3be
RH		 3987 .cie.return_column = 65,
3988
3989 /* Total FDE size does not include the "len" member. */
3990 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
3991
3992 .fde_def_cfa = {
802ca56e 3993 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
fa94c3be
RH		 3994 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
3995 (FRAME_SIZE >> 7)
3996 },
3997 .fde_reg_ofs = {
802ca56e
RH		 3998 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
3999 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
fa94c3be
RH		 4000 }
4001};
4002
755bf9e5 4003void tcg_register_jit(const void *buf, size_t buf_size)
fa94c3be
RH		 4004{
4005 uint8_t *p = &debug_frame.fde_reg_ofs[3];
4006 int i;
4007
4008 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
4009 p[0] = 0x80 + tcg_target_callee_save_regs[i];
802ca56e 4010 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
fa94c3be
RH		 4011 }
4012
802ca56e 4013 debug_frame.fde.func_start = (uintptr_t)buf;
fa94c3be
RH		 4014 debug_frame.fde.func_len = buf_size;
4015
4016 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
4017}
ffcfbece 4018#endif /* __ELF__ */
80eca687
LMC		 4019#undef VMULEUB
4020#undef VMULEUH
4021#undef VMULEUW
4022#undef VMULOUB
4023#undef VMULOUH
4024#undef VMULOUW
89a5a1ae 4025#undef VMSUMUHM
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