]> git.proxmox.com Git - mirror_qemu.git/blame - tcg/ppc/tcg-target.inc.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h
[mirror_qemu.git] / tcg / ppc / tcg-target.inc.c
CommitLineData
810260a8 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
9ecefc84
RH		 25#include "tcg-be-ldst.h"
26
ffcfbece
RH		 27#if defined _CALL_DARWIN || defined __APPLE__
28#define TCG_TARGET_CALL_DARWIN
29#endif
7f25c469
RH		 30#ifdef _CALL_SYSV
31# define TCG_TARGET_CALL_ALIGN_ARGS 1
32#endif
ffcfbece 33
dfca1778
RH		 34/* For some memory operations, we need a scratch that isn't R0. For the AIX
35 calling convention, we can re-use the TOC register since we'll be reloading
36 it at every call. Otherwise R12 will do nicely as neither a call-saved
37 register nor a parameter register. */
38#ifdef _CALL_AIX
39# define TCG_REG_TMP1 TCG_REG_R2
40#else
41# define TCG_REG_TMP1 TCG_REG_R12
42#endif
43
a84ac4cb
RH		 44/* For the 64-bit target, we don't like the 5 insn sequence needed to build
45 full 64-bit addresses. Better to have a base register to which we can
46 apply a 32-bit displacement.
47
48 There are generally three items of interest:
49 (1) helper functions in the main executable,
50 (2) TranslationBlock data structures,
51 (3) the return address in the epilogue.
52
53 For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer
54 will be inside the main executable, and thus near enough to make a
55 pointer to the epilogue be within 2GB of all helper functions.
56
57 For softmmu, we'll let the kernel choose the address of code_gen_buffer,
58 and odds are it'll be somewhere close to the main malloc arena, and so
59 a pointer to the epilogue will be within 2GB of the TranslationBlocks.
60
61 For --enable-pie, everything will be kinda near everything else,
62 somewhere in high memory.
63
64 Thus we choose to keep the return address in a call-saved register. */
65#define TCG_REG_RA TCG_REG_R31
66#define USE_REG_RA (TCG_TARGET_REG_BITS == 64)
67
de3d636d
RH		 68/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
69#define SZP ((int)sizeof(void *))
70
4c3831a0
RH		 71/* Shorthand for size of a register. */
72#define SZR (TCG_TARGET_REG_BITS / 8)
73
3d582c61
RH		 74#define TCG_CT_CONST_S16 0x100
75#define TCG_CT_CONST_U16 0x200
76#define TCG_CT_CONST_S32 0x400
77#define TCG_CT_CONST_U32 0x800
78#define TCG_CT_CONST_ZERO 0x1000
6c858762 79#define TCG_CT_CONST_MONE 0x2000
d0b07481 80#define TCG_CT_CONST_WSZ 0x4000
fe6f943f 81
e083c4a2 82static tcg_insn_unit *tb_ret_addr;
810260a8 83
cd629de1 84#include "elf.h"
d0b07481 85
33e75fb9 86bool have_isa_2_06;
d0b07481
RH		 87bool have_isa_3_00;
88
1e6e9aca
RH		 89#define HAVE_ISA_2_06 have_isa_2_06
90#define HAVE_ISEL have_isa_2_06
49d9870a 91
4cbea598 92#ifndef CONFIG_SOFTMMU
f6548c0a 93#define TCG_GUEST_BASE_REG 30
f6548c0a 94#endif
95
8d8fdbae 96#ifdef CONFIG_DEBUG_TCG
810260a8 97static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
98 "r0",
99 "r1",
98926b0a 100 "r2",
810260a8 101 "r3",
102 "r4",
103 "r5",
104 "r6",
105 "r7",
106 "r8",
107 "r9",
108 "r10",
109 "r11",
110 "r12",
111 "r13",
112 "r14",
113 "r15",
114 "r16",
115 "r17",
116 "r18",
117 "r19",
118 "r20",
119 "r21",
120 "r22",
121 "r23",
122 "r24",
123 "r25",
124 "r26",
125 "r27",
126 "r28",
127 "r29",
128 "r30",
129 "r31"
130};
d4a9eb1f 131#endif
810260a8 132
133static const int tcg_target_reg_alloc_order[] = {
5e1702b0 134 TCG_REG_R14, /* call saved registers */
810260a8 135 TCG_REG_R15,
136 TCG_REG_R16,
137 TCG_REG_R17,
138 TCG_REG_R18,
139 TCG_REG_R19,
140 TCG_REG_R20,
141 TCG_REG_R21,
142 TCG_REG_R22,
143 TCG_REG_R23,
5e1702b0
RH		 144 TCG_REG_R24,
145 TCG_REG_R25,
146 TCG_REG_R26,
147 TCG_REG_R27,
810260a8 148 TCG_REG_R28,
149 TCG_REG_R29,
150 TCG_REG_R30,
151 TCG_REG_R31,
5e1702b0
RH		 152 TCG_REG_R12, /* call clobbered, non-arguments */
153 TCG_REG_R11,
dfca1778
RH		 154 TCG_REG_R2,
155 TCG_REG_R13,
5e1702b0 156 TCG_REG_R10, /* call clobbered, arguments */
810260a8 157 TCG_REG_R9,
5e1702b0
RH		 158 TCG_REG_R8,
159 TCG_REG_R7,
160 TCG_REG_R6,
161 TCG_REG_R5,
162 TCG_REG_R4,
163 TCG_REG_R3,
810260a8 164};
165
166static const int tcg_target_call_iarg_regs[] = {
167 TCG_REG_R3,
168 TCG_REG_R4,
169 TCG_REG_R5,
170 TCG_REG_R6,
171 TCG_REG_R7,
172 TCG_REG_R8,
173 TCG_REG_R9,
174 TCG_REG_R10
175};
176
be9c4183 177static const int tcg_target_call_oarg_regs[] = {
dfca1778
RH		 178 TCG_REG_R3,
179 TCG_REG_R4
810260a8 180};
181
182static const int tcg_target_callee_save_regs[] = {
dfca1778 183#ifdef TCG_TARGET_CALL_DARWIN
5d7ff5bb
AF		 184 TCG_REG_R11,
185#endif
810260a8 186 TCG_REG_R14,
187 TCG_REG_R15,
188 TCG_REG_R16,
189 TCG_REG_R17,
190 TCG_REG_R18,
191 TCG_REG_R19,
192 TCG_REG_R20,
193 TCG_REG_R21,
194 TCG_REG_R22,
195 TCG_REG_R23,
095271d4 196 TCG_REG_R24,
197 TCG_REG_R25,
198 TCG_REG_R26,
cea5f9a2 199 TCG_REG_R27, /* currently used for the global env */
810260a8 200 TCG_REG_R28,
201 TCG_REG_R29,
202 TCG_REG_R30,
203 TCG_REG_R31
204};
205
b0940da0
RH		 206static inline bool in_range_b(tcg_target_long target)
207{
208 return target == sextract64(target, 0, 26);
209}
210
e083c4a2 211static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 212{
e083c4a2 213 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 214 tcg_debug_assert(in_range_b(disp));
810260a8 215 return disp & 0x3fffffc;
216}
217
e083c4a2 218static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 219{
e083c4a2 220 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
810260a8 221}
222
e083c4a2 223static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 224{
e083c4a2 225 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 226 tcg_debug_assert(disp == (int16_t) disp);
810260a8 227 return disp & 0xfffc;
228}
229
e083c4a2 230static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 231{
e083c4a2 232 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
810260a8 233}
234
c7ca6a2b
RH		 235static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
236{
e083c4a2 237 unsigned retrans = *s->code_ptr & 0x3fffffc;
c7ca6a2b
RH		 238 tcg_out32(s, insn | retrans);
239}
240
241static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
242{
e083c4a2 243 unsigned retrans = *s->code_ptr & 0xfffc;
c7ca6a2b
RH		 244 tcg_out32(s, insn | retrans);
245}
246
e083c4a2 247static void patch_reloc(tcg_insn_unit *code_ptr, int type,
541dd4ce 248 intptr_t value, intptr_t addend)
810260a8 249{
e083c4a2
RH		 250 tcg_insn_unit *target = (tcg_insn_unit *)value;
251
eabb7b91 252 tcg_debug_assert(addend == 0);
810260a8 253 switch (type) {
254 case R_PPC_REL14:
e083c4a2 255 reloc_pc14(code_ptr, target);
810260a8 256 break;
257 case R_PPC_REL24:
e083c4a2 258 reloc_pc24(code_ptr, target);
810260a8 259 break;
260 default:
541dd4ce 261 tcg_abort();
810260a8 262 }
263}
264
810260a8 265/* parse target specific constraints */
069ea736
RH		 266static const char *target_parse_constraint(TCGArgConstraint *ct,
267 const char *ct_str, TCGType type)
810260a8 268{
069ea736 269 switch (*ct_str++) {
810260a8 270 case 'A': case 'B': case 'C': case 'D':
271 ct->ct |= TCG_CT_REG;
541dd4ce 272 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
810260a8 273 break;
274 case 'r':
275 ct->ct |= TCG_CT_REG;
541dd4ce 276 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
810260a8 277 break;
278 case 'L': /* qemu_ld constraint */
279 ct->ct |= TCG_CT_REG;
541dd4ce
RH		 280 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
281 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 282#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 283 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
284 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
735ee40d 285#endif
810260a8 286 break;
c070355d 287 case 'S': /* qemu_st constraint */
810260a8 288 ct->ct |= TCG_CT_REG;
541dd4ce
RH		 289 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
290 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 291#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 292 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
293 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
294 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
735ee40d 295#endif
810260a8 296 break;
3d582c61
RH		 297 case 'I':
298 ct->ct |= TCG_CT_CONST_S16;
299 break;
300 case 'J':
301 ct->ct |= TCG_CT_CONST_U16;
302 break;
6c858762
RH		 303 case 'M':
304 ct->ct |= TCG_CT_CONST_MONE;
305 break;
3d582c61
RH		 306 case 'T':
307 ct->ct |= TCG_CT_CONST_S32;
308 break;
309 case 'U':
fe6f943f 310 ct->ct |= TCG_CT_CONST_U32;
311 break;
d0b07481
RH		 312 case 'W':
313 ct->ct |= TCG_CT_CONST_WSZ;
314 break;
3d582c61
RH		 315 case 'Z':
316 ct->ct |= TCG_CT_CONST_ZERO;
317 break;
810260a8 318 default:
069ea736 319 return NULL;
810260a8 320 }
069ea736 321 return ct_str;
810260a8 322}
323
324/* test if a constant matches the constraint */
f6c6afc1 325static int tcg_target_const_match(tcg_target_long val, TCGType type,
541dd4ce 326 const TCGArgConstraint *arg_ct)
810260a8 327{
3d582c61
RH		 328 int ct = arg_ct->ct;
329 if (ct & TCG_CT_CONST) {
330 return 1;
1194dcba
RH		 331 }
332
333 /* The only 32-bit constraint we use aside from
334 TCG_CT_CONST is TCG_CT_CONST_S16. */
335 if (type == TCG_TYPE_I32) {
336 val = (int32_t)val;
337 }
338
339 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
3d582c61
RH		 340 return 1;
341 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
810260a8 342 return 1;
3d582c61 343 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
fe6f943f 344 return 1;
3d582c61
RH		 345 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
346 return 1;
347 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
348 return 1;
6c858762
RH		 349 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
350 return 1;
d0b07481
RH		 351 } else if ((ct & TCG_CT_CONST_WSZ)
352 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
353 return 1;
3d582c61 354 }
810260a8 355 return 0;
356}
357
358#define OPCD(opc) ((opc)<<26)
359#define XO19(opc) (OPCD(19)|((opc)<<1))
8a94cfb0
AB		 360#define MD30(opc) (OPCD(30)|((opc)<<2))
361#define MDS30(opc) (OPCD(30)|((opc)<<1))
810260a8 362#define XO31(opc) (OPCD(31)|((opc)<<1))
363#define XO58(opc) (OPCD(58)|(opc))
364#define XO62(opc) (OPCD(62)|(opc))
365
366#define B OPCD( 18)
367#define BC OPCD( 16)
368#define LBZ OPCD( 34)
369#define LHZ OPCD( 40)
370#define LHA OPCD( 42)
371#define LWZ OPCD( 32)
372#define STB OPCD( 38)
373#define STH OPCD( 44)
374#define STW OPCD( 36)
375
376#define STD XO62( 0)
377#define STDU XO62( 1)
378#define STDX XO31(149)
379
380#define LD XO58( 0)
381#define LDX XO31( 21)
382#define LDU XO58( 1)
301f6d90 383#define LWA XO58( 2)
810260a8 384#define LWAX XO31(341)
385
1cd62ae9 386#define ADDIC OPCD( 12)
810260a8 387#define ADDI OPCD( 14)
388#define ADDIS OPCD( 15)
389#define ORI OPCD( 24)
390#define ORIS OPCD( 25)
391#define XORI OPCD( 26)
392#define XORIS OPCD( 27)
393#define ANDI OPCD( 28)
394#define ANDIS OPCD( 29)
395#define MULLI OPCD( 7)
396#define CMPLI OPCD( 10)
397#define CMPI OPCD( 11)
148bdd23 398#define SUBFIC OPCD( 8)
810260a8 399
400#define LWZU OPCD( 33)
401#define STWU OPCD( 37)
402
313d91c7 403#define RLWIMI OPCD( 20)
810260a8 404#define RLWINM OPCD( 21)
313d91c7 405#define RLWNM OPCD( 23)
810260a8 406
8a94cfb0
AB		 407#define RLDICL MD30( 0)
408#define RLDICR MD30( 1)
409#define RLDIMI MD30( 3)
410#define RLDCL MDS30( 8)
810260a8 411
412#define BCLR XO19( 16)
413#define BCCTR XO19(528)
414#define CRAND XO19(257)
415#define CRANDC XO19(129)
416#define CRNAND XO19(225)
417#define CROR XO19(449)
1cd62ae9 418#define CRNOR XO19( 33)
810260a8 419
420#define EXTSB XO31(954)
421#define EXTSH XO31(922)
422#define EXTSW XO31(986)
423#define ADD XO31(266)
424#define ADDE XO31(138)
6c858762
RH		 425#define ADDME XO31(234)
426#define ADDZE XO31(202)
810260a8 427#define ADDC XO31( 10)
428#define AND XO31( 28)
429#define SUBF XO31( 40)
430#define SUBFC XO31( 8)
431#define SUBFE XO31(136)
6c858762
RH		 432#define SUBFME XO31(232)
433#define SUBFZE XO31(200)
810260a8 434#define OR XO31(444)
435#define XOR XO31(316)
436#define MULLW XO31(235)
8fa391a0 437#define MULHW XO31( 75)
810260a8 438#define MULHWU XO31( 11)
439#define DIVW XO31(491)
440#define DIVWU XO31(459)
441#define CMP XO31( 0)
442#define CMPL XO31( 32)
443#define LHBRX XO31(790)
444#define LWBRX XO31(534)
49d9870a 445#define LDBRX XO31(532)
810260a8 446#define STHBRX XO31(918)
447#define STWBRX XO31(662)
49d9870a 448#define STDBRX XO31(660)
810260a8 449#define MFSPR XO31(339)
450#define MTSPR XO31(467)
451#define SRAWI XO31(824)
452#define NEG XO31(104)
1cd62ae9 453#define MFCR XO31( 19)
6995a4a0 454#define MFOCRF (MFCR | (1u << 20))
157f2662 455#define NOR XO31(124)
1cd62ae9 456#define CNTLZW XO31( 26)
457#define CNTLZD XO31( 58)
d0b07481
RH		 458#define CNTTZW XO31(538)
459#define CNTTZD XO31(570)
33e75fb9
RH		 460#define CNTPOPW XO31(378)
461#define CNTPOPD XO31(506)
ce1010d6
RH		 462#define ANDC XO31( 60)
463#define ORC XO31(412)
464#define EQV XO31(284)
465#define NAND XO31(476)
70fac59a 466#define ISEL XO31( 15)
810260a8 467
468#define MULLD XO31(233)
469#define MULHD XO31( 73)
470#define MULHDU XO31( 9)
471#define DIVD XO31(489)
472#define DIVDU XO31(457)
473
474#define LBZX XO31( 87)
4f4a67ae 475#define LHZX XO31(279)
810260a8 476#define LHAX XO31(343)
477#define LWZX XO31( 23)
478#define STBX XO31(215)
479#define STHX XO31(407)
480#define STWX XO31(151)
481
7b4af5ee
PK		 482#define EIEIO XO31(854)
483#define HWSYNC XO31(598)
484#define LWSYNC (HWSYNC | (1u << 21))
485
541dd4ce 486#define SPR(a, b) ((((a)<<5)|(b))<<11)
810260a8 487#define LR SPR(8, 0)
488#define CTR SPR(9, 0)
489
490#define SLW XO31( 24)
491#define SRW XO31(536)
492#define SRAW XO31(792)
493
494#define SLD XO31( 27)
495#define SRD XO31(539)
496#define SRAD XO31(794)
fe6f943f 497#define SRADI XO31(413<<1)
810260a8 498
810260a8 499#define TW XO31( 4)
541dd4ce 500#define TRAP (TW | TO(31))
810260a8 501
a84ac4cb
RH		 502#define NOP ORI /* ori 0,0,0 */
503
810260a8 504#define RT(r) ((r)<<21)
505#define RS(r) ((r)<<21)
506#define RA(r) ((r)<<16)
507#define RB(r) ((r)<<11)
508#define TO(t) ((t)<<21)
509#define SH(s) ((s)<<11)
510#define MB(b) ((b)<<6)
511#define ME(e) ((e)<<1)
512#define BO(o) ((o)<<21)
513#define MB64(b) ((b)<<5)
6995a4a0 514#define FXM(b) (1 << (19 - (b)))
810260a8 515
516#define LK 1
517
2fd8eddc
RH		 518#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
519#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
520#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
521#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
810260a8 522
523#define BF(n) ((n)<<23)
524#define BI(n, c) (((c)+((n)*4))<<16)
525#define BT(n, c) (((c)+((n)*4))<<21)
526#define BA(n, c) (((c)+((n)*4))<<16)
527#define BB(n, c) (((c)+((n)*4))<<11)
70fac59a 528#define BC_(n, c) (((c)+((n)*4))<<6)
810260a8 529
541dd4ce
RH		 530#define BO_COND_TRUE BO(12)
531#define BO_COND_FALSE BO( 4)
532#define BO_ALWAYS BO(20)
810260a8 533
534enum {
535 CR_LT,
536 CR_GT,
537 CR_EQ,
538 CR_SO
539};
540
0aed257f 541static const uint32_t tcg_to_bc[] = {
541dd4ce
RH		 542 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
543 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
544 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
545 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
546 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
547 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
548 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
549 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
550 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
551 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
810260a8 552};
553
70fac59a
RH		 554/* The low bit here is set if the RA and RB fields must be inverted. */
555static const uint32_t tcg_to_isel[] = {
556 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
557 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
558 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
559 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
560 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
561 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
562 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
563 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
564 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
565 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
566};
567
a84ac4cb
RH		 568static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
569 TCGReg base, tcg_target_long offset);
570
796f1a68 571static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
810260a8 572{
796f1a68 573 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
f8b84129
RH		 574 if (ret != arg) {
575 tcg_out32(s, OR | SAB(arg, ret, arg));
576 }
810260a8 577}
578
aceac8d6
RH		 579static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
580 int sh, int mb)
810260a8 581{
eabb7b91 582 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
541dd4ce
RH		 583 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
584 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
585 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
810260a8 586}
587
9e555b73
RH		 588static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
589 int sh, int mb, int me)
590{
591 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
592}
593
6e5e0602
RH		 594static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
595{
596 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
597}
598
a757e1ee
RH		 599static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
600{
601 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
602}
603
0a9564b9
RH		 604static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
605{
606 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
607}
608
a757e1ee
RH		 609static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
610{
611 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
612}
613
5e916c28
RH		 614static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
615{
616 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
617}
618
aceac8d6 619static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
810260a8 620{
2fd8eddc
RH		 621 if (arg == (int16_t) arg) {
622 tcg_out32(s, ADDI | TAI(ret, 0, arg));
623 } else {
624 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
625 if (arg & 0xffff) {
626 tcg_out32(s, ORI | SAI(ret, ret, arg));
627 }
810260a8 628 }
629}
630
421233a1
RH		 631static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
632 tcg_target_long arg)
810260a8 633{
796f1a68 634 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
421233a1
RH		 635 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
636 tcg_out_movi32(s, ret, arg);
637 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
638 tcg_out32(s, ADDI | TAI(ret, 0, arg));
639 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
640 } else {
a84ac4cb
RH		 641 int32_t high;
642
643 if (USE_REG_RA) {
644 intptr_t diff = arg - (intptr_t)tb_ret_addr;
645 if (diff == (int32_t)diff) {
646 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff);
647 return;
648 }
649 }
650
651 high = arg >> 31 >> 1;
421233a1
RH		 652 tcg_out_movi32(s, ret, high);
653 if (high) {
0a9564b9 654 tcg_out_shli64(s, ret, ret, 32);
421233a1
RH		 655 }
656 if (arg & 0xffff0000) {
657 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
658 }
659 if (arg & 0xffff) {
660 tcg_out32(s, ORI | SAI(ret, ret, arg));
810260a8 661 }
662 }
663}
664
637af30c 665static bool mask_operand(uint32_t c, int *mb, int *me)
a9249dff
RH		 666{
667 uint32_t lsb, test;
668
669 /* Accept a bit pattern like:
670 0....01....1
671 1....10....0
672 0..01..10..0
673 Keep track of the transitions. */
674 if (c == 0 || c == -1) {
675 return false;
676 }
677 test = c;
678 lsb = test & -test;
679 test += lsb;
680 if (test & (test - 1)) {
681 return false;
682 }
683
684 *me = clz32(lsb);
685 *mb = test ? clz32(test & -test) + 1 : 0;
686 return true;
687}
688
637af30c
RH		 689static bool mask64_operand(uint64_t c, int *mb, int *me)
690{
691 uint64_t lsb;
692
693 if (c == 0) {
694 return false;
695 }
696
697 lsb = c & -c;
698 /* Accept 1..10..0. */
699 if (c == -lsb) {
700 *mb = 0;
701 *me = clz64(lsb);
702 return true;
703 }
704 /* Accept 0..01..1. */
705 if (lsb == 1 && (c & (c + 1)) == 0) {
706 *mb = clz64(c + 1) + 1;
707 *me = 63;
708 return true;
709 }
710 return false;
711}
712
a9249dff
RH		 713static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
714{
715 int mb, me;
716
1e1df962
RH		 717 if (mask_operand(c, &mb, &me)) {
718 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
719 } else if ((c & 0xffff) == c) {
a9249dff
RH		 720 tcg_out32(s, ANDI | SAI(src, dst, c));
721 return;
722 } else if ((c & 0xffff0000) == c) {
723 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
724 return;
a9249dff 725 } else {
8327a470
RH		 726 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
727 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
a9249dff
RH		 728 }
729}
730
637af30c
RH		 731static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
732{
733 int mb, me;
734
eabb7b91 735 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1e1df962 736 if (mask64_operand(c, &mb, &me)) {
637af30c
RH		 737 if (mb == 0) {
738 tcg_out_rld(s, RLDICR, dst, src, 0, me);
739 } else {
740 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
741 }
1e1df962
RH		 742 } else if ((c & 0xffff) == c) {
743 tcg_out32(s, ANDI | SAI(src, dst, c));
744 return;
745 } else if ((c & 0xffff0000) == c) {
746 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
747 return;
637af30c 748 } else {
8327a470
RH		 749 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
750 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
637af30c
RH		 751 }
752}
753
dce74c57
RH		 754static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
755 int op_lo, int op_hi)
756{
757 if (c >> 16) {
758 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
759 src = dst;
760 }
761 if (c & 0xffff) {
762 tcg_out32(s, op_lo | SAI(src, dst, c));
763 src = dst;
764 }
765}
766
767static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
768{
769 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
770}
771
772static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
773{
774 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
775}
776
e083c4a2 777static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
5d7ff5bb 778{
e083c4a2 779 ptrdiff_t disp = tcg_pcrel_diff(s, target);
b0940da0 780 if (in_range_b(disp)) {
541dd4ce
RH		 781 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
782 } else {
de3d636d 783 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
8327a470 784 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
541dd4ce 785 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
5d7ff5bb
AF		 786 }
787}
788
b18d5d2b
RH		 789static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
790 TCGReg base, tcg_target_long offset)
810260a8 791{
b18d5d2b 792 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
de7761a3 793 bool is_store = false;
dfca1778 794 TCGReg rs = TCG_REG_TMP1;
b18d5d2b 795
b18d5d2b
RH		 796 switch (opi) {
797 case LD: case LWA:
798 align = 3;
799 /* FALLTHRU */
800 default:
801 if (rt != TCG_REG_R0) {
802 rs = rt;
de7761a3 803 break;
b18d5d2b
RH		 804 }
805 break;
806 case STD:
807 align = 3;
de7761a3 808 /* FALLTHRU */
b18d5d2b 809 case STB: case STH: case STW:
de7761a3 810 is_store = true;
b18d5d2b 811 break;
810260a8 812 }
810260a8 813
b18d5d2b
RH		 814 /* For unaligned, or very large offsets, use the indexed form. */
815 if (offset & align || offset != (int32_t)offset) {
d4cba13b
RH		 816 if (rs == base) {
817 rs = TCG_REG_R0;
818 }
819 tcg_debug_assert(!is_store || rs != rt);
de7761a3
RH		 820 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
821 tcg_out32(s, opx | TAB(rt, base, rs));
b18d5d2b
RH		 822 return;
823 }
824
825 l0 = (int16_t)offset;
826 offset = (offset - l0) >> 16;
827 l1 = (int16_t)offset;
828
829 if (l1 < 0 && orig >= 0) {
830 extra = 0x4000;
831 l1 = (int16_t)(offset - 0x4000);
832 }
833 if (l1) {
834 tcg_out32(s, ADDIS | TAI(rs, base, l1));
835 base = rs;
836 }
837 if (extra) {
838 tcg_out32(s, ADDIS | TAI(rs, base, extra));
839 base = rs;
840 }
841 if (opi != ADDI || base != rt || l0 != 0) {
842 tcg_out32(s, opi | TAI(rt, base, l0));
828808f5 843 }
844}
845
d604f1a9
RH		 846static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
847 TCGReg arg1, intptr_t arg2)
848{
849 int opi, opx;
810260a8 850
eabb7b91 851 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
d604f1a9
RH		 852 if (type == TCG_TYPE_I32) {
853 opi = LWZ, opx = LWZX;
854 } else {
855 opi = LD, opx = LDX;
856 }
857 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
858}
fedee3e7 859
d604f1a9
RH		 860static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
861 TCGReg arg1, intptr_t arg2)
810260a8 862{
d604f1a9 863 int opi, opx;
fedee3e7 864
eabb7b91 865 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
d604f1a9
RH		 866 if (type == TCG_TYPE_I32) {
867 opi = STW, opx = STWX;
fedee3e7 868 } else {
d604f1a9 869 opi = STD, opx = STDX;
fedee3e7 870 }
d604f1a9
RH		 871 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
872}
810260a8 873
59d7c14e
RH		 874static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
875 TCGReg base, intptr_t ofs)
876{
877 return false;
878}
879
d604f1a9
RH		 880static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
881 int const_arg2, int cr, TCGType type)
882{
883 int imm;
884 uint32_t op;
810260a8 885
abcf61c4
RH		 886 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
887
d604f1a9
RH		 888 /* Simplify the comparisons below wrt CMPI. */
889 if (type == TCG_TYPE_I32) {
890 arg2 = (int32_t)arg2;
4a40e231 891 }
fedee3e7 892
d604f1a9
RH		 893 switch (cond) {
894 case TCG_COND_EQ:
895 case TCG_COND_NE:
896 if (const_arg2) {
897 if ((int16_t) arg2 == arg2) {
898 op = CMPI;
899 imm = 1;
900 break;
901 } else if ((uint16_t) arg2 == arg2) {
902 op = CMPLI;
903 imm = 1;
904 break;
905 }
906 }
907 op = CMPL;
908 imm = 0;
909 break;
fedee3e7 910
d604f1a9
RH		 911 case TCG_COND_LT:
912 case TCG_COND_GE:
913 case TCG_COND_LE:
914 case TCG_COND_GT:
915 if (const_arg2) {
916 if ((int16_t) arg2 == arg2) {
917 op = CMPI;
918 imm = 1;
919 break;
920 }
921 }
922 op = CMP;
923 imm = 0;
924 break;
fedee3e7 925
d604f1a9
RH		 926 case TCG_COND_LTU:
927 case TCG_COND_GEU:
928 case TCG_COND_LEU:
929 case TCG_COND_GTU:
930 if (const_arg2) {
931 if ((uint16_t) arg2 == arg2) {
932 op = CMPLI;
933 imm = 1;
934 break;
935 }
936 }
937 op = CMPL;
938 imm = 0;
939 break;
fedee3e7 940
d604f1a9
RH		 941 default:
942 tcg_abort();
fedee3e7 943 }
d604f1a9 944 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
fedee3e7 945
d604f1a9
RH		 946 if (imm) {
947 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
948 } else {
949 if (const_arg2) {
950 tcg_out_movi(s, type, TCG_REG_R0, arg2);
951 arg2 = TCG_REG_R0;
952 }
953 tcg_out32(s, op | RA(arg1) | RB(arg2));
954 }
810260a8 955}
956
d604f1a9
RH		 957static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
958 TCGReg dst, TCGReg src)
7f12d649 959{
a757e1ee
RH		 960 if (type == TCG_TYPE_I32) {
961 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
962 tcg_out_shri32(s, dst, dst, 5);
963 } else {
964 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
965 tcg_out_shri64(s, dst, dst, 6);
966 }
7f12d649
RH		 967}
968
d604f1a9 969static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
7f12d649 970{
d604f1a9
RH		 971 /* X != 0 implies X + -1 generates a carry. Extra addition
972 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
973 if (dst != src) {
974 tcg_out32(s, ADDIC | TAI(dst, src, -1));
975 tcg_out32(s, SUBFE | TAB(dst, dst, src));
7f12d649 976 } else {
d604f1a9
RH		 977 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
978 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
7f12d649 979 }
d604f1a9 980}
7f12d649 981
d604f1a9
RH		 982static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
983 bool const_arg2)
984{
985 if (const_arg2) {
986 if ((uint32_t)arg2 == arg2) {
987 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
988 } else {
989 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
990 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
991 }
992 } else {
993 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
994 }
995 return TCG_REG_R0;
7f12d649
RH		 996}
997
d604f1a9
RH		 998static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
999 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1000 int const_arg2)
7f12d649 1001{
d604f1a9 1002 int crop, sh;
7f12d649 1003
eabb7b91 1004 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
a757e1ee 1005
d604f1a9
RH		 1006 /* Ignore high bits of a potential constant arg2. */
1007 if (type == TCG_TYPE_I32) {
1008 arg2 = (uint32_t)arg2;
1009 }
7f12d649 1010
d604f1a9
RH		 1011 /* Handle common and trivial cases before handling anything else. */
1012 if (arg2 == 0) {
1013 switch (cond) {
1014 case TCG_COND_EQ:
1015 tcg_out_setcond_eq0(s, type, arg0, arg1);
1016 return;
1017 case TCG_COND_NE:
a757e1ee 1018 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1019 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1020 arg1 = TCG_REG_R0;
1021 }
1022 tcg_out_setcond_ne0(s, arg0, arg1);
1023 return;
1024 case TCG_COND_GE:
1025 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1026 arg1 = arg0;
1027 /* FALLTHRU */
1028 case TCG_COND_LT:
1029 /* Extract the sign bit. */
a757e1ee
RH		 1030 if (type == TCG_TYPE_I32) {
1031 tcg_out_shri32(s, arg0, arg1, 31);
1032 } else {
1033 tcg_out_shri64(s, arg0, arg1, 63);
1034 }
d604f1a9
RH		 1035 return;
1036 default:
1037 break;
1038 }
1039 }
7f12d649 1040
d604f1a9
RH		 1041 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1042 All other cases below are also at least 3 insns, so speed up the
1043 code generator by not considering them and always using ISEL. */
1044 if (HAVE_ISEL) {
1045 int isel, tab;
7f12d649 1046
d604f1a9 1047 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
7f12d649 1048
d604f1a9 1049 isel = tcg_to_isel[cond];
7f12d649 1050
d604f1a9
RH		 1051 tcg_out_movi(s, type, arg0, 1);
1052 if (isel & 1) {
1053 /* arg0 = (bc ? 0 : 1) */
1054 tab = TAB(arg0, 0, arg0);
1055 isel &= ~1;
1056 } else {
1057 /* arg0 = (bc ? 1 : 0) */
1058 tcg_out_movi(s, type, TCG_REG_R0, 0);
1059 tab = TAB(arg0, arg0, TCG_REG_R0);
1060 }
1061 tcg_out32(s, isel | tab);
1062 return;
1063 }
49d9870a 1064
d604f1a9
RH		 1065 switch (cond) {
1066 case TCG_COND_EQ:
1067 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1068 tcg_out_setcond_eq0(s, type, arg0, arg1);
1069 return;
810260a8 1070
d604f1a9
RH		 1071 case TCG_COND_NE:
1072 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1073 /* Discard the high bits only once, rather than both inputs. */
a757e1ee 1074 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1075 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1076 arg1 = TCG_REG_R0;
1077 }
1078 tcg_out_setcond_ne0(s, arg0, arg1);
1079 return;
810260a8 1080
d604f1a9
RH		 1081 case TCG_COND_GT:
1082 case TCG_COND_GTU:
1083 sh = 30;
1084 crop = 0;
1085 goto crtest;
810260a8 1086
d604f1a9
RH		 1087 case TCG_COND_LT:
1088 case TCG_COND_LTU:
1089 sh = 29;
1090 crop = 0;
1091 goto crtest;
810260a8 1092
d604f1a9
RH		 1093 case TCG_COND_GE:
1094 case TCG_COND_GEU:
1095 sh = 31;
1096 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1097 goto crtest;
810260a8 1098
d604f1a9
RH		 1099 case TCG_COND_LE:
1100 case TCG_COND_LEU:
1101 sh = 31;
1102 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1103 crtest:
1104 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1105 if (crop) {
1106 tcg_out32(s, crop);
1107 }
1108 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1109 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1110 break;
1111
1112 default:
1113 tcg_abort();
1114 }
810260a8 1115}
1116
bec16311 1117static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
810260a8 1118{
d604f1a9
RH		 1119 if (l->has_value) {
1120 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
49d9870a 1121 } else {
bec16311 1122 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
d604f1a9 1123 tcg_out_bc_noaddr(s, bc);
810260a8 1124 }
810260a8 1125}
1126
d604f1a9
RH		 1127static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1128 TCGArg arg1, TCGArg arg2, int const_arg2,
bec16311 1129 TCGLabel *l, TCGType type)
810260a8 1130{
d604f1a9 1131 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
bec16311 1132 tcg_out_bc(s, tcg_to_bc[cond], l);
d604f1a9 1133}
fa94c3be 1134
d604f1a9
RH		 1135static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1136 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1137 TCGArg v2, bool const_c2)
1138{
1139 /* If for some reason both inputs are zero, don't produce bad code. */
1140 if (v1 == 0 && v2 == 0) {
1141 tcg_out_movi(s, type, dest, 0);
1142 return;
b9e946c7 1143 }
f6548c0a 1144
d604f1a9 1145 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
a69abbe0 1146
d604f1a9
RH		 1147 if (HAVE_ISEL) {
1148 int isel = tcg_to_isel[cond];
810260a8 1149
d604f1a9
RH		 1150 /* Swap the V operands if the operation indicates inversion. */
1151 if (isel & 1) {
1152 int t = v1;
1153 v1 = v2;
1154 v2 = t;
1155 isel &= ~1;
1156 }
1157 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1158 if (v2 == 0) {
1159 tcg_out_movi(s, type, TCG_REG_R0, 0);
1160 }
1161 tcg_out32(s, isel | TAB(dest, v1, v2));
1162 } else {
1163 if (dest == v2) {
1164 cond = tcg_invert_cond(cond);
1165 v2 = v1;
1166 } else if (dest != v1) {
1167 if (v1 == 0) {
1168 tcg_out_movi(s, type, dest, 0);
1169 } else {
1170 tcg_out_mov(s, type, dest, v1);
1171 }
1172 }
1173 /* Branch forward over one insn */
1174 tcg_out32(s, tcg_to_bc[cond] | 8);
1175 if (v2 == 0) {
1176 tcg_out_movi(s, type, dest, 0);
1177 } else {
1178 tcg_out_mov(s, type, dest, v2);
1179 }
29b69198 1180 }
810260a8 1181}
1182
d0b07481
RH		 1183static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
1184 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
1185{
1186 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
1187 tcg_out32(s, opc | RA(a0) | RS(a1));
1188 } else {
1189 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
1190 /* Note that the only other valid constant for a2 is 0. */
1191 if (HAVE_ISEL) {
1192 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
1193 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
1194 } else if (!const_a2 && a0 == a2) {
1195 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
1196 tcg_out32(s, opc | RA(a0) | RS(a1));
1197 } else {
1198 tcg_out32(s, opc | RA(a0) | RS(a1));
1199 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
1200 if (const_a2) {
1201 tcg_out_movi(s, type, a0, 0);
1202 } else {
1203 tcg_out_mov(s, type, a0, a2);
1204 }
1205 }
1206 }
1207}
1208
abcf61c4
RH		 1209static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1210 const int *const_args)
1211{
1212 static const struct { uint8_t bit1, bit2; } bits[] = {
1213 [TCG_COND_LT ] = { CR_LT, CR_LT },
1214 [TCG_COND_LE ] = { CR_LT, CR_GT },
1215 [TCG_COND_GT ] = { CR_GT, CR_GT },
1216 [TCG_COND_GE ] = { CR_GT, CR_LT },
1217 [TCG_COND_LTU] = { CR_LT, CR_LT },
1218 [TCG_COND_LEU] = { CR_LT, CR_GT },
1219 [TCG_COND_GTU] = { CR_GT, CR_GT },
1220 [TCG_COND_GEU] = { CR_GT, CR_LT },
1221 };
1222
1223 TCGCond cond = args[4], cond2;
1224 TCGArg al, ah, bl, bh;
1225 int blconst, bhconst;
1226 int op, bit1, bit2;
1227
1228 al = args[0];
1229 ah = args[1];
1230 bl = args[2];
1231 bh = args[3];
1232 blconst = const_args[2];
1233 bhconst = const_args[3];
1234
1235 switch (cond) {
1236 case TCG_COND_EQ:
1237 op = CRAND;
1238 goto do_equality;
1239 case TCG_COND_NE:
1240 op = CRNAND;
1241 do_equality:
1242 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1243 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1244 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1245 break;
1246
1247 case TCG_COND_LT:
1248 case TCG_COND_LE:
1249 case TCG_COND_GT:
1250 case TCG_COND_GE:
1251 case TCG_COND_LTU:
1252 case TCG_COND_LEU:
1253 case TCG_COND_GTU:
1254 case TCG_COND_GEU:
1255 bit1 = bits[cond].bit1;
1256 bit2 = bits[cond].bit2;
1257 op = (bit1 != bit2 ? CRANDC : CRAND);
1258 cond2 = tcg_unsigned_cond(cond);
1259
1260 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1261 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1262 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1263 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1264 break;
1265
1266 default:
1267 tcg_abort();
1268 }
1269}
1270
1271static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1272 const int *const_args)
1273{
1274 tcg_out_cmp2(s, args + 1, const_args + 1);
1275 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1276 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1277}
1278
1279static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1280 const int *const_args)
1281{
1282 tcg_out_cmp2(s, args, const_args);
bec16311 1283 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
abcf61c4
RH		 1284}
1285
7b4af5ee
PK		 1286static void tcg_out_mb(TCGContext *s, TCGArg a0)
1287{
1288 uint32_t insn = HWSYNC;
1289 a0 &= TCG_MO_ALL;
1290 if (a0 == TCG_MO_LD_LD) {
1291 insn = LWSYNC;
1292 } else if (a0 == TCG_MO_ST_ST) {
1293 insn = EIEIO;
1294 }
1295 tcg_out32(s, insn);
1296}
1297
399f1648 1298#ifdef __powerpc64__
a8583393
RH		 1299void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
1300 uintptr_t addr)
810260a8 1301{
5bfd75a3
RH		 1302 tcg_insn_unit i1, i2;
1303 uint64_t pair;
1304 intptr_t diff = addr - jmp_addr;
b18d5d2b 1305
5bfd75a3
RH		 1306 if (in_range_b(diff)) {
1307 i1 = B | (diff & 0x3fffffc);
1308 i2 = NOP;
1309 } else if (USE_REG_RA) {
1310 intptr_t lo, hi;
1311 diff = addr - (uintptr_t)tb_ret_addr;
1312 lo = (int16_t)diff;
1313 hi = (int32_t)(diff - lo);
eabb7b91 1314 tcg_debug_assert(diff == hi + lo);
5bfd75a3
RH		 1315 i1 = ADDIS | TAI(TCG_REG_TMP1, TCG_REG_RA, hi >> 16);
1316 i2 = ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, lo);
1317 } else {
eabb7b91 1318 tcg_debug_assert(TCG_TARGET_REG_BITS == 32 || addr == (int32_t)addr);
5bfd75a3
RH		 1319 i1 = ADDIS | TAI(TCG_REG_TMP1, 0, addr >> 16);
1320 i2 = ORI | SAI(TCG_REG_TMP1, TCG_REG_TMP1, addr);
1321 }
1322#ifdef HOST_WORDS_BIGENDIAN
1323 pair = (uint64_t)i1 << 32 | i2;
1324#else
1325 pair = (uint64_t)i2 << 32 | i1;
1326#endif
1327
399f1648 1328 atomic_set((uint64_t *)jmp_addr, pair);
5bfd75a3 1329 flush_icache_range(jmp_addr, jmp_addr + 8);
810260a8 1330}
399f1648 1331#else
a8583393
RH		 1332void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
1333 uintptr_t addr)
399f1648
SF		 1334{
1335 intptr_t diff = addr - jmp_addr;
1336 tcg_debug_assert(in_range_b(diff));
1337 atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
1338 flush_icache_range(jmp_addr, jmp_addr + 4);
1339}
1340#endif
810260a8 1341
d604f1a9 1342static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
810260a8 1343{
eaf7d1cf 1344#ifdef _CALL_AIX
d604f1a9
RH		 1345 /* Look through the descriptor. If the branch is in range, and we
1346 don't have to spend too much effort on building the toc. */
1347 void *tgt = ((void **)target)[0];
1348 uintptr_t toc = ((uintptr_t *)target)[1];
1349 intptr_t diff = tcg_pcrel_diff(s, tgt);
b18d5d2b 1350
d604f1a9 1351 if (in_range_b(diff) && toc == (uint32_t)toc) {
dfca1778 1352 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
d604f1a9 1353 tcg_out_b(s, LK, tgt);
541dd4ce 1354 } else {
d604f1a9
RH		 1355 /* Fold the low bits of the constant into the addresses below. */
1356 intptr_t arg = (intptr_t)target;
1357 int ofs = (int16_t)arg;
1358
1359 if (ofs + 8 < 0x8000) {
1360 arg -= ofs;
1361 } else {
1362 ofs = 0;
1363 }
dfca1778
RH		 1364 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1365 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
d604f1a9 1366 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
dfca1778 1367 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
d604f1a9 1368 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
541dd4ce 1369 }
77e58d0d
UW		 1370#elif defined(_CALL_ELF) && _CALL_ELF == 2
1371 intptr_t diff;
1372
1373 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1374 address, which the callee uses to compute its TOC address. */
1375 /* FIXME: when the branch is in range, we could avoid r12 load if we
1376 knew that the destination uses the same TOC, and what its local
1377 entry point offset is. */
1378 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1379
1380 diff = tcg_pcrel_diff(s, target);
1381 if (in_range_b(diff)) {
1382 tcg_out_b(s, LK, target);
1383 } else {
1384 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1385 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1386 }
eaf7d1cf
RH		 1387#else
1388 tcg_out_b(s, LK, target);
d604f1a9 1389#endif
810260a8 1390}
1391
d604f1a9
RH		 1392static const uint32_t qemu_ldx_opc[16] = {
1393 [MO_UB] = LBZX,
1394 [MO_UW] = LHZX,
1395 [MO_UL] = LWZX,
1396 [MO_Q] = LDX,
1397 [MO_SW] = LHAX,
1398 [MO_SL] = LWAX,
1399 [MO_BSWAP | MO_UB] = LBZX,
1400 [MO_BSWAP | MO_UW] = LHBRX,
1401 [MO_BSWAP | MO_UL] = LWBRX,
1402 [MO_BSWAP | MO_Q] = LDBRX,
1403};
810260a8 1404
d604f1a9
RH		 1405static const uint32_t qemu_stx_opc[16] = {
1406 [MO_UB] = STBX,
1407 [MO_UW] = STHX,
1408 [MO_UL] = STWX,
1409 [MO_Q] = STDX,
1410 [MO_BSWAP | MO_UB] = STBX,
1411 [MO_BSWAP | MO_UW] = STHBRX,
1412 [MO_BSWAP | MO_UL] = STWBRX,
1413 [MO_BSWAP | MO_Q] = STDBRX,
1414};
991041a4 1415
d604f1a9
RH		 1416static const uint32_t qemu_exts_opc[4] = {
1417 EXTSB, EXTSH, EXTSW, 0
1418};
810260a8 1419
d604f1a9
RH		 1420#if defined (CONFIG_SOFTMMU)
1421/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1422 * int mmu_idx, uintptr_t ra)
1423 */
1424static void * const qemu_ld_helpers[16] = {
1425 [MO_UB] = helper_ret_ldub_mmu,
1426 [MO_LEUW] = helper_le_lduw_mmu,
1427 [MO_LEUL] = helper_le_ldul_mmu,
1428 [MO_LEQ] = helper_le_ldq_mmu,
1429 [MO_BEUW] = helper_be_lduw_mmu,
1430 [MO_BEUL] = helper_be_ldul_mmu,
1431 [MO_BEQ] = helper_be_ldq_mmu,
1432};
810260a8 1433
d604f1a9
RH		 1434/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1435 * uintxx_t val, int mmu_idx, uintptr_t ra)
1436 */
1437static void * const qemu_st_helpers[16] = {
1438 [MO_UB] = helper_ret_stb_mmu,
1439 [MO_LEUW] = helper_le_stw_mmu,
1440 [MO_LEUL] = helper_le_stl_mmu,
1441 [MO_LEQ] = helper_le_stq_mmu,
1442 [MO_BEUW] = helper_be_stw_mmu,
1443 [MO_BEUL] = helper_be_stl_mmu,
1444 [MO_BEQ] = helper_be_stq_mmu,
1445};
810260a8 1446
d604f1a9
RH		 1447/* Perform the TLB load and compare. Places the result of the comparison
1448 in CR7, loads the addend of the TLB into R3, and returns the register
1449 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1450
68d45bb6 1451static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
7f25c469 1452 TCGReg addrlo, TCGReg addrhi,
d604f1a9
RH		 1453 int mem_index, bool is_read)
1454{
1455 int cmp_off
1456 = (is_read
1457 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1458 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1459 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1460 TCGReg base = TCG_AREG0;
85aa8081
RH		 1461 unsigned s_bits = opc & MO_SIZE;
1462 unsigned a_bits = get_alignment_bits(opc);
d604f1a9
RH		 1463
1464 /* Extract the page index, shifted into place for tlb index. */
7f25c469
RH		 1465 if (TCG_TARGET_REG_BITS == 64) {
1466 if (TARGET_LONG_BITS == 32) {
1467 /* Zero-extend the address into a place helpful for further use. */
1468 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1469 addrlo = TCG_REG_R4;
1470 } else {
1471 tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo,
1472 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
1473 }
810260a8 1474 }
810260a8 1475
d604f1a9
RH		 1476 /* Compensate for very large offsets. */
1477 if (add_off >= 0x8000) {
1478 /* Most target env are smaller than 32k; none are larger than 64k.
1479 Simplify the logic here merely to offset by 0x7ff0, giving us a
1480 range just shy of 64k. Check this assumption. */
1481 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
1482 tlb_table[NB_MMU_MODES - 1][1])
1483 > 0x7ff0 + 0x7fff);
dfca1778
RH		 1484 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0));
1485 base = TCG_REG_TMP1;
d604f1a9
RH		 1486 cmp_off -= 0x7ff0;
1487 add_off -= 0x7ff0;
1488 }
1489
1490 /* Extraction and shifting, part 2. */
7f25c469
RH		 1491 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1492 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo,
d604f1a9
RH		 1493 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
1494 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
1495 31 - CPU_TLB_ENTRY_BITS);
4c314da6 1496 } else {
d604f1a9 1497 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
810260a8 1498 }
810260a8 1499
d604f1a9 1500 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
1cd62ae9 1501
d604f1a9 1502 /* Load the tlb comparator. */
7f25c469
RH		 1503 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1504 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
dfca1778 1505 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
7f25c469 1506 } else {
dfca1778 1507 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
7f25c469 1508 }
d604f1a9
RH		 1509
1510 /* Load the TLB addend for use on the fast path. Do this asap
1511 to minimize any load use delay. */
4c3831a0 1512 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
d604f1a9 1513
68d45bb6 1514 /* Clear the non-page, non-alignment bits from the address */
85aa8081
RH		 1515 if (TCG_TARGET_REG_BITS == 32) {
1516 /* We don't support unaligned accesses on 32-bits.
1517 * Preserve the bottom bits and thus trigger a comparison
1518 * failure on unaligned accesses.
68d45bb6 1519 */
85aa8081 1520 if (a_bits < s_bits) {
1f00b27f
SS		 1521 a_bits = s_bits;
1522 }
7f25c469 1523 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
1f00b27f 1524 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
85aa8081
RH		 1525 } else {
1526 TCGReg t = addrlo;
1527
1528 /* If the access is unaligned, we need to make sure we fail if we
1529 * cross a page boundary. The trick is to add the access size-1
1530 * to the address before masking the low bits. That will make the
1531 * address overflow to the next page if we cross a page boundary,
1532 * which will then force a mismatch of the TLB compare.
1533 */
1534 if (a_bits < s_bits) {
1535 unsigned a_mask = (1 << a_bits) - 1;
1536 unsigned s_mask = (1 << s_bits) - 1;
1537 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
1538 t = TCG_REG_R0;
1539 }
1540
1541 /* Mask the address for the requested alignment. */
1542 if (TARGET_LONG_BITS == 32) {
1543 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
1544 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
1545 } else if (a_bits == 0) {
1546 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
1547 } else {
1548 tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
1f00b27f 1549 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
68d45bb6 1550 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
68d45bb6 1551 }
70fac59a 1552 }
d604f1a9 1553
7f25c469 1554 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
dfca1778
RH		 1555 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1556 0, 7, TCG_TYPE_I32);
7f25c469
RH		 1557 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1558 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1559 } else {
dfca1778
RH		 1560 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1561 0, 7, TCG_TYPE_TL);
7f25c469 1562 }
d604f1a9 1563
7f25c469 1564 return addrlo;
70fac59a 1565}
1cd62ae9 1566
d604f1a9
RH		 1567/* Record the context of a call to the out of line helper code for the slow
1568 path for a load or store, so that we can later generate the correct
1569 helper code. */
3972ef6f 1570static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
7f25c469
RH		 1571 TCGReg datalo_reg, TCGReg datahi_reg,
1572 TCGReg addrlo_reg, TCGReg addrhi_reg,
3972ef6f 1573 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
70fac59a 1574{
d604f1a9
RH		 1575 TCGLabelQemuLdst *label = new_ldst_label(s);
1576
1577 label->is_ld = is_ld;
3972ef6f 1578 label->oi = oi;
7f25c469
RH		 1579 label->datalo_reg = datalo_reg;
1580 label->datahi_reg = datahi_reg;
1581 label->addrlo_reg = addrlo_reg;
1582 label->addrhi_reg = addrhi_reg;
d604f1a9 1583 label->raddr = raddr;
7f25c469 1584 label->label_ptr[0] = lptr;
70fac59a 1585}
1cd62ae9 1586
d604f1a9 1587static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
70fac59a 1588{
3972ef6f
RH		 1589 TCGMemOpIdx oi = lb->oi;
1590 TCGMemOp opc = get_memop(oi);
7f25c469 1591 TCGReg hi, lo, arg = TCG_REG_R3;
70fac59a 1592
d604f1a9 1593 reloc_pc14(lb->label_ptr[0], s->code_ptr);
70fac59a 1594
7f25c469 1595 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1cd62ae9 1596
7f25c469
RH		 1597 lo = lb->addrlo_reg;
1598 hi = lb->addrhi_reg;
1599 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1600#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1601 arg |= 1;
1602#endif
1603 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1604 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1605 } else {
1606 /* If the address needed to be zero-extended, we'll have already
1607 placed it in R4. The only remaining case is 64-bit guest. */
1608 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1609 }
752c1fdb 1610
3972ef6f 1611 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 1612 tcg_out32(s, MFSPR | RT(arg) | LR);
70fac59a 1613
2b7ec66f 1614 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
70fac59a 1615
7f25c469
RH		 1616 lo = lb->datalo_reg;
1617 hi = lb->datahi_reg;
1618 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1619 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
1620 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
1621 } else if (opc & MO_SIGN) {
d604f1a9 1622 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
7f25c469 1623 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
d604f1a9 1624 } else {
7f25c469 1625 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
70fac59a
RH		 1626 }
1627
d604f1a9
RH		 1628 tcg_out_b(s, 0, lb->raddr);
1629}
70fac59a 1630
d604f1a9
RH		 1631static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1632{
3972ef6f
RH		 1633 TCGMemOpIdx oi = lb->oi;
1634 TCGMemOp opc = get_memop(oi);
d604f1a9 1635 TCGMemOp s_bits = opc & MO_SIZE;
7f25c469 1636 TCGReg hi, lo, arg = TCG_REG_R3;
1cd62ae9 1637
d604f1a9 1638 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1cd62ae9 1639
7f25c469
RH		 1640 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1641
1642 lo = lb->addrlo_reg;
1643 hi = lb->addrhi_reg;
1644 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1645#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1646 arg |= 1;
1647#endif
1648 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1649 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1650 } else {
1651 /* If the address needed to be zero-extended, we'll have already
1652 placed it in R4. The only remaining case is 64-bit guest. */
1653 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1654 }
1cd62ae9 1655
7f25c469
RH		 1656 lo = lb->datalo_reg;
1657 hi = lb->datahi_reg;
1658 if (TCG_TARGET_REG_BITS == 32) {
1659 switch (s_bits) {
1660 case MO_64:
1661#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1662 arg |= 1;
1663#endif
1664 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1665 /* FALLTHRU */
1666 case MO_32:
1667 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1668 break;
1669 default:
1670 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
1671 break;
1672 }
1673 } else {
1674 if (s_bits == MO_64) {
1675 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
1676 } else {
1677 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
1678 }
1679 }
1cd62ae9 1680
3972ef6f 1681 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 1682 tcg_out32(s, MFSPR | RT(arg) | LR);
1cd62ae9 1683
2b7ec66f 1684 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
d604f1a9
RH		 1685
1686 tcg_out_b(s, 0, lb->raddr);
1cd62ae9 1687}
d604f1a9 1688#endif /* SOFTMMU */
1cd62ae9 1689
7f25c469 1690static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
810260a8 1691{
7f25c469
RH		 1692 TCGReg datalo, datahi, addrlo, rbase;
1693 TCGReg addrhi __attribute__((unused));
59227d5d 1694 TCGMemOpIdx oi;
7f25c469 1695 TCGMemOp opc, s_bits;
d604f1a9 1696#ifdef CONFIG_SOFTMMU
7f25c469 1697 int mem_index;
d604f1a9
RH		 1698 tcg_insn_unit *label_ptr;
1699#endif
810260a8 1700
7f25c469
RH		 1701 datalo = *args++;
1702 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1703 addrlo = *args++;
1704 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1705 oi = *args++;
1706 opc = get_memop(oi);
7f25c469
RH		 1707 s_bits = opc & MO_SIZE;
1708
d604f1a9 1709#ifdef CONFIG_SOFTMMU
59227d5d 1710 mem_index = get_mmuidx(oi);
68d45bb6 1711 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
d604f1a9
RH		 1712
1713 /* Load a pointer into the current opcode w/conditional branch-link. */
1714 label_ptr = s->code_ptr;
1715 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1716
1717 rbase = TCG_REG_R3;
1718#else /* !CONFIG_SOFTMMU */
b76f21a7 1719 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 1720 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 1721 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1722 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 1723 }
1724#endif
1725
7f25c469
RH		 1726 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1727 if (opc & MO_BSWAP) {
1728 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1729 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1730 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
1731 } else if (rbase != 0) {
1732 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1733 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
1734 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
1735 } else if (addrlo == datahi) {
1736 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1737 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1738 } else {
1739 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1740 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1741 }
541dd4ce 1742 } else {
2b7ec66f 1743 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
7f25c469
RH		 1744 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1745 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1746 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1747 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1748 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
1749 } else if (insn) {
1750 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1751 } else {
1752 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1753 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1754 insn = qemu_exts_opc[s_bits];
1755 tcg_out32(s, insn | RA(datalo) | RS(datalo));
1756 }
810260a8 1757 }
810260a8 1758
d604f1a9 1759#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 1760 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1761 s->code_ptr, label_ptr);
d604f1a9 1762#endif
810260a8 1763}
1764
7f25c469 1765static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
027ffea9 1766{
7f25c469
RH		 1767 TCGReg datalo, datahi, addrlo, rbase;
1768 TCGReg addrhi __attribute__((unused));
59227d5d 1769 TCGMemOpIdx oi;
7f25c469 1770 TCGMemOp opc, s_bits;
d604f1a9 1771#ifdef CONFIG_SOFTMMU
7f25c469 1772 int mem_index;
d604f1a9
RH		 1773 tcg_insn_unit *label_ptr;
1774#endif
027ffea9 1775
7f25c469
RH		 1776 datalo = *args++;
1777 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1778 addrlo = *args++;
1779 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1780 oi = *args++;
1781 opc = get_memop(oi);
7f25c469
RH		 1782 s_bits = opc & MO_SIZE;
1783
d604f1a9 1784#ifdef CONFIG_SOFTMMU
59227d5d 1785 mem_index = get_mmuidx(oi);
68d45bb6 1786 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
027ffea9 1787
d604f1a9
RH		 1788 /* Load a pointer into the current opcode w/conditional branch-link. */
1789 label_ptr = s->code_ptr;
1790 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
027ffea9 1791
d604f1a9
RH		 1792 rbase = TCG_REG_R3;
1793#else /* !CONFIG_SOFTMMU */
b76f21a7 1794 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 1795 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 1796 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1797 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 1798 }
1799#endif
1800
7f25c469
RH		 1801 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1802 if (opc & MO_BSWAP) {
1803 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1804 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1805 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
1806 } else if (rbase != 0) {
1807 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1808 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
1809 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
1810 } else {
1811 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
1812 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
1813 }
027ffea9 1814 } else {
2b7ec66f 1815 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
7f25c469
RH		 1816 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1817 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
dfca1778 1818 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
7f25c469 1819 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
dfca1778 1820 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
7f25c469
RH		 1821 } else {
1822 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
1823 }
027ffea9 1824 }
d604f1a9
RH		 1825
1826#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 1827 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1828 s->code_ptr, label_ptr);
d604f1a9 1829#endif
027ffea9
RH		 1830}
1831
a921fddc
RH		 1832/* Parameters for function call generation, used in tcg.c. */
1833#define TCG_TARGET_STACK_ALIGN 16
a921fddc
RH		 1834#define TCG_TARGET_EXTEND_ARGS 1
1835
802ca56e
RH		 1836#ifdef _CALL_AIX
1837# define LINK_AREA_SIZE (6 * SZR)
1838# define LR_OFFSET (1 * SZR)
1839# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1045fc04
PM		 1840#elif defined(TCG_TARGET_CALL_DARWIN)
1841# define LINK_AREA_SIZE (6 * SZR)
1842# define LR_OFFSET (2 * SZR)
ffcfbece
RH		 1843#elif TCG_TARGET_REG_BITS == 64
1844# if defined(_CALL_ELF) && _CALL_ELF == 2
1845# define LINK_AREA_SIZE (4 * SZR)
1846# define LR_OFFSET (1 * SZR)
1847# endif
1848#else /* TCG_TARGET_REG_BITS == 32 */
1849# if defined(_CALL_SYSV)
ffcfbece
RH		 1850# define LINK_AREA_SIZE (2 * SZR)
1851# define LR_OFFSET (1 * SZR)
ffcfbece
RH		 1852# endif
1853#endif
1854#ifndef LR_OFFSET
1855# error "Unhandled abi"
1856#endif
1857#ifndef TCG_TARGET_CALL_STACK_OFFSET
a2a98f80 1858# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
802ca56e
RH		 1859#endif
1860
1861#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1862#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
d604f1a9 1863
802ca56e
RH		 1864#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1865 + TCG_STATIC_CALL_ARGS_SIZE \
1866 + CPU_TEMP_BUF_SIZE \
1867 + REG_SAVE_SIZE \
1868 + TCG_TARGET_STACK_ALIGN - 1) \
1869 & -TCG_TARGET_STACK_ALIGN)
1870
1871#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
d604f1a9
RH		 1872
1873static void tcg_target_qemu_prologue(TCGContext *s)
810260a8 1874{
d604f1a9 1875 int i;
810260a8 1876
802ca56e 1877#ifdef _CALL_AIX
a84ac4cb
RH		 1878 void **desc = (void **)s->code_ptr;
1879 desc[0] = desc + 2; /* entry point */
1880 desc[1] = 0; /* environment pointer */
1881 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
d604f1a9
RH		 1882#endif
1883
a84ac4cb
RH		 1884 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1885 CPU_TEMP_BUF_SIZE);
1886
d604f1a9
RH		 1887 /* Prologue */
1888 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
ffcfbece
RH		 1889 tcg_out32(s, (SZR == 8 ? STDU : STWU)
1890 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
802ca56e 1891
d604f1a9 1892 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 1893 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1894 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 1895 }
802ca56e 1896 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 1897
4cbea598 1898#ifndef CONFIG_SOFTMMU
b76f21a7
LV		 1899 if (guest_base) {
1900 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
d604f1a9
RH		 1901 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1902 }
1903#endif
1904
1905 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1906 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
a84ac4cb
RH		 1907
1908 if (USE_REG_RA) {
1909#ifdef _CALL_AIX
1910 /* Make the caller load the value as the TOC into R2. */
1911 tb_ret_addr = s->code_ptr + 2;
1912 desc[1] = tb_ret_addr;
1913 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2);
1914 tcg_out32(s, BCCTR | BO_ALWAYS);
1915#elif defined(_CALL_ELF) && _CALL_ELF == 2
1916 /* Compute from the incoming R12 value. */
1917 tb_ret_addr = s->code_ptr + 2;
1918 tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12,
1919 tcg_ptr_byte_diff(tb_ret_addr, s->code_buf)));
1920 tcg_out32(s, BCCTR | BO_ALWAYS);
1921#else
1922 /* Reserve max 5 insns for the constant load. */
1923 tb_ret_addr = s->code_ptr + 6;
1924 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr);
1925 tcg_out32(s, BCCTR | BO_ALWAYS);
1926 while (s->code_ptr < tb_ret_addr) {
1927 tcg_out32(s, NOP);
1928 }
1929#endif
1930 } else {
1931 tcg_out32(s, BCCTR | BO_ALWAYS);
1932 tb_ret_addr = s->code_ptr;
1933 }
d604f1a9
RH		 1934
1935 /* Epilogue */
eabb7b91 1936 tcg_debug_assert(tb_ret_addr == s->code_ptr);
0c240785 1937 s->code_gen_epilogue = tb_ret_addr;
d604f1a9 1938
802ca56e 1939 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 1940 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 1941 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1942 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 1943 }
d604f1a9
RH		 1944 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1945 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1946 tcg_out32(s, BCLR | BO_ALWAYS);
810260a8 1947}
1948
541dd4ce
RH		 1949static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1950 const int *const_args)
810260a8 1951{
ee924fa6 1952 TCGArg a0, a1, a2;
e46b9681 1953 int c;
1954
810260a8 1955 switch (opc) {
1956 case INDEX_op_exit_tb:
a84ac4cb
RH		 1957 if (USE_REG_RA) {
1958 ptrdiff_t disp = tcg_pcrel_diff(s, tb_ret_addr);
1959
70f897bd
RH		 1960 /* Use a direct branch if we can, otherwise use the value in RA.
1961 Note that the direct branch is always backward, thus we need
1962 to account for the possibility of 5 insns from the movi. */
1963 if (!in_range_b(disp - 20)) {
a84ac4cb
RH		 1964 tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR);
1965 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1966 tcg_out32(s, BCCTR | BO_ALWAYS);
1967 break;
1968 }
1969 }
de3d636d 1970 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
e083c4a2 1971 tcg_out_b(s, 0, tb_ret_addr);
810260a8 1972 break;
1973 case INDEX_op_goto_tb:
f309101c 1974 tcg_debug_assert(s->tb_jmp_insn_offset);
399f1648
SF		 1975 /* Direct jump. */
1976#ifdef __powerpc64__
1977 /* Ensure the next insns are 8-byte aligned. */
5bfd75a3
RH		 1978 if ((uintptr_t)s->code_ptr & 7) {
1979 tcg_out32(s, NOP);
810260a8 1980 }
f309101c 1981 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
5bfd75a3
RH		 1982 /* To be replaced by either a branch+nop or a load into TMP1. */
1983 s->code_ptr += 2;
1984 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR);
1985 tcg_out32(s, BCCTR | BO_ALWAYS);
399f1648
SF		 1986#else
1987 /* To be replaced by a branch. */
1988 s->code_ptr++;
1989#endif
f309101c 1990 s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
810260a8 1991 break;
0c240785
RH		 1992 case INDEX_op_goto_ptr:
1993 tcg_out32(s, MTSPR | RS(args[0]) | CTR);
1994 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, 0);
1995 tcg_out32(s, BCCTR | BO_ALWAYS);
1996 break;
810260a8 1997 case INDEX_op_br:
1998 {
bec16311 1999 TCGLabel *l = arg_label(args[0]);
810260a8 2000
2001 if (l->has_value) {
e083c4a2 2002 tcg_out_b(s, 0, l->u.value_ptr);
541dd4ce 2003 } else {
bec16311 2004 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
c7ca6a2b 2005 tcg_out_b_noaddr(s, B);
810260a8 2006 }
2007 }
2008 break;
810260a8 2009 case INDEX_op_ld8u_i32:
2010 case INDEX_op_ld8u_i64:
b18d5d2b 2011 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
810260a8 2012 break;
2013 case INDEX_op_ld8s_i32:
2014 case INDEX_op_ld8s_i64:
b18d5d2b 2015 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
541dd4ce 2016 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
810260a8 2017 break;
2018 case INDEX_op_ld16u_i32:
2019 case INDEX_op_ld16u_i64:
b18d5d2b 2020 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
810260a8 2021 break;
2022 case INDEX_op_ld16s_i32:
2023 case INDEX_op_ld16s_i64:
b18d5d2b 2024 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
810260a8 2025 break;
2026 case INDEX_op_ld_i32:
2027 case INDEX_op_ld32u_i64:
b18d5d2b 2028 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
810260a8 2029 break;
2030 case INDEX_op_ld32s_i64:
b18d5d2b 2031 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
810260a8 2032 break;
2033 case INDEX_op_ld_i64:
b18d5d2b 2034 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
810260a8 2035 break;
2036 case INDEX_op_st8_i32:
2037 case INDEX_op_st8_i64:
b18d5d2b 2038 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
810260a8 2039 break;
2040 case INDEX_op_st16_i32:
2041 case INDEX_op_st16_i64:
b18d5d2b 2042 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
810260a8 2043 break;
2044 case INDEX_op_st_i32:
2045 case INDEX_op_st32_i64:
b18d5d2b 2046 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
810260a8 2047 break;
2048 case INDEX_op_st_i64:
b18d5d2b 2049 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
810260a8 2050 break;
2051
2052 case INDEX_op_add_i32:
ee924fa6
RH		 2053 a0 = args[0], a1 = args[1], a2 = args[2];
2054 if (const_args[2]) {
ee924fa6 2055 do_addi_32:
b18d5d2b 2056 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
ee924fa6
RH		 2057 } else {
2058 tcg_out32(s, ADD | TAB(a0, a1, a2));
2059 }
810260a8 2060 break;
2061 case INDEX_op_sub_i32:
ee924fa6 2062 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2063 if (const_args[1]) {
2064 if (const_args[2]) {
2065 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
2066 } else {
2067 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2068 }
2069 } else if (const_args[2]) {
ee924fa6
RH		 2070 a2 = -a2;
2071 goto do_addi_32;
2072 } else {
2073 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2074 }
810260a8 2075 break;
2076
2077 case INDEX_op_and_i32:
37251b98 2078 a0 = args[0], a1 = args[1], a2 = args[2];
a9249dff 2079 if (const_args[2]) {
37251b98 2080 tcg_out_andi32(s, a0, a1, a2);
a9249dff 2081 } else {
37251b98 2082 tcg_out32(s, AND | SAB(a1, a0, a2));
a9249dff
RH		 2083 }
2084 break;
2085 case INDEX_op_and_i64:
37251b98 2086 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2087 if (const_args[2]) {
37251b98 2088 tcg_out_andi64(s, a0, a1, a2);
637af30c 2089 } else {
37251b98 2090 tcg_out32(s, AND | SAB(a1, a0, a2));
810260a8 2091 }
810260a8 2092 break;
fe6f943f 2093 case INDEX_op_or_i64:
810260a8 2094 case INDEX_op_or_i32:
dce74c57 2095 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2096 if (const_args[2]) {
dce74c57
RH		 2097 tcg_out_ori32(s, a0, a1, a2);
2098 } else {
2099 tcg_out32(s, OR | SAB(a1, a0, a2));
810260a8 2100 }
810260a8 2101 break;
fe6f943f 2102 case INDEX_op_xor_i64:
810260a8 2103 case INDEX_op_xor_i32:
dce74c57 2104 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2105 if (const_args[2]) {
dce74c57
RH		 2106 tcg_out_xori32(s, a0, a1, a2);
2107 } else {
2108 tcg_out32(s, XOR | SAB(a1, a0, a2));
810260a8 2109 }
810260a8 2110 break;
ce1010d6 2111 case INDEX_op_andc_i32:
37251b98
RH		 2112 a0 = args[0], a1 = args[1], a2 = args[2];
2113 if (const_args[2]) {
2114 tcg_out_andi32(s, a0, a1, ~a2);
2115 } else {
2116 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2117 }
2118 break;
ce1010d6 2119 case INDEX_op_andc_i64:
37251b98
RH		 2120 a0 = args[0], a1 = args[1], a2 = args[2];
2121 if (const_args[2]) {
2122 tcg_out_andi64(s, a0, a1, ~a2);
2123 } else {
2124 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2125 }
ce1010d6
RH		 2126 break;
2127 case INDEX_op_orc_i32:
37251b98
RH		 2128 if (const_args[2]) {
2129 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2130 break;
2131 }
2132 /* FALLTHRU */
ce1010d6
RH		 2133 case INDEX_op_orc_i64:
2134 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2135 break;
2136 case INDEX_op_eqv_i32:
37251b98
RH		 2137 if (const_args[2]) {
2138 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2139 break;
2140 }
2141 /* FALLTHRU */
ce1010d6
RH		 2142 case INDEX_op_eqv_i64:
2143 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2144 break;
2145 case INDEX_op_nand_i32:
2146 case INDEX_op_nand_i64:
2147 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2148 break;
2149 case INDEX_op_nor_i32:
2150 case INDEX_op_nor_i64:
2151 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2152 break;
810260a8 2153
d0b07481
RH		 2154 case INDEX_op_clz_i32:
2155 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
2156 args[2], const_args[2]);
2157 break;
2158 case INDEX_op_ctz_i32:
2159 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
2160 args[2], const_args[2]);
2161 break;
33e75fb9
RH		 2162 case INDEX_op_ctpop_i32:
2163 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
2164 break;
d0b07481
RH		 2165
2166 case INDEX_op_clz_i64:
2167 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
2168 args[2], const_args[2]);
2169 break;
2170 case INDEX_op_ctz_i64:
2171 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
2172 args[2], const_args[2]);
2173 break;
33e75fb9
RH		 2174 case INDEX_op_ctpop_i64:
2175 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
2176 break;
d0b07481 2177
810260a8 2178 case INDEX_op_mul_i32:
ef809300 2179 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2180 if (const_args[2]) {
ef809300
RH		 2181 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2182 } else {
2183 tcg_out32(s, MULLW | TAB(a0, a1, a2));
810260a8 2184 }
810260a8 2185 break;
2186
2187 case INDEX_op_div_i32:
541dd4ce 2188 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
810260a8 2189 break;
2190
2191 case INDEX_op_divu_i32:
541dd4ce 2192 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
810260a8 2193 break;
2194
810260a8 2195 case INDEX_op_shl_i32:
2196 if (const_args[2]) {
a757e1ee 2197 tcg_out_shli32(s, args[0], args[1], args[2]);
9e555b73 2198 } else {
541dd4ce 2199 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
9e555b73 2200 }
810260a8 2201 break;
2202 case INDEX_op_shr_i32:
2203 if (const_args[2]) {
a757e1ee 2204 tcg_out_shri32(s, args[0], args[1], args[2]);
9e555b73 2205 } else {
541dd4ce 2206 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
9e555b73 2207 }
810260a8 2208 break;
2209 case INDEX_op_sar_i32:
541dd4ce
RH		 2210 if (const_args[2]) {
2211 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
2212 } else {
2213 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2214 }
810260a8 2215 break;
313d91c7
RH		 2216 case INDEX_op_rotl_i32:
2217 if (const_args[2]) {
2218 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2219 } else {
2220 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2221 | MB(0) | ME(31));
2222 }
2223 break;
2224 case INDEX_op_rotr_i32:
2225 if (const_args[2]) {
2226 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2227 } else {
8327a470
RH		 2228 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2229 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
313d91c7
RH		 2230 | MB(0) | ME(31));
2231 }
2232 break;
810260a8 2233
2234 case INDEX_op_brcond_i32:
4c314da6 2235 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2236 arg_label(args[3]), TCG_TYPE_I32);
e924bbec 2237 break;
810260a8 2238 case INDEX_op_brcond_i64:
4c314da6 2239 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2240 arg_label(args[3]), TCG_TYPE_I64);
810260a8 2241 break;
abcf61c4
RH		 2242 case INDEX_op_brcond2_i32:
2243 tcg_out_brcond2(s, args, const_args);
2244 break;
810260a8 2245
2246 case INDEX_op_neg_i32:
810260a8 2247 case INDEX_op_neg_i64:
541dd4ce 2248 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
810260a8 2249 break;
2250
157f2662 2251 case INDEX_op_not_i32:
2252 case INDEX_op_not_i64:
541dd4ce 2253 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
157f2662 2254 break;
2255
810260a8 2256 case INDEX_op_add_i64:
ee924fa6
RH		 2257 a0 = args[0], a1 = args[1], a2 = args[2];
2258 if (const_args[2]) {
ee924fa6 2259 do_addi_64:
b18d5d2b 2260 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
ee924fa6
RH		 2261 } else {
2262 tcg_out32(s, ADD | TAB(a0, a1, a2));
2263 }
810260a8 2264 break;
2265 case INDEX_op_sub_i64:
ee924fa6 2266 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2267 if (const_args[1]) {
2268 if (const_args[2]) {
2269 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2270 } else {
2271 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2272 }
2273 } else if (const_args[2]) {
ee924fa6
RH		 2274 a2 = -a2;
2275 goto do_addi_64;
2276 } else {
2277 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2278 }
810260a8 2279 break;
2280
2281 case INDEX_op_shl_i64:
541dd4ce 2282 if (const_args[2]) {
0a9564b9 2283 tcg_out_shli64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2284 } else {
2285 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2286 }
810260a8 2287 break;
2288 case INDEX_op_shr_i64:
541dd4ce 2289 if (const_args[2]) {
5e916c28 2290 tcg_out_shri64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2291 } else {
2292 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2293 }
810260a8 2294 break;
2295 case INDEX_op_sar_i64:
fe6f943f 2296 if (const_args[2]) {
541dd4ce
RH		 2297 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2298 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2299 } else {
2300 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
fe6f943f 2301 }
810260a8 2302 break;
313d91c7
RH		 2303 case INDEX_op_rotl_i64:
2304 if (const_args[2]) {
2305 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2306 } else {
2307 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2308 }
2309 break;
2310 case INDEX_op_rotr_i64:
2311 if (const_args[2]) {
2312 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2313 } else {
8327a470
RH		 2314 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2315 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
313d91c7
RH		 2316 }
2317 break;
810260a8 2318
2319 case INDEX_op_mul_i64:
ef809300
RH		 2320 a0 = args[0], a1 = args[1], a2 = args[2];
2321 if (const_args[2]) {
2322 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2323 } else {
2324 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2325 }
810260a8 2326 break;
2327 case INDEX_op_div_i64:
541dd4ce 2328 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
810260a8 2329 break;
2330 case INDEX_op_divu_i64:
541dd4ce 2331 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
810260a8 2332 break;
810260a8 2333
1768ec06 2334 case INDEX_op_qemu_ld_i32:
7f25c469
RH		 2335 tcg_out_qemu_ld(s, args, false);
2336 break;
1768ec06 2337 case INDEX_op_qemu_ld_i64:
7f25c469 2338 tcg_out_qemu_ld(s, args, true);
810260a8 2339 break;
1768ec06 2340 case INDEX_op_qemu_st_i32:
7f25c469
RH		 2341 tcg_out_qemu_st(s, args, false);
2342 break;
1768ec06 2343 case INDEX_op_qemu_st_i64:
7f25c469 2344 tcg_out_qemu_st(s, args, true);
810260a8 2345 break;
2346
e46b9681 2347 case INDEX_op_ext8s_i32:
2348 case INDEX_op_ext8s_i64:
2349 c = EXTSB;
2350 goto gen_ext;
2351 case INDEX_op_ext16s_i32:
2352 case INDEX_op_ext16s_i64:
2353 c = EXTSH;
2354 goto gen_ext;
4f2331e5 2355 case INDEX_op_ext_i32_i64:
e46b9681 2356 case INDEX_op_ext32s_i64:
2357 c = EXTSW;
2358 goto gen_ext;
2359 gen_ext:
541dd4ce 2360 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
e46b9681 2361 break;
4f2331e5
AJ		 2362 case INDEX_op_extu_i32_i64:
2363 tcg_out_ext32u(s, args[0], args[1]);
2364 break;
e46b9681 2365
1cd62ae9 2366 case INDEX_op_setcond_i32:
541dd4ce
RH		 2367 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2368 const_args[2]);
1cd62ae9 2369 break;
2370 case INDEX_op_setcond_i64:
541dd4ce
RH		 2371 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2372 const_args[2]);
1cd62ae9 2373 break;
abcf61c4
RH		 2374 case INDEX_op_setcond2_i32:
2375 tcg_out_setcond2(s, args, const_args);
2376 break;
1cd62ae9 2377
5d221582
RH		 2378 case INDEX_op_bswap16_i32:
2379 case INDEX_op_bswap16_i64:
2380 a0 = args[0], a1 = args[1];
2381 /* a1 = abcd */
2382 if (a0 != a1) {
2383 /* a0 = (a1 r<< 24) & 0xff # 000c */
2384 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2385 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2386 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2387 } else {
2388 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2389 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2390 /* a0 = (a1 r<< 24) & 0xff # 000c */
2391 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2392 /* a0 = a0 | r0 # 00dc */
2393 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2394 }
2395 break;
2396
2397 case INDEX_op_bswap32_i32:
2398 case INDEX_op_bswap32_i64:
2399 /* Stolen from gcc's builtin_bswap32 */
2400 a1 = args[1];
2401 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2402
2403 /* a1 = args[1] # abcd */
2404 /* a0 = rotate_left (a1, 8) # bcda */
2405 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2406 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2407 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2408 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2409 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2410
2411 if (a0 == TCG_REG_R0) {
de3d636d 2412 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
5d221582
RH		 2413 }
2414 break;
2415
68aebd45 2416 case INDEX_op_bswap64_i64:
8327a470 2417 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
68aebd45 2418 if (a0 == a1) {
8327a470 2419 a0 = TCG_REG_R0;
68aebd45
RH		 2420 a2 = a1;
2421 }
2422
2423 /* a1 = # abcd efgh */
2424 /* a0 = rl32(a1, 8) # 0000 fghe */
2425 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2426 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2427 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2428 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2429 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2430
2431 /* a0 = rl64(a0, 32) # hgfe 0000 */
2432 /* a2 = rl64(a1, 32) # efgh abcd */
2433 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2434 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2435
2436 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2437 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2438 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2439 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2440 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2441 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2442
2443 if (a0 == 0) {
de3d636d 2444 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
68aebd45
RH		 2445 }
2446 break;
2447
33de9ed2 2448 case INDEX_op_deposit_i32:
39dc85b9
RH		 2449 if (const_args[2]) {
2450 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2451 tcg_out_andi32(s, args[0], args[0], ~mask);
2452 } else {
2453 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2454 32 - args[3] - args[4], 31 - args[3]);
2455 }
33de9ed2
RH		 2456 break;
2457 case INDEX_op_deposit_i64:
39dc85b9
RH		 2458 if (const_args[2]) {
2459 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2460 tcg_out_andi64(s, args[0], args[0], ~mask);
2461 } else {
2462 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2463 64 - args[3] - args[4]);
2464 }
33de9ed2
RH		 2465 break;
2466
c05021c3
RH		 2467 case INDEX_op_extract_i32:
2468 tcg_out_rlw(s, RLWINM, args[0], args[1],
2469 32 - args[2], 32 - args[3], 31);
2470 break;
2471 case INDEX_op_extract_i64:
2472 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
2473 break;
2474
027ffea9
RH		 2475 case INDEX_op_movcond_i32:
2476 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2477 args[3], args[4], const_args[2]);
2478 break;
2479 case INDEX_op_movcond_i64:
2480 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2481 args[3], args[4], const_args[2]);
2482 break;
2483
796f1a68 2484#if TCG_TARGET_REG_BITS == 64
6c858762 2485 case INDEX_op_add2_i64:
796f1a68
RH		 2486#else
2487 case INDEX_op_add2_i32:
2488#endif
6c858762
RH		 2489 /* Note that the CA bit is defined based on the word size of the
2490 environment. So in 64-bit mode it's always carry-out of bit 63.
2491 The fallback code using deposit works just as well for 32-bit. */
2492 a0 = args[0], a1 = args[1];
84247357 2493 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
6c858762
RH		 2494 a0 = TCG_REG_R0;
2495 }
84247357
AB		 2496 if (const_args[4]) {
2497 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
6c858762 2498 } else {
84247357 2499 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
6c858762
RH		 2500 }
2501 if (const_args[5]) {
84247357 2502 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
6c858762 2503 } else {
84247357 2504 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
6c858762
RH		 2505 }
2506 if (a0 != args[0]) {
de3d636d 2507 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2508 }
2509 break;
2510
796f1a68 2511#if TCG_TARGET_REG_BITS == 64
6c858762 2512 case INDEX_op_sub2_i64:
796f1a68
RH		 2513#else
2514 case INDEX_op_sub2_i32:
2515#endif
6c858762 2516 a0 = args[0], a1 = args[1];
b31284ce 2517 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
6c858762
RH		 2518 a0 = TCG_REG_R0;
2519 }
2520 if (const_args[2]) {
b31284ce 2521 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
6c858762 2522 } else {
b31284ce 2523 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
6c858762 2524 }
b31284ce
RH		 2525 if (const_args[3]) {
2526 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
6c858762 2527 } else {
b31284ce 2528 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
6c858762
RH		 2529 }
2530 if (a0 != args[0]) {
de3d636d 2531 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2532 }
2533 break;
2534
abcf61c4
RH		 2535 case INDEX_op_muluh_i32:
2536 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2537 break;
8fa391a0
RH		 2538 case INDEX_op_mulsh_i32:
2539 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2540 break;
32f5717f
RH		 2541 case INDEX_op_muluh_i64:
2542 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2543 break;
2544 case INDEX_op_mulsh_i64:
2545 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
6645c147
RH		 2546 break;
2547
7b4af5ee
PK		 2548 case INDEX_op_mb:
2549 tcg_out_mb(s, args[0]);
2550 break;
2551
96d0ee7f
RH		 2552 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2553 case INDEX_op_mov_i64:
2554 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2555 case INDEX_op_movi_i64:
2556 case INDEX_op_call: /* Always emitted via tcg_out_call. */
810260a8 2557 default:
541dd4ce 2558 tcg_abort();
810260a8 2559 }
2560}
2561
2562static const TCGTargetOpDef ppc_op_defs[] = {
2563 { INDEX_op_exit_tb, { } },
2564 { INDEX_op_goto_tb, { } },
810260a8 2565 { INDEX_op_br, { } },
0c240785 2566 { INDEX_op_goto_ptr, { "r" } },
810260a8 2567
810260a8 2568 { INDEX_op_ld8u_i32, { "r", "r" } },
2569 { INDEX_op_ld8s_i32, { "r", "r" } },
2570 { INDEX_op_ld16u_i32, { "r", "r" } },
2571 { INDEX_op_ld16s_i32, { "r", "r" } },
2572 { INDEX_op_ld_i32, { "r", "r" } },
796f1a68 2573
810260a8 2574 { INDEX_op_st8_i32, { "r", "r" } },
810260a8 2575 { INDEX_op_st16_i32, { "r", "r" } },
810260a8 2576 { INDEX_op_st_i32, { "r", "r" } },
810260a8 2577
2578 { INDEX_op_add_i32, { "r", "r", "ri" } },
ef809300 2579 { INDEX_op_mul_i32, { "r", "r", "rI" } },
810260a8 2580 { INDEX_op_div_i32, { "r", "r", "r" } },
2581 { INDEX_op_divu_i32, { "r", "r", "r" } },
148bdd23 2582 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
810260a8 2583 { INDEX_op_and_i32, { "r", "r", "ri" } },
2584 { INDEX_op_or_i32, { "r", "r", "ri" } },
2585 { INDEX_op_xor_i32, { "r", "r", "ri" } },
37251b98
RH		 2586 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2587 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2588 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
ce1010d6
RH		 2589 { INDEX_op_nand_i32, { "r", "r", "r" } },
2590 { INDEX_op_nor_i32, { "r", "r", "r" } },
d0b07481
RH		 2591 { INDEX_op_clz_i32, { "r", "r", "rZW" } },
2592 { INDEX_op_ctz_i32, { "r", "r", "rZW" } },
33e75fb9 2593 { INDEX_op_ctpop_i32, { "r", "r" } },
810260a8 2594
2595 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2596 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2597 { INDEX_op_sar_i32, { "r", "r", "ri" } },
313d91c7
RH		 2598 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2599 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
810260a8 2600
810260a8 2601 { INDEX_op_neg_i32, { "r", "r" } },
157f2662 2602 { INDEX_op_not_i32, { "r", "r" } },
796f1a68
RH		 2603 { INDEX_op_ext8s_i32, { "r", "r" } },
2604 { INDEX_op_ext16s_i32, { "r", "r" } },
2605 { INDEX_op_bswap16_i32, { "r", "r" } },
2606 { INDEX_op_bswap32_i32, { "r", "r" } },
2607
2608 { INDEX_op_brcond_i32, { "r", "ri" } },
2609 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2610 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2611
2612 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
c05021c3 2613 { INDEX_op_extract_i32, { "r", "r" } },
796f1a68 2614
abcf61c4 2615 { INDEX_op_muluh_i32, { "r", "r", "r" } },
8fa391a0 2616 { INDEX_op_mulsh_i32, { "r", "r", "r" } },
abcf61c4 2617
796f1a68
RH		 2618#if TCG_TARGET_REG_BITS == 64
2619 { INDEX_op_ld8u_i64, { "r", "r" } },
2620 { INDEX_op_ld8s_i64, { "r", "r" } },
2621 { INDEX_op_ld16u_i64, { "r", "r" } },
2622 { INDEX_op_ld16s_i64, { "r", "r" } },
2623 { INDEX_op_ld32u_i64, { "r", "r" } },
2624 { INDEX_op_ld32s_i64, { "r", "r" } },
2625 { INDEX_op_ld_i64, { "r", "r" } },
2626
2627 { INDEX_op_st8_i64, { "r", "r" } },
2628 { INDEX_op_st16_i64, { "r", "r" } },
2629 { INDEX_op_st32_i64, { "r", "r" } },
2630 { INDEX_op_st_i64, { "r", "r" } },
810260a8 2631
ee924fa6 2632 { INDEX_op_add_i64, { "r", "r", "rT" } },
148bdd23 2633 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
37251b98 2634 { INDEX_op_and_i64, { "r", "r", "ri" } },
3d582c61
RH		 2635 { INDEX_op_or_i64, { "r", "r", "rU" } },
2636 { INDEX_op_xor_i64, { "r", "r", "rU" } },
37251b98 2637 { INDEX_op_andc_i64, { "r", "r", "ri" } },
ce1010d6
RH		 2638 { INDEX_op_orc_i64, { "r", "r", "r" } },
2639 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2640 { INDEX_op_nand_i64, { "r", "r", "r" } },
2641 { INDEX_op_nor_i64, { "r", "r", "r" } },
d0b07481
RH		 2642 { INDEX_op_clz_i64, { "r", "r", "rZW" } },
2643 { INDEX_op_ctz_i64, { "r", "r", "rZW" } },
33e75fb9 2644 { INDEX_op_ctpop_i64, { "r", "r" } },
810260a8 2645
fe6f943f 2646 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2647 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2648 { INDEX_op_sar_i64, { "r", "r", "ri" } },
313d91c7
RH		 2649 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2650 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
810260a8 2651
ef809300 2652 { INDEX_op_mul_i64, { "r", "r", "rI" } },
810260a8 2653 { INDEX_op_div_i64, { "r", "r", "r" } },
2654 { INDEX_op_divu_i64, { "r", "r", "r" } },
810260a8 2655
2656 { INDEX_op_neg_i64, { "r", "r" } },
157f2662 2657 { INDEX_op_not_i64, { "r", "r" } },
e46b9681 2658 { INDEX_op_ext8s_i64, { "r", "r" } },
2659 { INDEX_op_ext16s_i64, { "r", "r" } },
2660 { INDEX_op_ext32s_i64, { "r", "r" } },
4f2331e5
AJ		 2661 { INDEX_op_ext_i32_i64, { "r", "r" } },
2662 { INDEX_op_extu_i32_i64, { "r", "r" } },
5d221582 2663 { INDEX_op_bswap16_i64, { "r", "r" } },
5d221582 2664 { INDEX_op_bswap32_i64, { "r", "r" } },
68aebd45 2665 { INDEX_op_bswap64_i64, { "r", "r" } },
5d221582 2666
796f1a68
RH		 2667 { INDEX_op_brcond_i64, { "r", "ri" } },
2668 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2669 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2670
39dc85b9 2671 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
c05021c3 2672 { INDEX_op_extract_i64, { "r", "r" } },
33de9ed2 2673
32f5717f
RH		 2674 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2675 { INDEX_op_muluh_i64, { "r", "r", "r" } },
796f1a68
RH		 2676#endif
2677
abcf61c4
RH		 2678#if TCG_TARGET_REG_BITS == 32
2679 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
2680 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
2681#endif
2682
796f1a68
RH		 2683#if TCG_TARGET_REG_BITS == 64
2684 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2685 { INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } },
2686#else
2687 { INDEX_op_add2_i32, { "r", "r", "r", "r", "rI", "rZM" } },
2688 { INDEX_op_sub2_i32, { "r", "r", "rI", "rZM", "r", "r" } },
2689#endif
2690
2691#if TCG_TARGET_REG_BITS == 64
2692 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2693 { INDEX_op_qemu_st_i32, { "S", "S" } },
2694 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2695 { INDEX_op_qemu_st_i64, { "S", "S" } },
2696#elif TARGET_LONG_BITS == 32
2697 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2698 { INDEX_op_qemu_st_i32, { "S", "S" } },
7f25c469 2699 { INDEX_op_qemu_ld_i64, { "L", "L", "L" } },
796f1a68
RH		 2700 { INDEX_op_qemu_st_i64, { "S", "S", "S" } },
2701#else
2702 { INDEX_op_qemu_ld_i32, { "r", "L", "L" } },
2703 { INDEX_op_qemu_st_i32, { "S", "S", "S" } },
7f25c469 2704 { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } },
796f1a68
RH		 2705 { INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
2706#endif
6c858762 2707
7b4af5ee 2708 { INDEX_op_mb, { } },
810260a8 2709 { -1 },
2710};
2711
f69d277e
RH		 2712static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2713{
2714 int i, n = ARRAY_SIZE(ppc_op_defs);
2715
2716 for (i = 0; i < n; ++i) {
2717 if (ppc_op_defs[i].op == op) {
2718 return &ppc_op_defs[i];
2719 }
2720 }
2721 return NULL;
2722}
2723
541dd4ce 2724static void tcg_target_init(TCGContext *s)
810260a8 2725{
cd629de1 2726 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
d0b07481
RH		 2727 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
2728
1e6e9aca
RH		 2729 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2730 have_isa_2_06 = true;
2731 }
d0b07481
RH		 2732#ifdef PPC_FEATURE2_ARCH_3_00
2733 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
2734 have_isa_3_00 = true;
2735 }
2736#endif
1e6e9aca 2737
541dd4ce
RH		 2738 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2739 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2740 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
810260a8 2741 (1 << TCG_REG_R0) |
5d7ff5bb 2742 (1 << TCG_REG_R2) |
810260a8 2743 (1 << TCG_REG_R3) |
2744 (1 << TCG_REG_R4) |
2745 (1 << TCG_REG_R5) |
2746 (1 << TCG_REG_R6) |
2747 (1 << TCG_REG_R7) |
2748 (1 << TCG_REG_R8) |
2749 (1 << TCG_REG_R9) |
2750 (1 << TCG_REG_R10) |
2751 (1 << TCG_REG_R11) |
5e1702b0 2752 (1 << TCG_REG_R12));
810260a8 2753
541dd4ce 2754 tcg_regset_clear(s->reserved_regs);
5e1702b0
RH		 2755 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2756 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
dfca1778
RH		 2757#if defined(_CALL_SYSV)
2758 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
5d7ff5bb 2759#endif
dfca1778 2760#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
5e1702b0 2761 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
dfca1778
RH		 2762#endif
2763 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
a84ac4cb
RH		 2764 if (USE_REG_RA) {
2765 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */
2766 }
810260a8 2767}
fa94c3be 2768
ffcfbece 2769#ifdef __ELF__
fa94c3be
RH		 2770typedef struct {
2771 DebugFrameCIE cie;
2772 DebugFrameFDEHeader fde;
2773 uint8_t fde_def_cfa[4];
2774 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2775} DebugFrame;
2776
2777/* We're expecting a 2 byte uleb128 encoded value. */
2778QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2779
ffcfbece
RH		 2780#if TCG_TARGET_REG_BITS == 64
2781# define ELF_HOST_MACHINE EM_PPC64
2782#else
2783# define ELF_HOST_MACHINE EM_PPC
2784#endif
fa94c3be
RH		 2785
2786static DebugFrame debug_frame = {
2787 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2788 .cie.id = -1,
2789 .cie.version = 1,
2790 .cie.code_align = 1,
802ca56e 2791 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
fa94c3be
RH		 2792 .cie.return_column = 65,
2793
2794 /* Total FDE size does not include the "len" member. */
2795 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2796
2797 .fde_def_cfa = {
802ca56e 2798 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
fa94c3be
RH		 2799 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2800 (FRAME_SIZE >> 7)
2801 },
2802 .fde_reg_ofs = {
802ca56e
RH		 2803 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2804 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
fa94c3be
RH		 2805 }
2806};
2807
2808void tcg_register_jit(void *buf, size_t buf_size)
2809{
2810 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2811 int i;
2812
2813 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2814 p[0] = 0x80 + tcg_target_callee_save_regs[i];
802ca56e 2815 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
fa94c3be
RH		 2816 }
2817
802ca56e 2818 debug_frame.fde.func_start = (uintptr_t)buf;
fa94c3be
RH		 2819 debug_frame.fde.func_len = buf_size;
2820
2821 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2822}
ffcfbece 2823#endif /* __ELF__ */
224f9fd4 2824
224f9fd4
RH		 2825void flush_icache_range(uintptr_t start, uintptr_t stop)
2826{
2827 uintptr_t p, start1, stop1;
b255b2c8
EC		 2828 size_t dsize = qemu_dcache_linesize;
2829 size_t isize = qemu_icache_linesize;
224f9fd4
RH		 2830
2831 start1 = start & ~(dsize - 1);
2832 stop1 = (stop + dsize - 1) & ~(dsize - 1);
2833 for (p = start1; p < stop1; p += dsize) {
2834 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
2835 }
2836 asm volatile ("sync" : : : "memory");
2837
2838 start &= start & ~(isize - 1);
2839 stop1 = (stop + isize - 1) & ~(isize - 1);
2840 for (p = start1; p < stop1; p += isize) {
2841 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
2842 }
2843 asm volatile ("sync" : : : "memory");
2844 asm volatile ("isync" : : : "memory");
2845}
QEMU mirror