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tcg-ppc: Support new ldst opcodes
[mirror_qemu.git] / tcg / ppc64 / tcg-target.c
CommitLineData
810260a8 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
9ecefc84
RH		 25#include "tcg-be-ldst.h"
26
3d582c61
RH		 27#define TCG_CT_CONST_S16 0x100
28#define TCG_CT_CONST_U16 0x200
29#define TCG_CT_CONST_S32 0x400
30#define TCG_CT_CONST_U32 0x800
31#define TCG_CT_CONST_ZERO 0x1000
6c858762 32#define TCG_CT_CONST_MONE 0x2000
fe6f943f 33
810260a8 34static uint8_t *tb_ret_addr;
35
810260a8 36#if TARGET_LONG_BITS == 32
fedee3e7 37#define LD_ADDR LWZ
e924bbec 38#define CMP_L 0
810260a8 39#else
fedee3e7 40#define LD_ADDR LD
e924bbec 41#define CMP_L (1<<21)
810260a8 42#endif
43
f6548c0a 44#ifndef GUEST_BASE
45#define GUEST_BASE 0
46#endif
47
1e6e9aca
RH		 48#ifdef CONFIG_GETAUXVAL
49#include <sys/auxv.h>
50static bool have_isa_2_06;
51#define HAVE_ISA_2_06 have_isa_2_06
52#define HAVE_ISEL have_isa_2_06
53#else
49d9870a 54#define HAVE_ISA_2_06 0
70fac59a 55#define HAVE_ISEL 0
1e6e9aca 56#endif
49d9870a 57
f6548c0a 58#ifdef CONFIG_USE_GUEST_BASE
59#define TCG_GUEST_BASE_REG 30
60#else
61#define TCG_GUEST_BASE_REG 0
62#endif
63
d4a9eb1f 64#ifndef NDEBUG
810260a8 65static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
66 "r0",
67 "r1",
98926b0a 68 "r2",
810260a8 69 "r3",
70 "r4",
71 "r5",
72 "r6",
73 "r7",
74 "r8",
75 "r9",
76 "r10",
77 "r11",
78 "r12",
79 "r13",
80 "r14",
81 "r15",
82 "r16",
83 "r17",
84 "r18",
85 "r19",
86 "r20",
87 "r21",
88 "r22",
89 "r23",
90 "r24",
91 "r25",
92 "r26",
93 "r27",
94 "r28",
95 "r29",
96 "r30",
97 "r31"
98};
d4a9eb1f 99#endif
810260a8 100
101static const int tcg_target_reg_alloc_order[] = {
5e1702b0 102 TCG_REG_R14, /* call saved registers */
810260a8 103 TCG_REG_R15,
104 TCG_REG_R16,
105 TCG_REG_R17,
106 TCG_REG_R18,
107 TCG_REG_R19,
108 TCG_REG_R20,
109 TCG_REG_R21,
110 TCG_REG_R22,
111 TCG_REG_R23,
5e1702b0
RH		 112 TCG_REG_R24,
113 TCG_REG_R25,
114 TCG_REG_R26,
115 TCG_REG_R27,
810260a8 116 TCG_REG_R28,
117 TCG_REG_R29,
118 TCG_REG_R30,
119 TCG_REG_R31,
5e1702b0
RH		 120 TCG_REG_R12, /* call clobbered, non-arguments */
121 TCG_REG_R11,
5e1702b0 122 TCG_REG_R10, /* call clobbered, arguments */
810260a8 123 TCG_REG_R9,
5e1702b0
RH		 124 TCG_REG_R8,
125 TCG_REG_R7,
126 TCG_REG_R6,
127 TCG_REG_R5,
128 TCG_REG_R4,
129 TCG_REG_R3,
810260a8 130};
131
132static const int tcg_target_call_iarg_regs[] = {
133 TCG_REG_R3,
134 TCG_REG_R4,
135 TCG_REG_R5,
136 TCG_REG_R6,
137 TCG_REG_R7,
138 TCG_REG_R8,
139 TCG_REG_R9,
140 TCG_REG_R10
141};
142
be9c4183 143static const int tcg_target_call_oarg_regs[] = {
810260a8 144 TCG_REG_R3
145};
146
147static const int tcg_target_callee_save_regs[] = {
5d7ff5bb
AF		 148#ifdef __APPLE__
149 TCG_REG_R11,
150#endif
810260a8 151 TCG_REG_R14,
152 TCG_REG_R15,
153 TCG_REG_R16,
154 TCG_REG_R17,
155 TCG_REG_R18,
156 TCG_REG_R19,
157 TCG_REG_R20,
158 TCG_REG_R21,
159 TCG_REG_R22,
160 TCG_REG_R23,
095271d4 161 TCG_REG_R24,
162 TCG_REG_R25,
163 TCG_REG_R26,
cea5f9a2 164 TCG_REG_R27, /* currently used for the global env */
810260a8 165 TCG_REG_R28,
166 TCG_REG_R29,
167 TCG_REG_R30,
168 TCG_REG_R31
169};
170
b0940da0
RH		 171static inline bool in_range_b(tcg_target_long target)
172{
173 return target == sextract64(target, 0, 26);
174}
175
541dd4ce 176static uint32_t reloc_pc24_val(void *pc, tcg_target_long target)
810260a8 177{
178 tcg_target_long disp;
179
541dd4ce 180 disp = target - (tcg_target_long)pc;
b0940da0 181 assert(in_range_b(disp));
810260a8 182
183 return disp & 0x3fffffc;
184}
185
541dd4ce 186static void reloc_pc24(void *pc, tcg_target_long target)
810260a8 187{
541dd4ce
RH		 188 *(uint32_t *)pc = (*(uint32_t *)pc & ~0x3fffffc)
189 | reloc_pc24_val(pc, target);
810260a8 190}
191
541dd4ce 192static uint16_t reloc_pc14_val(void *pc, tcg_target_long target)
810260a8 193{
194 tcg_target_long disp;
195
541dd4ce
RH		 196 disp = target - (tcg_target_long)pc;
197 if (disp != (int16_t) disp) {
198 tcg_abort();
199 }
810260a8 200
201 return disp & 0xfffc;
202}
203
541dd4ce 204static void reloc_pc14(void *pc, tcg_target_long target)
810260a8 205{
541dd4ce 206 *(uint32_t *)pc = (*(uint32_t *)pc & ~0xfffc) | reloc_pc14_val(pc, target);
810260a8 207}
208
c7ca6a2b
RH		 209static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
210{
211 unsigned retrans = *(uint32_t *)s->code_ptr & 0x3fffffc;
212 tcg_out32(s, insn | retrans);
213}
214
215static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
216{
217 unsigned retrans = *(uint32_t *)s->code_ptr & 0xfffc;
218 tcg_out32(s, insn | retrans);
219}
220
541dd4ce
RH		 221static void patch_reloc(uint8_t *code_ptr, int type,
222 intptr_t value, intptr_t addend)
810260a8 223{
224 value += addend;
225 switch (type) {
226 case R_PPC_REL14:
541dd4ce 227 reloc_pc14(code_ptr, value);
810260a8 228 break;
229 case R_PPC_REL24:
541dd4ce 230 reloc_pc24(code_ptr, value);
810260a8 231 break;
232 default:
541dd4ce 233 tcg_abort();
810260a8 234 }
235}
236
810260a8 237/* parse target specific constraints */
541dd4ce 238static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
810260a8 239{
240 const char *ct_str;
241
242 ct_str = *pct_str;
243 switch (ct_str[0]) {
244 case 'A': case 'B': case 'C': case 'D':
245 ct->ct |= TCG_CT_REG;
541dd4ce 246 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
810260a8 247 break;
248 case 'r':
249 ct->ct |= TCG_CT_REG;
541dd4ce 250 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
810260a8 251 break;
252 case 'L': /* qemu_ld constraint */
253 ct->ct |= TCG_CT_REG;
541dd4ce
RH		 254 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
255 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 256#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 257 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
258 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
735ee40d 259#endif
810260a8 260 break;
c070355d 261 case 'S': /* qemu_st constraint */
810260a8 262 ct->ct |= TCG_CT_REG;
541dd4ce
RH		 263 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
264 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 265#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 266 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
267 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
268 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
735ee40d 269#endif
810260a8 270 break;
3d582c61
RH		 271 case 'I':
272 ct->ct |= TCG_CT_CONST_S16;
273 break;
274 case 'J':
275 ct->ct |= TCG_CT_CONST_U16;
276 break;
6c858762
RH		 277 case 'M':
278 ct->ct |= TCG_CT_CONST_MONE;
279 break;
3d582c61
RH		 280 case 'T':
281 ct->ct |= TCG_CT_CONST_S32;
282 break;
283 case 'U':
fe6f943f 284 ct->ct |= TCG_CT_CONST_U32;
285 break;
3d582c61
RH		 286 case 'Z':
287 ct->ct |= TCG_CT_CONST_ZERO;
288 break;
810260a8 289 default:
290 return -1;
291 }
292 ct_str++;
293 *pct_str = ct_str;
294 return 0;
295}
296
297/* test if a constant matches the constraint */
541dd4ce
RH		 298static int tcg_target_const_match(tcg_target_long val,
299 const TCGArgConstraint *arg_ct)
810260a8 300{
3d582c61
RH		 301 int ct = arg_ct->ct;
302 if (ct & TCG_CT_CONST) {
303 return 1;
304 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
305 return 1;
306 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
810260a8 307 return 1;
3d582c61 308 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
fe6f943f 309 return 1;
3d582c61
RH		 310 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
311 return 1;
312 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
313 return 1;
6c858762
RH		 314 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
315 return 1;
3d582c61 316 }
810260a8 317 return 0;
318}
319
320#define OPCD(opc) ((opc)<<26)
321#define XO19(opc) (OPCD(19)|((opc)<<1))
8a94cfb0
AB		 322#define MD30(opc) (OPCD(30)|((opc)<<2))
323#define MDS30(opc) (OPCD(30)|((opc)<<1))
810260a8 324#define XO31(opc) (OPCD(31)|((opc)<<1))
325#define XO58(opc) (OPCD(58)|(opc))
326#define XO62(opc) (OPCD(62)|(opc))
327
328#define B OPCD( 18)
329#define BC OPCD( 16)
330#define LBZ OPCD( 34)
331#define LHZ OPCD( 40)
332#define LHA OPCD( 42)
333#define LWZ OPCD( 32)
334#define STB OPCD( 38)
335#define STH OPCD( 44)
336#define STW OPCD( 36)
337
338#define STD XO62( 0)
339#define STDU XO62( 1)
340#define STDX XO31(149)
341
342#define LD XO58( 0)
343#define LDX XO31( 21)
344#define LDU XO58( 1)
301f6d90 345#define LWA XO58( 2)
810260a8 346#define LWAX XO31(341)
347
1cd62ae9 348#define ADDIC OPCD( 12)
810260a8 349#define ADDI OPCD( 14)
350#define ADDIS OPCD( 15)
351#define ORI OPCD( 24)
352#define ORIS OPCD( 25)
353#define XORI OPCD( 26)
354#define XORIS OPCD( 27)
355#define ANDI OPCD( 28)
356#define ANDIS OPCD( 29)
357#define MULLI OPCD( 7)
358#define CMPLI OPCD( 10)
359#define CMPI OPCD( 11)
148bdd23 360#define SUBFIC OPCD( 8)
810260a8 361
362#define LWZU OPCD( 33)
363#define STWU OPCD( 37)
364
313d91c7 365#define RLWIMI OPCD( 20)
810260a8 366#define RLWINM OPCD( 21)
313d91c7 367#define RLWNM OPCD( 23)
810260a8 368
8a94cfb0
AB		 369#define RLDICL MD30( 0)
370#define RLDICR MD30( 1)
371#define RLDIMI MD30( 3)
372#define RLDCL MDS30( 8)
810260a8 373
374#define BCLR XO19( 16)
375#define BCCTR XO19(528)
376#define CRAND XO19(257)
377#define CRANDC XO19(129)
378#define CRNAND XO19(225)
379#define CROR XO19(449)
1cd62ae9 380#define CRNOR XO19( 33)
810260a8 381
382#define EXTSB XO31(954)
383#define EXTSH XO31(922)
384#define EXTSW XO31(986)
385#define ADD XO31(266)
386#define ADDE XO31(138)
6c858762
RH		 387#define ADDME XO31(234)
388#define ADDZE XO31(202)
810260a8 389#define ADDC XO31( 10)
390#define AND XO31( 28)
391#define SUBF XO31( 40)
392#define SUBFC XO31( 8)
393#define SUBFE XO31(136)
6c858762
RH		 394#define SUBFME XO31(232)
395#define SUBFZE XO31(200)
810260a8 396#define OR XO31(444)
397#define XOR XO31(316)
398#define MULLW XO31(235)
399#define MULHWU XO31( 11)
400#define DIVW XO31(491)
401#define DIVWU XO31(459)
402#define CMP XO31( 0)
403#define CMPL XO31( 32)
404#define LHBRX XO31(790)
405#define LWBRX XO31(534)
49d9870a 406#define LDBRX XO31(532)
810260a8 407#define STHBRX XO31(918)
408#define STWBRX XO31(662)
49d9870a 409#define STDBRX XO31(660)
810260a8 410#define MFSPR XO31(339)
411#define MTSPR XO31(467)
412#define SRAWI XO31(824)
413#define NEG XO31(104)
1cd62ae9 414#define MFCR XO31( 19)
6995a4a0 415#define MFOCRF (MFCR | (1u << 20))
157f2662 416#define NOR XO31(124)
1cd62ae9 417#define CNTLZW XO31( 26)
418#define CNTLZD XO31( 58)
ce1010d6
RH		 419#define ANDC XO31( 60)
420#define ORC XO31(412)
421#define EQV XO31(284)
422#define NAND XO31(476)
70fac59a 423#define ISEL XO31( 15)
810260a8 424
425#define MULLD XO31(233)
426#define MULHD XO31( 73)
427#define MULHDU XO31( 9)
428#define DIVD XO31(489)
429#define DIVDU XO31(457)
430
431#define LBZX XO31( 87)
4f4a67ae 432#define LHZX XO31(279)
810260a8 433#define LHAX XO31(343)
434#define LWZX XO31( 23)
435#define STBX XO31(215)
436#define STHX XO31(407)
437#define STWX XO31(151)
438
541dd4ce 439#define SPR(a, b) ((((a)<<5)|(b))<<11)
810260a8 440#define LR SPR(8, 0)
441#define CTR SPR(9, 0)
442
443#define SLW XO31( 24)
444#define SRW XO31(536)
445#define SRAW XO31(792)
446
447#define SLD XO31( 27)
448#define SRD XO31(539)
449#define SRAD XO31(794)
fe6f943f 450#define SRADI XO31(413<<1)
810260a8 451
810260a8 452#define TW XO31( 4)
541dd4ce 453#define TRAP (TW | TO(31))
810260a8 454
455#define RT(r) ((r)<<21)
456#define RS(r) ((r)<<21)
457#define RA(r) ((r)<<16)
458#define RB(r) ((r)<<11)
459#define TO(t) ((t)<<21)
460#define SH(s) ((s)<<11)
461#define MB(b) ((b)<<6)
462#define ME(e) ((e)<<1)
463#define BO(o) ((o)<<21)
464#define MB64(b) ((b)<<5)
6995a4a0 465#define FXM(b) (1 << (19 - (b)))
810260a8 466
467#define LK 1
468
2fd8eddc
RH		 469#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
470#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
471#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
472#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
810260a8 473
474#define BF(n) ((n)<<23)
475#define BI(n, c) (((c)+((n)*4))<<16)
476#define BT(n, c) (((c)+((n)*4))<<21)
477#define BA(n, c) (((c)+((n)*4))<<16)
478#define BB(n, c) (((c)+((n)*4))<<11)
70fac59a 479#define BC_(n, c) (((c)+((n)*4))<<6)
810260a8 480
541dd4ce
RH		 481#define BO_COND_TRUE BO(12)
482#define BO_COND_FALSE BO( 4)
483#define BO_ALWAYS BO(20)
810260a8 484
485enum {
486 CR_LT,
487 CR_GT,
488 CR_EQ,
489 CR_SO
490};
491
0aed257f 492static const uint32_t tcg_to_bc[] = {
541dd4ce
RH		 493 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
494 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
495 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
496 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
497 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
498 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
499 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
500 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
501 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
502 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
810260a8 503};
504
70fac59a
RH		 505/* The low bit here is set if the RA and RB fields must be inverted. */
506static const uint32_t tcg_to_isel[] = {
507 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
508 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
509 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
510 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
511 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
512 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
513 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
514 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
515 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
516 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
517};
518
aceac8d6
RH		 519static inline void tcg_out_mov(TCGContext *s, TCGType type,
520 TCGReg ret, TCGReg arg)
810260a8 521{
f8b84129
RH		 522 if (ret != arg) {
523 tcg_out32(s, OR | SAB(arg, ret, arg));
524 }
810260a8 525}
526
aceac8d6
RH		 527static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
528 int sh, int mb)
810260a8 529{
541dd4ce
RH		 530 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
531 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
532 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
810260a8 533}
534
9e555b73
RH		 535static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
536 int sh, int mb, int me)
537{
538 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
539}
540
6e5e0602
RH		 541static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
542{
543 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
544}
545
0a9564b9
RH		 546static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
547{
548 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
549}
550
5e916c28
RH		 551static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
552{
553 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
554}
555
aceac8d6 556static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
810260a8 557{
2fd8eddc
RH		 558 if (arg == (int16_t) arg) {
559 tcg_out32(s, ADDI | TAI(ret, 0, arg));
560 } else {
561 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
562 if (arg & 0xffff) {
563 tcg_out32(s, ORI | SAI(ret, ret, arg));
564 }
810260a8 565 }
566}
567
421233a1
RH		 568static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
569 tcg_target_long arg)
810260a8 570{
421233a1
RH		 571 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
572 tcg_out_movi32(s, ret, arg);
573 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
574 tcg_out32(s, ADDI | TAI(ret, 0, arg));
575 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
576 } else {
577 int32_t high = arg >> 32;
578 tcg_out_movi32(s, ret, high);
579 if (high) {
0a9564b9 580 tcg_out_shli64(s, ret, ret, 32);
421233a1
RH		 581 }
582 if (arg & 0xffff0000) {
583 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
584 }
585 if (arg & 0xffff) {
586 tcg_out32(s, ORI | SAI(ret, ret, arg));
810260a8 587 }
588 }
589}
590
637af30c 591static bool mask_operand(uint32_t c, int *mb, int *me)
a9249dff
RH		 592{
593 uint32_t lsb, test;
594
595 /* Accept a bit pattern like:
596 0....01....1
597 1....10....0
598 0..01..10..0
599 Keep track of the transitions. */
600 if (c == 0 || c == -1) {
601 return false;
602 }
603 test = c;
604 lsb = test & -test;
605 test += lsb;
606 if (test & (test - 1)) {
607 return false;
608 }
609
610 *me = clz32(lsb);
611 *mb = test ? clz32(test & -test) + 1 : 0;
612 return true;
613}
614
637af30c
RH		 615static bool mask64_operand(uint64_t c, int *mb, int *me)
616{
617 uint64_t lsb;
618
619 if (c == 0) {
620 return false;
621 }
622
623 lsb = c & -c;
624 /* Accept 1..10..0. */
625 if (c == -lsb) {
626 *mb = 0;
627 *me = clz64(lsb);
628 return true;
629 }
630 /* Accept 0..01..1. */
631 if (lsb == 1 && (c & (c + 1)) == 0) {
632 *mb = clz64(c + 1) + 1;
633 *me = 63;
634 return true;
635 }
636 return false;
637}
638
a9249dff
RH		 639static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
640{
641 int mb, me;
642
643 if ((c & 0xffff) == c) {
644 tcg_out32(s, ANDI | SAI(src, dst, c));
645 return;
646 } else if ((c & 0xffff0000) == c) {
647 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
648 return;
649 } else if (mask_operand(c, &mb, &me)) {
650 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
651 } else {
8327a470
RH		 652 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
653 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
a9249dff
RH		 654 }
655}
656
637af30c
RH		 657static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
658{
659 int mb, me;
660
661 if ((c & 0xffff) == c) {
662 tcg_out32(s, ANDI | SAI(src, dst, c));
663 return;
664 } else if ((c & 0xffff0000) == c) {
665 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
666 return;
667 } else if (mask64_operand(c, &mb, &me)) {
668 if (mb == 0) {
669 tcg_out_rld(s, RLDICR, dst, src, 0, me);
670 } else {
671 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
672 }
673 } else {
8327a470
RH		 674 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
675 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
637af30c
RH		 676 }
677}
678
dce74c57
RH		 679static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
680 int op_lo, int op_hi)
681{
682 if (c >> 16) {
683 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
684 src = dst;
685 }
686 if (c & 0xffff) {
687 tcg_out32(s, op_lo | SAI(src, dst, c));
688 src = dst;
689 }
690}
691
692static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
693{
694 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
695}
696
697static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
698{
699 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
700}
701
541dd4ce 702static void tcg_out_b(TCGContext *s, int mask, tcg_target_long target)
5d7ff5bb
AF		 703{
704 tcg_target_long disp;
705
541dd4ce 706 disp = target - (tcg_target_long)s->code_ptr;
b0940da0 707 if (in_range_b(disp)) {
541dd4ce
RH		 708 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
709 } else {
8327a470
RH		 710 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, (tcg_target_long)target);
711 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
541dd4ce 712 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
5d7ff5bb
AF		 713 }
714}
715
541dd4ce 716static void tcg_out_call(TCGContext *s, tcg_target_long arg, int const_arg)
810260a8 717{
5d7ff5bb
AF		 718#ifdef __APPLE__
719 if (const_arg) {
541dd4ce
RH		 720 tcg_out_b(s, LK, arg);
721 } else {
722 tcg_out32(s, MTSPR | RS(arg) | LR);
723 tcg_out32(s, BCLR | BO_ALWAYS | LK);
5d7ff5bb
AF		 724 }
725#else
d40f3cb1
RH		 726 TCGReg reg = arg;
727 int ofs = 0;
810260a8 728
729 if (const_arg) {
b0940da0
RH		 730 /* Look through the descriptor. If the branch is in range, and we
731 don't have to spend too much effort on building the toc. */
732 intptr_t tgt = ((intptr_t *)arg)[0];
733 intptr_t toc = ((intptr_t *)arg)[1];
734 intptr_t diff = tgt - (intptr_t)s->code_ptr;
735
736 if (in_range_b(diff) && toc == (uint32_t)toc) {
737 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, toc);
738 tcg_out_b(s, LK, tgt);
739 return;
740 }
741
d40f3cb1
RH		 742 /* Fold the low bits of the constant into the addresses below. */
743 ofs = (int16_t)arg;
744 if (ofs + 8 < 0x8000) {
745 arg -= ofs;
746 } else {
747 ofs = 0;
748 }
8327a470 749 reg = TCG_REG_R2;
541dd4ce 750 tcg_out_movi(s, TCG_TYPE_I64, reg, arg);
810260a8 751 }
810260a8 752
d40f3cb1 753 tcg_out32(s, LD | TAI(TCG_REG_R0, reg, ofs));
8327a470 754 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
d40f3cb1 755 tcg_out32(s, LD | TAI(TCG_REG_R2, reg, ofs + 8));
541dd4ce 756 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
5d7ff5bb 757#endif
810260a8 758}
759
b18d5d2b
RH		 760static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
761 TCGReg base, tcg_target_long offset)
810260a8 762{
b18d5d2b
RH		 763 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
764 TCGReg rs = TCG_REG_R2;
765
766 assert(rt != TCG_REG_R2 && base != TCG_REG_R2);
767
768 switch (opi) {
769 case LD: case LWA:
770 align = 3;
771 /* FALLTHRU */
772 default:
773 if (rt != TCG_REG_R0) {
774 rs = rt;
775 }
776 break;
777 case STD:
778 align = 3;
779 break;
780 case STB: case STH: case STW:
781 break;
810260a8 782 }
810260a8 783
b18d5d2b
RH		 784 /* For unaligned, or very large offsets, use the indexed form. */
785 if (offset & align || offset != (int32_t)offset) {
786 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, orig);
787 tcg_out32(s, opx | TAB(rt, base, TCG_REG_R2));
788 return;
789 }
790
791 l0 = (int16_t)offset;
792 offset = (offset - l0) >> 16;
793 l1 = (int16_t)offset;
794
795 if (l1 < 0 && orig >= 0) {
796 extra = 0x4000;
797 l1 = (int16_t)(offset - 0x4000);
798 }
799 if (l1) {
800 tcg_out32(s, ADDIS | TAI(rs, base, l1));
801 base = rs;
802 }
803 if (extra) {
804 tcg_out32(s, ADDIS | TAI(rs, base, extra));
805 base = rs;
806 }
807 if (opi != ADDI || base != rt || l0 != 0) {
808 tcg_out32(s, opi | TAI(rt, base, l0));
828808f5 809 }
810}
811
a0585573
RH		 812static const uint32_t qemu_ldx_opc[16] = {
813 [MO_UB] = LBZX,
814 [MO_UW] = LHZX,
815 [MO_UL] = LWZX,
816 [MO_Q] = LDX,
817 [MO_SW] = LHAX,
818 [MO_SL] = LWAX,
819 [MO_BSWAP | MO_UB] = LBZX,
820 [MO_BSWAP | MO_UW] = LHBRX,
821 [MO_BSWAP | MO_UL] = LWBRX,
822 [MO_BSWAP | MO_Q] = LDBRX,
7f12d649
RH		 823};
824
a0585573
RH		 825static const uint32_t qemu_stx_opc[16] = {
826 [MO_UB] = STBX,
827 [MO_UW] = STHX,
828 [MO_UL] = STWX,
829 [MO_Q] = STDX,
830 [MO_BSWAP | MO_UB] = STBX,
831 [MO_BSWAP | MO_UW] = STHBRX,
832 [MO_BSWAP | MO_UL] = STWBRX,
833 [MO_BSWAP | MO_Q] = STDBRX,
7f12d649
RH		 834};
835
836static const uint32_t qemu_exts_opc[4] = {
837 EXTSB, EXTSH, EXTSW, 0
838};
839
840#if defined (CONFIG_SOFTMMU)
e141ab52 841/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
7f12d649
RH		 842 * int mmu_idx, uintptr_t ra)
843 */
e349a8d4
RH		 844static const void * const qemu_ld_helpers[16] = {
845 [MO_UB] = helper_ret_ldub_mmu,
846 [MO_LEUW] = helper_le_lduw_mmu,
847 [MO_LEUL] = helper_le_ldul_mmu,
848 [MO_LEQ] = helper_le_ldq_mmu,
849 [MO_BEUW] = helper_be_lduw_mmu,
850 [MO_BEUL] = helper_be_ldul_mmu,
851 [MO_BEQ] = helper_be_ldq_mmu,
e141ab52
BS		 852};
853
854/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
7f12d649
RH		 855 * uintxx_t val, int mmu_idx, uintptr_t ra)
856 */
e349a8d4
RH		 857static const void * const qemu_st_helpers[16] = {
858 [MO_UB] = helper_ret_stb_mmu,
859 [MO_LEUW] = helper_le_stw_mmu,
860 [MO_LEUL] = helper_le_stl_mmu,
861 [MO_LEQ] = helper_le_stq_mmu,
862 [MO_BEUW] = helper_be_stw_mmu,
863 [MO_BEUL] = helper_be_stl_mmu,
864 [MO_BEQ] = helper_be_stq_mmu,
e141ab52 865};
810260a8 866
fedee3e7
RH		 867/* Perform the TLB load and compare. Places the result of the comparison
868 in CR7, loads the addend of the TLB into R3, and returns the register
869 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
870
a0585573 871static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, TCGReg addr_reg,
fedee3e7 872 int mem_index, bool is_read)
810260a8 873{
fedee3e7
RH		 874 int cmp_off
875 = (is_read
876 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
877 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
878 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
879 TCGReg base = TCG_AREG0;
880
881 /* Extract the page index, shifted into place for tlb index. */
882 if (TARGET_LONG_BITS == 32) {
883 /* Zero-extend the address into a place helpful for further use. */
884 tcg_out_ext32u(s, TCG_REG_R4, addr_reg);
885 addr_reg = TCG_REG_R4;
886 } else {
887 tcg_out_rld(s, RLDICL, TCG_REG_R3, addr_reg,
888 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
889 }
810260a8 890
fedee3e7
RH		 891 /* Compensate for very large offsets. */
892 if (add_off >= 0x8000) {
893 /* Most target env are smaller than 32k; none are larger than 64k.
894 Simplify the logic here merely to offset by 0x7ff0, giving us a
895 range just shy of 64k. Check this assumption. */
896 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
897 tlb_table[NB_MMU_MODES - 1][1])
898 > 0x7ff0 + 0x7fff);
899 tcg_out32(s, ADDI | TAI(TCG_REG_R2, base, 0x7ff0));
900 base = TCG_REG_R2;
901 cmp_off -= 0x7ff0;
902 add_off -= 0x7ff0;
903 }
810260a8 904
fedee3e7
RH		 905 /* Extraction and shifting, part 2. */
906 if (TARGET_LONG_BITS == 32) {
907 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addr_reg,
908 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
909 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
910 31 - CPU_TLB_ENTRY_BITS);
541dd4ce 911 } else {
fedee3e7 912 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
4a40e231 913 }
fedee3e7
RH		 914
915 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
916
917 /* Load the tlb comparator. */
918 tcg_out32(s, LD_ADDR | TAI(TCG_REG_R2, TCG_REG_R3, cmp_off));
919
920 /* Load the TLB addend for use on the fast path. Do this asap
921 to minimize any load use delay. */
922 tcg_out32(s, LD | TAI(TCG_REG_R3, TCG_REG_R3, add_off));
923
924 /* Clear the non-page, non-alignment bits from the address. */
925 if (TARGET_LONG_BITS == 32) {
926 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr_reg, 0,
927 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
928 } else if (!s_bits) {
929 tcg_out_rld(s, RLDICR, TCG_REG_R0, addr_reg, 0, 63 - TARGET_PAGE_BITS);
930 } else {
931 tcg_out_rld(s, RLDICL, TCG_REG_R0, addr_reg,
932 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
933 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
934 }
935
936 tcg_out32(s, CMP | BF(7) | RA(TCG_REG_R0) | RB(TCG_REG_R2) | CMP_L);
937
938 return addr_reg;
810260a8 939}
940
7f12d649
RH		 941/* Record the context of a call to the out of line helper code for the slow
942 path for a load or store, so that we can later generate the correct
943 helper code. */
a0585573 944static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,
7f12d649
RH		 945 int data_reg, int addr_reg, int mem_index,
946 uint8_t *raddr, uint8_t *label_ptr)
947{
9ecefc84 948 TCGLabelQemuLdst *label = new_ldst_label(s);
49d9870a 949
7f12d649
RH		 950 label->is_ld = is_ld;
951 label->opc = opc;
952 label->datalo_reg = data_reg;
953 label->addrlo_reg = addr_reg;
954 label->mem_index = mem_index;
955 label->raddr = raddr;
956 label->label_ptr[0] = label_ptr;
957}
958
959static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
960{
e349a8d4 961 TCGMemOp opc = lb->opc;
7f12d649
RH		 962
963 reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
964
965 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0);
966
967 /* If the address needed to be zero-extended, we'll have already
968 placed it in R4. The only remaining case is 64-bit guest. */
969 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
970
971 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, lb->mem_index);
972 tcg_out32(s, MFSPR | RT(TCG_REG_R6) | LR);
973
e349a8d4 974 tcg_out_call(s, (tcg_target_long)qemu_ld_helpers[opc & ~MO_SIGN], 1);
7f12d649 975
a0585573 976 if (opc & MO_SIGN) {
e349a8d4 977 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
7f12d649
RH		 978 tcg_out32(s, insn | RA(lb->datalo_reg) | RS(TCG_REG_R3));
979 } else {
980 tcg_out_mov(s, TCG_TYPE_I64, lb->datalo_reg, TCG_REG_R3);
981 }
982
983 tcg_out_b(s, 0, (uintptr_t)lb->raddr);
984}
985
986static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
987{
e349a8d4
RH		 988 TCGMemOp opc = lb->opc;
989 TCGMemOp s_bits = opc & MO_SIZE;
7f12d649
RH		 990
991 reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
992
993 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, TCG_AREG0);
994
995 /* If the address needed to be zero-extended, we'll have already
996 placed it in R4. The only remaining case is 64-bit guest. */
997 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
998
999 tcg_out_rld(s, RLDICL, TCG_REG_R5, lb->datalo_reg,
a0585573 1000 0, 64 - (1 << (3 + s_bits)));
7f12d649
RH		 1001 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R6, lb->mem_index);
1002 tcg_out32(s, MFSPR | RT(TCG_REG_R7) | LR);
1003
e349a8d4 1004 tcg_out_call(s, (tcg_target_long)qemu_st_helpers[opc], 1);
7f12d649
RH		 1005
1006 tcg_out_b(s, 0, (uintptr_t)lb->raddr);
1007}
7f12d649 1008#endif /* SOFTMMU */
49d9870a 1009
a0585573 1010static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
810260a8 1011{
fedee3e7 1012 TCGReg addr_reg, data_reg, rbase;
a0585573
RH		 1013 uint32_t insn;
1014 TCGMemOp s_bits = opc & MO_SIZE;
810260a8 1015#ifdef CONFIG_SOFTMMU
49d9870a 1016 int mem_index;
7f12d649 1017 void *label_ptr;
810260a8 1018#endif
1019
1020 data_reg = *args++;
1021 addr_reg = *args++;
9df3b45d
DG		 1022
1023#ifdef CONFIG_SOFTMMU
810260a8 1024 mem_index = *args;
810260a8 1025
fedee3e7 1026 addr_reg = tcg_out_tlb_read(s, s_bits, addr_reg, mem_index, true);
810260a8 1027
7f12d649
RH		 1028 /* Load a pointer into the current opcode w/conditional branch-link. */
1029 label_ptr = s->code_ptr;
1030 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
810260a8 1031
fedee3e7 1032 rbase = TCG_REG_R3;
810260a8 1033#else /* !CONFIG_SOFTMMU */
f6548c0a 1034 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
fedee3e7
RH		 1035 if (TARGET_LONG_BITS == 32) {
1036 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1037 addr_reg = TCG_REG_R2;
1038 }
810260a8 1039#endif
1040
49d9870a
RH		 1041 insn = qemu_ldx_opc[opc];
1042 if (!HAVE_ISA_2_06 && insn == LDBRX) {
fedee3e7
RH		 1043 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addr_reg, 4));
1044 tcg_out32(s, LWBRX | TAB(data_reg, rbase, addr_reg));
1045 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1046 tcg_out_rld(s, RLDIMI, data_reg, TCG_REG_R0, 32, 0);
49d9870a 1047 } else if (insn) {
fedee3e7 1048 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
49d9870a 1049 } else {
a0585573 1050 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
fedee3e7 1051 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
49d9870a 1052 insn = qemu_exts_opc[s_bits];
541dd4ce 1053 tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
810260a8 1054 }
1055
1056#ifdef CONFIG_SOFTMMU
7f12d649
RH		 1057 add_qemu_ldst_label(s, true, opc, data_reg, addr_reg, mem_index,
1058 s->code_ptr, label_ptr);
810260a8 1059#endif
1060}
1061
a0585573 1062static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
810260a8 1063{
fedee3e7 1064 TCGReg addr_reg, rbase, data_reg;
49d9870a 1065 uint32_t insn;
810260a8 1066#ifdef CONFIG_SOFTMMU
aceac8d6 1067 int mem_index;
7f12d649 1068 void *label_ptr;
810260a8 1069#endif
1070
1071 data_reg = *args++;
1072 addr_reg = *args++;
810260a8 1073
1074#ifdef CONFIG_SOFTMMU
9df3b45d
DG		 1075 mem_index = *args;
1076
a0585573 1077 addr_reg = tcg_out_tlb_read(s, opc & MO_SIZE, addr_reg, mem_index, false);
810260a8 1078
7f12d649
RH		 1079 /* Load a pointer into the current opcode w/conditional branch-link. */
1080 label_ptr = s->code_ptr;
1081 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
810260a8 1082
fedee3e7 1083 rbase = TCG_REG_R3;
810260a8 1084#else /* !CONFIG_SOFTMMU */
f6548c0a 1085 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
fedee3e7
RH		 1086 if (TARGET_LONG_BITS == 32) {
1087 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1088 addr_reg = TCG_REG_R2;
1089 }
810260a8 1090#endif
1091
49d9870a
RH		 1092 insn = qemu_stx_opc[opc];
1093 if (!HAVE_ISA_2_06 && insn == STDBRX) {
fedee3e7
RH		 1094 tcg_out32(s, STWBRX | SAB(data_reg, rbase, addr_reg));
1095 tcg_out32(s, ADDI | TAI(TCG_REG_R2, addr_reg, 4));
8327a470 1096 tcg_out_shri64(s, TCG_REG_R0, data_reg, 32);
fedee3e7 1097 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_R2));
49d9870a 1098 } else {
fedee3e7 1099 tcg_out32(s, insn | SAB(data_reg, rbase, addr_reg));
810260a8 1100 }
1101
1102#ifdef CONFIG_SOFTMMU
7f12d649
RH		 1103 add_qemu_ldst_label(s, false, opc, data_reg, addr_reg, mem_index,
1104 s->code_ptr, label_ptr);
810260a8 1105#endif
1106}
1107
fa94c3be
RH		 1108#define FRAME_SIZE ((int) \
1109 ((8 /* back chain */ \
1110 + 8 /* CR */ \
1111 + 8 /* LR */ \
1112 + 8 /* compiler doubleword */ \
1113 + 8 /* link editor doubleword */ \
1114 + 8 /* TOC save area */ \
1115 + TCG_STATIC_CALL_ARGS_SIZE \
1116 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
1117 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8 \
1118 + 15) & ~15))
1119
1120#define REG_SAVE_BOT (FRAME_SIZE - ARRAY_SIZE(tcg_target_callee_save_regs) * 8)
1121
541dd4ce 1122static void tcg_target_qemu_prologue(TCGContext *s)
810260a8 1123{
fa94c3be
RH		 1124 int i;
1125
1126 tcg_set_frame(s, TCG_REG_CALL_STACK,
1127 REG_SAVE_BOT - CPU_TEMP_BUF_NLONGS * sizeof(long),
541dd4ce 1128 CPU_TEMP_BUF_NLONGS * sizeof(long));
136a0b5a 1129
5d7ff5bb 1130#ifndef __APPLE__
a69abbe0 1131 /* First emit adhoc function descriptor */
5e0f40cf 1132 tcg_out64(s, (uint64_t)s->code_ptr + 24); /* entry point */
a69abbe0 1133 s->code_ptr += 16; /* skip TOC and environment pointer */
5d7ff5bb 1134#endif
a69abbe0 1135
1136 /* Prologue */
8327a470 1137 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
fa94c3be 1138 tcg_out32(s, STDU | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
29b69198
RH		 1139 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1140 tcg_out32(s, STD | SAI(tcg_target_callee_save_regs[i], 1,
fa94c3be 1141 REG_SAVE_BOT + i * 8));
29b69198 1142 }
fa94c3be 1143 tcg_out32(s, STD | SAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
810260a8 1144
f6548c0a 1145#ifdef CONFIG_USE_GUEST_BASE
b9e946c7 1146 if (GUEST_BASE) {
541dd4ce
RH		 1147 tcg_out_movi(s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
1148 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
b9e946c7 1149 }
f6548c0a 1150#endif
1151
541dd4ce
RH		 1152 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1153 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1154 tcg_out32(s, BCCTR | BO_ALWAYS);
a69abbe0 1155
1156 /* Epilogue */
810260a8 1157 tb_ret_addr = s->code_ptr;
1158
29b69198 1159 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
8327a470 1160 tcg_out32(s, LD | TAI(tcg_target_callee_save_regs[i], TCG_REG_R1,
fa94c3be 1161 REG_SAVE_BOT + i * 8));
29b69198 1162 }
fa94c3be 1163 tcg_out32(s, LD | TAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
8327a470 1164 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
fa94c3be 1165 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
2fd8eddc 1166 tcg_out32(s, BCLR | BO_ALWAYS);
810260a8 1167}
1168
b18d5d2b
RH		 1169static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1170 TCGReg arg1, intptr_t arg2)
810260a8 1171{
b18d5d2b
RH		 1172 int opi, opx;
1173
541dd4ce 1174 if (type == TCG_TYPE_I32) {
b18d5d2b 1175 opi = LWZ, opx = LWZX;
541dd4ce 1176 } else {
b18d5d2b 1177 opi = LD, opx = LDX;
541dd4ce 1178 }
b18d5d2b 1179 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
810260a8 1180}
1181
b18d5d2b
RH		 1182static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1183 TCGReg arg1, intptr_t arg2)
810260a8 1184{
b18d5d2b
RH		 1185 int opi, opx;
1186
541dd4ce 1187 if (type == TCG_TYPE_I32) {
b18d5d2b 1188 opi = STW, opx = STWX;
541dd4ce 1189 } else {
b18d5d2b 1190 opi = STD, opx = STDX;
541dd4ce 1191 }
b18d5d2b 1192 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
810260a8 1193}
1194
4c314da6
RH		 1195static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1196 int const_arg2, int cr, TCGType type)
810260a8 1197{
1198 int imm;
1199 uint32_t op;
1200
991041a4
RH		 1201 /* Simplify the comparisons below wrt CMPI. */
1202 if (type == TCG_TYPE_I32) {
1203 arg2 = (int32_t)arg2;
1204 }
1205
810260a8 1206 switch (cond) {
1207 case TCG_COND_EQ:
1208 case TCG_COND_NE:
1209 if (const_arg2) {
1210 if ((int16_t) arg2 == arg2) {
1211 op = CMPI;
1212 imm = 1;
1213 break;
541dd4ce 1214 } else if ((uint16_t) arg2 == arg2) {
810260a8 1215 op = CMPLI;
1216 imm = 1;
1217 break;
1218 }
1219 }
1220 op = CMPL;
1221 imm = 0;
1222 break;
1223
1224 case TCG_COND_LT:
1225 case TCG_COND_GE:
1226 case TCG_COND_LE:
1227 case TCG_COND_GT:
1228 if (const_arg2) {
1229 if ((int16_t) arg2 == arg2) {
1230 op = CMPI;
1231 imm = 1;
1232 break;
1233 }
1234 }
1235 op = CMP;
1236 imm = 0;
1237 break;
1238
1239 case TCG_COND_LTU:
1240 case TCG_COND_GEU:
1241 case TCG_COND_LEU:
1242 case TCG_COND_GTU:
1243 if (const_arg2) {
1244 if ((uint16_t) arg2 == arg2) {
1245 op = CMPLI;
1246 imm = 1;
1247 break;
1248 }
1249 }
1250 op = CMPL;
1251 imm = 0;
1252 break;
1253
1254 default:
541dd4ce 1255 tcg_abort();
810260a8 1256 }
4c314da6 1257 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
810260a8 1258
4c314da6
RH		 1259 if (imm) {
1260 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1261 } else {
810260a8 1262 if (const_arg2) {
8327a470
RH		 1263 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1264 arg2 = TCG_REG_R0;
810260a8 1265 }
4c314da6 1266 tcg_out32(s, op | RA(arg1) | RB(arg2));
810260a8 1267 }
810260a8 1268}
1269
70fac59a
RH		 1270static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1271 TCGReg dst, TCGReg src)
1cd62ae9 1272{
70fac59a
RH		 1273 tcg_out32(s, (type == TCG_TYPE_I64 ? CNTLZD : CNTLZW) | RS(src) | RA(dst));
1274 tcg_out_shri64(s, dst, dst, type == TCG_TYPE_I64 ? 6 : 5);
1275}
1cd62ae9 1276
70fac59a
RH		 1277static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
1278{
1279 /* X != 0 implies X + -1 generates a carry. Extra addition
1280 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1281 if (dst != src) {
1282 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1283 tcg_out32(s, SUBFE | TAB(dst, dst, src));
1284 } else {
8327a470
RH		 1285 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1286 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
70fac59a
RH		 1287 }
1288}
1cd62ae9 1289
70fac59a
RH		 1290static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1291 bool const_arg2)
1292{
1293 if (const_arg2) {
1294 if ((uint32_t)arg2 == arg2) {
1295 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1296 } else {
1297 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1298 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1cd62ae9 1299 }
70fac59a
RH		 1300 } else {
1301 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1302 }
1303 return TCG_REG_R0;
1304}
1cd62ae9 1305
70fac59a
RH		 1306static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1307 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1308 int const_arg2)
1309{
1310 int crop, sh;
1311
1312 /* Ignore high bits of a potential constant arg2. */
1313 if (type == TCG_TYPE_I32) {
1314 arg2 = (uint32_t)arg2;
1315 }
1316
1317 /* Handle common and trivial cases before handling anything else. */
1318 if (arg2 == 0) {
1319 switch (cond) {
1320 case TCG_COND_EQ:
1321 tcg_out_setcond_eq0(s, type, arg0, arg1);
1322 return;
1323 case TCG_COND_NE:
1324 if (type == TCG_TYPE_I32) {
1325 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1326 arg1 = TCG_REG_R0;
1cd62ae9 1327 }
70fac59a
RH		 1328 tcg_out_setcond_ne0(s, arg0, arg1);
1329 return;
1330 case TCG_COND_GE:
1331 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1332 arg1 = arg0;
1333 /* FALLTHRU */
1334 case TCG_COND_LT:
1335 /* Extract the sign bit. */
1336 tcg_out_rld(s, RLDICL, arg0, arg1,
1337 type == TCG_TYPE_I64 ? 1 : 33, 63);
1338 return;
1339 default:
1340 break;
1cd62ae9 1341 }
70fac59a 1342 }
1cd62ae9 1343
70fac59a
RH		 1344 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1345 All other cases below are also at least 3 insns, so speed up the
1346 code generator by not considering them and always using ISEL. */
1347 if (HAVE_ISEL) {
1348 int isel, tab;
752c1fdb 1349
70fac59a
RH		 1350 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1351
1352 isel = tcg_to_isel[cond];
1353
1354 tcg_out_movi(s, type, arg0, 1);
1355 if (isel & 1) {
1356 /* arg0 = (bc ? 0 : 1) */
1357 tab = TAB(arg0, 0, arg0);
1358 isel &= ~1;
1359 } else {
1360 /* arg0 = (bc ? 1 : 0) */
1361 tcg_out_movi(s, type, TCG_REG_R0, 0);
1362 tab = TAB(arg0, arg0, TCG_REG_R0);
1cd62ae9 1363 }
70fac59a
RH		 1364 tcg_out32(s, isel | tab);
1365 return;
1366 }
1367
1368 switch (cond) {
1369 case TCG_COND_EQ:
1370 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1371 tcg_out_setcond_eq0(s, type, arg0, arg1);
1372 return;
1373
1374 case TCG_COND_NE:
1375 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1376 /* Discard the high bits only once, rather than both inputs. */
1377 if (type == TCG_TYPE_I32) {
1378 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1379 arg1 = TCG_REG_R0;
1cd62ae9 1380 }
70fac59a
RH		 1381 tcg_out_setcond_ne0(s, arg0, arg1);
1382 return;
1cd62ae9 1383
1384 case TCG_COND_GT:
1385 case TCG_COND_GTU:
1386 sh = 30;
1387 crop = 0;
1388 goto crtest;
1389
1390 case TCG_COND_LT:
1391 case TCG_COND_LTU:
1392 sh = 29;
1393 crop = 0;
1394 goto crtest;
1395
1396 case TCG_COND_GE:
1397 case TCG_COND_GEU:
1398 sh = 31;
541dd4ce 1399 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1cd62ae9 1400 goto crtest;
1401
1402 case TCG_COND_LE:
1403 case TCG_COND_LEU:
1404 sh = 31;
541dd4ce 1405 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1cd62ae9 1406 crtest:
6995a4a0
RH		 1407 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1408 if (crop) {
1409 tcg_out32(s, crop);
1410 }
1411 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1412 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1cd62ae9 1413 break;
1414
1415 default:
541dd4ce 1416 tcg_abort();
1cd62ae9 1417 }
1418}
1419
541dd4ce 1420static void tcg_out_bc(TCGContext *s, int bc, int label_index)
810260a8 1421{
1422 TCGLabel *l = &s->labels[label_index];
1423
541dd4ce
RH		 1424 if (l->has_value) {
1425 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value));
1426 } else {
c7ca6a2b
RH		 1427 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, label_index, 0);
1428 tcg_out_bc_noaddr(s, bc);
810260a8 1429 }
1430}
1431
4c314da6
RH		 1432static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1433 TCGArg arg1, TCGArg arg2, int const_arg2,
1434 int label_index, TCGType type)
810260a8 1435{
4c314da6
RH		 1436 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1437 tcg_out_bc(s, tcg_to_bc[cond], label_index);
810260a8 1438}
1439
027ffea9
RH		 1440static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1441 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1442 TCGArg v2, bool const_c2)
1443{
1444 /* If for some reason both inputs are zero, don't produce bad code. */
1445 if (v1 == 0 && v2 == 0) {
1446 tcg_out_movi(s, type, dest, 0);
1447 return;
1448 }
1449
1450 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1451
1452 if (HAVE_ISEL) {
1453 int isel = tcg_to_isel[cond];
1454
1455 /* Swap the V operands if the operation indicates inversion. */
1456 if (isel & 1) {
1457 int t = v1;
1458 v1 = v2;
1459 v2 = t;
1460 isel &= ~1;
1461 }
1462 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1463 if (v2 == 0) {
8327a470 1464 tcg_out_movi(s, type, TCG_REG_R0, 0);
027ffea9
RH		 1465 }
1466 tcg_out32(s, isel | TAB(dest, v1, v2));
1467 } else {
1468 if (dest == v2) {
1469 cond = tcg_invert_cond(cond);
1470 v2 = v1;
1471 } else if (dest != v1) {
1472 if (v1 == 0) {
1473 tcg_out_movi(s, type, dest, 0);
1474 } else {
1475 tcg_out_mov(s, type, dest, v1);
1476 }
1477 }
1478 /* Branch forward over one insn */
1479 tcg_out32(s, tcg_to_bc[cond] | 8);
1480 if (v2 == 0) {
1481 tcg_out_movi(s, type, dest, 0);
1482 } else {
1483 tcg_out_mov(s, type, dest, v2);
1484 }
1485 }
1486}
1487
541dd4ce 1488void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr)
810260a8 1489{
1490 TCGContext s;
1491 unsigned long patch_size;
1492
1493 s.code_ptr = (uint8_t *) jmp_addr;
541dd4ce 1494 tcg_out_b(&s, 0, addr);
810260a8 1495 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
541dd4ce 1496 flush_icache_range(jmp_addr, jmp_addr + patch_size);
810260a8 1497}
1498
541dd4ce
RH		 1499static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1500 const int *const_args)
810260a8 1501{
ee924fa6 1502 TCGArg a0, a1, a2;
e46b9681 1503 int c;
1504
810260a8 1505 switch (opc) {
1506 case INDEX_op_exit_tb:
541dd4ce
RH		 1507 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1508 tcg_out_b(s, 0, (tcg_target_long)tb_ret_addr);
810260a8 1509 break;
1510 case INDEX_op_goto_tb:
1511 if (s->tb_jmp_offset) {
541dd4ce 1512 /* Direct jump method. */
810260a8 1513 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
5424fd10 1514 s->code_ptr += 28;
541dd4ce
RH		 1515 } else {
1516 /* Indirect jump method. */
1517 tcg_abort();
810260a8 1518 }
1519 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1520 break;
1521 case INDEX_op_br:
1522 {
1523 TCGLabel *l = &s->labels[args[0]];
1524
1525 if (l->has_value) {
541dd4ce
RH		 1526 tcg_out_b(s, 0, l->u.value);
1527 } else {
c7ca6a2b
RH		 1528 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, args[0], 0);
1529 tcg_out_b_noaddr(s, B);
810260a8 1530 }
1531 }
1532 break;
1533 case INDEX_op_call:
541dd4ce 1534 tcg_out_call(s, args[0], const_args[0]);
810260a8 1535 break;
810260a8 1536 case INDEX_op_movi_i32:
541dd4ce 1537 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
810260a8 1538 break;
1539 case INDEX_op_movi_i64:
541dd4ce 1540 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
810260a8 1541 break;
1542 case INDEX_op_ld8u_i32:
1543 case INDEX_op_ld8u_i64:
b18d5d2b 1544 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
810260a8 1545 break;
1546 case INDEX_op_ld8s_i32:
1547 case INDEX_op_ld8s_i64:
b18d5d2b 1548 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
541dd4ce 1549 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
810260a8 1550 break;
1551 case INDEX_op_ld16u_i32:
1552 case INDEX_op_ld16u_i64:
b18d5d2b 1553 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
810260a8 1554 break;
1555 case INDEX_op_ld16s_i32:
1556 case INDEX_op_ld16s_i64:
b18d5d2b 1557 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
810260a8 1558 break;
1559 case INDEX_op_ld_i32:
1560 case INDEX_op_ld32u_i64:
b18d5d2b 1561 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
810260a8 1562 break;
1563 case INDEX_op_ld32s_i64:
b18d5d2b 1564 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
810260a8 1565 break;
1566 case INDEX_op_ld_i64:
b18d5d2b 1567 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
810260a8 1568 break;
1569 case INDEX_op_st8_i32:
1570 case INDEX_op_st8_i64:
b18d5d2b 1571 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
810260a8 1572 break;
1573 case INDEX_op_st16_i32:
1574 case INDEX_op_st16_i64:
b18d5d2b 1575 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
810260a8 1576 break;
1577 case INDEX_op_st_i32:
1578 case INDEX_op_st32_i64:
b18d5d2b 1579 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
810260a8 1580 break;
1581 case INDEX_op_st_i64:
b18d5d2b 1582 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
810260a8 1583 break;
1584
1585 case INDEX_op_add_i32:
ee924fa6
RH		 1586 a0 = args[0], a1 = args[1], a2 = args[2];
1587 if (const_args[2]) {
ee924fa6 1588 do_addi_32:
b18d5d2b 1589 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
ee924fa6
RH		 1590 } else {
1591 tcg_out32(s, ADD | TAB(a0, a1, a2));
1592 }
810260a8 1593 break;
1594 case INDEX_op_sub_i32:
ee924fa6 1595 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 1596 if (const_args[1]) {
1597 if (const_args[2]) {
1598 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1599 } else {
1600 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1601 }
1602 } else if (const_args[2]) {
ee924fa6
RH		 1603 a2 = -a2;
1604 goto do_addi_32;
1605 } else {
1606 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1607 }
810260a8 1608 break;
1609
1610 case INDEX_op_and_i32:
37251b98 1611 a0 = args[0], a1 = args[1], a2 = args[2];
a9249dff 1612 if (const_args[2]) {
37251b98 1613 tcg_out_andi32(s, a0, a1, a2);
a9249dff 1614 } else {
37251b98 1615 tcg_out32(s, AND | SAB(a1, a0, a2));
a9249dff
RH		 1616 }
1617 break;
1618 case INDEX_op_and_i64:
37251b98 1619 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1620 if (const_args[2]) {
37251b98 1621 tcg_out_andi64(s, a0, a1, a2);
637af30c 1622 } else {
37251b98 1623 tcg_out32(s, AND | SAB(a1, a0, a2));
810260a8 1624 }
810260a8 1625 break;
fe6f943f 1626 case INDEX_op_or_i64:
810260a8 1627 case INDEX_op_or_i32:
dce74c57 1628 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1629 if (const_args[2]) {
dce74c57
RH		 1630 tcg_out_ori32(s, a0, a1, a2);
1631 } else {
1632 tcg_out32(s, OR | SAB(a1, a0, a2));
810260a8 1633 }
810260a8 1634 break;
fe6f943f 1635 case INDEX_op_xor_i64:
810260a8 1636 case INDEX_op_xor_i32:
dce74c57 1637 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1638 if (const_args[2]) {
dce74c57
RH		 1639 tcg_out_xori32(s, a0, a1, a2);
1640 } else {
1641 tcg_out32(s, XOR | SAB(a1, a0, a2));
810260a8 1642 }
810260a8 1643 break;
ce1010d6 1644 case INDEX_op_andc_i32:
37251b98
RH		 1645 a0 = args[0], a1 = args[1], a2 = args[2];
1646 if (const_args[2]) {
1647 tcg_out_andi32(s, a0, a1, ~a2);
1648 } else {
1649 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1650 }
1651 break;
ce1010d6 1652 case INDEX_op_andc_i64:
37251b98
RH		 1653 a0 = args[0], a1 = args[1], a2 = args[2];
1654 if (const_args[2]) {
1655 tcg_out_andi64(s, a0, a1, ~a2);
1656 } else {
1657 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1658 }
ce1010d6
RH		 1659 break;
1660 case INDEX_op_orc_i32:
37251b98
RH		 1661 if (const_args[2]) {
1662 tcg_out_ori32(s, args[0], args[1], ~args[2]);
1663 break;
1664 }
1665 /* FALLTHRU */
ce1010d6
RH		 1666 case INDEX_op_orc_i64:
1667 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
1668 break;
1669 case INDEX_op_eqv_i32:
37251b98
RH		 1670 if (const_args[2]) {
1671 tcg_out_xori32(s, args[0], args[1], ~args[2]);
1672 break;
1673 }
1674 /* FALLTHRU */
ce1010d6
RH		 1675 case INDEX_op_eqv_i64:
1676 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
1677 break;
1678 case INDEX_op_nand_i32:
1679 case INDEX_op_nand_i64:
1680 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
1681 break;
1682 case INDEX_op_nor_i32:
1683 case INDEX_op_nor_i64:
1684 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
1685 break;
810260a8 1686
1687 case INDEX_op_mul_i32:
ef809300 1688 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 1689 if (const_args[2]) {
ef809300
RH		 1690 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1691 } else {
1692 tcg_out32(s, MULLW | TAB(a0, a1, a2));
810260a8 1693 }
810260a8 1694 break;
1695
1696 case INDEX_op_div_i32:
541dd4ce 1697 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
810260a8 1698 break;
1699
1700 case INDEX_op_divu_i32:
541dd4ce 1701 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
810260a8 1702 break;
1703
810260a8 1704 case INDEX_op_shl_i32:
1705 if (const_args[2]) {
9e555b73
RH		 1706 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
1707 } else {
541dd4ce 1708 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
9e555b73 1709 }
810260a8 1710 break;
1711 case INDEX_op_shr_i32:
1712 if (const_args[2]) {
9e555b73
RH		 1713 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], args[2], 31);
1714 } else {
541dd4ce 1715 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
9e555b73 1716 }
810260a8 1717 break;
1718 case INDEX_op_sar_i32:
541dd4ce
RH		 1719 if (const_args[2]) {
1720 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
1721 } else {
1722 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
1723 }
810260a8 1724 break;
313d91c7
RH		 1725 case INDEX_op_rotl_i32:
1726 if (const_args[2]) {
1727 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
1728 } else {
1729 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
1730 | MB(0) | ME(31));
1731 }
1732 break;
1733 case INDEX_op_rotr_i32:
1734 if (const_args[2]) {
1735 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
1736 } else {
8327a470
RH		 1737 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
1738 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
313d91c7
RH		 1739 | MB(0) | ME(31));
1740 }
1741 break;
810260a8 1742
1743 case INDEX_op_brcond_i32:
4c314da6
RH		 1744 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1745 args[3], TCG_TYPE_I32);
e924bbec 1746 break;
1747
810260a8 1748 case INDEX_op_brcond_i64:
4c314da6
RH		 1749 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1750 args[3], TCG_TYPE_I64);
810260a8 1751 break;
1752
1753 case INDEX_op_neg_i32:
810260a8 1754 case INDEX_op_neg_i64:
541dd4ce 1755 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
810260a8 1756 break;
1757
157f2662 1758 case INDEX_op_not_i32:
1759 case INDEX_op_not_i64:
541dd4ce 1760 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
157f2662 1761 break;
1762
810260a8 1763 case INDEX_op_add_i64:
ee924fa6
RH		 1764 a0 = args[0], a1 = args[1], a2 = args[2];
1765 if (const_args[2]) {
ee924fa6 1766 do_addi_64:
b18d5d2b 1767 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
ee924fa6
RH		 1768 } else {
1769 tcg_out32(s, ADD | TAB(a0, a1, a2));
1770 }
810260a8 1771 break;
1772 case INDEX_op_sub_i64:
ee924fa6 1773 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 1774 if (const_args[1]) {
1775 if (const_args[2]) {
1776 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
1777 } else {
1778 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1779 }
1780 } else if (const_args[2]) {
ee924fa6
RH		 1781 a2 = -a2;
1782 goto do_addi_64;
1783 } else {
1784 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1785 }
810260a8 1786 break;
1787
1788 case INDEX_op_shl_i64:
541dd4ce 1789 if (const_args[2]) {
0a9564b9 1790 tcg_out_shli64(s, args[0], args[1], args[2]);
541dd4ce
RH		 1791 } else {
1792 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
1793 }
810260a8 1794 break;
1795 case INDEX_op_shr_i64:
541dd4ce 1796 if (const_args[2]) {
5e916c28 1797 tcg_out_shri64(s, args[0], args[1], args[2]);
541dd4ce
RH		 1798 } else {
1799 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
1800 }
810260a8 1801 break;
1802 case INDEX_op_sar_i64:
fe6f943f 1803 if (const_args[2]) {
541dd4ce
RH		 1804 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1805 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
1806 } else {
1807 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
fe6f943f 1808 }
810260a8 1809 break;
313d91c7
RH		 1810 case INDEX_op_rotl_i64:
1811 if (const_args[2]) {
1812 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
1813 } else {
1814 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
1815 }
1816 break;
1817 case INDEX_op_rotr_i64:
1818 if (const_args[2]) {
1819 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
1820 } else {
8327a470
RH		 1821 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
1822 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
313d91c7
RH		 1823 }
1824 break;
810260a8 1825
1826 case INDEX_op_mul_i64:
ef809300
RH		 1827 a0 = args[0], a1 = args[1], a2 = args[2];
1828 if (const_args[2]) {
1829 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1830 } else {
1831 tcg_out32(s, MULLD | TAB(a0, a1, a2));
1832 }
810260a8 1833 break;
1834 case INDEX_op_div_i64:
541dd4ce 1835 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
810260a8 1836 break;
1837 case INDEX_op_divu_i64:
541dd4ce 1838 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
810260a8 1839 break;
810260a8 1840
1841 case INDEX_op_qemu_ld8u:
a0585573 1842 tcg_out_qemu_ld(s, args, MO_UB);
810260a8 1843 break;
1844 case INDEX_op_qemu_ld8s:
a0585573 1845 tcg_out_qemu_ld(s, args, MO_SB);
810260a8 1846 break;
1847 case INDEX_op_qemu_ld16u:
a0585573 1848 tcg_out_qemu_ld(s, args, MO_TEUW);
810260a8 1849 break;
1850 case INDEX_op_qemu_ld16s:
a0585573 1851 tcg_out_qemu_ld(s, args, MO_TESW);
810260a8 1852 break;
86feb1c8 1853 case INDEX_op_qemu_ld32:
810260a8 1854 case INDEX_op_qemu_ld32u:
a0585573 1855 tcg_out_qemu_ld(s, args, MO_TEUL);
810260a8 1856 break;
1857 case INDEX_op_qemu_ld32s:
a0585573 1858 tcg_out_qemu_ld(s, args, MO_TESL);
810260a8 1859 break;
1860 case INDEX_op_qemu_ld64:
a0585573 1861 tcg_out_qemu_ld(s, args, MO_TEQ);
810260a8 1862 break;
1863 case INDEX_op_qemu_st8:
a0585573 1864 tcg_out_qemu_st(s, args, MO_UB);
810260a8 1865 break;
1866 case INDEX_op_qemu_st16:
a0585573 1867 tcg_out_qemu_st(s, args, MO_TEUW);
810260a8 1868 break;
1869 case INDEX_op_qemu_st32:
a0585573 1870 tcg_out_qemu_st(s, args, MO_TEUL);
810260a8 1871 break;
1872 case INDEX_op_qemu_st64:
a0585573 1873 tcg_out_qemu_st(s, args, MO_TEQ);
810260a8 1874 break;
1875
e46b9681 1876 case INDEX_op_ext8s_i32:
1877 case INDEX_op_ext8s_i64:
1878 c = EXTSB;
1879 goto gen_ext;
1880 case INDEX_op_ext16s_i32:
1881 case INDEX_op_ext16s_i64:
1882 c = EXTSH;
1883 goto gen_ext;
1884 case INDEX_op_ext32s_i64:
1885 c = EXTSW;
1886 goto gen_ext;
1887 gen_ext:
541dd4ce 1888 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
e46b9681 1889 break;
1890
1cd62ae9 1891 case INDEX_op_setcond_i32:
541dd4ce
RH		 1892 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1893 const_args[2]);
1cd62ae9 1894 break;
1895 case INDEX_op_setcond_i64:
541dd4ce
RH		 1896 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1897 const_args[2]);
1cd62ae9 1898 break;
1899
5d221582
RH		 1900 case INDEX_op_bswap16_i32:
1901 case INDEX_op_bswap16_i64:
1902 a0 = args[0], a1 = args[1];
1903 /* a1 = abcd */
1904 if (a0 != a1) {
1905 /* a0 = (a1 r<< 24) & 0xff # 000c */
1906 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1907 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
1908 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
1909 } else {
1910 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
1911 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
1912 /* a0 = (a1 r<< 24) & 0xff # 000c */
1913 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1914 /* a0 = a0 | r0 # 00dc */
1915 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
1916 }
1917 break;
1918
1919 case INDEX_op_bswap32_i32:
1920 case INDEX_op_bswap32_i64:
1921 /* Stolen from gcc's builtin_bswap32 */
1922 a1 = args[1];
1923 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
1924
1925 /* a1 = args[1] # abcd */
1926 /* a0 = rotate_left (a1, 8) # bcda */
1927 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1928 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
1929 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1930 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
1931 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1932
1933 if (a0 == TCG_REG_R0) {
1934 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
1935 }
1936 break;
1937
68aebd45 1938 case INDEX_op_bswap64_i64:
8327a470 1939 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
68aebd45 1940 if (a0 == a1) {
8327a470 1941 a0 = TCG_REG_R0;
68aebd45
RH		 1942 a2 = a1;
1943 }
1944
1945 /* a1 = # abcd efgh */
1946 /* a0 = rl32(a1, 8) # 0000 fghe */
1947 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1948 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
1949 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1950 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
1951 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1952
1953 /* a0 = rl64(a0, 32) # hgfe 0000 */
1954 /* a2 = rl64(a1, 32) # efgh abcd */
1955 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
1956 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
1957
1958 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
1959 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
1960 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
1961 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
1962 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
1963 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
1964
1965 if (a0 == 0) {
1966 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
68aebd45
RH		 1967 }
1968 break;
1969
33de9ed2 1970 case INDEX_op_deposit_i32:
39dc85b9
RH		 1971 if (const_args[2]) {
1972 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
1973 tcg_out_andi32(s, args[0], args[0], ~mask);
1974 } else {
1975 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
1976 32 - args[3] - args[4], 31 - args[3]);
1977 }
33de9ed2
RH		 1978 break;
1979 case INDEX_op_deposit_i64:
39dc85b9
RH		 1980 if (const_args[2]) {
1981 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
1982 tcg_out_andi64(s, args[0], args[0], ~mask);
1983 } else {
1984 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
1985 64 - args[3] - args[4]);
1986 }
33de9ed2
RH		 1987 break;
1988
027ffea9
RH		 1989 case INDEX_op_movcond_i32:
1990 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
1991 args[3], args[4], const_args[2]);
1992 break;
1993 case INDEX_op_movcond_i64:
1994 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
1995 args[3], args[4], const_args[2]);
1996 break;
1997
6c858762
RH		 1998 case INDEX_op_add2_i64:
1999 /* Note that the CA bit is defined based on the word size of the
2000 environment. So in 64-bit mode it's always carry-out of bit 63.
2001 The fallback code using deposit works just as well for 32-bit. */
2002 a0 = args[0], a1 = args[1];
84247357 2003 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
6c858762
RH		 2004 a0 = TCG_REG_R0;
2005 }
84247357
AB		 2006 if (const_args[4]) {
2007 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
6c858762 2008 } else {
84247357 2009 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
6c858762
RH		 2010 }
2011 if (const_args[5]) {
84247357 2012 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
6c858762 2013 } else {
84247357 2014 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
6c858762
RH		 2015 }
2016 if (a0 != args[0]) {
2017 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
2018 }
2019 break;
2020
2021 case INDEX_op_sub2_i64:
2022 a0 = args[0], a1 = args[1];
2023 if (a0 == args[5] || (!const_args[4] && a0 == args[4])) {
2024 a0 = TCG_REG_R0;
2025 }
2026 if (const_args[2]) {
2027 tcg_out32(s, SUBFIC | TAI(a0, args[3], args[2]));
2028 } else {
2029 tcg_out32(s, SUBFC | TAB(a0, args[3], args[2]));
2030 }
2031 if (const_args[4]) {
2032 tcg_out32(s, (args[4] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
2033 } else {
2034 tcg_out32(s, SUBFE | TAB(a1, args[5], args[4]));
2035 }
2036 if (a0 != args[0]) {
2037 tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
2038 }
2039 break;
2040
32f5717f
RH		 2041 case INDEX_op_muluh_i64:
2042 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2043 break;
2044 case INDEX_op_mulsh_i64:
2045 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
6645c147
RH		 2046 break;
2047
810260a8 2048 default:
541dd4ce
RH		 2049 tcg_dump_ops(s);
2050 tcg_abort();
810260a8 2051 }
2052}
2053
2054static const TCGTargetOpDef ppc_op_defs[] = {
2055 { INDEX_op_exit_tb, { } },
2056 { INDEX_op_goto_tb, { } },
2057 { INDEX_op_call, { "ri" } },
810260a8 2058 { INDEX_op_br, { } },
2059
2060 { INDEX_op_mov_i32, { "r", "r" } },
2061 { INDEX_op_mov_i64, { "r", "r" } },
2062 { INDEX_op_movi_i32, { "r" } },
2063 { INDEX_op_movi_i64, { "r" } },
2064
2065 { INDEX_op_ld8u_i32, { "r", "r" } },
2066 { INDEX_op_ld8s_i32, { "r", "r" } },
2067 { INDEX_op_ld16u_i32, { "r", "r" } },
2068 { INDEX_op_ld16s_i32, { "r", "r" } },
2069 { INDEX_op_ld_i32, { "r", "r" } },
2070 { INDEX_op_ld_i64, { "r", "r" } },
2071 { INDEX_op_st8_i32, { "r", "r" } },
2072 { INDEX_op_st8_i64, { "r", "r" } },
2073 { INDEX_op_st16_i32, { "r", "r" } },
2074 { INDEX_op_st16_i64, { "r", "r" } },
2075 { INDEX_op_st_i32, { "r", "r" } },
2076 { INDEX_op_st_i64, { "r", "r" } },
2077 { INDEX_op_st32_i64, { "r", "r" } },
2078
2079 { INDEX_op_ld8u_i64, { "r", "r" } },
2080 { INDEX_op_ld8s_i64, { "r", "r" } },
2081 { INDEX_op_ld16u_i64, { "r", "r" } },
2082 { INDEX_op_ld16s_i64, { "r", "r" } },
2083 { INDEX_op_ld32u_i64, { "r", "r" } },
2084 { INDEX_op_ld32s_i64, { "r", "r" } },
810260a8 2085
2086 { INDEX_op_add_i32, { "r", "r", "ri" } },
ef809300 2087 { INDEX_op_mul_i32, { "r", "r", "rI" } },
810260a8 2088 { INDEX_op_div_i32, { "r", "r", "r" } },
2089 { INDEX_op_divu_i32, { "r", "r", "r" } },
148bdd23 2090 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
810260a8 2091 { INDEX_op_and_i32, { "r", "r", "ri" } },
2092 { INDEX_op_or_i32, { "r", "r", "ri" } },
2093 { INDEX_op_xor_i32, { "r", "r", "ri" } },
37251b98
RH		 2094 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2095 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2096 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
ce1010d6
RH		 2097 { INDEX_op_nand_i32, { "r", "r", "r" } },
2098 { INDEX_op_nor_i32, { "r", "r", "r" } },
810260a8 2099
2100 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2101 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2102 { INDEX_op_sar_i32, { "r", "r", "ri" } },
313d91c7
RH		 2103 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2104 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
810260a8 2105
2106 { INDEX_op_brcond_i32, { "r", "ri" } },
2107 { INDEX_op_brcond_i64, { "r", "ri" } },
2108
2109 { INDEX_op_neg_i32, { "r", "r" } },
157f2662 2110 { INDEX_op_not_i32, { "r", "r" } },
810260a8 2111
ee924fa6 2112 { INDEX_op_add_i64, { "r", "r", "rT" } },
148bdd23 2113 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
37251b98 2114 { INDEX_op_and_i64, { "r", "r", "ri" } },
3d582c61
RH		 2115 { INDEX_op_or_i64, { "r", "r", "rU" } },
2116 { INDEX_op_xor_i64, { "r", "r", "rU" } },
37251b98 2117 { INDEX_op_andc_i64, { "r", "r", "ri" } },
ce1010d6
RH		 2118 { INDEX_op_orc_i64, { "r", "r", "r" } },
2119 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2120 { INDEX_op_nand_i64, { "r", "r", "r" } },
2121 { INDEX_op_nor_i64, { "r", "r", "r" } },
810260a8 2122
fe6f943f 2123 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2124 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2125 { INDEX_op_sar_i64, { "r", "r", "ri" } },
313d91c7
RH		 2126 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2127 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
810260a8 2128
ef809300 2129 { INDEX_op_mul_i64, { "r", "r", "rI" } },
810260a8 2130 { INDEX_op_div_i64, { "r", "r", "r" } },
2131 { INDEX_op_divu_i64, { "r", "r", "r" } },
810260a8 2132
2133 { INDEX_op_neg_i64, { "r", "r" } },
157f2662 2134 { INDEX_op_not_i64, { "r", "r" } },
810260a8 2135
2136 { INDEX_op_qemu_ld8u, { "r", "L" } },
2137 { INDEX_op_qemu_ld8s, { "r", "L" } },
2138 { INDEX_op_qemu_ld16u, { "r", "L" } },
2139 { INDEX_op_qemu_ld16s, { "r", "L" } },
86feb1c8 2140 { INDEX_op_qemu_ld32, { "r", "L" } },
810260a8 2141 { INDEX_op_qemu_ld32u, { "r", "L" } },
2142 { INDEX_op_qemu_ld32s, { "r", "L" } },
b01d9fea 2143 { INDEX_op_qemu_ld64, { "r", "L" } },
810260a8 2144
c070355d 2145 { INDEX_op_qemu_st8, { "S", "S" } },
2146 { INDEX_op_qemu_st16, { "S", "S" } },
2147 { INDEX_op_qemu_st32, { "S", "S" } },
016b2b28 2148 { INDEX_op_qemu_st64, { "S", "S" } },
810260a8 2149
e46b9681 2150 { INDEX_op_ext8s_i32, { "r", "r" } },
2151 { INDEX_op_ext16s_i32, { "r", "r" } },
2152 { INDEX_op_ext8s_i64, { "r", "r" } },
2153 { INDEX_op_ext16s_i64, { "r", "r" } },
2154 { INDEX_op_ext32s_i64, { "r", "r" } },
2155
1cd62ae9 2156 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2157 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
027ffea9
RH		 2158 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2159 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
1cd62ae9 2160
5d221582
RH		 2161 { INDEX_op_bswap16_i32, { "r", "r" } },
2162 { INDEX_op_bswap16_i64, { "r", "r" } },
2163 { INDEX_op_bswap32_i32, { "r", "r" } },
2164 { INDEX_op_bswap32_i64, { "r", "r" } },
68aebd45 2165 { INDEX_op_bswap64_i64, { "r", "r" } },
5d221582 2166
39dc85b9
RH		 2167 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2168 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
33de9ed2 2169
84247357 2170 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
6c858762 2171 { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
32f5717f
RH		 2172 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2173 { INDEX_op_muluh_i64, { "r", "r", "r" } },
6c858762 2174
810260a8 2175 { -1 },
2176};
2177
541dd4ce 2178static void tcg_target_init(TCGContext *s)
810260a8 2179{
1e6e9aca
RH		 2180#ifdef CONFIG_GETAUXVAL
2181 unsigned long hwcap = getauxval(AT_HWCAP);
2182 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2183 have_isa_2_06 = true;
2184 }
2185#endif
2186
541dd4ce
RH		 2187 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2188 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2189 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
810260a8 2190 (1 << TCG_REG_R0) |
5d7ff5bb 2191 (1 << TCG_REG_R2) |
810260a8 2192 (1 << TCG_REG_R3) |
2193 (1 << TCG_REG_R4) |
2194 (1 << TCG_REG_R5) |
2195 (1 << TCG_REG_R6) |
2196 (1 << TCG_REG_R7) |
2197 (1 << TCG_REG_R8) |
2198 (1 << TCG_REG_R9) |
2199 (1 << TCG_REG_R10) |
2200 (1 << TCG_REG_R11) |
5e1702b0 2201 (1 << TCG_REG_R12));
810260a8 2202
541dd4ce 2203 tcg_regset_clear(s->reserved_regs);
5e1702b0
RH		 2204 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2205 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
b18d5d2b 2206 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* mem temp */
5e1702b0
RH		 2207#ifdef __APPLE__
2208 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R11); /* ??? */
5d7ff5bb 2209#endif
5e1702b0 2210 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
810260a8 2211
541dd4ce 2212 tcg_add_target_add_op_defs(ppc_op_defs);
810260a8 2213}
fa94c3be
RH		 2214
2215typedef struct {
2216 DebugFrameCIE cie;
2217 DebugFrameFDEHeader fde;
2218 uint8_t fde_def_cfa[4];
2219 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2220} DebugFrame;
2221
2222/* We're expecting a 2 byte uleb128 encoded value. */
2223QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2224
2225#define ELF_HOST_MACHINE EM_PPC64
2226
2227static DebugFrame debug_frame = {
2228 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2229 .cie.id = -1,
2230 .cie.version = 1,
2231 .cie.code_align = 1,
2232 .cie.data_align = 0x78, /* sleb128 -8 */
2233 .cie.return_column = 65,
2234
2235 /* Total FDE size does not include the "len" member. */
2236 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2237
2238 .fde_def_cfa = {
2239 12, 1, /* DW_CFA_def_cfa r1, ... */
2240 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2241 (FRAME_SIZE >> 7)
2242 },
2243 .fde_reg_ofs = {
2244 0x11, 65, 0x7e, /* DW_CFA_offset_extended_sf, lr, 16 */
2245 }
2246};
2247
2248void tcg_register_jit(void *buf, size_t buf_size)
2249{
2250 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2251 int i;
2252
2253 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2254 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2255 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * 8)) / 8;
2256 }
2257
2258 debug_frame.fde.func_start = (tcg_target_long) buf;
2259 debug_frame.fde.func_len = buf_size;
2260
2261 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2262}
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