]>
Commit | Line | Data |
---|---|---|
810260a8 | 1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
9ecefc84 RH |
25 | #include "tcg-be-ldst.h" |
26 | ||
ffcfbece RH |
27 | #if defined _CALL_DARWIN || defined __APPLE__ |
28 | #define TCG_TARGET_CALL_DARWIN | |
29 | #endif | |
7f25c469 RH |
30 | #ifdef _CALL_SYSV |
31 | # define TCG_TARGET_CALL_ALIGN_ARGS 1 | |
32 | #endif | |
ffcfbece | 33 | |
dfca1778 RH |
34 | /* For some memory operations, we need a scratch that isn't R0. For the AIX |
35 | calling convention, we can re-use the TOC register since we'll be reloading | |
36 | it at every call. Otherwise R12 will do nicely as neither a call-saved | |
37 | register nor a parameter register. */ | |
38 | #ifdef _CALL_AIX | |
39 | # define TCG_REG_TMP1 TCG_REG_R2 | |
40 | #else | |
41 | # define TCG_REG_TMP1 TCG_REG_R12 | |
42 | #endif | |
43 | ||
de3d636d RH |
44 | /* Shorthand for size of a pointer. Avoid promotion to unsigned. */ |
45 | #define SZP ((int)sizeof(void *)) | |
46 | ||
4c3831a0 RH |
47 | /* Shorthand for size of a register. */ |
48 | #define SZR (TCG_TARGET_REG_BITS / 8) | |
49 | ||
3d582c61 RH |
50 | #define TCG_CT_CONST_S16 0x100 |
51 | #define TCG_CT_CONST_U16 0x200 | |
52 | #define TCG_CT_CONST_S32 0x400 | |
53 | #define TCG_CT_CONST_U32 0x800 | |
54 | #define TCG_CT_CONST_ZERO 0x1000 | |
6c858762 | 55 | #define TCG_CT_CONST_MONE 0x2000 |
fe6f943f | 56 | |
e083c4a2 | 57 | static tcg_insn_unit *tb_ret_addr; |
810260a8 | 58 | |
f6548c0a | 59 | #ifndef GUEST_BASE |
60 | #define GUEST_BASE 0 | |
61 | #endif | |
62 | ||
cd629de1 | 63 | #include "elf.h" |
1e6e9aca RH |
64 | static bool have_isa_2_06; |
65 | #define HAVE_ISA_2_06 have_isa_2_06 | |
66 | #define HAVE_ISEL have_isa_2_06 | |
49d9870a | 67 | |
f6548c0a | 68 | #ifdef CONFIG_USE_GUEST_BASE |
69 | #define TCG_GUEST_BASE_REG 30 | |
70 | #else | |
71 | #define TCG_GUEST_BASE_REG 0 | |
72 | #endif | |
73 | ||
d4a9eb1f | 74 | #ifndef NDEBUG |
810260a8 | 75 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
76 | "r0", | |
77 | "r1", | |
98926b0a | 78 | "r2", |
810260a8 | 79 | "r3", |
80 | "r4", | |
81 | "r5", | |
82 | "r6", | |
83 | "r7", | |
84 | "r8", | |
85 | "r9", | |
86 | "r10", | |
87 | "r11", | |
88 | "r12", | |
89 | "r13", | |
90 | "r14", | |
91 | "r15", | |
92 | "r16", | |
93 | "r17", | |
94 | "r18", | |
95 | "r19", | |
96 | "r20", | |
97 | "r21", | |
98 | "r22", | |
99 | "r23", | |
100 | "r24", | |
101 | "r25", | |
102 | "r26", | |
103 | "r27", | |
104 | "r28", | |
105 | "r29", | |
106 | "r30", | |
107 | "r31" | |
108 | }; | |
d4a9eb1f | 109 | #endif |
810260a8 | 110 | |
111 | static const int tcg_target_reg_alloc_order[] = { | |
5e1702b0 | 112 | TCG_REG_R14, /* call saved registers */ |
810260a8 | 113 | TCG_REG_R15, |
114 | TCG_REG_R16, | |
115 | TCG_REG_R17, | |
116 | TCG_REG_R18, | |
117 | TCG_REG_R19, | |
118 | TCG_REG_R20, | |
119 | TCG_REG_R21, | |
120 | TCG_REG_R22, | |
121 | TCG_REG_R23, | |
5e1702b0 RH |
122 | TCG_REG_R24, |
123 | TCG_REG_R25, | |
124 | TCG_REG_R26, | |
125 | TCG_REG_R27, | |
810260a8 | 126 | TCG_REG_R28, |
127 | TCG_REG_R29, | |
128 | TCG_REG_R30, | |
129 | TCG_REG_R31, | |
5e1702b0 RH |
130 | TCG_REG_R12, /* call clobbered, non-arguments */ |
131 | TCG_REG_R11, | |
dfca1778 RH |
132 | TCG_REG_R2, |
133 | TCG_REG_R13, | |
5e1702b0 | 134 | TCG_REG_R10, /* call clobbered, arguments */ |
810260a8 | 135 | TCG_REG_R9, |
5e1702b0 RH |
136 | TCG_REG_R8, |
137 | TCG_REG_R7, | |
138 | TCG_REG_R6, | |
139 | TCG_REG_R5, | |
140 | TCG_REG_R4, | |
141 | TCG_REG_R3, | |
810260a8 | 142 | }; |
143 | ||
144 | static const int tcg_target_call_iarg_regs[] = { | |
145 | TCG_REG_R3, | |
146 | TCG_REG_R4, | |
147 | TCG_REG_R5, | |
148 | TCG_REG_R6, | |
149 | TCG_REG_R7, | |
150 | TCG_REG_R8, | |
151 | TCG_REG_R9, | |
152 | TCG_REG_R10 | |
153 | }; | |
154 | ||
be9c4183 | 155 | static const int tcg_target_call_oarg_regs[] = { |
dfca1778 RH |
156 | TCG_REG_R3, |
157 | TCG_REG_R4 | |
810260a8 | 158 | }; |
159 | ||
160 | static const int tcg_target_callee_save_regs[] = { | |
dfca1778 | 161 | #ifdef TCG_TARGET_CALL_DARWIN |
5d7ff5bb AF |
162 | TCG_REG_R11, |
163 | #endif | |
810260a8 | 164 | TCG_REG_R14, |
165 | TCG_REG_R15, | |
166 | TCG_REG_R16, | |
167 | TCG_REG_R17, | |
168 | TCG_REG_R18, | |
169 | TCG_REG_R19, | |
170 | TCG_REG_R20, | |
171 | TCG_REG_R21, | |
172 | TCG_REG_R22, | |
173 | TCG_REG_R23, | |
095271d4 | 174 | TCG_REG_R24, |
175 | TCG_REG_R25, | |
176 | TCG_REG_R26, | |
cea5f9a2 | 177 | TCG_REG_R27, /* currently used for the global env */ |
810260a8 | 178 | TCG_REG_R28, |
179 | TCG_REG_R29, | |
180 | TCG_REG_R30, | |
181 | TCG_REG_R31 | |
182 | }; | |
183 | ||
b0940da0 RH |
184 | static inline bool in_range_b(tcg_target_long target) |
185 | { | |
186 | return target == sextract64(target, 0, 26); | |
187 | } | |
188 | ||
e083c4a2 | 189 | static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) |
810260a8 | 190 | { |
e083c4a2 | 191 | ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); |
b0940da0 | 192 | assert(in_range_b(disp)); |
810260a8 | 193 | return disp & 0x3fffffc; |
194 | } | |
195 | ||
e083c4a2 | 196 | static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) |
810260a8 | 197 | { |
e083c4a2 | 198 | *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target); |
810260a8 | 199 | } |
200 | ||
e083c4a2 | 201 | static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) |
810260a8 | 202 | { |
e083c4a2 RH |
203 | ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); |
204 | assert(disp == (int16_t) disp); | |
810260a8 | 205 | return disp & 0xfffc; |
206 | } | |
207 | ||
e083c4a2 | 208 | static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target) |
810260a8 | 209 | { |
e083c4a2 | 210 | *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target); |
810260a8 | 211 | } |
212 | ||
c7ca6a2b RH |
213 | static inline void tcg_out_b_noaddr(TCGContext *s, int insn) |
214 | { | |
e083c4a2 | 215 | unsigned retrans = *s->code_ptr & 0x3fffffc; |
c7ca6a2b RH |
216 | tcg_out32(s, insn | retrans); |
217 | } | |
218 | ||
219 | static inline void tcg_out_bc_noaddr(TCGContext *s, int insn) | |
220 | { | |
e083c4a2 | 221 | unsigned retrans = *s->code_ptr & 0xfffc; |
c7ca6a2b RH |
222 | tcg_out32(s, insn | retrans); |
223 | } | |
224 | ||
e083c4a2 | 225 | static void patch_reloc(tcg_insn_unit *code_ptr, int type, |
541dd4ce | 226 | intptr_t value, intptr_t addend) |
810260a8 | 227 | { |
e083c4a2 RH |
228 | tcg_insn_unit *target = (tcg_insn_unit *)value; |
229 | ||
230 | assert(addend == 0); | |
810260a8 | 231 | switch (type) { |
232 | case R_PPC_REL14: | |
e083c4a2 | 233 | reloc_pc14(code_ptr, target); |
810260a8 | 234 | break; |
235 | case R_PPC_REL24: | |
e083c4a2 | 236 | reloc_pc24(code_ptr, target); |
810260a8 | 237 | break; |
238 | default: | |
541dd4ce | 239 | tcg_abort(); |
810260a8 | 240 | } |
241 | } | |
242 | ||
810260a8 | 243 | /* parse target specific constraints */ |
541dd4ce | 244 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
810260a8 | 245 | { |
246 | const char *ct_str; | |
247 | ||
248 | ct_str = *pct_str; | |
249 | switch (ct_str[0]) { | |
250 | case 'A': case 'B': case 'C': case 'D': | |
251 | ct->ct |= TCG_CT_REG; | |
541dd4ce | 252 | tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A'); |
810260a8 | 253 | break; |
254 | case 'r': | |
255 | ct->ct |= TCG_CT_REG; | |
541dd4ce | 256 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
810260a8 | 257 | break; |
258 | case 'L': /* qemu_ld constraint */ | |
259 | ct->ct |= TCG_CT_REG; | |
541dd4ce RH |
260 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
261 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); | |
735ee40d | 262 | #ifdef CONFIG_SOFTMMU |
541dd4ce RH |
263 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); |
264 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); | |
735ee40d | 265 | #endif |
810260a8 | 266 | break; |
c070355d | 267 | case 'S': /* qemu_st constraint */ |
810260a8 | 268 | ct->ct |= TCG_CT_REG; |
541dd4ce RH |
269 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
270 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); | |
735ee40d | 271 | #ifdef CONFIG_SOFTMMU |
541dd4ce RH |
272 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); |
273 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); | |
274 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); | |
735ee40d | 275 | #endif |
810260a8 | 276 | break; |
3d582c61 RH |
277 | case 'I': |
278 | ct->ct |= TCG_CT_CONST_S16; | |
279 | break; | |
280 | case 'J': | |
281 | ct->ct |= TCG_CT_CONST_U16; | |
282 | break; | |
6c858762 RH |
283 | case 'M': |
284 | ct->ct |= TCG_CT_CONST_MONE; | |
285 | break; | |
3d582c61 RH |
286 | case 'T': |
287 | ct->ct |= TCG_CT_CONST_S32; | |
288 | break; | |
289 | case 'U': | |
fe6f943f | 290 | ct->ct |= TCG_CT_CONST_U32; |
291 | break; | |
3d582c61 RH |
292 | case 'Z': |
293 | ct->ct |= TCG_CT_CONST_ZERO; | |
294 | break; | |
810260a8 | 295 | default: |
296 | return -1; | |
297 | } | |
298 | ct_str++; | |
299 | *pct_str = ct_str; | |
300 | return 0; | |
301 | } | |
302 | ||
303 | /* test if a constant matches the constraint */ | |
f6c6afc1 | 304 | static int tcg_target_const_match(tcg_target_long val, TCGType type, |
541dd4ce | 305 | const TCGArgConstraint *arg_ct) |
810260a8 | 306 | { |
3d582c61 RH |
307 | int ct = arg_ct->ct; |
308 | if (ct & TCG_CT_CONST) { | |
309 | return 1; | |
1194dcba RH |
310 | } |
311 | ||
312 | /* The only 32-bit constraint we use aside from | |
313 | TCG_CT_CONST is TCG_CT_CONST_S16. */ | |
314 | if (type == TCG_TYPE_I32) { | |
315 | val = (int32_t)val; | |
316 | } | |
317 | ||
318 | if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { | |
3d582c61 RH |
319 | return 1; |
320 | } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { | |
810260a8 | 321 | return 1; |
3d582c61 | 322 | } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { |
fe6f943f | 323 | return 1; |
3d582c61 RH |
324 | } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { |
325 | return 1; | |
326 | } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { | |
327 | return 1; | |
6c858762 RH |
328 | } else if ((ct & TCG_CT_CONST_MONE) && val == -1) { |
329 | return 1; | |
3d582c61 | 330 | } |
810260a8 | 331 | return 0; |
332 | } | |
333 | ||
334 | #define OPCD(opc) ((opc)<<26) | |
335 | #define XO19(opc) (OPCD(19)|((opc)<<1)) | |
8a94cfb0 AB |
336 | #define MD30(opc) (OPCD(30)|((opc)<<2)) |
337 | #define MDS30(opc) (OPCD(30)|((opc)<<1)) | |
810260a8 | 338 | #define XO31(opc) (OPCD(31)|((opc)<<1)) |
339 | #define XO58(opc) (OPCD(58)|(opc)) | |
340 | #define XO62(opc) (OPCD(62)|(opc)) | |
341 | ||
342 | #define B OPCD( 18) | |
343 | #define BC OPCD( 16) | |
344 | #define LBZ OPCD( 34) | |
345 | #define LHZ OPCD( 40) | |
346 | #define LHA OPCD( 42) | |
347 | #define LWZ OPCD( 32) | |
348 | #define STB OPCD( 38) | |
349 | #define STH OPCD( 44) | |
350 | #define STW OPCD( 36) | |
351 | ||
352 | #define STD XO62( 0) | |
353 | #define STDU XO62( 1) | |
354 | #define STDX XO31(149) | |
355 | ||
356 | #define LD XO58( 0) | |
357 | #define LDX XO31( 21) | |
358 | #define LDU XO58( 1) | |
301f6d90 | 359 | #define LWA XO58( 2) |
810260a8 | 360 | #define LWAX XO31(341) |
361 | ||
1cd62ae9 | 362 | #define ADDIC OPCD( 12) |
810260a8 | 363 | #define ADDI OPCD( 14) |
364 | #define ADDIS OPCD( 15) | |
365 | #define ORI OPCD( 24) | |
366 | #define ORIS OPCD( 25) | |
367 | #define XORI OPCD( 26) | |
368 | #define XORIS OPCD( 27) | |
369 | #define ANDI OPCD( 28) | |
370 | #define ANDIS OPCD( 29) | |
371 | #define MULLI OPCD( 7) | |
372 | #define CMPLI OPCD( 10) | |
373 | #define CMPI OPCD( 11) | |
148bdd23 | 374 | #define SUBFIC OPCD( 8) |
810260a8 | 375 | |
376 | #define LWZU OPCD( 33) | |
377 | #define STWU OPCD( 37) | |
378 | ||
313d91c7 | 379 | #define RLWIMI OPCD( 20) |
810260a8 | 380 | #define RLWINM OPCD( 21) |
313d91c7 | 381 | #define RLWNM OPCD( 23) |
810260a8 | 382 | |
8a94cfb0 AB |
383 | #define RLDICL MD30( 0) |
384 | #define RLDICR MD30( 1) | |
385 | #define RLDIMI MD30( 3) | |
386 | #define RLDCL MDS30( 8) | |
810260a8 | 387 | |
388 | #define BCLR XO19( 16) | |
389 | #define BCCTR XO19(528) | |
390 | #define CRAND XO19(257) | |
391 | #define CRANDC XO19(129) | |
392 | #define CRNAND XO19(225) | |
393 | #define CROR XO19(449) | |
1cd62ae9 | 394 | #define CRNOR XO19( 33) |
810260a8 | 395 | |
396 | #define EXTSB XO31(954) | |
397 | #define EXTSH XO31(922) | |
398 | #define EXTSW XO31(986) | |
399 | #define ADD XO31(266) | |
400 | #define ADDE XO31(138) | |
6c858762 RH |
401 | #define ADDME XO31(234) |
402 | #define ADDZE XO31(202) | |
810260a8 | 403 | #define ADDC XO31( 10) |
404 | #define AND XO31( 28) | |
405 | #define SUBF XO31( 40) | |
406 | #define SUBFC XO31( 8) | |
407 | #define SUBFE XO31(136) | |
6c858762 RH |
408 | #define SUBFME XO31(232) |
409 | #define SUBFZE XO31(200) | |
810260a8 | 410 | #define OR XO31(444) |
411 | #define XOR XO31(316) | |
412 | #define MULLW XO31(235) | |
8fa391a0 | 413 | #define MULHW XO31( 75) |
810260a8 | 414 | #define MULHWU XO31( 11) |
415 | #define DIVW XO31(491) | |
416 | #define DIVWU XO31(459) | |
417 | #define CMP XO31( 0) | |
418 | #define CMPL XO31( 32) | |
419 | #define LHBRX XO31(790) | |
420 | #define LWBRX XO31(534) | |
49d9870a | 421 | #define LDBRX XO31(532) |
810260a8 | 422 | #define STHBRX XO31(918) |
423 | #define STWBRX XO31(662) | |
49d9870a | 424 | #define STDBRX XO31(660) |
810260a8 | 425 | #define MFSPR XO31(339) |
426 | #define MTSPR XO31(467) | |
427 | #define SRAWI XO31(824) | |
428 | #define NEG XO31(104) | |
1cd62ae9 | 429 | #define MFCR XO31( 19) |
6995a4a0 | 430 | #define MFOCRF (MFCR | (1u << 20)) |
157f2662 | 431 | #define NOR XO31(124) |
1cd62ae9 | 432 | #define CNTLZW XO31( 26) |
433 | #define CNTLZD XO31( 58) | |
ce1010d6 RH |
434 | #define ANDC XO31( 60) |
435 | #define ORC XO31(412) | |
436 | #define EQV XO31(284) | |
437 | #define NAND XO31(476) | |
70fac59a | 438 | #define ISEL XO31( 15) |
810260a8 | 439 | |
440 | #define MULLD XO31(233) | |
441 | #define MULHD XO31( 73) | |
442 | #define MULHDU XO31( 9) | |
443 | #define DIVD XO31(489) | |
444 | #define DIVDU XO31(457) | |
445 | ||
446 | #define LBZX XO31( 87) | |
4f4a67ae | 447 | #define LHZX XO31(279) |
810260a8 | 448 | #define LHAX XO31(343) |
449 | #define LWZX XO31( 23) | |
450 | #define STBX XO31(215) | |
451 | #define STHX XO31(407) | |
452 | #define STWX XO31(151) | |
453 | ||
541dd4ce | 454 | #define SPR(a, b) ((((a)<<5)|(b))<<11) |
810260a8 | 455 | #define LR SPR(8, 0) |
456 | #define CTR SPR(9, 0) | |
457 | ||
458 | #define SLW XO31( 24) | |
459 | #define SRW XO31(536) | |
460 | #define SRAW XO31(792) | |
461 | ||
462 | #define SLD XO31( 27) | |
463 | #define SRD XO31(539) | |
464 | #define SRAD XO31(794) | |
fe6f943f | 465 | #define SRADI XO31(413<<1) |
810260a8 | 466 | |
810260a8 | 467 | #define TW XO31( 4) |
541dd4ce | 468 | #define TRAP (TW | TO(31)) |
810260a8 | 469 | |
470 | #define RT(r) ((r)<<21) | |
471 | #define RS(r) ((r)<<21) | |
472 | #define RA(r) ((r)<<16) | |
473 | #define RB(r) ((r)<<11) | |
474 | #define TO(t) ((t)<<21) | |
475 | #define SH(s) ((s)<<11) | |
476 | #define MB(b) ((b)<<6) | |
477 | #define ME(e) ((e)<<1) | |
478 | #define BO(o) ((o)<<21) | |
479 | #define MB64(b) ((b)<<5) | |
6995a4a0 | 480 | #define FXM(b) (1 << (19 - (b))) |
810260a8 | 481 | |
482 | #define LK 1 | |
483 | ||
2fd8eddc RH |
484 | #define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) |
485 | #define SAB(s, a, b) (RS(s) | RA(a) | RB(b)) | |
486 | #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff)) | |
487 | #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff)) | |
810260a8 | 488 | |
489 | #define BF(n) ((n)<<23) | |
490 | #define BI(n, c) (((c)+((n)*4))<<16) | |
491 | #define BT(n, c) (((c)+((n)*4))<<21) | |
492 | #define BA(n, c) (((c)+((n)*4))<<16) | |
493 | #define BB(n, c) (((c)+((n)*4))<<11) | |
70fac59a | 494 | #define BC_(n, c) (((c)+((n)*4))<<6) |
810260a8 | 495 | |
541dd4ce RH |
496 | #define BO_COND_TRUE BO(12) |
497 | #define BO_COND_FALSE BO( 4) | |
498 | #define BO_ALWAYS BO(20) | |
810260a8 | 499 | |
500 | enum { | |
501 | CR_LT, | |
502 | CR_GT, | |
503 | CR_EQ, | |
504 | CR_SO | |
505 | }; | |
506 | ||
0aed257f | 507 | static const uint32_t tcg_to_bc[] = { |
541dd4ce RH |
508 | [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE, |
509 | [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE, | |
510 | [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE, | |
511 | [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE, | |
512 | [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE, | |
513 | [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE, | |
514 | [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE, | |
515 | [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE, | |
516 | [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE, | |
517 | [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE, | |
810260a8 | 518 | }; |
519 | ||
70fac59a RH |
520 | /* The low bit here is set if the RA and RB fields must be inverted. */ |
521 | static const uint32_t tcg_to_isel[] = { | |
522 | [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ), | |
523 | [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1, | |
524 | [TCG_COND_LT] = ISEL | BC_(7, CR_LT), | |
525 | [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1, | |
526 | [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1, | |
527 | [TCG_COND_GT] = ISEL | BC_(7, CR_GT), | |
528 | [TCG_COND_LTU] = ISEL | BC_(7, CR_LT), | |
529 | [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1, | |
530 | [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1, | |
531 | [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), | |
532 | }; | |
533 | ||
796f1a68 | 534 | static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) |
810260a8 | 535 | { |
796f1a68 | 536 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); |
f8b84129 RH |
537 | if (ret != arg) { |
538 | tcg_out32(s, OR | SAB(arg, ret, arg)); | |
539 | } | |
810260a8 | 540 | } |
541 | ||
aceac8d6 RH |
542 | static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, |
543 | int sh, int mb) | |
810260a8 | 544 | { |
a757e1ee | 545 | assert(TCG_TARGET_REG_BITS == 64); |
541dd4ce RH |
546 | sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); |
547 | mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); | |
548 | tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb); | |
810260a8 | 549 | } |
550 | ||
9e555b73 RH |
551 | static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, |
552 | int sh, int mb, int me) | |
553 | { | |
554 | tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); | |
555 | } | |
556 | ||
6e5e0602 RH |
557 | static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) |
558 | { | |
559 | tcg_out_rld(s, RLDICL, dst, src, 0, 32); | |
560 | } | |
561 | ||
a757e1ee RH |
562 | static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) |
563 | { | |
564 | tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); | |
565 | } | |
566 | ||
0a9564b9 RH |
567 | static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) |
568 | { | |
569 | tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); | |
570 | } | |
571 | ||
a757e1ee RH |
572 | static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) |
573 | { | |
574 | tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); | |
575 | } | |
576 | ||
5e916c28 RH |
577 | static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) |
578 | { | |
579 | tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); | |
580 | } | |
581 | ||
aceac8d6 | 582 | static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg) |
810260a8 | 583 | { |
2fd8eddc RH |
584 | if (arg == (int16_t) arg) { |
585 | tcg_out32(s, ADDI | TAI(ret, 0, arg)); | |
586 | } else { | |
587 | tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); | |
588 | if (arg & 0xffff) { | |
589 | tcg_out32(s, ORI | SAI(ret, ret, arg)); | |
590 | } | |
810260a8 | 591 | } |
592 | } | |
593 | ||
421233a1 RH |
594 | static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, |
595 | tcg_target_long arg) | |
810260a8 | 596 | { |
796f1a68 | 597 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); |
421233a1 RH |
598 | if (type == TCG_TYPE_I32 || arg == (int32_t)arg) { |
599 | tcg_out_movi32(s, ret, arg); | |
600 | } else if (arg == (uint32_t)arg && !(arg & 0x8000)) { | |
601 | tcg_out32(s, ADDI | TAI(ret, 0, arg)); | |
602 | tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); | |
603 | } else { | |
796f1a68 | 604 | int32_t high = arg >> 31 >> 1; |
421233a1 RH |
605 | tcg_out_movi32(s, ret, high); |
606 | if (high) { | |
0a9564b9 | 607 | tcg_out_shli64(s, ret, ret, 32); |
421233a1 RH |
608 | } |
609 | if (arg & 0xffff0000) { | |
610 | tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); | |
611 | } | |
612 | if (arg & 0xffff) { | |
613 | tcg_out32(s, ORI | SAI(ret, ret, arg)); | |
810260a8 | 614 | } |
615 | } | |
616 | } | |
617 | ||
637af30c | 618 | static bool mask_operand(uint32_t c, int *mb, int *me) |
a9249dff RH |
619 | { |
620 | uint32_t lsb, test; | |
621 | ||
622 | /* Accept a bit pattern like: | |
623 | 0....01....1 | |
624 | 1....10....0 | |
625 | 0..01..10..0 | |
626 | Keep track of the transitions. */ | |
627 | if (c == 0 || c == -1) { | |
628 | return false; | |
629 | } | |
630 | test = c; | |
631 | lsb = test & -test; | |
632 | test += lsb; | |
633 | if (test & (test - 1)) { | |
634 | return false; | |
635 | } | |
636 | ||
637 | *me = clz32(lsb); | |
638 | *mb = test ? clz32(test & -test) + 1 : 0; | |
639 | return true; | |
640 | } | |
641 | ||
637af30c RH |
642 | static bool mask64_operand(uint64_t c, int *mb, int *me) |
643 | { | |
644 | uint64_t lsb; | |
645 | ||
646 | if (c == 0) { | |
647 | return false; | |
648 | } | |
649 | ||
650 | lsb = c & -c; | |
651 | /* Accept 1..10..0. */ | |
652 | if (c == -lsb) { | |
653 | *mb = 0; | |
654 | *me = clz64(lsb); | |
655 | return true; | |
656 | } | |
657 | /* Accept 0..01..1. */ | |
658 | if (lsb == 1 && (c & (c + 1)) == 0) { | |
659 | *mb = clz64(c + 1) + 1; | |
660 | *me = 63; | |
661 | return true; | |
662 | } | |
663 | return false; | |
664 | } | |
665 | ||
a9249dff RH |
666 | static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) |
667 | { | |
668 | int mb, me; | |
669 | ||
670 | if ((c & 0xffff) == c) { | |
671 | tcg_out32(s, ANDI | SAI(src, dst, c)); | |
672 | return; | |
673 | } else if ((c & 0xffff0000) == c) { | |
674 | tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); | |
675 | return; | |
676 | } else if (mask_operand(c, &mb, &me)) { | |
677 | tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); | |
678 | } else { | |
8327a470 RH |
679 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); |
680 | tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); | |
a9249dff RH |
681 | } |
682 | } | |
683 | ||
637af30c RH |
684 | static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) |
685 | { | |
686 | int mb, me; | |
687 | ||
a757e1ee | 688 | assert(TCG_TARGET_REG_BITS == 64); |
637af30c RH |
689 | if ((c & 0xffff) == c) { |
690 | tcg_out32(s, ANDI | SAI(src, dst, c)); | |
691 | return; | |
692 | } else if ((c & 0xffff0000) == c) { | |
693 | tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); | |
694 | return; | |
695 | } else if (mask64_operand(c, &mb, &me)) { | |
696 | if (mb == 0) { | |
697 | tcg_out_rld(s, RLDICR, dst, src, 0, me); | |
698 | } else { | |
699 | tcg_out_rld(s, RLDICL, dst, src, 0, mb); | |
700 | } | |
701 | } else { | |
8327a470 RH |
702 | tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); |
703 | tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); | |
637af30c RH |
704 | } |
705 | } | |
706 | ||
dce74c57 RH |
707 | static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, |
708 | int op_lo, int op_hi) | |
709 | { | |
710 | if (c >> 16) { | |
711 | tcg_out32(s, op_hi | SAI(src, dst, c >> 16)); | |
712 | src = dst; | |
713 | } | |
714 | if (c & 0xffff) { | |
715 | tcg_out32(s, op_lo | SAI(src, dst, c)); | |
716 | src = dst; | |
717 | } | |
718 | } | |
719 | ||
720 | static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) | |
721 | { | |
722 | tcg_out_zori32(s, dst, src, c, ORI, ORIS); | |
723 | } | |
724 | ||
725 | static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) | |
726 | { | |
727 | tcg_out_zori32(s, dst, src, c, XORI, XORIS); | |
728 | } | |
729 | ||
e083c4a2 | 730 | static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target) |
5d7ff5bb | 731 | { |
e083c4a2 | 732 | ptrdiff_t disp = tcg_pcrel_diff(s, target); |
b0940da0 | 733 | if (in_range_b(disp)) { |
541dd4ce RH |
734 | tcg_out32(s, B | (disp & 0x3fffffc) | mask); |
735 | } else { | |
de3d636d | 736 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target); |
8327a470 | 737 | tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); |
541dd4ce | 738 | tcg_out32(s, BCCTR | BO_ALWAYS | mask); |
5d7ff5bb AF |
739 | } |
740 | } | |
741 | ||
b18d5d2b RH |
742 | static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, |
743 | TCGReg base, tcg_target_long offset) | |
810260a8 | 744 | { |
b18d5d2b | 745 | tcg_target_long orig = offset, l0, l1, extra = 0, align = 0; |
de7761a3 | 746 | bool is_store = false; |
dfca1778 | 747 | TCGReg rs = TCG_REG_TMP1; |
b18d5d2b | 748 | |
b18d5d2b RH |
749 | switch (opi) { |
750 | case LD: case LWA: | |
751 | align = 3; | |
752 | /* FALLTHRU */ | |
753 | default: | |
754 | if (rt != TCG_REG_R0) { | |
755 | rs = rt; | |
de7761a3 | 756 | break; |
b18d5d2b RH |
757 | } |
758 | break; | |
759 | case STD: | |
760 | align = 3; | |
de7761a3 | 761 | /* FALLTHRU */ |
b18d5d2b | 762 | case STB: case STH: case STW: |
de7761a3 | 763 | is_store = true; |
b18d5d2b | 764 | break; |
810260a8 | 765 | } |
810260a8 | 766 | |
b18d5d2b RH |
767 | /* For unaligned, or very large offsets, use the indexed form. */ |
768 | if (offset & align || offset != (int32_t)offset) { | |
de7761a3 RH |
769 | tcg_debug_assert(rs != base && (!is_store || rs != rt)); |
770 | tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); | |
771 | tcg_out32(s, opx | TAB(rt, base, rs)); | |
b18d5d2b RH |
772 | return; |
773 | } | |
774 | ||
775 | l0 = (int16_t)offset; | |
776 | offset = (offset - l0) >> 16; | |
777 | l1 = (int16_t)offset; | |
778 | ||
779 | if (l1 < 0 && orig >= 0) { | |
780 | extra = 0x4000; | |
781 | l1 = (int16_t)(offset - 0x4000); | |
782 | } | |
783 | if (l1) { | |
784 | tcg_out32(s, ADDIS | TAI(rs, base, l1)); | |
785 | base = rs; | |
786 | } | |
787 | if (extra) { | |
788 | tcg_out32(s, ADDIS | TAI(rs, base, extra)); | |
789 | base = rs; | |
790 | } | |
791 | if (opi != ADDI || base != rt || l0 != 0) { | |
792 | tcg_out32(s, opi | TAI(rt, base, l0)); | |
828808f5 | 793 | } |
794 | } | |
795 | ||
d604f1a9 RH |
796 | static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, |
797 | TCGReg arg1, intptr_t arg2) | |
798 | { | |
799 | int opi, opx; | |
810260a8 | 800 | |
a757e1ee | 801 | assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); |
d604f1a9 RH |
802 | if (type == TCG_TYPE_I32) { |
803 | opi = LWZ, opx = LWZX; | |
804 | } else { | |
805 | opi = LD, opx = LDX; | |
806 | } | |
807 | tcg_out_mem_long(s, opi, opx, ret, arg1, arg2); | |
808 | } | |
fedee3e7 | 809 | |
d604f1a9 RH |
810 | static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
811 | TCGReg arg1, intptr_t arg2) | |
810260a8 | 812 | { |
d604f1a9 | 813 | int opi, opx; |
fedee3e7 | 814 | |
a757e1ee | 815 | assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); |
d604f1a9 RH |
816 | if (type == TCG_TYPE_I32) { |
817 | opi = STW, opx = STWX; | |
fedee3e7 | 818 | } else { |
d604f1a9 | 819 | opi = STD, opx = STDX; |
fedee3e7 | 820 | } |
d604f1a9 RH |
821 | tcg_out_mem_long(s, opi, opx, arg, arg1, arg2); |
822 | } | |
810260a8 | 823 | |
d604f1a9 RH |
824 | static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, |
825 | int const_arg2, int cr, TCGType type) | |
826 | { | |
827 | int imm; | |
828 | uint32_t op; | |
810260a8 | 829 | |
abcf61c4 RH |
830 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); |
831 | ||
d604f1a9 RH |
832 | /* Simplify the comparisons below wrt CMPI. */ |
833 | if (type == TCG_TYPE_I32) { | |
834 | arg2 = (int32_t)arg2; | |
4a40e231 | 835 | } |
fedee3e7 | 836 | |
d604f1a9 RH |
837 | switch (cond) { |
838 | case TCG_COND_EQ: | |
839 | case TCG_COND_NE: | |
840 | if (const_arg2) { | |
841 | if ((int16_t) arg2 == arg2) { | |
842 | op = CMPI; | |
843 | imm = 1; | |
844 | break; | |
845 | } else if ((uint16_t) arg2 == arg2) { | |
846 | op = CMPLI; | |
847 | imm = 1; | |
848 | break; | |
849 | } | |
850 | } | |
851 | op = CMPL; | |
852 | imm = 0; | |
853 | break; | |
fedee3e7 | 854 | |
d604f1a9 RH |
855 | case TCG_COND_LT: |
856 | case TCG_COND_GE: | |
857 | case TCG_COND_LE: | |
858 | case TCG_COND_GT: | |
859 | if (const_arg2) { | |
860 | if ((int16_t) arg2 == arg2) { | |
861 | op = CMPI; | |
862 | imm = 1; | |
863 | break; | |
864 | } | |
865 | } | |
866 | op = CMP; | |
867 | imm = 0; | |
868 | break; | |
fedee3e7 | 869 | |
d604f1a9 RH |
870 | case TCG_COND_LTU: |
871 | case TCG_COND_GEU: | |
872 | case TCG_COND_LEU: | |
873 | case TCG_COND_GTU: | |
874 | if (const_arg2) { | |
875 | if ((uint16_t) arg2 == arg2) { | |
876 | op = CMPLI; | |
877 | imm = 1; | |
878 | break; | |
879 | } | |
880 | } | |
881 | op = CMPL; | |
882 | imm = 0; | |
883 | break; | |
fedee3e7 | 884 | |
d604f1a9 RH |
885 | default: |
886 | tcg_abort(); | |
fedee3e7 | 887 | } |
d604f1a9 | 888 | op |= BF(cr) | ((type == TCG_TYPE_I64) << 21); |
fedee3e7 | 889 | |
d604f1a9 RH |
890 | if (imm) { |
891 | tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); | |
892 | } else { | |
893 | if (const_arg2) { | |
894 | tcg_out_movi(s, type, TCG_REG_R0, arg2); | |
895 | arg2 = TCG_REG_R0; | |
896 | } | |
897 | tcg_out32(s, op | RA(arg1) | RB(arg2)); | |
898 | } | |
810260a8 | 899 | } |
900 | ||
d604f1a9 RH |
901 | static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, |
902 | TCGReg dst, TCGReg src) | |
7f12d649 | 903 | { |
a757e1ee RH |
904 | if (type == TCG_TYPE_I32) { |
905 | tcg_out32(s, CNTLZW | RS(src) | RA(dst)); | |
906 | tcg_out_shri32(s, dst, dst, 5); | |
907 | } else { | |
908 | tcg_out32(s, CNTLZD | RS(src) | RA(dst)); | |
909 | tcg_out_shri64(s, dst, dst, 6); | |
910 | } | |
7f12d649 RH |
911 | } |
912 | ||
d604f1a9 | 913 | static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src) |
7f12d649 | 914 | { |
d604f1a9 RH |
915 | /* X != 0 implies X + -1 generates a carry. Extra addition |
916 | trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */ | |
917 | if (dst != src) { | |
918 | tcg_out32(s, ADDIC | TAI(dst, src, -1)); | |
919 | tcg_out32(s, SUBFE | TAB(dst, dst, src)); | |
7f12d649 | 920 | } else { |
d604f1a9 RH |
921 | tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); |
922 | tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); | |
7f12d649 | 923 | } |
d604f1a9 | 924 | } |
7f12d649 | 925 | |
d604f1a9 RH |
926 | static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, |
927 | bool const_arg2) | |
928 | { | |
929 | if (const_arg2) { | |
930 | if ((uint32_t)arg2 == arg2) { | |
931 | tcg_out_xori32(s, TCG_REG_R0, arg1, arg2); | |
932 | } else { | |
933 | tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2); | |
934 | tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0)); | |
935 | } | |
936 | } else { | |
937 | tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2)); | |
938 | } | |
939 | return TCG_REG_R0; | |
7f12d649 RH |
940 | } |
941 | ||
d604f1a9 RH |
942 | static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, |
943 | TCGArg arg0, TCGArg arg1, TCGArg arg2, | |
944 | int const_arg2) | |
7f12d649 | 945 | { |
d604f1a9 | 946 | int crop, sh; |
7f12d649 | 947 | |
a757e1ee RH |
948 | assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); |
949 | ||
d604f1a9 RH |
950 | /* Ignore high bits of a potential constant arg2. */ |
951 | if (type == TCG_TYPE_I32) { | |
952 | arg2 = (uint32_t)arg2; | |
953 | } | |
7f12d649 | 954 | |
d604f1a9 RH |
955 | /* Handle common and trivial cases before handling anything else. */ |
956 | if (arg2 == 0) { | |
957 | switch (cond) { | |
958 | case TCG_COND_EQ: | |
959 | tcg_out_setcond_eq0(s, type, arg0, arg1); | |
960 | return; | |
961 | case TCG_COND_NE: | |
a757e1ee | 962 | if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { |
d604f1a9 RH |
963 | tcg_out_ext32u(s, TCG_REG_R0, arg1); |
964 | arg1 = TCG_REG_R0; | |
965 | } | |
966 | tcg_out_setcond_ne0(s, arg0, arg1); | |
967 | return; | |
968 | case TCG_COND_GE: | |
969 | tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); | |
970 | arg1 = arg0; | |
971 | /* FALLTHRU */ | |
972 | case TCG_COND_LT: | |
973 | /* Extract the sign bit. */ | |
a757e1ee RH |
974 | if (type == TCG_TYPE_I32) { |
975 | tcg_out_shri32(s, arg0, arg1, 31); | |
976 | } else { | |
977 | tcg_out_shri64(s, arg0, arg1, 63); | |
978 | } | |
d604f1a9 RH |
979 | return; |
980 | default: | |
981 | break; | |
982 | } | |
983 | } | |
7f12d649 | 984 | |
d604f1a9 RH |
985 | /* If we have ISEL, we can implement everything with 3 or 4 insns. |
986 | All other cases below are also at least 3 insns, so speed up the | |
987 | code generator by not considering them and always using ISEL. */ | |
988 | if (HAVE_ISEL) { | |
989 | int isel, tab; | |
7f12d649 | 990 | |
d604f1a9 | 991 | tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); |
7f12d649 | 992 | |
d604f1a9 | 993 | isel = tcg_to_isel[cond]; |
7f12d649 | 994 | |
d604f1a9 RH |
995 | tcg_out_movi(s, type, arg0, 1); |
996 | if (isel & 1) { | |
997 | /* arg0 = (bc ? 0 : 1) */ | |
998 | tab = TAB(arg0, 0, arg0); | |
999 | isel &= ~1; | |
1000 | } else { | |
1001 | /* arg0 = (bc ? 1 : 0) */ | |
1002 | tcg_out_movi(s, type, TCG_REG_R0, 0); | |
1003 | tab = TAB(arg0, arg0, TCG_REG_R0); | |
1004 | } | |
1005 | tcg_out32(s, isel | tab); | |
1006 | return; | |
1007 | } | |
49d9870a | 1008 | |
d604f1a9 RH |
1009 | switch (cond) { |
1010 | case TCG_COND_EQ: | |
1011 | arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); | |
1012 | tcg_out_setcond_eq0(s, type, arg0, arg1); | |
1013 | return; | |
810260a8 | 1014 | |
d604f1a9 RH |
1015 | case TCG_COND_NE: |
1016 | arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); | |
1017 | /* Discard the high bits only once, rather than both inputs. */ | |
a757e1ee | 1018 | if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { |
d604f1a9 RH |
1019 | tcg_out_ext32u(s, TCG_REG_R0, arg1); |
1020 | arg1 = TCG_REG_R0; | |
1021 | } | |
1022 | tcg_out_setcond_ne0(s, arg0, arg1); | |
1023 | return; | |
810260a8 | 1024 | |
d604f1a9 RH |
1025 | case TCG_COND_GT: |
1026 | case TCG_COND_GTU: | |
1027 | sh = 30; | |
1028 | crop = 0; | |
1029 | goto crtest; | |
810260a8 | 1030 | |
d604f1a9 RH |
1031 | case TCG_COND_LT: |
1032 | case TCG_COND_LTU: | |
1033 | sh = 29; | |
1034 | crop = 0; | |
1035 | goto crtest; | |
810260a8 | 1036 | |
d604f1a9 RH |
1037 | case TCG_COND_GE: |
1038 | case TCG_COND_GEU: | |
1039 | sh = 31; | |
1040 | crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT); | |
1041 | goto crtest; | |
810260a8 | 1042 | |
d604f1a9 RH |
1043 | case TCG_COND_LE: |
1044 | case TCG_COND_LEU: | |
1045 | sh = 31; | |
1046 | crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT); | |
1047 | crtest: | |
1048 | tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); | |
1049 | if (crop) { | |
1050 | tcg_out32(s, crop); | |
1051 | } | |
1052 | tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); | |
1053 | tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); | |
1054 | break; | |
1055 | ||
1056 | default: | |
1057 | tcg_abort(); | |
1058 | } | |
810260a8 | 1059 | } |
1060 | ||
d604f1a9 | 1061 | static void tcg_out_bc(TCGContext *s, int bc, int label_index) |
810260a8 | 1062 | { |
d604f1a9 | 1063 | TCGLabel *l = &s->labels[label_index]; |
810260a8 | 1064 | |
d604f1a9 RH |
1065 | if (l->has_value) { |
1066 | tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr)); | |
49d9870a | 1067 | } else { |
d604f1a9 RH |
1068 | tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, label_index, 0); |
1069 | tcg_out_bc_noaddr(s, bc); | |
810260a8 | 1070 | } |
810260a8 | 1071 | } |
1072 | ||
d604f1a9 RH |
1073 | static void tcg_out_brcond(TCGContext *s, TCGCond cond, |
1074 | TCGArg arg1, TCGArg arg2, int const_arg2, | |
1075 | int label_index, TCGType type) | |
810260a8 | 1076 | { |
d604f1a9 RH |
1077 | tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); |
1078 | tcg_out_bc(s, tcg_to_bc[cond], label_index); | |
1079 | } | |
fa94c3be | 1080 | |
d604f1a9 RH |
1081 | static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, |
1082 | TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, | |
1083 | TCGArg v2, bool const_c2) | |
1084 | { | |
1085 | /* If for some reason both inputs are zero, don't produce bad code. */ | |
1086 | if (v1 == 0 && v2 == 0) { | |
1087 | tcg_out_movi(s, type, dest, 0); | |
1088 | return; | |
b9e946c7 | 1089 | } |
f6548c0a | 1090 | |
d604f1a9 | 1091 | tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); |
a69abbe0 | 1092 | |
d604f1a9 RH |
1093 | if (HAVE_ISEL) { |
1094 | int isel = tcg_to_isel[cond]; | |
810260a8 | 1095 | |
d604f1a9 RH |
1096 | /* Swap the V operands if the operation indicates inversion. */ |
1097 | if (isel & 1) { | |
1098 | int t = v1; | |
1099 | v1 = v2; | |
1100 | v2 = t; | |
1101 | isel &= ~1; | |
1102 | } | |
1103 | /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ | |
1104 | if (v2 == 0) { | |
1105 | tcg_out_movi(s, type, TCG_REG_R0, 0); | |
1106 | } | |
1107 | tcg_out32(s, isel | TAB(dest, v1, v2)); | |
1108 | } else { | |
1109 | if (dest == v2) { | |
1110 | cond = tcg_invert_cond(cond); | |
1111 | v2 = v1; | |
1112 | } else if (dest != v1) { | |
1113 | if (v1 == 0) { | |
1114 | tcg_out_movi(s, type, dest, 0); | |
1115 | } else { | |
1116 | tcg_out_mov(s, type, dest, v1); | |
1117 | } | |
1118 | } | |
1119 | /* Branch forward over one insn */ | |
1120 | tcg_out32(s, tcg_to_bc[cond] | 8); | |
1121 | if (v2 == 0) { | |
1122 | tcg_out_movi(s, type, dest, 0); | |
1123 | } else { | |
1124 | tcg_out_mov(s, type, dest, v2); | |
1125 | } | |
29b69198 | 1126 | } |
810260a8 | 1127 | } |
1128 | ||
abcf61c4 RH |
1129 | static void tcg_out_cmp2(TCGContext *s, const TCGArg *args, |
1130 | const int *const_args) | |
1131 | { | |
1132 | static const struct { uint8_t bit1, bit2; } bits[] = { | |
1133 | [TCG_COND_LT ] = { CR_LT, CR_LT }, | |
1134 | [TCG_COND_LE ] = { CR_LT, CR_GT }, | |
1135 | [TCG_COND_GT ] = { CR_GT, CR_GT }, | |
1136 | [TCG_COND_GE ] = { CR_GT, CR_LT }, | |
1137 | [TCG_COND_LTU] = { CR_LT, CR_LT }, | |
1138 | [TCG_COND_LEU] = { CR_LT, CR_GT }, | |
1139 | [TCG_COND_GTU] = { CR_GT, CR_GT }, | |
1140 | [TCG_COND_GEU] = { CR_GT, CR_LT }, | |
1141 | }; | |
1142 | ||
1143 | TCGCond cond = args[4], cond2; | |
1144 | TCGArg al, ah, bl, bh; | |
1145 | int blconst, bhconst; | |
1146 | int op, bit1, bit2; | |
1147 | ||
1148 | al = args[0]; | |
1149 | ah = args[1]; | |
1150 | bl = args[2]; | |
1151 | bh = args[3]; | |
1152 | blconst = const_args[2]; | |
1153 | bhconst = const_args[3]; | |
1154 | ||
1155 | switch (cond) { | |
1156 | case TCG_COND_EQ: | |
1157 | op = CRAND; | |
1158 | goto do_equality; | |
1159 | case TCG_COND_NE: | |
1160 | op = CRNAND; | |
1161 | do_equality: | |
1162 | tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); | |
1163 | tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); | |
1164 | tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); | |
1165 | break; | |
1166 | ||
1167 | case TCG_COND_LT: | |
1168 | case TCG_COND_LE: | |
1169 | case TCG_COND_GT: | |
1170 | case TCG_COND_GE: | |
1171 | case TCG_COND_LTU: | |
1172 | case TCG_COND_LEU: | |
1173 | case TCG_COND_GTU: | |
1174 | case TCG_COND_GEU: | |
1175 | bit1 = bits[cond].bit1; | |
1176 | bit2 = bits[cond].bit2; | |
1177 | op = (bit1 != bit2 ? CRANDC : CRAND); | |
1178 | cond2 = tcg_unsigned_cond(cond); | |
1179 | ||
1180 | tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); | |
1181 | tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); | |
1182 | tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); | |
1183 | tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); | |
1184 | break; | |
1185 | ||
1186 | default: | |
1187 | tcg_abort(); | |
1188 | } | |
1189 | } | |
1190 | ||
1191 | static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, | |
1192 | const int *const_args) | |
1193 | { | |
1194 | tcg_out_cmp2(s, args + 1, const_args + 1); | |
1195 | tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); | |
1196 | tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); | |
1197 | } | |
1198 | ||
1199 | static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, | |
1200 | const int *const_args) | |
1201 | { | |
1202 | tcg_out_cmp2(s, args, const_args); | |
1203 | tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, args[5]); | |
1204 | } | |
1205 | ||
d604f1a9 | 1206 | void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) |
810260a8 | 1207 | { |
d604f1a9 | 1208 | TCGContext s; |
b18d5d2b | 1209 | |
d604f1a9 RH |
1210 | s.code_buf = s.code_ptr = (tcg_insn_unit *)jmp_addr; |
1211 | tcg_out_b(&s, 0, (tcg_insn_unit *)addr); | |
1212 | flush_icache_range(jmp_addr, jmp_addr + tcg_current_code_size(&s)); | |
810260a8 | 1213 | } |
1214 | ||
d604f1a9 | 1215 | static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) |
810260a8 | 1216 | { |
eaf7d1cf | 1217 | #ifdef _CALL_AIX |
d604f1a9 RH |
1218 | /* Look through the descriptor. If the branch is in range, and we |
1219 | don't have to spend too much effort on building the toc. */ | |
1220 | void *tgt = ((void **)target)[0]; | |
1221 | uintptr_t toc = ((uintptr_t *)target)[1]; | |
1222 | intptr_t diff = tcg_pcrel_diff(s, tgt); | |
b18d5d2b | 1223 | |
d604f1a9 | 1224 | if (in_range_b(diff) && toc == (uint32_t)toc) { |
dfca1778 | 1225 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); |
d604f1a9 | 1226 | tcg_out_b(s, LK, tgt); |
541dd4ce | 1227 | } else { |
d604f1a9 RH |
1228 | /* Fold the low bits of the constant into the addresses below. */ |
1229 | intptr_t arg = (intptr_t)target; | |
1230 | int ofs = (int16_t)arg; | |
1231 | ||
1232 | if (ofs + 8 < 0x8000) { | |
1233 | arg -= ofs; | |
1234 | } else { | |
1235 | ofs = 0; | |
1236 | } | |
dfca1778 RH |
1237 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg); |
1238 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); | |
d604f1a9 | 1239 | tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); |
dfca1778 | 1240 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); |
d604f1a9 | 1241 | tcg_out32(s, BCCTR | BO_ALWAYS | LK); |
541dd4ce | 1242 | } |
77e58d0d UW |
1243 | #elif defined(_CALL_ELF) && _CALL_ELF == 2 |
1244 | intptr_t diff; | |
1245 | ||
1246 | /* In the ELFv2 ABI, we have to set up r12 to contain the destination | |
1247 | address, which the callee uses to compute its TOC address. */ | |
1248 | /* FIXME: when the branch is in range, we could avoid r12 load if we | |
1249 | knew that the destination uses the same TOC, and what its local | |
1250 | entry point offset is. */ | |
1251 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target); | |
1252 | ||
1253 | diff = tcg_pcrel_diff(s, target); | |
1254 | if (in_range_b(diff)) { | |
1255 | tcg_out_b(s, LK, target); | |
1256 | } else { | |
1257 | tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); | |
1258 | tcg_out32(s, BCCTR | BO_ALWAYS | LK); | |
1259 | } | |
eaf7d1cf RH |
1260 | #else |
1261 | tcg_out_b(s, LK, target); | |
d604f1a9 | 1262 | #endif |
810260a8 | 1263 | } |
1264 | ||
d604f1a9 RH |
1265 | static const uint32_t qemu_ldx_opc[16] = { |
1266 | [MO_UB] = LBZX, | |
1267 | [MO_UW] = LHZX, | |
1268 | [MO_UL] = LWZX, | |
1269 | [MO_Q] = LDX, | |
1270 | [MO_SW] = LHAX, | |
1271 | [MO_SL] = LWAX, | |
1272 | [MO_BSWAP | MO_UB] = LBZX, | |
1273 | [MO_BSWAP | MO_UW] = LHBRX, | |
1274 | [MO_BSWAP | MO_UL] = LWBRX, | |
1275 | [MO_BSWAP | MO_Q] = LDBRX, | |
1276 | }; | |
810260a8 | 1277 | |
d604f1a9 RH |
1278 | static const uint32_t qemu_stx_opc[16] = { |
1279 | [MO_UB] = STBX, | |
1280 | [MO_UW] = STHX, | |
1281 | [MO_UL] = STWX, | |
1282 | [MO_Q] = STDX, | |
1283 | [MO_BSWAP | MO_UB] = STBX, | |
1284 | [MO_BSWAP | MO_UW] = STHBRX, | |
1285 | [MO_BSWAP | MO_UL] = STWBRX, | |
1286 | [MO_BSWAP | MO_Q] = STDBRX, | |
1287 | }; | |
991041a4 | 1288 | |
d604f1a9 RH |
1289 | static const uint32_t qemu_exts_opc[4] = { |
1290 | EXTSB, EXTSH, EXTSW, 0 | |
1291 | }; | |
810260a8 | 1292 | |
d604f1a9 RH |
1293 | #if defined (CONFIG_SOFTMMU) |
1294 | /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, | |
1295 | * int mmu_idx, uintptr_t ra) | |
1296 | */ | |
1297 | static void * const qemu_ld_helpers[16] = { | |
1298 | [MO_UB] = helper_ret_ldub_mmu, | |
1299 | [MO_LEUW] = helper_le_lduw_mmu, | |
1300 | [MO_LEUL] = helper_le_ldul_mmu, | |
1301 | [MO_LEQ] = helper_le_ldq_mmu, | |
1302 | [MO_BEUW] = helper_be_lduw_mmu, | |
1303 | [MO_BEUL] = helper_be_ldul_mmu, | |
1304 | [MO_BEQ] = helper_be_ldq_mmu, | |
1305 | }; | |
810260a8 | 1306 | |
d604f1a9 RH |
1307 | /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, |
1308 | * uintxx_t val, int mmu_idx, uintptr_t ra) | |
1309 | */ | |
1310 | static void * const qemu_st_helpers[16] = { | |
1311 | [MO_UB] = helper_ret_stb_mmu, | |
1312 | [MO_LEUW] = helper_le_stw_mmu, | |
1313 | [MO_LEUL] = helper_le_stl_mmu, | |
1314 | [MO_LEQ] = helper_le_stq_mmu, | |
1315 | [MO_BEUW] = helper_be_stw_mmu, | |
1316 | [MO_BEUL] = helper_be_stl_mmu, | |
1317 | [MO_BEQ] = helper_be_stq_mmu, | |
1318 | }; | |
810260a8 | 1319 | |
d604f1a9 RH |
1320 | /* Perform the TLB load and compare. Places the result of the comparison |
1321 | in CR7, loads the addend of the TLB into R3, and returns the register | |
1322 | containing the guest address (zero-extended into R4). Clobbers R0 and R2. */ | |
1323 | ||
7f25c469 RH |
1324 | static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, |
1325 | TCGReg addrlo, TCGReg addrhi, | |
d604f1a9 RH |
1326 | int mem_index, bool is_read) |
1327 | { | |
1328 | int cmp_off | |
1329 | = (is_read | |
1330 | ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) | |
1331 | : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write)); | |
1332 | int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend); | |
1333 | TCGReg base = TCG_AREG0; | |
1334 | ||
1335 | /* Extract the page index, shifted into place for tlb index. */ | |
7f25c469 RH |
1336 | if (TCG_TARGET_REG_BITS == 64) { |
1337 | if (TARGET_LONG_BITS == 32) { | |
1338 | /* Zero-extend the address into a place helpful for further use. */ | |
1339 | tcg_out_ext32u(s, TCG_REG_R4, addrlo); | |
1340 | addrlo = TCG_REG_R4; | |
1341 | } else { | |
1342 | tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo, | |
1343 | 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS); | |
1344 | } | |
810260a8 | 1345 | } |
810260a8 | 1346 | |
d604f1a9 RH |
1347 | /* Compensate for very large offsets. */ |
1348 | if (add_off >= 0x8000) { | |
1349 | /* Most target env are smaller than 32k; none are larger than 64k. | |
1350 | Simplify the logic here merely to offset by 0x7ff0, giving us a | |
1351 | range just shy of 64k. Check this assumption. */ | |
1352 | QEMU_BUILD_BUG_ON(offsetof(CPUArchState, | |
1353 | tlb_table[NB_MMU_MODES - 1][1]) | |
1354 | > 0x7ff0 + 0x7fff); | |
dfca1778 RH |
1355 | tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0)); |
1356 | base = TCG_REG_TMP1; | |
d604f1a9 RH |
1357 | cmp_off -= 0x7ff0; |
1358 | add_off -= 0x7ff0; | |
1359 | } | |
1360 | ||
1361 | /* Extraction and shifting, part 2. */ | |
7f25c469 RH |
1362 | if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) { |
1363 | tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo, | |
d604f1a9 RH |
1364 | 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), |
1365 | 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS), | |
1366 | 31 - CPU_TLB_ENTRY_BITS); | |
4c314da6 | 1367 | } else { |
d604f1a9 | 1368 | tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS); |
810260a8 | 1369 | } |
810260a8 | 1370 | |
d604f1a9 | 1371 | tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base)); |
1cd62ae9 | 1372 | |
d604f1a9 | 1373 | /* Load the tlb comparator. */ |
7f25c469 RH |
1374 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
1375 | tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); | |
dfca1778 | 1376 | tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4); |
7f25c469 | 1377 | } else { |
dfca1778 | 1378 | tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); |
7f25c469 | 1379 | } |
d604f1a9 RH |
1380 | |
1381 | /* Load the TLB addend for use on the fast path. Do this asap | |
1382 | to minimize any load use delay. */ | |
4c3831a0 | 1383 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off); |
d604f1a9 RH |
1384 | |
1385 | /* Clear the non-page, non-alignment bits from the address. */ | |
7f25c469 RH |
1386 | if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) { |
1387 | tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, | |
d604f1a9 RH |
1388 | (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS); |
1389 | } else if (!s_bits) { | |
7f25c469 RH |
1390 | tcg_out_rld(s, RLDICR, TCG_REG_R0, addrlo, |
1391 | 0, 63 - TARGET_PAGE_BITS); | |
70fac59a | 1392 | } else { |
7f25c469 | 1393 | tcg_out_rld(s, RLDICL, TCG_REG_R0, addrlo, |
d604f1a9 RH |
1394 | 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits); |
1395 | tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0); | |
70fac59a | 1396 | } |
d604f1a9 | 1397 | |
7f25c469 | 1398 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { |
dfca1778 RH |
1399 | tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, |
1400 | 0, 7, TCG_TYPE_I32); | |
7f25c469 RH |
1401 | tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32); |
1402 | tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); | |
1403 | } else { | |
dfca1778 RH |
1404 | tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, |
1405 | 0, 7, TCG_TYPE_TL); | |
7f25c469 | 1406 | } |
d604f1a9 | 1407 | |
7f25c469 | 1408 | return addrlo; |
70fac59a | 1409 | } |
1cd62ae9 | 1410 | |
d604f1a9 RH |
1411 | /* Record the context of a call to the out of line helper code for the slow |
1412 | path for a load or store, so that we can later generate the correct | |
1413 | helper code. */ | |
1414 | static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc, | |
7f25c469 RH |
1415 | TCGReg datalo_reg, TCGReg datahi_reg, |
1416 | TCGReg addrlo_reg, TCGReg addrhi_reg, | |
1417 | int mem_index, tcg_insn_unit *raddr, | |
1418 | tcg_insn_unit *lptr) | |
70fac59a | 1419 | { |
d604f1a9 RH |
1420 | TCGLabelQemuLdst *label = new_ldst_label(s); |
1421 | ||
1422 | label->is_ld = is_ld; | |
1423 | label->opc = opc; | |
7f25c469 RH |
1424 | label->datalo_reg = datalo_reg; |
1425 | label->datahi_reg = datahi_reg; | |
1426 | label->addrlo_reg = addrlo_reg; | |
1427 | label->addrhi_reg = addrhi_reg; | |
d604f1a9 RH |
1428 | label->mem_index = mem_index; |
1429 | label->raddr = raddr; | |
7f25c469 | 1430 | label->label_ptr[0] = lptr; |
70fac59a | 1431 | } |
1cd62ae9 | 1432 | |
d604f1a9 | 1433 | static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) |
70fac59a | 1434 | { |
d604f1a9 | 1435 | TCGMemOp opc = lb->opc; |
7f25c469 | 1436 | TCGReg hi, lo, arg = TCG_REG_R3; |
70fac59a | 1437 | |
d604f1a9 | 1438 | reloc_pc14(lb->label_ptr[0], s->code_ptr); |
70fac59a | 1439 | |
7f25c469 | 1440 | tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); |
1cd62ae9 | 1441 | |
7f25c469 RH |
1442 | lo = lb->addrlo_reg; |
1443 | hi = lb->addrhi_reg; | |
1444 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { | |
1445 | #ifdef TCG_TARGET_CALL_ALIGN_ARGS | |
1446 | arg |= 1; | |
1447 | #endif | |
1448 | tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); | |
1449 | tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); | |
1450 | } else { | |
1451 | /* If the address needed to be zero-extended, we'll have already | |
1452 | placed it in R4. The only remaining case is 64-bit guest. */ | |
1453 | tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); | |
1454 | } | |
752c1fdb | 1455 | |
7f25c469 RH |
1456 | tcg_out_movi(s, TCG_TYPE_I32, arg++, lb->mem_index); |
1457 | tcg_out32(s, MFSPR | RT(arg) | LR); | |
70fac59a | 1458 | |
d604f1a9 | 1459 | tcg_out_call(s, qemu_ld_helpers[opc & ~MO_SIGN]); |
70fac59a | 1460 | |
7f25c469 RH |
1461 | lo = lb->datalo_reg; |
1462 | hi = lb->datahi_reg; | |
1463 | if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { | |
1464 | tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); | |
1465 | tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); | |
1466 | } else if (opc & MO_SIGN) { | |
d604f1a9 | 1467 | uint32_t insn = qemu_exts_opc[opc & MO_SIZE]; |
7f25c469 | 1468 | tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3)); |
d604f1a9 | 1469 | } else { |
7f25c469 | 1470 | tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3); |
70fac59a RH |
1471 | } |
1472 | ||
d604f1a9 RH |
1473 | tcg_out_b(s, 0, lb->raddr); |
1474 | } | |
70fac59a | 1475 | |
d604f1a9 RH |
1476 | static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) |
1477 | { | |
1478 | TCGMemOp opc = lb->opc; | |
1479 | TCGMemOp s_bits = opc & MO_SIZE; | |
7f25c469 | 1480 | TCGReg hi, lo, arg = TCG_REG_R3; |
1cd62ae9 | 1481 | |
d604f1a9 | 1482 | reloc_pc14(lb->label_ptr[0], s->code_ptr); |
1cd62ae9 | 1483 | |
7f25c469 RH |
1484 | tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); |
1485 | ||
1486 | lo = lb->addrlo_reg; | |
1487 | hi = lb->addrhi_reg; | |
1488 | if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { | |
1489 | #ifdef TCG_TARGET_CALL_ALIGN_ARGS | |
1490 | arg |= 1; | |
1491 | #endif | |
1492 | tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); | |
1493 | tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); | |
1494 | } else { | |
1495 | /* If the address needed to be zero-extended, we'll have already | |
1496 | placed it in R4. The only remaining case is 64-bit guest. */ | |
1497 | tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); | |
1498 | } | |
1cd62ae9 | 1499 | |
7f25c469 RH |
1500 | lo = lb->datalo_reg; |
1501 | hi = lb->datahi_reg; | |
1502 | if (TCG_TARGET_REG_BITS == 32) { | |
1503 | switch (s_bits) { | |
1504 | case MO_64: | |
1505 | #ifdef TCG_TARGET_CALL_ALIGN_ARGS | |
1506 | arg |= 1; | |
1507 | #endif | |
1508 | tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); | |
1509 | /* FALLTHRU */ | |
1510 | case MO_32: | |
1511 | tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); | |
1512 | break; | |
1513 | default: | |
1514 | tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31); | |
1515 | break; | |
1516 | } | |
1517 | } else { | |
1518 | if (s_bits == MO_64) { | |
1519 | tcg_out_mov(s, TCG_TYPE_I64, arg++, lo); | |
1520 | } else { | |
1521 | tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits)); | |
1522 | } | |
1523 | } | |
1cd62ae9 | 1524 | |
7f25c469 RH |
1525 | tcg_out_movi(s, TCG_TYPE_I32, arg++, lb->mem_index); |
1526 | tcg_out32(s, MFSPR | RT(arg) | LR); | |
1cd62ae9 | 1527 | |
d604f1a9 RH |
1528 | tcg_out_call(s, qemu_st_helpers[opc]); |
1529 | ||
1530 | tcg_out_b(s, 0, lb->raddr); | |
1cd62ae9 | 1531 | } |
d604f1a9 | 1532 | #endif /* SOFTMMU */ |
1cd62ae9 | 1533 | |
7f25c469 | 1534 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) |
810260a8 | 1535 | { |
7f25c469 RH |
1536 | TCGReg datalo, datahi, addrlo, rbase; |
1537 | TCGReg addrhi __attribute__((unused)); | |
1538 | TCGMemOp opc, s_bits; | |
d604f1a9 | 1539 | #ifdef CONFIG_SOFTMMU |
7f25c469 | 1540 | int mem_index; |
d604f1a9 RH |
1541 | tcg_insn_unit *label_ptr; |
1542 | #endif | |
810260a8 | 1543 | |
7f25c469 RH |
1544 | datalo = *args++; |
1545 | datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); | |
1546 | addrlo = *args++; | |
1547 | addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); | |
1548 | opc = *args++; | |
1549 | s_bits = opc & MO_SIZE; | |
1550 | ||
d604f1a9 | 1551 | #ifdef CONFIG_SOFTMMU |
7f25c469 RH |
1552 | mem_index = *args; |
1553 | addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, true); | |
d604f1a9 RH |
1554 | |
1555 | /* Load a pointer into the current opcode w/conditional branch-link. */ | |
1556 | label_ptr = s->code_ptr; | |
1557 | tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); | |
1558 | ||
1559 | rbase = TCG_REG_R3; | |
1560 | #else /* !CONFIG_SOFTMMU */ | |
1561 | rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0; | |
7f25c469 | 1562 | if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { |
dfca1778 RH |
1563 | tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); |
1564 | addrlo = TCG_REG_TMP1; | |
d604f1a9 RH |
1565 | } |
1566 | #endif | |
1567 | ||
7f25c469 RH |
1568 | if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { |
1569 | if (opc & MO_BSWAP) { | |
1570 | tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); | |
1571 | tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); | |
1572 | tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0)); | |
1573 | } else if (rbase != 0) { | |
1574 | tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); | |
1575 | tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo)); | |
1576 | tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0)); | |
1577 | } else if (addrlo == datahi) { | |
1578 | tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); | |
1579 | tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); | |
1580 | } else { | |
1581 | tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); | |
1582 | tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); | |
1583 | } | |
541dd4ce | 1584 | } else { |
7f25c469 RH |
1585 | uint32_t insn = qemu_ldx_opc[opc]; |
1586 | if (!HAVE_ISA_2_06 && insn == LDBRX) { | |
1587 | tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); | |
1588 | tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); | |
1589 | tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0)); | |
1590 | tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); | |
1591 | } else if (insn) { | |
1592 | tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); | |
1593 | } else { | |
1594 | insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; | |
1595 | tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); | |
1596 | insn = qemu_exts_opc[s_bits]; | |
1597 | tcg_out32(s, insn | RA(datalo) | RS(datalo)); | |
1598 | } | |
810260a8 | 1599 | } |
810260a8 | 1600 | |
d604f1a9 | 1601 | #ifdef CONFIG_SOFTMMU |
7f25c469 RH |
1602 | add_qemu_ldst_label(s, true, opc, datalo, datahi, addrlo, addrhi, |
1603 | mem_index, s->code_ptr, label_ptr); | |
d604f1a9 | 1604 | #endif |
810260a8 | 1605 | } |
1606 | ||
7f25c469 | 1607 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) |
027ffea9 | 1608 | { |
7f25c469 RH |
1609 | TCGReg datalo, datahi, addrlo, rbase; |
1610 | TCGReg addrhi __attribute__((unused)); | |
1611 | TCGMemOp opc, s_bits; | |
d604f1a9 | 1612 | #ifdef CONFIG_SOFTMMU |
7f25c469 | 1613 | int mem_index; |
d604f1a9 RH |
1614 | tcg_insn_unit *label_ptr; |
1615 | #endif | |
027ffea9 | 1616 | |
7f25c469 RH |
1617 | datalo = *args++; |
1618 | datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); | |
1619 | addrlo = *args++; | |
1620 | addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); | |
1621 | opc = *args++; | |
1622 | s_bits = opc & MO_SIZE; | |
1623 | ||
d604f1a9 | 1624 | #ifdef CONFIG_SOFTMMU |
7f25c469 RH |
1625 | mem_index = *args; |
1626 | addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, false); | |
027ffea9 | 1627 | |
d604f1a9 RH |
1628 | /* Load a pointer into the current opcode w/conditional branch-link. */ |
1629 | label_ptr = s->code_ptr; | |
1630 | tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); | |
027ffea9 | 1631 | |
d604f1a9 RH |
1632 | rbase = TCG_REG_R3; |
1633 | #else /* !CONFIG_SOFTMMU */ | |
1634 | rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0; | |
7f25c469 | 1635 | if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { |
dfca1778 RH |
1636 | tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); |
1637 | addrlo = TCG_REG_TMP1; | |
d604f1a9 RH |
1638 | } |
1639 | #endif | |
1640 | ||
7f25c469 RH |
1641 | if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { |
1642 | if (opc & MO_BSWAP) { | |
1643 | tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); | |
1644 | tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); | |
1645 | tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0)); | |
1646 | } else if (rbase != 0) { | |
1647 | tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); | |
1648 | tcg_out32(s, STWX | SAB(datahi, rbase, addrlo)); | |
1649 | tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0)); | |
1650 | } else { | |
1651 | tcg_out32(s, STW | TAI(datahi, addrlo, 0)); | |
1652 | tcg_out32(s, STW | TAI(datalo, addrlo, 4)); | |
1653 | } | |
027ffea9 | 1654 | } else { |
7f25c469 RH |
1655 | uint32_t insn = qemu_stx_opc[opc]; |
1656 | if (!HAVE_ISA_2_06 && insn == STDBRX) { | |
1657 | tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); | |
dfca1778 | 1658 | tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4)); |
7f25c469 | 1659 | tcg_out_shri64(s, TCG_REG_R0, datalo, 32); |
dfca1778 | 1660 | tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1)); |
7f25c469 RH |
1661 | } else { |
1662 | tcg_out32(s, insn | SAB(datalo, rbase, addrlo)); | |
1663 | } | |
027ffea9 | 1664 | } |
d604f1a9 RH |
1665 | |
1666 | #ifdef CONFIG_SOFTMMU | |
7f25c469 RH |
1667 | add_qemu_ldst_label(s, false, opc, datalo, datahi, addrlo, addrhi, |
1668 | mem_index, s->code_ptr, label_ptr); | |
d604f1a9 | 1669 | #endif |
027ffea9 RH |
1670 | } |
1671 | ||
a921fddc RH |
1672 | /* Parameters for function call generation, used in tcg.c. */ |
1673 | #define TCG_TARGET_STACK_ALIGN 16 | |
a921fddc RH |
1674 | #define TCG_TARGET_EXTEND_ARGS 1 |
1675 | ||
802ca56e RH |
1676 | #ifdef _CALL_AIX |
1677 | # define LINK_AREA_SIZE (6 * SZR) | |
1678 | # define LR_OFFSET (1 * SZR) | |
1679 | # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) | |
ffcfbece RH |
1680 | #elif TCG_TARGET_REG_BITS == 64 |
1681 | # if defined(_CALL_ELF) && _CALL_ELF == 2 | |
1682 | # define LINK_AREA_SIZE (4 * SZR) | |
1683 | # define LR_OFFSET (1 * SZR) | |
1684 | # endif | |
1685 | #else /* TCG_TARGET_REG_BITS == 32 */ | |
1686 | # if defined(_CALL_SYSV) | |
ffcfbece RH |
1687 | # define LINK_AREA_SIZE (2 * SZR) |
1688 | # define LR_OFFSET (1 * SZR) | |
1689 | # elif defined(TCG_TARGET_CALL_DARWIN) | |
1690 | # define LINK_AREA_SIZE 24 | |
1691 | # define LR_OFFSET 8 | |
1692 | # endif | |
1693 | #endif | |
1694 | #ifndef LR_OFFSET | |
1695 | # error "Unhandled abi" | |
1696 | #endif | |
1697 | #ifndef TCG_TARGET_CALL_STACK_OFFSET | |
a2a98f80 | 1698 | # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE |
802ca56e RH |
1699 | #endif |
1700 | ||
1701 | #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) | |
1702 | #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR) | |
d604f1a9 | 1703 | |
802ca56e RH |
1704 | #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \ |
1705 | + TCG_STATIC_CALL_ARGS_SIZE \ | |
1706 | + CPU_TEMP_BUF_SIZE \ | |
1707 | + REG_SAVE_SIZE \ | |
1708 | + TCG_TARGET_STACK_ALIGN - 1) \ | |
1709 | & -TCG_TARGET_STACK_ALIGN) | |
1710 | ||
1711 | #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE) | |
d604f1a9 RH |
1712 | |
1713 | static void tcg_target_qemu_prologue(TCGContext *s) | |
810260a8 | 1714 | { |
d604f1a9 | 1715 | int i; |
810260a8 | 1716 | |
802ca56e RH |
1717 | tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, |
1718 | CPU_TEMP_BUF_SIZE); | |
d604f1a9 | 1719 | |
802ca56e RH |
1720 | #ifdef _CALL_AIX |
1721 | { | |
1722 | void **desc = (void **)s->code_ptr; | |
1723 | desc[0] = desc + 2; /* entry point */ | |
1724 | desc[1] = 0; /* environment pointer */ | |
1725 | s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ | |
1726 | } | |
d604f1a9 RH |
1727 | #endif |
1728 | ||
1729 | /* Prologue */ | |
1730 | tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); | |
ffcfbece RH |
1731 | tcg_out32(s, (SZR == 8 ? STDU : STWU) |
1732 | | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); | |
802ca56e | 1733 | |
d604f1a9 | 1734 | for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { |
4c3831a0 RH |
1735 | tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], |
1736 | TCG_REG_R1, REG_SAVE_BOT + i * SZR); | |
d604f1a9 | 1737 | } |
802ca56e | 1738 | tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); |
d604f1a9 RH |
1739 | |
1740 | #ifdef CONFIG_USE_GUEST_BASE | |
1741 | if (GUEST_BASE) { | |
1742 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE); | |
1743 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); | |
1744 | } | |
1745 | #endif | |
1746 | ||
1747 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); | |
1748 | tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); | |
1749 | tcg_out32(s, BCCTR | BO_ALWAYS); | |
1750 | ||
1751 | /* Epilogue */ | |
1752 | tb_ret_addr = s->code_ptr; | |
1753 | ||
802ca56e | 1754 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); |
d604f1a9 | 1755 | for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { |
4c3831a0 RH |
1756 | tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], |
1757 | TCG_REG_R1, REG_SAVE_BOT + i * SZR); | |
d604f1a9 | 1758 | } |
d604f1a9 RH |
1759 | tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR); |
1760 | tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE)); | |
1761 | tcg_out32(s, BCLR | BO_ALWAYS); | |
810260a8 | 1762 | } |
1763 | ||
541dd4ce RH |
1764 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, |
1765 | const int *const_args) | |
810260a8 | 1766 | { |
ee924fa6 | 1767 | TCGArg a0, a1, a2; |
e46b9681 | 1768 | int c; |
1769 | ||
810260a8 | 1770 | switch (opc) { |
1771 | case INDEX_op_exit_tb: | |
de3d636d | 1772 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); |
e083c4a2 | 1773 | tcg_out_b(s, 0, tb_ret_addr); |
810260a8 | 1774 | break; |
1775 | case INDEX_op_goto_tb: | |
1776 | if (s->tb_jmp_offset) { | |
541dd4ce | 1777 | /* Direct jump method. */ |
e083c4a2 RH |
1778 | s->tb_jmp_offset[args[0]] = tcg_current_code_size(s); |
1779 | s->code_ptr += 7; | |
541dd4ce RH |
1780 | } else { |
1781 | /* Indirect jump method. */ | |
1782 | tcg_abort(); | |
810260a8 | 1783 | } |
e083c4a2 | 1784 | s->tb_next_offset[args[0]] = tcg_current_code_size(s); |
810260a8 | 1785 | break; |
1786 | case INDEX_op_br: | |
1787 | { | |
1788 | TCGLabel *l = &s->labels[args[0]]; | |
1789 | ||
1790 | if (l->has_value) { | |
e083c4a2 | 1791 | tcg_out_b(s, 0, l->u.value_ptr); |
541dd4ce | 1792 | } else { |
c7ca6a2b RH |
1793 | tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, args[0], 0); |
1794 | tcg_out_b_noaddr(s, B); | |
810260a8 | 1795 | } |
1796 | } | |
1797 | break; | |
810260a8 | 1798 | case INDEX_op_ld8u_i32: |
1799 | case INDEX_op_ld8u_i64: | |
b18d5d2b | 1800 | tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); |
810260a8 | 1801 | break; |
1802 | case INDEX_op_ld8s_i32: | |
1803 | case INDEX_op_ld8s_i64: | |
b18d5d2b | 1804 | tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); |
541dd4ce | 1805 | tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0])); |
810260a8 | 1806 | break; |
1807 | case INDEX_op_ld16u_i32: | |
1808 | case INDEX_op_ld16u_i64: | |
b18d5d2b | 1809 | tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); |
810260a8 | 1810 | break; |
1811 | case INDEX_op_ld16s_i32: | |
1812 | case INDEX_op_ld16s_i64: | |
b18d5d2b | 1813 | tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); |
810260a8 | 1814 | break; |
1815 | case INDEX_op_ld_i32: | |
1816 | case INDEX_op_ld32u_i64: | |
b18d5d2b | 1817 | tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); |
810260a8 | 1818 | break; |
1819 | case INDEX_op_ld32s_i64: | |
b18d5d2b | 1820 | tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); |
810260a8 | 1821 | break; |
1822 | case INDEX_op_ld_i64: | |
b18d5d2b | 1823 | tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); |
810260a8 | 1824 | break; |
1825 | case INDEX_op_st8_i32: | |
1826 | case INDEX_op_st8_i64: | |
b18d5d2b | 1827 | tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); |
810260a8 | 1828 | break; |
1829 | case INDEX_op_st16_i32: | |
1830 | case INDEX_op_st16_i64: | |
b18d5d2b | 1831 | tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); |
810260a8 | 1832 | break; |
1833 | case INDEX_op_st_i32: | |
1834 | case INDEX_op_st32_i64: | |
b18d5d2b | 1835 | tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); |
810260a8 | 1836 | break; |
1837 | case INDEX_op_st_i64: | |
b18d5d2b | 1838 | tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); |
810260a8 | 1839 | break; |
1840 | ||
1841 | case INDEX_op_add_i32: | |
ee924fa6 RH |
1842 | a0 = args[0], a1 = args[1], a2 = args[2]; |
1843 | if (const_args[2]) { | |
ee924fa6 | 1844 | do_addi_32: |
b18d5d2b | 1845 | tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); |
ee924fa6 RH |
1846 | } else { |
1847 | tcg_out32(s, ADD | TAB(a0, a1, a2)); | |
1848 | } | |
810260a8 | 1849 | break; |
1850 | case INDEX_op_sub_i32: | |
ee924fa6 | 1851 | a0 = args[0], a1 = args[1], a2 = args[2]; |
148bdd23 RH |
1852 | if (const_args[1]) { |
1853 | if (const_args[2]) { | |
1854 | tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); | |
1855 | } else { | |
1856 | tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); | |
1857 | } | |
1858 | } else if (const_args[2]) { | |
ee924fa6 RH |
1859 | a2 = -a2; |
1860 | goto do_addi_32; | |
1861 | } else { | |
1862 | tcg_out32(s, SUBF | TAB(a0, a2, a1)); | |
1863 | } | |
810260a8 | 1864 | break; |
1865 | ||
1866 | case INDEX_op_and_i32: | |
37251b98 | 1867 | a0 = args[0], a1 = args[1], a2 = args[2]; |
a9249dff | 1868 | if (const_args[2]) { |
37251b98 | 1869 | tcg_out_andi32(s, a0, a1, a2); |
a9249dff | 1870 | } else { |
37251b98 | 1871 | tcg_out32(s, AND | SAB(a1, a0, a2)); |
a9249dff RH |
1872 | } |
1873 | break; | |
1874 | case INDEX_op_and_i64: | |
37251b98 | 1875 | a0 = args[0], a1 = args[1], a2 = args[2]; |
810260a8 | 1876 | if (const_args[2]) { |
37251b98 | 1877 | tcg_out_andi64(s, a0, a1, a2); |
637af30c | 1878 | } else { |
37251b98 | 1879 | tcg_out32(s, AND | SAB(a1, a0, a2)); |
810260a8 | 1880 | } |
810260a8 | 1881 | break; |
fe6f943f | 1882 | case INDEX_op_or_i64: |
810260a8 | 1883 | case INDEX_op_or_i32: |
dce74c57 | 1884 | a0 = args[0], a1 = args[1], a2 = args[2]; |
810260a8 | 1885 | if (const_args[2]) { |
dce74c57 RH |
1886 | tcg_out_ori32(s, a0, a1, a2); |
1887 | } else { | |
1888 | tcg_out32(s, OR | SAB(a1, a0, a2)); | |
810260a8 | 1889 | } |
810260a8 | 1890 | break; |
fe6f943f | 1891 | case INDEX_op_xor_i64: |
810260a8 | 1892 | case INDEX_op_xor_i32: |
dce74c57 | 1893 | a0 = args[0], a1 = args[1], a2 = args[2]; |
810260a8 | 1894 | if (const_args[2]) { |
dce74c57 RH |
1895 | tcg_out_xori32(s, a0, a1, a2); |
1896 | } else { | |
1897 | tcg_out32(s, XOR | SAB(a1, a0, a2)); | |
810260a8 | 1898 | } |
810260a8 | 1899 | break; |
ce1010d6 | 1900 | case INDEX_op_andc_i32: |
37251b98 RH |
1901 | a0 = args[0], a1 = args[1], a2 = args[2]; |
1902 | if (const_args[2]) { | |
1903 | tcg_out_andi32(s, a0, a1, ~a2); | |
1904 | } else { | |
1905 | tcg_out32(s, ANDC | SAB(a1, a0, a2)); | |
1906 | } | |
1907 | break; | |
ce1010d6 | 1908 | case INDEX_op_andc_i64: |
37251b98 RH |
1909 | a0 = args[0], a1 = args[1], a2 = args[2]; |
1910 | if (const_args[2]) { | |
1911 | tcg_out_andi64(s, a0, a1, ~a2); | |
1912 | } else { | |
1913 | tcg_out32(s, ANDC | SAB(a1, a0, a2)); | |
1914 | } | |
ce1010d6 RH |
1915 | break; |
1916 | case INDEX_op_orc_i32: | |
37251b98 RH |
1917 | if (const_args[2]) { |
1918 | tcg_out_ori32(s, args[0], args[1], ~args[2]); | |
1919 | break; | |
1920 | } | |
1921 | /* FALLTHRU */ | |
ce1010d6 RH |
1922 | case INDEX_op_orc_i64: |
1923 | tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); | |
1924 | break; | |
1925 | case INDEX_op_eqv_i32: | |
37251b98 RH |
1926 | if (const_args[2]) { |
1927 | tcg_out_xori32(s, args[0], args[1], ~args[2]); | |
1928 | break; | |
1929 | } | |
1930 | /* FALLTHRU */ | |
ce1010d6 RH |
1931 | case INDEX_op_eqv_i64: |
1932 | tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); | |
1933 | break; | |
1934 | case INDEX_op_nand_i32: | |
1935 | case INDEX_op_nand_i64: | |
1936 | tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); | |
1937 | break; | |
1938 | case INDEX_op_nor_i32: | |
1939 | case INDEX_op_nor_i64: | |
1940 | tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); | |
1941 | break; | |
810260a8 | 1942 | |
1943 | case INDEX_op_mul_i32: | |
ef809300 | 1944 | a0 = args[0], a1 = args[1], a2 = args[2]; |
810260a8 | 1945 | if (const_args[2]) { |
ef809300 RH |
1946 | tcg_out32(s, MULLI | TAI(a0, a1, a2)); |
1947 | } else { | |
1948 | tcg_out32(s, MULLW | TAB(a0, a1, a2)); | |
810260a8 | 1949 | } |
810260a8 | 1950 | break; |
1951 | ||
1952 | case INDEX_op_div_i32: | |
541dd4ce | 1953 | tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); |
810260a8 | 1954 | break; |
1955 | ||
1956 | case INDEX_op_divu_i32: | |
541dd4ce | 1957 | tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); |
810260a8 | 1958 | break; |
1959 | ||
810260a8 | 1960 | case INDEX_op_shl_i32: |
1961 | if (const_args[2]) { | |
a757e1ee | 1962 | tcg_out_shli32(s, args[0], args[1], args[2]); |
9e555b73 | 1963 | } else { |
541dd4ce | 1964 | tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); |
9e555b73 | 1965 | } |
810260a8 | 1966 | break; |
1967 | case INDEX_op_shr_i32: | |
1968 | if (const_args[2]) { | |
a757e1ee | 1969 | tcg_out_shri32(s, args[0], args[1], args[2]); |
9e555b73 | 1970 | } else { |
541dd4ce | 1971 | tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); |
9e555b73 | 1972 | } |
810260a8 | 1973 | break; |
1974 | case INDEX_op_sar_i32: | |
541dd4ce RH |
1975 | if (const_args[2]) { |
1976 | tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2])); | |
1977 | } else { | |
1978 | tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); | |
1979 | } | |
810260a8 | 1980 | break; |
313d91c7 RH |
1981 | case INDEX_op_rotl_i32: |
1982 | if (const_args[2]) { | |
1983 | tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); | |
1984 | } else { | |
1985 | tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) | |
1986 | | MB(0) | ME(31)); | |
1987 | } | |
1988 | break; | |
1989 | case INDEX_op_rotr_i32: | |
1990 | if (const_args[2]) { | |
1991 | tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); | |
1992 | } else { | |
8327a470 RH |
1993 | tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); |
1994 | tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) | |
313d91c7 RH |
1995 | | MB(0) | ME(31)); |
1996 | } | |
1997 | break; | |
810260a8 | 1998 | |
1999 | case INDEX_op_brcond_i32: | |
4c314da6 RH |
2000 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
2001 | args[3], TCG_TYPE_I32); | |
e924bbec | 2002 | break; |
810260a8 | 2003 | case INDEX_op_brcond_i64: |
4c314da6 RH |
2004 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
2005 | args[3], TCG_TYPE_I64); | |
810260a8 | 2006 | break; |
abcf61c4 RH |
2007 | case INDEX_op_brcond2_i32: |
2008 | tcg_out_brcond2(s, args, const_args); | |
2009 | break; | |
810260a8 | 2010 | |
2011 | case INDEX_op_neg_i32: | |
810260a8 | 2012 | case INDEX_op_neg_i64: |
541dd4ce | 2013 | tcg_out32(s, NEG | RT(args[0]) | RA(args[1])); |
810260a8 | 2014 | break; |
2015 | ||
157f2662 | 2016 | case INDEX_op_not_i32: |
2017 | case INDEX_op_not_i64: | |
541dd4ce | 2018 | tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); |
157f2662 | 2019 | break; |
2020 | ||
810260a8 | 2021 | case INDEX_op_add_i64: |
ee924fa6 RH |
2022 | a0 = args[0], a1 = args[1], a2 = args[2]; |
2023 | if (const_args[2]) { | |
ee924fa6 | 2024 | do_addi_64: |
b18d5d2b | 2025 | tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); |
ee924fa6 RH |
2026 | } else { |
2027 | tcg_out32(s, ADD | TAB(a0, a1, a2)); | |
2028 | } | |
810260a8 | 2029 | break; |
2030 | case INDEX_op_sub_i64: | |
ee924fa6 | 2031 | a0 = args[0], a1 = args[1], a2 = args[2]; |
148bdd23 RH |
2032 | if (const_args[1]) { |
2033 | if (const_args[2]) { | |
2034 | tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); | |
2035 | } else { | |
2036 | tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); | |
2037 | } | |
2038 | } else if (const_args[2]) { | |
ee924fa6 RH |
2039 | a2 = -a2; |
2040 | goto do_addi_64; | |
2041 | } else { | |
2042 | tcg_out32(s, SUBF | TAB(a0, a2, a1)); | |
2043 | } | |
810260a8 | 2044 | break; |
2045 | ||
2046 | case INDEX_op_shl_i64: | |
541dd4ce | 2047 | if (const_args[2]) { |
0a9564b9 | 2048 | tcg_out_shli64(s, args[0], args[1], args[2]); |
541dd4ce RH |
2049 | } else { |
2050 | tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); | |
2051 | } | |
810260a8 | 2052 | break; |
2053 | case INDEX_op_shr_i64: | |
541dd4ce | 2054 | if (const_args[2]) { |
5e916c28 | 2055 | tcg_out_shri64(s, args[0], args[1], args[2]); |
541dd4ce RH |
2056 | } else { |
2057 | tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); | |
2058 | } | |
810260a8 | 2059 | break; |
2060 | case INDEX_op_sar_i64: | |
fe6f943f | 2061 | if (const_args[2]) { |
541dd4ce RH |
2062 | int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); |
2063 | tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh); | |
2064 | } else { | |
2065 | tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); | |
fe6f943f | 2066 | } |
810260a8 | 2067 | break; |
313d91c7 RH |
2068 | case INDEX_op_rotl_i64: |
2069 | if (const_args[2]) { | |
2070 | tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); | |
2071 | } else { | |
2072 | tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); | |
2073 | } | |
2074 | break; | |
2075 | case INDEX_op_rotr_i64: | |
2076 | if (const_args[2]) { | |
2077 | tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); | |
2078 | } else { | |
8327a470 RH |
2079 | tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); |
2080 | tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); | |
313d91c7 RH |
2081 | } |
2082 | break; | |
810260a8 | 2083 | |
2084 | case INDEX_op_mul_i64: | |
ef809300 RH |
2085 | a0 = args[0], a1 = args[1], a2 = args[2]; |
2086 | if (const_args[2]) { | |
2087 | tcg_out32(s, MULLI | TAI(a0, a1, a2)); | |
2088 | } else { | |
2089 | tcg_out32(s, MULLD | TAB(a0, a1, a2)); | |
2090 | } | |
810260a8 | 2091 | break; |
2092 | case INDEX_op_div_i64: | |
541dd4ce | 2093 | tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); |
810260a8 | 2094 | break; |
2095 | case INDEX_op_divu_i64: | |
541dd4ce | 2096 | tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); |
810260a8 | 2097 | break; |
810260a8 | 2098 | |
1768ec06 | 2099 | case INDEX_op_qemu_ld_i32: |
7f25c469 RH |
2100 | tcg_out_qemu_ld(s, args, false); |
2101 | break; | |
1768ec06 | 2102 | case INDEX_op_qemu_ld_i64: |
7f25c469 | 2103 | tcg_out_qemu_ld(s, args, true); |
810260a8 | 2104 | break; |
1768ec06 | 2105 | case INDEX_op_qemu_st_i32: |
7f25c469 RH |
2106 | tcg_out_qemu_st(s, args, false); |
2107 | break; | |
1768ec06 | 2108 | case INDEX_op_qemu_st_i64: |
7f25c469 | 2109 | tcg_out_qemu_st(s, args, true); |
810260a8 | 2110 | break; |
2111 | ||
e46b9681 | 2112 | case INDEX_op_ext8s_i32: |
2113 | case INDEX_op_ext8s_i64: | |
2114 | c = EXTSB; | |
2115 | goto gen_ext; | |
2116 | case INDEX_op_ext16s_i32: | |
2117 | case INDEX_op_ext16s_i64: | |
2118 | c = EXTSH; | |
2119 | goto gen_ext; | |
2120 | case INDEX_op_ext32s_i64: | |
2121 | c = EXTSW; | |
2122 | goto gen_ext; | |
2123 | gen_ext: | |
541dd4ce | 2124 | tcg_out32(s, c | RS(args[1]) | RA(args[0])); |
e46b9681 | 2125 | break; |
2126 | ||
1cd62ae9 | 2127 | case INDEX_op_setcond_i32: |
541dd4ce RH |
2128 | tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], |
2129 | const_args[2]); | |
1cd62ae9 | 2130 | break; |
2131 | case INDEX_op_setcond_i64: | |
541dd4ce RH |
2132 | tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], |
2133 | const_args[2]); | |
1cd62ae9 | 2134 | break; |
abcf61c4 RH |
2135 | case INDEX_op_setcond2_i32: |
2136 | tcg_out_setcond2(s, args, const_args); | |
2137 | break; | |
1cd62ae9 | 2138 | |
5d221582 RH |
2139 | case INDEX_op_bswap16_i32: |
2140 | case INDEX_op_bswap16_i64: | |
2141 | a0 = args[0], a1 = args[1]; | |
2142 | /* a1 = abcd */ | |
2143 | if (a0 != a1) { | |
2144 | /* a0 = (a1 r<< 24) & 0xff # 000c */ | |
2145 | tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31); | |
2146 | /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */ | |
2147 | tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23); | |
2148 | } else { | |
2149 | /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */ | |
2150 | tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23); | |
2151 | /* a0 = (a1 r<< 24) & 0xff # 000c */ | |
2152 | tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31); | |
2153 | /* a0 = a0 | r0 # 00dc */ | |
2154 | tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0)); | |
2155 | } | |
2156 | break; | |
2157 | ||
2158 | case INDEX_op_bswap32_i32: | |
2159 | case INDEX_op_bswap32_i64: | |
2160 | /* Stolen from gcc's builtin_bswap32 */ | |
2161 | a1 = args[1]; | |
2162 | a0 = args[0] == a1 ? TCG_REG_R0 : args[0]; | |
2163 | ||
2164 | /* a1 = args[1] # abcd */ | |
2165 | /* a0 = rotate_left (a1, 8) # bcda */ | |
2166 | tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31); | |
2167 | /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */ | |
2168 | tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7); | |
2169 | /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */ | |
2170 | tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23); | |
2171 | ||
2172 | if (a0 == TCG_REG_R0) { | |
de3d636d | 2173 | tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); |
5d221582 RH |
2174 | } |
2175 | break; | |
2176 | ||
68aebd45 | 2177 | case INDEX_op_bswap64_i64: |
8327a470 | 2178 | a0 = args[0], a1 = args[1], a2 = TCG_REG_R0; |
68aebd45 | 2179 | if (a0 == a1) { |
8327a470 | 2180 | a0 = TCG_REG_R0; |
68aebd45 RH |
2181 | a2 = a1; |
2182 | } | |
2183 | ||
2184 | /* a1 = # abcd efgh */ | |
2185 | /* a0 = rl32(a1, 8) # 0000 fghe */ | |
2186 | tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31); | |
2187 | /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */ | |
2188 | tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7); | |
2189 | /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */ | |
2190 | tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23); | |
2191 | ||
2192 | /* a0 = rl64(a0, 32) # hgfe 0000 */ | |
2193 | /* a2 = rl64(a1, 32) # efgh abcd */ | |
2194 | tcg_out_rld(s, RLDICL, a0, a0, 32, 0); | |
2195 | tcg_out_rld(s, RLDICL, a2, a1, 32, 0); | |
2196 | ||
2197 | /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */ | |
2198 | tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31); | |
2199 | /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */ | |
2200 | tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7); | |
2201 | /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */ | |
2202 | tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23); | |
2203 | ||
2204 | if (a0 == 0) { | |
de3d636d | 2205 | tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); |
68aebd45 RH |
2206 | } |
2207 | break; | |
2208 | ||
33de9ed2 | 2209 | case INDEX_op_deposit_i32: |
39dc85b9 RH |
2210 | if (const_args[2]) { |
2211 | uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; | |
2212 | tcg_out_andi32(s, args[0], args[0], ~mask); | |
2213 | } else { | |
2214 | tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], | |
2215 | 32 - args[3] - args[4], 31 - args[3]); | |
2216 | } | |
33de9ed2 RH |
2217 | break; |
2218 | case INDEX_op_deposit_i64: | |
39dc85b9 RH |
2219 | if (const_args[2]) { |
2220 | uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; | |
2221 | tcg_out_andi64(s, args[0], args[0], ~mask); | |
2222 | } else { | |
2223 | tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], | |
2224 | 64 - args[3] - args[4]); | |
2225 | } | |
33de9ed2 RH |
2226 | break; |
2227 | ||
027ffea9 RH |
2228 | case INDEX_op_movcond_i32: |
2229 | tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], | |
2230 | args[3], args[4], const_args[2]); | |
2231 | break; | |
2232 | case INDEX_op_movcond_i64: | |
2233 | tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], | |
2234 | args[3], args[4], const_args[2]); | |
2235 | break; | |
2236 | ||
796f1a68 | 2237 | #if TCG_TARGET_REG_BITS == 64 |
6c858762 | 2238 | case INDEX_op_add2_i64: |
796f1a68 RH |
2239 | #else |
2240 | case INDEX_op_add2_i32: | |
2241 | #endif | |
6c858762 RH |
2242 | /* Note that the CA bit is defined based on the word size of the |
2243 | environment. So in 64-bit mode it's always carry-out of bit 63. | |
2244 | The fallback code using deposit works just as well for 32-bit. */ | |
2245 | a0 = args[0], a1 = args[1]; | |
84247357 | 2246 | if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { |
6c858762 RH |
2247 | a0 = TCG_REG_R0; |
2248 | } | |
84247357 AB |
2249 | if (const_args[4]) { |
2250 | tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); | |
6c858762 | 2251 | } else { |
84247357 | 2252 | tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); |
6c858762 RH |
2253 | } |
2254 | if (const_args[5]) { | |
84247357 | 2255 | tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); |
6c858762 | 2256 | } else { |
84247357 | 2257 | tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); |
6c858762 RH |
2258 | } |
2259 | if (a0 != args[0]) { | |
de3d636d | 2260 | tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); |
6c858762 RH |
2261 | } |
2262 | break; | |
2263 | ||
796f1a68 | 2264 | #if TCG_TARGET_REG_BITS == 64 |
6c858762 | 2265 | case INDEX_op_sub2_i64: |
796f1a68 RH |
2266 | #else |
2267 | case INDEX_op_sub2_i32: | |
2268 | #endif | |
6c858762 | 2269 | a0 = args[0], a1 = args[1]; |
b31284ce | 2270 | if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { |
6c858762 RH |
2271 | a0 = TCG_REG_R0; |
2272 | } | |
2273 | if (const_args[2]) { | |
b31284ce | 2274 | tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); |
6c858762 | 2275 | } else { |
b31284ce | 2276 | tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); |
6c858762 | 2277 | } |
b31284ce RH |
2278 | if (const_args[3]) { |
2279 | tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); | |
6c858762 | 2280 | } else { |
b31284ce | 2281 | tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); |
6c858762 RH |
2282 | } |
2283 | if (a0 != args[0]) { | |
de3d636d | 2284 | tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); |
6c858762 RH |
2285 | } |
2286 | break; | |
2287 | ||
abcf61c4 RH |
2288 | case INDEX_op_muluh_i32: |
2289 | tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); | |
2290 | break; | |
8fa391a0 RH |
2291 | case INDEX_op_mulsh_i32: |
2292 | tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); | |
2293 | break; | |
32f5717f RH |
2294 | case INDEX_op_muluh_i64: |
2295 | tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); | |
2296 | break; | |
2297 | case INDEX_op_mulsh_i64: | |
2298 | tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); | |
6645c147 RH |
2299 | break; |
2300 | ||
96d0ee7f RH |
2301 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ |
2302 | case INDEX_op_mov_i64: | |
2303 | case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | |
2304 | case INDEX_op_movi_i64: | |
2305 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | |
810260a8 | 2306 | default: |
541dd4ce | 2307 | tcg_abort(); |
810260a8 | 2308 | } |
2309 | } | |
2310 | ||
2311 | static const TCGTargetOpDef ppc_op_defs[] = { | |
2312 | { INDEX_op_exit_tb, { } }, | |
2313 | { INDEX_op_goto_tb, { } }, | |
810260a8 | 2314 | { INDEX_op_br, { } }, |
2315 | ||
810260a8 | 2316 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
2317 | { INDEX_op_ld8s_i32, { "r", "r" } }, | |
2318 | { INDEX_op_ld16u_i32, { "r", "r" } }, | |
2319 | { INDEX_op_ld16s_i32, { "r", "r" } }, | |
2320 | { INDEX_op_ld_i32, { "r", "r" } }, | |
796f1a68 | 2321 | |
810260a8 | 2322 | { INDEX_op_st8_i32, { "r", "r" } }, |
810260a8 | 2323 | { INDEX_op_st16_i32, { "r", "r" } }, |
810260a8 | 2324 | { INDEX_op_st_i32, { "r", "r" } }, |
810260a8 | 2325 | |
2326 | { INDEX_op_add_i32, { "r", "r", "ri" } }, | |
ef809300 | 2327 | { INDEX_op_mul_i32, { "r", "r", "rI" } }, |
810260a8 | 2328 | { INDEX_op_div_i32, { "r", "r", "r" } }, |
2329 | { INDEX_op_divu_i32, { "r", "r", "r" } }, | |
148bdd23 | 2330 | { INDEX_op_sub_i32, { "r", "rI", "ri" } }, |
810260a8 | 2331 | { INDEX_op_and_i32, { "r", "r", "ri" } }, |
2332 | { INDEX_op_or_i32, { "r", "r", "ri" } }, | |
2333 | { INDEX_op_xor_i32, { "r", "r", "ri" } }, | |
37251b98 RH |
2334 | { INDEX_op_andc_i32, { "r", "r", "ri" } }, |
2335 | { INDEX_op_orc_i32, { "r", "r", "ri" } }, | |
2336 | { INDEX_op_eqv_i32, { "r", "r", "ri" } }, | |
ce1010d6 RH |
2337 | { INDEX_op_nand_i32, { "r", "r", "r" } }, |
2338 | { INDEX_op_nor_i32, { "r", "r", "r" } }, | |
810260a8 | 2339 | |
2340 | { INDEX_op_shl_i32, { "r", "r", "ri" } }, | |
2341 | { INDEX_op_shr_i32, { "r", "r", "ri" } }, | |
2342 | { INDEX_op_sar_i32, { "r", "r", "ri" } }, | |
313d91c7 RH |
2343 | { INDEX_op_rotl_i32, { "r", "r", "ri" } }, |
2344 | { INDEX_op_rotr_i32, { "r", "r", "ri" } }, | |
810260a8 | 2345 | |
810260a8 | 2346 | { INDEX_op_neg_i32, { "r", "r" } }, |
157f2662 | 2347 | { INDEX_op_not_i32, { "r", "r" } }, |
796f1a68 RH |
2348 | { INDEX_op_ext8s_i32, { "r", "r" } }, |
2349 | { INDEX_op_ext16s_i32, { "r", "r" } }, | |
2350 | { INDEX_op_bswap16_i32, { "r", "r" } }, | |
2351 | { INDEX_op_bswap32_i32, { "r", "r" } }, | |
2352 | ||
2353 | { INDEX_op_brcond_i32, { "r", "ri" } }, | |
2354 | { INDEX_op_setcond_i32, { "r", "r", "ri" } }, | |
2355 | { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } }, | |
2356 | ||
2357 | { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, | |
2358 | ||
abcf61c4 | 2359 | { INDEX_op_muluh_i32, { "r", "r", "r" } }, |
8fa391a0 | 2360 | { INDEX_op_mulsh_i32, { "r", "r", "r" } }, |
abcf61c4 | 2361 | |
796f1a68 RH |
2362 | #if TCG_TARGET_REG_BITS == 64 |
2363 | { INDEX_op_ld8u_i64, { "r", "r" } }, | |
2364 | { INDEX_op_ld8s_i64, { "r", "r" } }, | |
2365 | { INDEX_op_ld16u_i64, { "r", "r" } }, | |
2366 | { INDEX_op_ld16s_i64, { "r", "r" } }, | |
2367 | { INDEX_op_ld32u_i64, { "r", "r" } }, | |
2368 | { INDEX_op_ld32s_i64, { "r", "r" } }, | |
2369 | { INDEX_op_ld_i64, { "r", "r" } }, | |
2370 | ||
2371 | { INDEX_op_st8_i64, { "r", "r" } }, | |
2372 | { INDEX_op_st16_i64, { "r", "r" } }, | |
2373 | { INDEX_op_st32_i64, { "r", "r" } }, | |
2374 | { INDEX_op_st_i64, { "r", "r" } }, | |
810260a8 | 2375 | |
ee924fa6 | 2376 | { INDEX_op_add_i64, { "r", "r", "rT" } }, |
148bdd23 | 2377 | { INDEX_op_sub_i64, { "r", "rI", "rT" } }, |
37251b98 | 2378 | { INDEX_op_and_i64, { "r", "r", "ri" } }, |
3d582c61 RH |
2379 | { INDEX_op_or_i64, { "r", "r", "rU" } }, |
2380 | { INDEX_op_xor_i64, { "r", "r", "rU" } }, | |
37251b98 | 2381 | { INDEX_op_andc_i64, { "r", "r", "ri" } }, |
ce1010d6 RH |
2382 | { INDEX_op_orc_i64, { "r", "r", "r" } }, |
2383 | { INDEX_op_eqv_i64, { "r", "r", "r" } }, | |
2384 | { INDEX_op_nand_i64, { "r", "r", "r" } }, | |
2385 | { INDEX_op_nor_i64, { "r", "r", "r" } }, | |
810260a8 | 2386 | |
fe6f943f | 2387 | { INDEX_op_shl_i64, { "r", "r", "ri" } }, |
2388 | { INDEX_op_shr_i64, { "r", "r", "ri" } }, | |
2389 | { INDEX_op_sar_i64, { "r", "r", "ri" } }, | |
313d91c7 RH |
2390 | { INDEX_op_rotl_i64, { "r", "r", "ri" } }, |
2391 | { INDEX_op_rotr_i64, { "r", "r", "ri" } }, | |
810260a8 | 2392 | |
ef809300 | 2393 | { INDEX_op_mul_i64, { "r", "r", "rI" } }, |
810260a8 | 2394 | { INDEX_op_div_i64, { "r", "r", "r" } }, |
2395 | { INDEX_op_divu_i64, { "r", "r", "r" } }, | |
810260a8 | 2396 | |
2397 | { INDEX_op_neg_i64, { "r", "r" } }, | |
157f2662 | 2398 | { INDEX_op_not_i64, { "r", "r" } }, |
e46b9681 | 2399 | { INDEX_op_ext8s_i64, { "r", "r" } }, |
2400 | { INDEX_op_ext16s_i64, { "r", "r" } }, | |
2401 | { INDEX_op_ext32s_i64, { "r", "r" } }, | |
5d221582 | 2402 | { INDEX_op_bswap16_i64, { "r", "r" } }, |
5d221582 | 2403 | { INDEX_op_bswap32_i64, { "r", "r" } }, |
68aebd45 | 2404 | { INDEX_op_bswap64_i64, { "r", "r" } }, |
5d221582 | 2405 | |
796f1a68 RH |
2406 | { INDEX_op_brcond_i64, { "r", "ri" } }, |
2407 | { INDEX_op_setcond_i64, { "r", "r", "ri" } }, | |
2408 | { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } }, | |
2409 | ||
39dc85b9 | 2410 | { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, |
33de9ed2 | 2411 | |
32f5717f RH |
2412 | { INDEX_op_mulsh_i64, { "r", "r", "r" } }, |
2413 | { INDEX_op_muluh_i64, { "r", "r", "r" } }, | |
796f1a68 RH |
2414 | #endif |
2415 | ||
abcf61c4 RH |
2416 | #if TCG_TARGET_REG_BITS == 32 |
2417 | { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } }, | |
2418 | { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } }, | |
2419 | #endif | |
2420 | ||
796f1a68 RH |
2421 | #if TCG_TARGET_REG_BITS == 64 |
2422 | { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } }, | |
2423 | { INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } }, | |
2424 | #else | |
2425 | { INDEX_op_add2_i32, { "r", "r", "r", "r", "rI", "rZM" } }, | |
2426 | { INDEX_op_sub2_i32, { "r", "r", "rI", "rZM", "r", "r" } }, | |
2427 | #endif | |
2428 | ||
2429 | #if TCG_TARGET_REG_BITS == 64 | |
2430 | { INDEX_op_qemu_ld_i32, { "r", "L" } }, | |
2431 | { INDEX_op_qemu_st_i32, { "S", "S" } }, | |
2432 | { INDEX_op_qemu_ld_i64, { "r", "L" } }, | |
2433 | { INDEX_op_qemu_st_i64, { "S", "S" } }, | |
2434 | #elif TARGET_LONG_BITS == 32 | |
2435 | { INDEX_op_qemu_ld_i32, { "r", "L" } }, | |
2436 | { INDEX_op_qemu_st_i32, { "S", "S" } }, | |
7f25c469 | 2437 | { INDEX_op_qemu_ld_i64, { "L", "L", "L" } }, |
796f1a68 RH |
2438 | { INDEX_op_qemu_st_i64, { "S", "S", "S" } }, |
2439 | #else | |
2440 | { INDEX_op_qemu_ld_i32, { "r", "L", "L" } }, | |
2441 | { INDEX_op_qemu_st_i32, { "S", "S", "S" } }, | |
7f25c469 | 2442 | { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } }, |
796f1a68 RH |
2443 | { INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } }, |
2444 | #endif | |
6c858762 | 2445 | |
810260a8 | 2446 | { -1 }, |
2447 | }; | |
2448 | ||
541dd4ce | 2449 | static void tcg_target_init(TCGContext *s) |
810260a8 | 2450 | { |
cd629de1 | 2451 | unsigned long hwcap = qemu_getauxval(AT_HWCAP); |
1e6e9aca RH |
2452 | if (hwcap & PPC_FEATURE_ARCH_2_06) { |
2453 | have_isa_2_06 = true; | |
2454 | } | |
1e6e9aca | 2455 | |
541dd4ce RH |
2456 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
2457 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); | |
2458 | tcg_regset_set32(tcg_target_call_clobber_regs, 0, | |
810260a8 | 2459 | (1 << TCG_REG_R0) | |
5d7ff5bb | 2460 | (1 << TCG_REG_R2) | |
810260a8 | 2461 | (1 << TCG_REG_R3) | |
2462 | (1 << TCG_REG_R4) | | |
2463 | (1 << TCG_REG_R5) | | |
2464 | (1 << TCG_REG_R6) | | |
2465 | (1 << TCG_REG_R7) | | |
2466 | (1 << TCG_REG_R8) | | |
2467 | (1 << TCG_REG_R9) | | |
2468 | (1 << TCG_REG_R10) | | |
2469 | (1 << TCG_REG_R11) | | |
5e1702b0 | 2470 | (1 << TCG_REG_R12)); |
810260a8 | 2471 | |
541dd4ce | 2472 | tcg_regset_clear(s->reserved_regs); |
5e1702b0 RH |
2473 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ |
2474 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ | |
dfca1778 RH |
2475 | #if defined(_CALL_SYSV) |
2476 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ | |
5d7ff5bb | 2477 | #endif |
dfca1778 | 2478 | #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64 |
5e1702b0 | 2479 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ |
dfca1778 RH |
2480 | #endif |
2481 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ | |
810260a8 | 2482 | |
541dd4ce | 2483 | tcg_add_target_add_op_defs(ppc_op_defs); |
810260a8 | 2484 | } |
fa94c3be | 2485 | |
ffcfbece | 2486 | #ifdef __ELF__ |
fa94c3be RH |
2487 | typedef struct { |
2488 | DebugFrameCIE cie; | |
2489 | DebugFrameFDEHeader fde; | |
2490 | uint8_t fde_def_cfa[4]; | |
2491 | uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3]; | |
2492 | } DebugFrame; | |
2493 | ||
2494 | /* We're expecting a 2 byte uleb128 encoded value. */ | |
2495 | QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); | |
2496 | ||
ffcfbece RH |
2497 | #if TCG_TARGET_REG_BITS == 64 |
2498 | # define ELF_HOST_MACHINE EM_PPC64 | |
2499 | #else | |
2500 | # define ELF_HOST_MACHINE EM_PPC | |
2501 | #endif | |
fa94c3be RH |
2502 | |
2503 | static DebugFrame debug_frame = { | |
2504 | .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ | |
2505 | .cie.id = -1, | |
2506 | .cie.version = 1, | |
2507 | .cie.code_align = 1, | |
802ca56e | 2508 | .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */ |
fa94c3be RH |
2509 | .cie.return_column = 65, |
2510 | ||
2511 | /* Total FDE size does not include the "len" member. */ | |
2512 | .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), | |
2513 | ||
2514 | .fde_def_cfa = { | |
802ca56e | 2515 | 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */ |
fa94c3be RH |
2516 | (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ |
2517 | (FRAME_SIZE >> 7) | |
2518 | }, | |
2519 | .fde_reg_ofs = { | |
802ca56e RH |
2520 | /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */ |
2521 | 0x11, 65, (LR_OFFSET / -SZR) & 0x7f, | |
fa94c3be RH |
2522 | } |
2523 | }; | |
2524 | ||
2525 | void tcg_register_jit(void *buf, size_t buf_size) | |
2526 | { | |
2527 | uint8_t *p = &debug_frame.fde_reg_ofs[3]; | |
2528 | int i; | |
2529 | ||
2530 | for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) { | |
2531 | p[0] = 0x80 + tcg_target_callee_save_regs[i]; | |
802ca56e | 2532 | p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR; |
fa94c3be RH |
2533 | } |
2534 | ||
802ca56e | 2535 | debug_frame.fde.func_start = (uintptr_t)buf; |
fa94c3be RH |
2536 | debug_frame.fde.func_len = buf_size; |
2537 | ||
2538 | tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); | |
2539 | } | |
ffcfbece | 2540 | #endif /* __ELF__ */ |