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505e75c5
AF		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2018 SiFive, Inc
5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
7 * Copyright (c) 2008 Fabrice Bellard
8 *
9 * Based on i386/tcg-target.c and mips/tcg-target.c
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a copy
12 * of this software and associated documentation files (the "Software"), to deal
13 * in the Software without restriction, including without limitation the rights
14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15 * copies of the Software, and to permit persons to whom the Software is
16 * furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice shall be included in
19 * all copies or substantial portions of the Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * THE SOFTWARE.
28 */
29
30#include "tcg-pool.inc.c"
31
32#ifdef CONFIG_DEBUG_TCG
33static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34 "zero",
35 "ra",
36 "sp",
37 "gp",
38 "tp",
39 "t0",
40 "t1",
41 "t2",
42 "s0",
43 "s1",
44 "a0",
45 "a1",
46 "a2",
47 "a3",
48 "a4",
49 "a5",
50 "a6",
51 "a7",
52 "s2",
53 "s3",
54 "s4",
55 "s5",
56 "s6",
57 "s7",
58 "s8",
59 "s9",
60 "s10",
61 "s11",
62 "t3",
63 "t4",
64 "t5",
65 "t6"
66};
67#endif
68
69static const int tcg_target_reg_alloc_order[] = {
70 /* Call saved registers */
71 /* TCG_REG_S0 reservered for TCG_AREG0 */
72 TCG_REG_S1,
73 TCG_REG_S2,
74 TCG_REG_S3,
75 TCG_REG_S4,
76 TCG_REG_S5,
77 TCG_REG_S6,
78 TCG_REG_S7,
79 TCG_REG_S8,
80 TCG_REG_S9,
81 TCG_REG_S10,
82 TCG_REG_S11,
83
84 /* Call clobbered registers */
85 TCG_REG_T0,
86 TCG_REG_T1,
87 TCG_REG_T2,
88 TCG_REG_T3,
89 TCG_REG_T4,
90 TCG_REG_T5,
91 TCG_REG_T6,
92
93 /* Argument registers */
94 TCG_REG_A0,
95 TCG_REG_A1,
96 TCG_REG_A2,
97 TCG_REG_A3,
98 TCG_REG_A4,
99 TCG_REG_A5,
100 TCG_REG_A6,
101 TCG_REG_A7,
102};
103
104static const int tcg_target_call_iarg_regs[] = {
105 TCG_REG_A0,
106 TCG_REG_A1,
107 TCG_REG_A2,
108 TCG_REG_A3,
109 TCG_REG_A4,
110 TCG_REG_A5,
111 TCG_REG_A6,
112 TCG_REG_A7,
113};
114
115static const int tcg_target_call_oarg_regs[] = {
116 TCG_REG_A0,
117 TCG_REG_A1,
118};
8ce23a13
AF		 119
120#define TCG_CT_CONST_ZERO 0x100
121#define TCG_CT_CONST_S12 0x200
122#define TCG_CT_CONST_N12 0x400
123#define TCG_CT_CONST_M12 0x800
124
125static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
126{
127 if (TCG_TARGET_REG_BITS == 32) {
128 return sextract32(val, pos, len);
129 } else {
130 return sextract64(val, pos, len);
131 }
132}
133
134/* parse target specific constraints */
135static const char *target_parse_constraint(TCGArgConstraint *ct,
136 const char *ct_str, TCGType type)
137{
138 switch (*ct_str++) {
139 case 'r':
140 ct->ct |= TCG_CT_REG;
141 ct->u.regs = 0xffffffff;
142 break;
143 case 'L':
144 /* qemu_ld/qemu_st constraint */
145 ct->ct |= TCG_CT_REG;
146 ct->u.regs = 0xffffffff;
147 /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
148#if defined(CONFIG_SOFTMMU)
149 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
150 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
151 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
152 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
153 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
154#endif
155 break;
156 case 'I':
157 ct->ct |= TCG_CT_CONST_S12;
158 break;
159 case 'N':
160 ct->ct |= TCG_CT_CONST_N12;
161 break;
162 case 'M':
163 ct->ct |= TCG_CT_CONST_M12;
164 break;
165 case 'Z':
166 /* we can use a zero immediate as a zero register argument. */
167 ct->ct |= TCG_CT_CONST_ZERO;
168 break;
169 default:
170 return NULL;
171 }
172 return ct_str;
173}
174
175/* test if a constant matches the constraint */
176static int tcg_target_const_match(tcg_target_long val, TCGType type,
177 const TCGArgConstraint *arg_ct)
178{
179 int ct = arg_ct->ct;
180 if (ct & TCG_CT_CONST) {
181 return 1;
182 }
183 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
184 return 1;
185 }
186 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
187 return 1;
188 }
189 if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
190 return 1;
191 }
192 if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
193 return 1;
194 }
195 return 0;
196}
197
198/*
199 * RISC-V Base ISA opcodes (IM)
200 */
201
202typedef enum {
203 OPC_ADD = 0x33,
204 OPC_ADDI = 0x13,
205 OPC_AND = 0x7033,
206 OPC_ANDI = 0x7013,
207 OPC_AUIPC = 0x17,
208 OPC_BEQ = 0x63,
209 OPC_BGE = 0x5063,
210 OPC_BGEU = 0x7063,
211 OPC_BLT = 0x4063,
212 OPC_BLTU = 0x6063,
213 OPC_BNE = 0x1063,
214 OPC_DIV = 0x2004033,
215 OPC_DIVU = 0x2005033,
216 OPC_JAL = 0x6f,
217 OPC_JALR = 0x67,
218 OPC_LB = 0x3,
219 OPC_LBU = 0x4003,
220 OPC_LD = 0x3003,
221 OPC_LH = 0x1003,
222 OPC_LHU = 0x5003,
223 OPC_LUI = 0x37,
224 OPC_LW = 0x2003,
225 OPC_LWU = 0x6003,
226 OPC_MUL = 0x2000033,
227 OPC_MULH = 0x2001033,
228 OPC_MULHSU = 0x2002033,
229 OPC_MULHU = 0x2003033,
230 OPC_OR = 0x6033,
231 OPC_ORI = 0x6013,
232 OPC_REM = 0x2006033,
233 OPC_REMU = 0x2007033,
234 OPC_SB = 0x23,
235 OPC_SD = 0x3023,
236 OPC_SH = 0x1023,
237 OPC_SLL = 0x1033,
238 OPC_SLLI = 0x1013,
239 OPC_SLT = 0x2033,
240 OPC_SLTI = 0x2013,
241 OPC_SLTIU = 0x3013,
242 OPC_SLTU = 0x3033,
243 OPC_SRA = 0x40005033,
244 OPC_SRAI = 0x40005013,
245 OPC_SRL = 0x5033,
246 OPC_SRLI = 0x5013,
247 OPC_SUB = 0x40000033,
248 OPC_SW = 0x2023,
249 OPC_XOR = 0x4033,
250 OPC_XORI = 0x4013,
251
252#if TCG_TARGET_REG_BITS == 64
253 OPC_ADDIW = 0x1b,
254 OPC_ADDW = 0x3b,
255 OPC_DIVUW = 0x200503b,
256 OPC_DIVW = 0x200403b,
257 OPC_MULW = 0x200003b,
258 OPC_REMUW = 0x200703b,
259 OPC_REMW = 0x200603b,
260 OPC_SLLIW = 0x101b,
261 OPC_SLLW = 0x103b,
262 OPC_SRAIW = 0x4000501b,
263 OPC_SRAW = 0x4000503b,
264 OPC_SRLIW = 0x501b,
265 OPC_SRLW = 0x503b,
266 OPC_SUBW = 0x4000003b,
267#else
268 /* Simplify code throughout by defining aliases for RV32. */
269 OPC_ADDIW = OPC_ADDI,
270 OPC_ADDW = OPC_ADD,
271 OPC_DIVUW = OPC_DIVU,
272 OPC_DIVW = OPC_DIV,
273 OPC_MULW = OPC_MUL,
274 OPC_REMUW = OPC_REMU,
275 OPC_REMW = OPC_REM,
276 OPC_SLLIW = OPC_SLLI,
277 OPC_SLLW = OPC_SLL,
278 OPC_SRAIW = OPC_SRAI,
279 OPC_SRAW = OPC_SRA,
280 OPC_SRLIW = OPC_SRLI,
281 OPC_SRLW = OPC_SRL,
282 OPC_SUBW = OPC_SUB,
283#endif
284
285 OPC_FENCE = 0x0000000f,
286} RISCVInsn;
54a9ce0f
AF		 287
288/*
289 * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
290 */
291
292/* Type-R */
293
294static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
295{
296 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
297}
298
299/* Type-I */
300
301static int32_t encode_imm12(uint32_t imm)
302{
303 return (imm & 0xfff) << 20;
304}
305
306static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
307{
308 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
309}
310
311/* Type-S */
312
313static int32_t encode_simm12(uint32_t imm)
314{
315 int32_t ret = 0;
316
317 ret |= (imm & 0xFE0) << 20;
318 ret |= (imm & 0x1F) << 7;
319
320 return ret;
321}
322
323static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
324{
325 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
326}
327
328/* Type-SB */
329
330static int32_t encode_sbimm12(uint32_t imm)
331{
332 int32_t ret = 0;
333
334 ret |= (imm & 0x1000) << 19;
335 ret |= (imm & 0x7e0) << 20;
336 ret |= (imm & 0x1e) << 7;
337 ret |= (imm & 0x800) >> 4;
338
339 return ret;
340}
341
342static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
343{
344 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
345}
346
347/* Type-U */
348
349static int32_t encode_uimm20(uint32_t imm)
350{
351 return imm & 0xfffff000;
352}
353
354static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
355{
356 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
357}
358
359/* Type-UJ */
360
361static int32_t encode_ujimm20(uint32_t imm)
362{
363 int32_t ret = 0;
364
365 ret |= (imm & 0x0007fe) << (21 - 1);
366 ret |= (imm & 0x000800) << (20 - 11);
367 ret |= (imm & 0x0ff000) << (12 - 12);
368 ret |= (imm & 0x100000) << (31 - 20);
369
370 return ret;
371}
372
373static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm)
374{
375 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
376}
bedf14e3
AF		 377
378/*
379 * RISC-V instruction emitters
380 */
381
382static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
383 TCGReg rd, TCGReg rs1, TCGReg rs2)
384{
385 tcg_out32(s, encode_r(opc, rd, rs1, rs2));
386}
387
388static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
389 TCGReg rd, TCGReg rs1, TCGArg imm)
390{
391 tcg_out32(s, encode_i(opc, rd, rs1, imm));
392}
393
394static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
395 TCGReg rs1, TCGReg rs2, uint32_t imm)
396{
397 tcg_out32(s, encode_s(opc, rs1, rs2, imm));
398}
399
400static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
401 TCGReg rs1, TCGReg rs2, uint32_t imm)
402{
403 tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
404}
405
406static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
407 TCGReg rd, uint32_t imm)
408{
409 tcg_out32(s, encode_u(opc, rd, imm));
410}
411
412static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
413 TCGReg rd, uint32_t imm)
414{
415 tcg_out32(s, encode_uj(opc, rd, imm));
416}
417
418static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
419{
420 int i;
421 for (i = 0; i < count; ++i) {
422 p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
423 }
424}
dfa8e74f
AF		 425
426/*
427 * Relocations
428 */
429
430static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
431{
432 intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
433
434 if (offset == sextreg(offset, 1, 12) << 1) {
435 code_ptr[0] |= encode_sbimm12(offset);
436 return true;
437 }
438
439 return false;
440}
441
442static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
443{
444 intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
445
446 if (offset == sextreg(offset, 1, 20) << 1) {
447 code_ptr[0] |= encode_ujimm20(offset);
448 return true;
449 }
450
451 return false;
452}
453
454static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
455{
456 intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
457 int32_t lo = sextreg(offset, 0, 12);
458 int32_t hi = offset - lo;
459
460 if (offset == hi + lo) {
461 code_ptr[0] |= encode_uimm20(hi);
462 code_ptr[1] |= encode_imm12(lo);
463 return true;
464 }
465
466 return false;
467}
468
469static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
470 intptr_t value, intptr_t addend)
471{
472 uint32_t insn = *code_ptr;
473 intptr_t diff;
474 bool short_jmp;
475
476 tcg_debug_assert(addend == 0);
477
478 switch (type) {
479 case R_RISCV_BRANCH:
480 diff = value - (uintptr_t)code_ptr;
481 short_jmp = diff == sextreg(diff, 0, 12);
482 if (short_jmp) {
483 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
484 } else {
485 /* Invert the condition */
486 insn = insn ^ (1 << 12);
487 /* Clear the offset */
488 insn &= 0x01fff07f;
489 /* Set the offset to the PC + 8 */
490 insn |= encode_sbimm12(8);
491
492 /* Move forward */
493 code_ptr[0] = insn;
494
495 /* Overwrite the NOP with jal x0,value */
496 diff = value - (uintptr_t)(code_ptr + 1);
497 insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff);
498 code_ptr[1] = insn;
499
500 return true;
501 }
502 break;
503 case R_RISCV_JAL:
504 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
505 break;
506 case R_RISCV_CALL:
507 return reloc_call(code_ptr, (tcg_insn_unit *)value);
508 break;
509 default:
510 tcg_abort();
511 }
512}
6cd2eda3
AF		 513
514/*
515 * TCG intrinsics
516 */
517
78113e83 518static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
6cd2eda3
AF		 519{
520 if (ret == arg) {
78113e83 521 return true;
6cd2eda3
AF		 522 }
523 switch (type) {
524 case TCG_TYPE_I32:
525 case TCG_TYPE_I64:
526 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
527 break;
528 default:
529 g_assert_not_reached();
530 }
78113e83 531 return true;
6cd2eda3
AF		 532}
533
534static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
535 tcg_target_long val)
536{
537 tcg_target_long lo, hi, tmp;
538 int shift, ret;
539
540 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
541 val = (int32_t)val;
542 }
543
544 lo = sextreg(val, 0, 12);
545 if (val == lo) {
546 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo);
547 return;
548 }
549
550 hi = val - lo;
551 if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) {
552 tcg_out_opc_upper(s, OPC_LUI, rd, hi);
553 if (lo != 0) {
554 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo);
555 }
556 return;
557 }
558
559 /* We can only be here if TCG_TARGET_REG_BITS != 32 */
560 tmp = tcg_pcrel_diff(s, (void *)val);
561 if (tmp == (int32_t)tmp) {
562 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
563 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
564 ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val);
565 tcg_debug_assert(ret == true);
566 return;
567 }
568
569 /* Look for a single 20-bit section. */
570 shift = ctz64(val);
571 tmp = val >> shift;
572 if (tmp == sextreg(tmp, 0, 20)) {
573 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12);
574 if (shift > 12) {
575 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12);
576 } else {
577 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift);
578 }
579 return;
580 }
581
582 /* Look for a few high zero bits, with lots of bits set in the middle. */
583 shift = clz64(val);
584 tmp = val << shift;
585 if (tmp == sextreg(tmp, 12, 20) << 12) {
586 tcg_out_opc_upper(s, OPC_LUI, rd, tmp);
587 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
588 return;
589 } else if (tmp == sextreg(tmp, 0, 12)) {
590 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp);
591 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
592 return;
593 }
594
595 /* Drop into the constant pool. */
596 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0);
597 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
598 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
599}
27fd6414
AF		 600
601static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
602{
603 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
604}
605
606static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
607{
608 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
609 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
610}
611
612static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
613{
614 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
615 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
616}
617
618static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
619{
620 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
621 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
622}
623
624static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
625{
626 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
627 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
628}
629
630static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
631{
632 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
633}
61535d49
AF		 634
635static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
636 TCGReg addr, intptr_t offset)
637{
638 intptr_t imm12 = sextreg(offset, 0, 12);
639
640 if (offset != imm12) {
641 intptr_t diff = offset - (uintptr_t)s->code_ptr;
642
643 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
644 imm12 = sextreg(diff, 0, 12);
645 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12);
646 } else {
647 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
648 if (addr != TCG_REG_ZERO) {
649 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
650 }
651 }
652 addr = TCG_REG_TMP2;
653 }
654
655 switch (opc) {
656 case OPC_SB:
657 case OPC_SH:
658 case OPC_SW:
659 case OPC_SD:
660 tcg_out_opc_store(s, opc, addr, data, imm12);
661 break;
662 case OPC_LB:
663 case OPC_LBU:
664 case OPC_LH:
665 case OPC_LHU:
666 case OPC_LW:
667 case OPC_LWU:
668 case OPC_LD:
669 tcg_out_opc_imm(s, opc, data, addr, imm12);
670 break;
671 default:
672 g_assert_not_reached();
673 }
674}
675
676static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
677 TCGReg arg1, intptr_t arg2)
678{
679 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
680 tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
681}
682
683static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
684 TCGReg arg1, intptr_t arg2)
685{
686 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
687 tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
688}
689
690static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
691 TCGReg base, intptr_t ofs)
692{
693 if (val == 0) {
694 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
695 return true;
696 }
697 return false;
698}
28ca738e
AF		 699
700static void tcg_out_addsub2(TCGContext *s,
701 TCGReg rl, TCGReg rh,
702 TCGReg al, TCGReg ah,
703 TCGArg bl, TCGArg bh,
704 bool cbl, bool cbh, bool is_sub, bool is32bit)
705{
706 const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD;
707 const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI;
708 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB;
709 TCGReg th = TCG_REG_TMP1;
710
711 /* If we have a negative constant such that negating it would
712 make the high part zero, we can (usually) eliminate one insn. */
713 if (cbl && cbh && bh == -1 && bl != 0) {
714 bl = -bl;
715 bh = 0;
716 is_sub = !is_sub;
717 }
718
719 /* By operating on the high part first, we get to use the final
720 carry operation to move back from the temporary. */
721 if (!cbh) {
722 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
723 } else if (bh != 0 || ah == rl) {
724 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
725 } else {
726 th = ah;
727 }
728
729 /* Note that tcg optimization should eliminate the bl == 0 case. */
730 if (is_sub) {
731 if (cbl) {
732 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl);
733 tcg_out_opc_imm(s, opc_addi, rl, al, -bl);
734 } else {
735 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl);
736 tcg_out_opc_reg(s, opc_sub, rl, al, bl);
737 }
738 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0);
739 } else {
740 if (cbl) {
741 tcg_out_opc_imm(s, opc_addi, rl, al, bl);
742 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
743 } else if (rl == al && rl == bl) {
744 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
745 tcg_out_opc_reg(s, opc_addi, rl, al, bl);
746 } else {
747 tcg_out_opc_reg(s, opc_add, rl, al, bl);
748 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
749 rl, (rl == bl ? al : bl));
750 }
751 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
752 }
753}
15840069
AF		 754
755static const struct {
756 RISCVInsn op;
757 bool swap;
758} tcg_brcond_to_riscv[] = {
759 [TCG_COND_EQ] = { OPC_BEQ, false },
760 [TCG_COND_NE] = { OPC_BNE, false },
761 [TCG_COND_LT] = { OPC_BLT, false },
762 [TCG_COND_GE] = { OPC_BGE, false },
763 [TCG_COND_LE] = { OPC_BGE, true },
764 [TCG_COND_GT] = { OPC_BLT, true },
765 [TCG_COND_LTU] = { OPC_BLTU, false },
766 [TCG_COND_GEU] = { OPC_BGEU, false },
767 [TCG_COND_LEU] = { OPC_BGEU, true },
768 [TCG_COND_GTU] = { OPC_BLTU, true }
769};
770
771static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
772 TCGReg arg2, TCGLabel *l)
773{
774 RISCVInsn op = tcg_brcond_to_riscv[cond].op;
775
776 tcg_debug_assert(op != 0);
777
778 if (tcg_brcond_to_riscv[cond].swap) {
779 TCGReg t = arg1;
780 arg1 = arg2;
781 arg2 = t;
782 }
783
784 if (l->has_value) {
785 intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr);
786 if (diff == sextreg(diff, 0, 12)) {
787 tcg_out_opc_branch(s, op, arg1, arg2, diff);
788 } else {
789 /* Invert the conditional branch. */
790 tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8);
791 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4);
792 }
793 } else {
794 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0);
795 tcg_out_opc_branch(s, op, arg1, arg2, 0);
796 /* NOP to allow patching later */
797 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
798 }
799}
800
801static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
802 TCGReg arg1, TCGReg arg2)
803{
804 switch (cond) {
805 case TCG_COND_EQ:
806 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
807 tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
808 break;
809 case TCG_COND_NE:
810 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
811 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
812 break;
813 case TCG_COND_LT:
814 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
815 break;
816 case TCG_COND_GE:
817 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
818 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
819 break;
820 case TCG_COND_LE:
821 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
822 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
823 break;
824 case TCG_COND_GT:
825 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
826 break;
827 case TCG_COND_LTU:
828 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
829 break;
830 case TCG_COND_GEU:
831 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
832 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
833 break;
834 case TCG_COND_LEU:
835 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
836 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
837 break;
838 case TCG_COND_GTU:
839 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
840 break;
841 default:
842 g_assert_not_reached();
843 break;
844 }
845}
846
847static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
848 TCGReg bl, TCGReg bh, TCGLabel *l)
849{
850 /* todo */
851 g_assert_not_reached();
852}
853
854static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
855 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
856{
857 /* todo */
858 g_assert_not_reached();
859}
860
861static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
862{
863 ptrdiff_t offset = tcg_pcrel_diff(s, target);
864 tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1);
865 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset);
866}
867
868static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
869{
870 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
871 ptrdiff_t offset = tcg_pcrel_diff(s, arg);
872 int ret;
873
874 if (offset == sextreg(offset, 1, 20) << 1) {
875 /* short jump: -2097150 to 2097152 */
876 tcg_out_opc_jump(s, OPC_JAL, link, offset);
877 } else if (TCG_TARGET_REG_BITS == 32 ||
878 offset == sextreg(offset, 1, 31) << 1) {
879 /* long jump: -2147483646 to 2147483648 */
880 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
881 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
882 ret = reloc_call(s->code_ptr - 2, arg);\
883 tcg_debug_assert(ret == true);
884 } else if (TCG_TARGET_REG_BITS == 64) {
885 /* far jump: 64-bit */
886 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
887 tcg_target_long base = (tcg_target_long)arg - imm;
888 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
889 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
890 } else {
891 g_assert_not_reached();
892 }
893}
894
895static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
896{
897 tcg_out_call_int(s, arg, false);
898}
efbea94c
AF		 899
900static void tcg_out_mb(TCGContext *s, TCGArg a0)
901{
902 tcg_insn_unit insn = OPC_FENCE;
903
904 if (a0 & TCG_MO_LD_LD) {
905 insn |= 0x02200000;
906 }
907 if (a0 & TCG_MO_ST_LD) {
908 insn |= 0x01200000;
909 }
910 if (a0 & TCG_MO_LD_ST) {
911 insn |= 0x02100000;
912 }
913 if (a0 & TCG_MO_ST_ST) {
914 insn |= 0x02200000;
915 }
916 tcg_out32(s, insn);
917}
918
919/*
920 * Load/store and TLB
921 */
922
923#if defined(CONFIG_SOFTMMU)
924#include "tcg-ldst.inc.c"
925
926/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
927 * TCGMemOpIdx oi, uintptr_t ra)
928 */
929static void * const qemu_ld_helpers[16] = {
930 [MO_UB] = helper_ret_ldub_mmu,
931 [MO_SB] = helper_ret_ldsb_mmu,
932 [MO_LEUW] = helper_le_lduw_mmu,
933 [MO_LESW] = helper_le_ldsw_mmu,
934 [MO_LEUL] = helper_le_ldul_mmu,
935#if TCG_TARGET_REG_BITS == 64
936 [MO_LESL] = helper_le_ldsl_mmu,
937#endif
938 [MO_LEQ] = helper_le_ldq_mmu,
939 [MO_BEUW] = helper_be_lduw_mmu,
940 [MO_BESW] = helper_be_ldsw_mmu,
941 [MO_BEUL] = helper_be_ldul_mmu,
942#if TCG_TARGET_REG_BITS == 64
943 [MO_BESL] = helper_be_ldsl_mmu,
944#endif
945 [MO_BEQ] = helper_be_ldq_mmu,
946};
947
948/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
949 * uintxx_t val, TCGMemOpIdx oi,
950 * uintptr_t ra)
951 */
952static void * const qemu_st_helpers[16] = {
953 [MO_UB] = helper_ret_stb_mmu,
954 [MO_LEUW] = helper_le_stw_mmu,
955 [MO_LEUL] = helper_le_stl_mmu,
956 [MO_LEQ] = helper_le_stq_mmu,
957 [MO_BEUW] = helper_be_stw_mmu,
958 [MO_BEUL] = helper_be_stl_mmu,
959 [MO_BEQ] = helper_be_stq_mmu,
960};
961
41b70f22
RH		 962/* We don't support oversize guests */
963QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS);
964
efbea94c
AF		 965static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
966 TCGReg addrh, TCGMemOpIdx oi,
967 tcg_insn_unit **label_ptr, bool is_load)
968{
969 TCGMemOp opc = get_memop(oi);
970 unsigned s_bits = opc & MO_SIZE;
971 unsigned a_bits = get_alignment_bits(opc);
41b70f22 972 tcg_target_long compare_mask;
efbea94c 973 int mem_index = get_mmuidx(oi);
41b70f22
RH		 974 int mask_off, table_off;
975 TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
976
a40ec84e
RH		 977 mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
978 table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
41b70f22
RH		 979 if (table_off > 0x7ff) {
980 int mask_hi = mask_off - sextreg(mask_off, 0, 12);
981 int table_hi = table_off - sextreg(table_off, 0, 12);
982
983 if (likely(mask_hi == table_hi)) {
984 mask_base = table_base = TCG_REG_TMP1;
985 tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi);
986 tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0);
987 mask_off -= mask_hi;
988 table_off -= mask_hi;
efbea94c 989 } else {
41b70f22
RH		 990 mask_base = TCG_REG_TMP0;
991 table_base = TCG_REG_TMP1;
992 tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi);
993 tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0);
994 table_off -= mask_off;
995 mask_off -= mask_hi;
996 tcg_out_opc_imm(s, OPC_ADDI, table_base, mask_base, mask_off);
efbea94c 997 }
efbea94c
AF		 998 }
999
41b70f22
RH		 1000 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off);
1001 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off);
efbea94c 1002
41b70f22
RH		 1003 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl,
1004 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1005 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
1006 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
efbea94c
AF		 1007
1008 /* Load the tlb comparator and the addend. */
41b70f22
RH		 1009 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
1010 is_load ? offsetof(CPUTLBEntry, addr_read)
1011 : offsetof(CPUTLBEntry, addr_write));
1012 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
1013 offsetof(CPUTLBEntry, addend));
efbea94c 1014
41b70f22
RH		 1015 /* We don't support unaligned accesses. */
1016 if (a_bits < s_bits) {
1017 a_bits = s_bits;
1018 }
efbea94c 1019 /* Clear the non-page, non-alignment bits from the address. */
41b70f22
RH		 1020 compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
1021 if (compare_mask == sextreg(compare_mask, 0, 12)) {
1022 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask);
efbea94c 1023 } else {
41b70f22 1024 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
efbea94c 1025 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl);
41b70f22 1026 }
efbea94c
AF		 1027
1028 /* Compare masked address with the TLB entry. */
1029 label_ptr[0] = s->code_ptr;
1030 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
1031 /* NOP to allow patching later */
1032 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
efbea94c
AF		 1033
1034 /* TLB Hit - translate address using addend. */
1035 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1036 tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
1037 addrl = TCG_REG_TMP0;
1038 }
1039 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
1040}
1041
1042static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1043 TCGType ext,
1044 TCGReg datalo, TCGReg datahi,
1045 TCGReg addrlo, TCGReg addrhi,
1046 void *raddr, tcg_insn_unit **label_ptr)
1047{
1048 TCGLabelQemuLdst *label = new_ldst_label(s);
1049
1050 label->is_ld = is_ld;
1051 label->oi = oi;
1052 label->type = ext;
1053 label->datalo_reg = datalo;
1054 label->datahi_reg = datahi;
1055 label->addrlo_reg = addrlo;
1056 label->addrhi_reg = addrhi;
1057 label->raddr = raddr;
1058 label->label_ptr[0] = label_ptr[0];
1059}
1060
aeee05f5 1061static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
efbea94c
AF		 1062{
1063 TCGMemOpIdx oi = l->oi;
1064 TCGMemOp opc = get_memop(oi);
1065 TCGReg a0 = tcg_target_call_iarg_regs[0];
1066 TCGReg a1 = tcg_target_call_iarg_regs[1];
1067 TCGReg a2 = tcg_target_call_iarg_regs[2];
1068 TCGReg a3 = tcg_target_call_iarg_regs[3];
1069
1070 /* We don't support oversize guests */
1071 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1072 g_assert_not_reached();
1073 }
1074
1075 /* resolve label address */
aeee05f5
RH		 1076 if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
1077 (intptr_t) s->code_ptr, 0)) {
1078 return false;
1079 }
efbea94c
AF		 1080
1081 /* call load helper */
1082 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
1083 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
1084 tcg_out_movi(s, TCG_TYPE_PTR, a2, oi);
1085 tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr);
1086
1087 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
1088 tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
1089
1090 tcg_out_goto(s, l->raddr);
aeee05f5 1091 return true;
efbea94c
AF		 1092}
1093
aeee05f5 1094static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
efbea94c
AF		 1095{
1096 TCGMemOpIdx oi = l->oi;
1097 TCGMemOp opc = get_memop(oi);
1098 TCGMemOp s_bits = opc & MO_SIZE;
1099 TCGReg a0 = tcg_target_call_iarg_regs[0];
1100 TCGReg a1 = tcg_target_call_iarg_regs[1];
1101 TCGReg a2 = tcg_target_call_iarg_regs[2];
1102 TCGReg a3 = tcg_target_call_iarg_regs[3];
1103 TCGReg a4 = tcg_target_call_iarg_regs[4];
1104
1105 /* We don't support oversize guests */
1106 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1107 g_assert_not_reached();
1108 }
1109
1110 /* resolve label address */
aeee05f5
RH		 1111 if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
1112 (intptr_t) s->code_ptr, 0)) {
1113 return false;
1114 }
efbea94c
AF		 1115
1116 /* call store helper */
1117 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
1118 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
1119 tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg);
1120 switch (s_bits) {
1121 case MO_8:
1122 tcg_out_ext8u(s, a2, a2);
1123 break;
1124 case MO_16:
1125 tcg_out_ext16u(s, a2, a2);
1126 break;
1127 default:
1128 break;
1129 }
1130 tcg_out_movi(s, TCG_TYPE_PTR, a3, oi);
1131 tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr);
1132
1133 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
1134
1135 tcg_out_goto(s, l->raddr);
aeee05f5 1136 return true;
efbea94c
AF		 1137}
1138#endif /* CONFIG_SOFTMMU */
03a7d021
AF		 1139
1140static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1141 TCGReg base, TCGMemOp opc, bool is_64)
1142{
1143 const TCGMemOp bswap = opc & MO_BSWAP;
1144
1145 /* We don't yet handle byteswapping, assert */
1146 g_assert(!bswap);
1147
1148 switch (opc & (MO_SSIZE)) {
1149 case MO_UB:
1150 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1151 break;
1152 case MO_SB:
1153 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1154 break;
1155 case MO_UW:
1156 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1157 break;
1158 case MO_SW:
1159 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1160 break;
1161 case MO_UL:
1162 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1163 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1164 break;
1165 }
1166 /* FALLTHRU */
1167 case MO_SL:
1168 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1169 break;
1170 case MO_Q:
1171 /* Prefer to load from offset 0 first, but allow for overlap. */
1172 if (TCG_TARGET_REG_BITS == 64) {
1173 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1174 } else if (lo != base) {
1175 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1176 tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
1177 } else {
1178 tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
1179 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1180 }
1181 break;
1182 default:
1183 g_assert_not_reached();
1184 }
1185}
1186
1187static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1188{
1189 TCGReg addr_regl, addr_regh __attribute__((unused));
1190 TCGReg data_regl, data_regh;
1191 TCGMemOpIdx oi;
1192 TCGMemOp opc;
1193#if defined(CONFIG_SOFTMMU)
1194 tcg_insn_unit *label_ptr[1];
1195#endif
1196 TCGReg base = TCG_REG_TMP0;
1197
1198 data_regl = *args++;
1199 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1200 addr_regl = *args++;
1201 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1202 oi = *args++;
1203 opc = get_memop(oi);
1204
1205#if defined(CONFIG_SOFTMMU)
1206 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
1207 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1208 add_qemu_ldst_label(s, 1, oi,
1209 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1210 data_regl, data_regh, addr_regl, addr_regh,
1211 s->code_ptr, label_ptr);
1212#else
1213 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1214 tcg_out_ext32u(s, base, addr_regl);
1215 addr_regl = base;
1216 }
1217
1218 if (guest_base == 0) {
1219 tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
1220 } else {
1221 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
1222 }
1223 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1224#endif
1225}
1226
1227static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1228 TCGReg base, TCGMemOp opc)
1229{
1230 const TCGMemOp bswap = opc & MO_BSWAP;
1231
1232 /* We don't yet handle byteswapping, assert */
1233 g_assert(!bswap);
1234
1235 switch (opc & (MO_SSIZE)) {
1236 case MO_8:
1237 tcg_out_opc_store(s, OPC_SB, base, lo, 0);
1238 break;
1239 case MO_16:
1240 tcg_out_opc_store(s, OPC_SH, base, lo, 0);
1241 break;
1242 case MO_32:
1243 tcg_out_opc_store(s, OPC_SW, base, lo, 0);
1244 break;
1245 case MO_64:
1246 if (TCG_TARGET_REG_BITS == 64) {
1247 tcg_out_opc_store(s, OPC_SD, base, lo, 0);
1248 } else {
1249 tcg_out_opc_store(s, OPC_SW, base, lo, 0);
1250 tcg_out_opc_store(s, OPC_SW, base, hi, 4);
1251 }
1252 break;
1253 default:
1254 g_assert_not_reached();
1255 }
1256}
1257
1258static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1259{
1260 TCGReg addr_regl, addr_regh __attribute__((unused));
1261 TCGReg data_regl, data_regh;
1262 TCGMemOpIdx oi;
1263 TCGMemOp opc;
1264#if defined(CONFIG_SOFTMMU)
1265 tcg_insn_unit *label_ptr[1];
1266#endif
1267 TCGReg base = TCG_REG_TMP0;
1268
1269 data_regl = *args++;
1270 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1271 addr_regl = *args++;
1272 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1273 oi = *args++;
1274 opc = get_memop(oi);
1275
1276#if defined(CONFIG_SOFTMMU)
1277 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
1278 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1279 add_qemu_ldst_label(s, 0, oi,
1280 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1281 data_regl, data_regh, addr_regl, addr_regh,
1282 s->code_ptr, label_ptr);
1283#else
1284 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1285 tcg_out_ext32u(s, base, addr_regl);
1286 addr_regl = base;
1287 }
1288
1289 if (guest_base == 0) {
1290 tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
1291 } else {
1292 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
1293 }
1294 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1295#endif
1296}
bdf50381
AF		 1297
1298static tcg_insn_unit *tb_ret_addr;
1299
1300static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1301 const TCGArg *args, const int *const_args)
1302{
1303 TCGArg a0 = args[0];
1304 TCGArg a1 = args[1];
1305 TCGArg a2 = args[2];
1306 int c2 = const_args[2];
1307
1308 switch (opc) {
1309 case INDEX_op_exit_tb:
1310 /* Reuse the zeroing that exists for goto_ptr. */
1311 if (a0 == 0) {
1312 tcg_out_call_int(s, s->code_gen_epilogue, true);
1313 } else {
1314 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
1315 tcg_out_call_int(s, tb_ret_addr, true);
1316 }
1317 break;
1318
1319 case INDEX_op_goto_tb:
1320 assert(s->tb_jmp_insn_offset == 0);
1321 /* indirect jump method */
1322 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
1323 (uintptr_t)(s->tb_jmp_target_addr + a0));
1324 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1325 set_jmp_reset_offset(s, a0);
1326 break;
1327
1328 case INDEX_op_goto_ptr:
1329 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1330 break;
1331
1332 case INDEX_op_br:
1333 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
1334 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
1335 break;
1336
1337 case INDEX_op_ld8u_i32:
1338 case INDEX_op_ld8u_i64:
1339 tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
1340 break;
1341 case INDEX_op_ld8s_i32:
1342 case INDEX_op_ld8s_i64:
1343 tcg_out_ldst(s, OPC_LB, a0, a1, a2);
1344 break;
1345 case INDEX_op_ld16u_i32:
1346 case INDEX_op_ld16u_i64:
1347 tcg_out_ldst(s, OPC_LHU, a0, a1, a2);
1348 break;
1349 case INDEX_op_ld16s_i32:
1350 case INDEX_op_ld16s_i64:
1351 tcg_out_ldst(s, OPC_LH, a0, a1, a2);
1352 break;
1353 case INDEX_op_ld32u_i64:
1354 tcg_out_ldst(s, OPC_LWU, a0, a1, a2);
1355 break;
1356 case INDEX_op_ld_i32:
1357 case INDEX_op_ld32s_i64:
1358 tcg_out_ldst(s, OPC_LW, a0, a1, a2);
1359 break;
1360 case INDEX_op_ld_i64:
1361 tcg_out_ldst(s, OPC_LD, a0, a1, a2);
1362 break;
1363
1364 case INDEX_op_st8_i32:
1365 case INDEX_op_st8_i64:
1366 tcg_out_ldst(s, OPC_SB, a0, a1, a2);
1367 break;
1368 case INDEX_op_st16_i32:
1369 case INDEX_op_st16_i64:
1370 tcg_out_ldst(s, OPC_SH, a0, a1, a2);
1371 break;
1372 case INDEX_op_st_i32:
1373 case INDEX_op_st32_i64:
1374 tcg_out_ldst(s, OPC_SW, a0, a1, a2);
1375 break;
1376 case INDEX_op_st_i64:
1377 tcg_out_ldst(s, OPC_SD, a0, a1, a2);
1378 break;
1379
1380 case INDEX_op_add_i32:
1381 if (c2) {
1382 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2);
1383 } else {
1384 tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2);
1385 }
1386 break;
1387 case INDEX_op_add_i64:
1388 if (c2) {
1389 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2);
1390 } else {
1391 tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2);
1392 }
1393 break;
1394
1395 case INDEX_op_sub_i32:
1396 if (c2) {
1397 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2);
1398 } else {
1399 tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2);
1400 }
1401 break;
1402 case INDEX_op_sub_i64:
1403 if (c2) {
1404 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
1405 } else {
1406 tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
1407 }
1408 break;
1409
1410 case INDEX_op_and_i32:
1411 case INDEX_op_and_i64:
1412 if (c2) {
1413 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2);
1414 } else {
1415 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2);
1416 }
1417 break;
1418
1419 case INDEX_op_or_i32:
1420 case INDEX_op_or_i64:
1421 if (c2) {
1422 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2);
1423 } else {
1424 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2);
1425 }
1426 break;
1427
1428 case INDEX_op_xor_i32:
1429 case INDEX_op_xor_i64:
1430 if (c2) {
1431 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
1432 } else {
1433 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
1434 }
1435 break;
1436
1437 case INDEX_op_not_i32:
1438 case INDEX_op_not_i64:
1439 tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
1440 break;
1441
1442 case INDEX_op_neg_i32:
1443 tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1);
1444 break;
1445 case INDEX_op_neg_i64:
1446 tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
1447 break;
1448
1449 case INDEX_op_mul_i32:
1450 tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
1451 break;
1452 case INDEX_op_mul_i64:
1453 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1454 break;
1455
1456 case INDEX_op_div_i32:
1457 tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2);
1458 break;
1459 case INDEX_op_div_i64:
1460 tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2);
1461 break;
1462
1463 case INDEX_op_divu_i32:
1464 tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2);
1465 break;
1466 case INDEX_op_divu_i64:
1467 tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2);
1468 break;
1469
1470 case INDEX_op_rem_i32:
1471 tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2);
1472 break;
1473 case INDEX_op_rem_i64:
1474 tcg_out_opc_reg(s, OPC_REM, a0, a1, a2);
1475 break;
1476
1477 case INDEX_op_remu_i32:
1478 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
1479 break;
1480 case INDEX_op_remu_i64:
1481 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
1482 break;
1483
1484 case INDEX_op_shl_i32:
1485 if (c2) {
1486 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2);
1487 } else {
1488 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
1489 }
1490 break;
1491 case INDEX_op_shl_i64:
1492 if (c2) {
1493 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2);
1494 } else {
1495 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
1496 }
1497 break;
1498
1499 case INDEX_op_shr_i32:
1500 if (c2) {
1501 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
1502 } else {
1503 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
1504 }
1505 break;
1506 case INDEX_op_shr_i64:
1507 if (c2) {
1508 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2);
1509 } else {
1510 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
1511 }
1512 break;
1513
1514 case INDEX_op_sar_i32:
1515 if (c2) {
1516 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
1517 } else {
1518 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
1519 }
1520 break;
1521 case INDEX_op_sar_i64:
1522 if (c2) {
1523 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2);
1524 } else {
1525 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
1526 }
1527 break;
1528
1529 case INDEX_op_add2_i32:
1530 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1531 const_args[4], const_args[5], false, true);
1532 break;
1533 case INDEX_op_add2_i64:
1534 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1535 const_args[4], const_args[5], false, false);
1536 break;
1537 case INDEX_op_sub2_i32:
1538 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1539 const_args[4], const_args[5], true, true);
1540 break;
1541 case INDEX_op_sub2_i64:
1542 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1543 const_args[4], const_args[5], true, false);
1544 break;
1545
1546 case INDEX_op_brcond_i32:
1547 case INDEX_op_brcond_i64:
1548 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
1549 break;
1550 case INDEX_op_brcond2_i32:
1551 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
1552 break;
1553
1554 case INDEX_op_setcond_i32:
1555 case INDEX_op_setcond_i64:
1556 tcg_out_setcond(s, args[3], a0, a1, a2);
1557 break;
1558 case INDEX_op_setcond2_i32:
1559 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
1560 break;
1561
1562 case INDEX_op_qemu_ld_i32:
1563 tcg_out_qemu_ld(s, args, false);
1564 break;
1565 case INDEX_op_qemu_ld_i64:
1566 tcg_out_qemu_ld(s, args, true);
1567 break;
1568 case INDEX_op_qemu_st_i32:
1569 tcg_out_qemu_st(s, args, false);
1570 break;
1571 case INDEX_op_qemu_st_i64:
1572 tcg_out_qemu_st(s, args, true);
1573 break;
1574
1575 case INDEX_op_ext8u_i32:
1576 case INDEX_op_ext8u_i64:
1577 tcg_out_ext8u(s, a0, a1);
1578 break;
1579
1580 case INDEX_op_ext16u_i32:
1581 case INDEX_op_ext16u_i64:
1582 tcg_out_ext16u(s, a0, a1);
1583 break;
1584
1585 case INDEX_op_ext32u_i64:
1586 case INDEX_op_extu_i32_i64:
1587 tcg_out_ext32u(s, a0, a1);
1588 break;
1589
1590 case INDEX_op_ext8s_i32:
1591 case INDEX_op_ext8s_i64:
1592 tcg_out_ext8s(s, a0, a1);
1593 break;
1594
1595 case INDEX_op_ext16s_i32:
1596 case INDEX_op_ext16s_i64:
1597 tcg_out_ext16s(s, a0, a1);
1598 break;
1599
1600 case INDEX_op_ext32s_i64:
1601 case INDEX_op_extrl_i64_i32:
1602 case INDEX_op_ext_i32_i64:
1603 tcg_out_ext32s(s, a0, a1);
1604 break;
1605
1606 case INDEX_op_extrh_i64_i32:
1607 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
1608 break;
1609
1610 case INDEX_op_mulsh_i32:
1611 case INDEX_op_mulsh_i64:
1612 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
1613 break;
1614
1615 case INDEX_op_muluh_i32:
1616 case INDEX_op_muluh_i64:
1617 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
1618 break;
1619
1620 case INDEX_op_mb:
1621 tcg_out_mb(s, a0);
1622 break;
1623
1624 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1625 case INDEX_op_mov_i64:
1626 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
1627 case INDEX_op_movi_i64:
1628 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1629 default:
1630 g_assert_not_reached();
1631 }
1632}
1633
1634static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
1635{
1636 static const TCGTargetOpDef r
1637 = { .args_ct_str = { "r" } };
1638 static const TCGTargetOpDef r_r
1639 = { .args_ct_str = { "r", "r" } };
1640 static const TCGTargetOpDef rZ_r
1641 = { .args_ct_str = { "rZ", "r" } };
1642 static const TCGTargetOpDef rZ_rZ
1643 = { .args_ct_str = { "rZ", "rZ" } };
1644 static const TCGTargetOpDef rZ_rZ_rZ_rZ
1645 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
1646 static const TCGTargetOpDef r_r_ri
1647 = { .args_ct_str = { "r", "r", "ri" } };
1648 static const TCGTargetOpDef r_r_rI
1649 = { .args_ct_str = { "r", "r", "rI" } };
1650 static const TCGTargetOpDef r_rZ_rN
1651 = { .args_ct_str = { "r", "rZ", "rN" } };
1652 static const TCGTargetOpDef r_rZ_rZ
1653 = { .args_ct_str = { "r", "rZ", "rZ" } };
1654 static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
1655 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
1656 static const TCGTargetOpDef r_L
1657 = { .args_ct_str = { "r", "L" } };
1658 static const TCGTargetOpDef r_r_L
1659 = { .args_ct_str = { "r", "r", "L" } };
1660 static const TCGTargetOpDef r_L_L
1661 = { .args_ct_str = { "r", "L", "L" } };
1662 static const TCGTargetOpDef r_r_L_L
1663 = { .args_ct_str = { "r", "r", "L", "L" } };
1664 static const TCGTargetOpDef LZ_L
1665 = { .args_ct_str = { "LZ", "L" } };
1666 static const TCGTargetOpDef LZ_L_L
1667 = { .args_ct_str = { "LZ", "L", "L" } };
1668 static const TCGTargetOpDef LZ_LZ_L
1669 = { .args_ct_str = { "LZ", "LZ", "L" } };
1670 static const TCGTargetOpDef LZ_LZ_L_L
1671 = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
1672 static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
1673 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
1674
1675 switch (op) {
1676 case INDEX_op_goto_ptr:
1677 return &r;
1678
1679 case INDEX_op_ld8u_i32:
1680 case INDEX_op_ld8s_i32:
1681 case INDEX_op_ld16u_i32:
1682 case INDEX_op_ld16s_i32:
1683 case INDEX_op_ld_i32:
1684 case INDEX_op_not_i32:
1685 case INDEX_op_neg_i32:
1686 case INDEX_op_ld8u_i64:
1687 case INDEX_op_ld8s_i64:
1688 case INDEX_op_ld16u_i64:
1689 case INDEX_op_ld16s_i64:
1690 case INDEX_op_ld32s_i64:
1691 case INDEX_op_ld32u_i64:
1692 case INDEX_op_ld_i64:
1693 case INDEX_op_not_i64:
1694 case INDEX_op_neg_i64:
1695 case INDEX_op_ext8u_i32:
1696 case INDEX_op_ext8u_i64:
1697 case INDEX_op_ext16u_i32:
1698 case INDEX_op_ext16u_i64:
1699 case INDEX_op_ext32u_i64:
1700 case INDEX_op_extu_i32_i64:
1701 case INDEX_op_ext8s_i32:
1702 case INDEX_op_ext8s_i64:
1703 case INDEX_op_ext16s_i32:
1704 case INDEX_op_ext16s_i64:
1705 case INDEX_op_ext32s_i64:
1706 case INDEX_op_extrl_i64_i32:
1707 case INDEX_op_extrh_i64_i32:
1708 case INDEX_op_ext_i32_i64:
1709 return &r_r;
1710
1711 case INDEX_op_st8_i32:
1712 case INDEX_op_st16_i32:
1713 case INDEX_op_st_i32:
1714 case INDEX_op_st8_i64:
1715 case INDEX_op_st16_i64:
1716 case INDEX_op_st32_i64:
1717 case INDEX_op_st_i64:
1718 return &rZ_r;
1719
1720 case INDEX_op_add_i32:
1721 case INDEX_op_and_i32:
1722 case INDEX_op_or_i32:
1723 case INDEX_op_xor_i32:
1724 case INDEX_op_add_i64:
1725 case INDEX_op_and_i64:
1726 case INDEX_op_or_i64:
1727 case INDEX_op_xor_i64:
1728 return &r_r_rI;
1729
1730 case INDEX_op_sub_i32:
1731 case INDEX_op_sub_i64:
1732 return &r_rZ_rN;
1733
1734 case INDEX_op_mul_i32:
1735 case INDEX_op_mulsh_i32:
1736 case INDEX_op_muluh_i32:
1737 case INDEX_op_div_i32:
1738 case INDEX_op_divu_i32:
1739 case INDEX_op_rem_i32:
1740 case INDEX_op_remu_i32:
1741 case INDEX_op_setcond_i32:
1742 case INDEX_op_mul_i64:
1743 case INDEX_op_mulsh_i64:
1744 case INDEX_op_muluh_i64:
1745 case INDEX_op_div_i64:
1746 case INDEX_op_divu_i64:
1747 case INDEX_op_rem_i64:
1748 case INDEX_op_remu_i64:
1749 case INDEX_op_setcond_i64:
1750 return &r_rZ_rZ;
1751
1752 case INDEX_op_shl_i32:
1753 case INDEX_op_shr_i32:
1754 case INDEX_op_sar_i32:
1755 case INDEX_op_shl_i64:
1756 case INDEX_op_shr_i64:
1757 case INDEX_op_sar_i64:
1758 return &r_r_ri;
1759
1760 case INDEX_op_brcond_i32:
1761 case INDEX_op_brcond_i64:
1762 return &rZ_rZ;
1763
1764 case INDEX_op_add2_i32:
1765 case INDEX_op_add2_i64:
1766 case INDEX_op_sub2_i32:
1767 case INDEX_op_sub2_i64:
1768 return &r_r_rZ_rZ_rM_rM;
1769
1770 case INDEX_op_brcond2_i32:
1771 return &rZ_rZ_rZ_rZ;
1772
1773 case INDEX_op_setcond2_i32:
1774 return &r_rZ_rZ_rZ_rZ;
1775
1776 case INDEX_op_qemu_ld_i32:
1777 return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
1778 case INDEX_op_qemu_st_i32:
1779 return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
1780 case INDEX_op_qemu_ld_i64:
1781 return TCG_TARGET_REG_BITS == 64 ? &r_L
1782 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
1783 : &r_r_L_L;
1784 case INDEX_op_qemu_st_i64:
1785 return TCG_TARGET_REG_BITS == 64 ? &LZ_L
1786 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
1787 : &LZ_LZ_L_L;
1788
1789 default:
1790 return NULL;
1791 }
1792}
92c041c5
AF		 1793
1794static const int tcg_target_callee_save_regs[] = {
1795 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
1796 TCG_REG_S1,
1797 TCG_REG_S2,
1798 TCG_REG_S3,
1799 TCG_REG_S4,
1800 TCG_REG_S5,
1801 TCG_REG_S6,
1802 TCG_REG_S7,
1803 TCG_REG_S8,
1804 TCG_REG_S9,
1805 TCG_REG_S10,
1806 TCG_REG_S11,
1807 TCG_REG_RA, /* should be last for ABI compliance */
1808};
1809
1810/* Stack frame parameters. */
1811#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
1812#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
1813#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1814#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
1815 + TCG_TARGET_STACK_ALIGN - 1) \
1816 & -TCG_TARGET_STACK_ALIGN)
1817#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
1818
1819/* We're expecting to be able to use an immediate for frame allocation. */
1820QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
1821
1822/* Generate global QEMU prologue and epilogue code */
1823static void tcg_target_qemu_prologue(TCGContext *s)
1824{
1825 int i;
1826
1827 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
1828
1829 /* TB prologue */
1830 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
1831 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1832 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1833 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1834 }
1835
1836#if !defined(CONFIG_SOFTMMU)
1837 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
1838 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1839#endif
1840
1841 /* Call generated code */
1842 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1843 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
1844
1845 /* Return path for goto_ptr. Set return value to 0 */
1846 s->code_gen_epilogue = s->code_ptr;
1847 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
1848
1849 /* TB epilogue */
1850 tb_ret_addr = s->code_ptr;
1851 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1852 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1853 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1854 }
1855
1856 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
1857 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
1858}
1859
7a5549f2
AF		 1860static void tcg_target_init(TCGContext *s)
1861{
1862 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
1863 if (TCG_TARGET_REG_BITS == 64) {
1864 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
1865 }
1866
1867 tcg_target_call_clobber_regs = -1u;
1868 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
1869 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
1870 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
1871 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
1872 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
1873 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
1874 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
1875 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
1876 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
1877 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
1878 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10);
1879 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11);
1880
1881 s->reserved_regs = 0;
1882 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
1883 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
1884 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
1885 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
1886 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
1887 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
1888 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
1889}
1890
92c041c5
AF		 1891typedef struct {
1892 DebugFrameHeader h;
1893 uint8_t fde_def_cfa[4];
1894 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
1895} DebugFrame;
1896
1897#define ELF_HOST_MACHINE EM_RISCV
1898
1899static const DebugFrame debug_frame = {
1900 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
1901 .h.cie.id = -1,
1902 .h.cie.version = 1,
1903 .h.cie.code_align = 1,
1904 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
1905 .h.cie.return_column = TCG_REG_RA,
1906
1907 /* Total FDE size does not include the "len" member. */
1908 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
1909
1910 .fde_def_cfa = {
1911 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
1912 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
1913 (FRAME_SIZE >> 7)
1914 },
1915 .fde_reg_ofs = {
1916 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
1917 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
1918 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
1919 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
1920 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
1921 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
1922 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
1923 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
1924 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
1925 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
1926 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
1927 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
1928 }
1929};
1930
1931void tcg_register_jit(void *buf, size_t buf_size)
1932{
1933 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
1934}
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