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[mirror_qemu.git] / tcg / s390x / tcg-target.c.inc
CommitLineData
2827822e
AG		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
48bb3750
RH		 5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
2827822e
AG		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
a01fc30d
RH		 27/* We only support generating code for 64-bit mode. */
28#if TCG_TARGET_REG_BITS != 64
29#error "unsupported code generation mode"
30#endif
31
1cd49868 32#include "../tcg-ldst.c.inc"
139c1837 33#include "../tcg-pool.c.inc"
c9baa30f
RH		 34#include "elf.h"
35
4134083f
RH		 36#define TCG_CT_CONST_S16 (1 << 8)
37#define TCG_CT_CONST_S32 (1 << 9)
38#define TCG_CT_CONST_S33 (1 << 10)
39#define TCG_CT_CONST_ZERO (1 << 11)
40#define TCG_CT_CONST_P32 (1 << 12)
41#define TCG_CT_CONST_INV (1 << 13)
42#define TCG_CT_CONST_INVRISBG (1 << 14)
48bb3750 43
c947deb1 44#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
34ef7676
RH		 45#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
46
48bb3750
RH		 47/* Several places within the instruction set 0 means "no register"
48 rather than TCG_REG_R0. */
49#define TCG_REG_NONE 0
50
51/* A scratch register that may be be used throughout the backend. */
ce411066 52#define TCG_TMP0 TCG_REG_R1
48bb3750 53
4cbea598 54#ifndef CONFIG_SOFTMMU
48bb3750 55#define TCG_GUEST_BASE_REG TCG_REG_R13
48bb3750
RH		 56#endif
57
48bb3750
RH		 58/* All of the following instructions are prefixed with their instruction
59 format, and are defined as 8- or 16-bit quantities, even when the two
60 halves of the 16-bit quantity may appear 32 bits apart in the insn.
61 This makes it easy to copy the values from the tables in Appendix B. */
62typedef enum S390Opcode {
63 RIL_AFI = 0xc209,
64 RIL_AGFI = 0xc208,
3790b918 65 RIL_ALFI = 0xc20b,
48bb3750
RH		 66 RIL_ALGFI = 0xc20a,
67 RIL_BRASL = 0xc005,
68 RIL_BRCL = 0xc004,
69 RIL_CFI = 0xc20d,
70 RIL_CGFI = 0xc20c,
71 RIL_CLFI = 0xc20f,
72 RIL_CLGFI = 0xc20e,
a534bb15
RH		 73 RIL_CLRL = 0xc60f,
74 RIL_CLGRL = 0xc60a,
75 RIL_CRL = 0xc60d,
76 RIL_CGRL = 0xc608,
48bb3750
RH		 77 RIL_IIHF = 0xc008,
78 RIL_IILF = 0xc009,
79 RIL_LARL = 0xc000,
80 RIL_LGFI = 0xc001,
81 RIL_LGRL = 0xc408,
82 RIL_LLIHF = 0xc00e,
83 RIL_LLILF = 0xc00f,
84 RIL_LRL = 0xc40d,
85 RIL_MSFI = 0xc201,
86 RIL_MSGFI = 0xc200,
87 RIL_NIHF = 0xc00a,
88 RIL_NILF = 0xc00b,
89 RIL_OIHF = 0xc00c,
90 RIL_OILF = 0xc00d,
3790b918 91 RIL_SLFI = 0xc205,
0db921e6 92 RIL_SLGFI = 0xc204,
48bb3750
RH		 93 RIL_XIHF = 0xc006,
94 RIL_XILF = 0xc007,
95
96 RI_AGHI = 0xa70b,
97 RI_AHI = 0xa70a,
98 RI_BRC = 0xa704,
a534bb15
RH		 99 RI_CHI = 0xa70e,
100 RI_CGHI = 0xa70f,
48bb3750
RH		 101 RI_IIHH = 0xa500,
102 RI_IIHL = 0xa501,
103 RI_IILH = 0xa502,
104 RI_IILL = 0xa503,
105 RI_LGHI = 0xa709,
106 RI_LLIHH = 0xa50c,
107 RI_LLIHL = 0xa50d,
108 RI_LLILH = 0xa50e,
109 RI_LLILL = 0xa50f,
110 RI_MGHI = 0xa70d,
111 RI_MHI = 0xa70c,
112 RI_NIHH = 0xa504,
113 RI_NIHL = 0xa505,
114 RI_NILH = 0xa506,
115 RI_NILL = 0xa507,
116 RI_OIHH = 0xa508,
117 RI_OIHL = 0xa509,
118 RI_OILH = 0xa50a,
119 RI_OILL = 0xa50b,
1cd49868 120 RI_TMLL = 0xa701,
48bb3750 121
d84ca804
RH		 122 RIEb_CGRJ = 0xec64,
123 RIEb_CLGRJ = 0xec65,
124 RIEb_CLRJ = 0xec77,
125 RIEb_CRJ = 0xec76,
126
127 RIEc_CGIJ = 0xec7c,
128 RIEc_CIJ = 0xec7e,
129 RIEc_CLGIJ = 0xec7d,
130 RIEc_CLIJ = 0xec7f,
131
132 RIEf_RISBG = 0xec55,
133
134 RIEg_LOCGHI = 0xec46,
48bb3750
RH		 135
136 RRE_AGR = 0xb908,
3790b918
RH		 137 RRE_ALGR = 0xb90a,
138 RRE_ALCR = 0xb998,
139 RRE_ALCGR = 0xb988,
8b1b4597 140 RRE_ALGFR = 0xb91a,
48bb3750
RH		 141 RRE_CGR = 0xb920,
142 RRE_CLGR = 0xb921,
143 RRE_DLGR = 0xb987,
144 RRE_DLR = 0xb997,
145 RRE_DSGFR = 0xb91d,
146 RRE_DSGR = 0xb90d,
ce411066 147 RRE_FLOGR = 0xb983,
48bb3750
RH		 148 RRE_LGBR = 0xb906,
149 RRE_LCGR = 0xb903,
150 RRE_LGFR = 0xb914,
151 RRE_LGHR = 0xb907,
152 RRE_LGR = 0xb904,
153 RRE_LLGCR = 0xb984,
154 RRE_LLGFR = 0xb916,
155 RRE_LLGHR = 0xb985,
156 RRE_LRVR = 0xb91f,
157 RRE_LRVGR = 0xb90f,
158 RRE_LTGR = 0xb902,
36017dc6 159 RRE_MLGR = 0xb986,
48bb3750
RH		 160 RRE_MSGR = 0xb90c,
161 RRE_MSR = 0xb252,
162 RRE_NGR = 0xb980,
163 RRE_OGR = 0xb981,
164 RRE_SGR = 0xb909,
3790b918
RH		 165 RRE_SLGR = 0xb90b,
166 RRE_SLBR = 0xb999,
167 RRE_SLBGR = 0xb989,
48bb3750
RH		 168 RRE_XGR = 0xb982,
169
668ce343 170 RRFa_MGRK = 0xb9ec,
92c89a07
RH		 171 RRFa_MSRKC = 0xb9fd,
172 RRFa_MSGRKC = 0xb9ed,
6c9b5c0f
RH		 173 RRFa_NCRK = 0xb9f5,
174 RRFa_NCGRK = 0xb9e5,
175 RRFa_NNRK = 0xb974,
176 RRFa_NNGRK = 0xb964,
177 RRFa_NORK = 0xb976,
178 RRFa_NOGRK = 0xb966,
1dd06b1a
RH		 179 RRFa_NRK = 0xb9f4,
180 RRFa_NGRK = 0xb9e4,
6c9b5c0f
RH		 181 RRFa_NXRK = 0xb977,
182 RRFa_NXGRK = 0xb967,
183 RRFa_OCRK = 0xb975,
184 RRFa_OCGRK = 0xb965,
1dd06b1a
RH		 185 RRFa_ORK = 0xb9f6,
186 RRFa_OGRK = 0xb9e6,
187 RRFa_SRK = 0xb9f9,
188 RRFa_SGRK = 0xb9e9,
189 RRFa_SLRK = 0xb9fb,
190 RRFa_SLGRK = 0xb9eb,
191 RRFa_XRK = 0xb9f7,
192 RRFa_XGRK = 0xb9e7,
193
0bbf0f7a
RH		 194 RRFam_SELGR = 0xb9e3,
195
1dd06b1a
RH		 196 RRFc_LOCR = 0xb9f2,
197 RRFc_LOCGR = 0xb9e2,
29a5ea73 198 RRFc_POPCNT = 0xb9e1,
96a9f093 199
48bb3750 200 RR_AR = 0x1a,
3790b918 201 RR_ALR = 0x1e,
48bb3750
RH		 202 RR_BASR = 0x0d,
203 RR_BCR = 0x07,
204 RR_CLR = 0x15,
205 RR_CR = 0x19,
206 RR_DR = 0x1d,
207 RR_LCR = 0x13,
208 RR_LR = 0x18,
209 RR_LTR = 0x12,
210 RR_NR = 0x14,
211 RR_OR = 0x16,
212 RR_SR = 0x1b,
3790b918 213 RR_SLR = 0x1f,
48bb3750
RH		 214 RR_XR = 0x17,
215
216 RSY_RLL = 0xeb1d,
217 RSY_RLLG = 0xeb1c,
218 RSY_SLLG = 0xeb0d,
c2097136 219 RSY_SLLK = 0xebdf,
48bb3750 220 RSY_SRAG = 0xeb0a,
c2097136 221 RSY_SRAK = 0xebdc,
48bb3750 222 RSY_SRLG = 0xeb0c,
c2097136 223 RSY_SRLK = 0xebde,
48bb3750
RH		 224
225 RS_SLL = 0x89,
226 RS_SRA = 0x8a,
227 RS_SRL = 0x88,
228
229 RXY_AG = 0xe308,
230 RXY_AY = 0xe35a,
231 RXY_CG = 0xe320,
a534bb15
RH		 232 RXY_CLG = 0xe321,
233 RXY_CLY = 0xe355,
48bb3750 234 RXY_CY = 0xe359,
0db921e6 235 RXY_LAY = 0xe371,
48bb3750
RH		 236 RXY_LB = 0xe376,
237 RXY_LG = 0xe304,
238 RXY_LGB = 0xe377,
239 RXY_LGF = 0xe314,
240 RXY_LGH = 0xe315,
241 RXY_LHY = 0xe378,
242 RXY_LLGC = 0xe390,
243 RXY_LLGF = 0xe316,
244 RXY_LLGH = 0xe391,
245 RXY_LMG = 0xeb04,
246 RXY_LRV = 0xe31e,
247 RXY_LRVG = 0xe30f,
248 RXY_LRVH = 0xe31f,
249 RXY_LY = 0xe358,
bdcd5d19 250 RXY_NG = 0xe380,
4046d9ca 251 RXY_OG = 0xe381,
48bb3750
RH		 252 RXY_STCY = 0xe372,
253 RXY_STG = 0xe324,
254 RXY_STHY = 0xe370,
255 RXY_STMG = 0xeb24,
256 RXY_STRV = 0xe33e,
257 RXY_STRVG = 0xe32f,
258 RXY_STRVH = 0xe33f,
259 RXY_STY = 0xe350,
5bf67a92 260 RXY_XG = 0xe382,
48bb3750
RH		 261
262 RX_A = 0x5a,
263 RX_C = 0x59,
264 RX_L = 0x58,
0db921e6 265 RX_LA = 0x41,
48bb3750
RH		 266 RX_LH = 0x48,
267 RX_ST = 0x50,
268 RX_STC = 0x42,
269 RX_STH = 0x40,
ed3d51ec 270
79cada86
RH		 271 VRIa_VGBM = 0xe744,
272 VRIa_VREPI = 0xe745,
273 VRIb_VGM = 0xe746,
274 VRIc_VREP = 0xe74d,
275
ae77bbe5
RH		 276 VRRa_VLC = 0xe7de,
277 VRRa_VLP = 0xe7df,
b33ce725 278 VRRa_VLR = 0xe756,
a429ee29
RH		 279 VRRc_VA = 0xe7f3,
280 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
281 VRRc_VCH = 0xe7fb, /* " */
282 VRRc_VCHL = 0xe7f9, /* " */
22cb37b4
RH		 283 VRRc_VERLLV = 0xe773,
284 VRRc_VESLV = 0xe770,
285 VRRc_VESRAV = 0xe77a,
286 VRRc_VESRLV = 0xe778,
479b61cb 287 VRRc_VML = 0xe7a2,
220db7a6
RH		 288 VRRc_VMN = 0xe7fe,
289 VRRc_VMNL = 0xe7fc,
290 VRRc_VMX = 0xe7ff,
291 VRRc_VMXL = 0xe7fd,
a429ee29 292 VRRc_VN = 0xe768,
ae77bbe5 293 VRRc_VNC = 0xe769,
21eab5bf 294 VRRc_VNN = 0xe76e,
ae77bbe5 295 VRRc_VNO = 0xe76b,
21eab5bf 296 VRRc_VNX = 0xe76c,
a429ee29 297 VRRc_VO = 0xe76a,
ae77bbe5 298 VRRc_VOC = 0xe76f,
4223c9c1 299 VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */
a429ee29 300 VRRc_VS = 0xe7f7,
4223c9c1
RH		 301 VRRa_VUPH = 0xe7d7,
302 VRRa_VUPL = 0xe7d6,
a429ee29 303 VRRc_VX = 0xe76d,
9bca986d 304 VRRe_VSEL = 0xe78d,
79cada86 305 VRRf_VLVGP = 0xe762,
b33ce725 306
22cb37b4
RH		 307 VRSa_VERLL = 0xe733,
308 VRSa_VESL = 0xe730,
309 VRSa_VESRA = 0xe73a,
310 VRSa_VESRL = 0xe738,
b33ce725
RH		 311 VRSb_VLVG = 0xe722,
312 VRSc_VLGV = 0xe721,
313
2dabf742
RH		 314 VRX_VL = 0xe706,
315 VRX_VLLEZ = 0xe704,
79cada86 316 VRX_VLREP = 0xe705,
2dabf742
RH		 317 VRX_VST = 0xe70e,
318 VRX_VSTEF = 0xe70b,
319 VRX_VSTEG = 0xe70a,
320
ed3d51ec 321 NOP = 0x0707,
48bb3750
RH		 322} S390Opcode;
323
8d8fdbae 324#ifdef CONFIG_DEBUG_TCG
48bb3750 325static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34ef7676
RH		 326 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
327 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
328 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
329 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
330 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
331 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
332 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
48bb3750
RH		 333};
334#endif
335
336/* Since R6 is a potential argument register, choose it last of the
337 call-saved registers. Likewise prefer the call-clobbered registers
338 in reverse order to maximize the chance of avoiding the arguments. */
2827822e 339static const int tcg_target_reg_alloc_order[] = {
f24efee4 340 /* Call saved registers. */
48bb3750
RH		 341 TCG_REG_R13,
342 TCG_REG_R12,
343 TCG_REG_R11,
344 TCG_REG_R10,
345 TCG_REG_R9,
346 TCG_REG_R8,
347 TCG_REG_R7,
348 TCG_REG_R6,
f24efee4 349 /* Call clobbered registers. */
48bb3750
RH		 350 TCG_REG_R14,
351 TCG_REG_R0,
352 TCG_REG_R1,
f24efee4 353 /* Argument registers, in reverse order of allocation. */
48bb3750
RH		 354 TCG_REG_R5,
355 TCG_REG_R4,
356 TCG_REG_R3,
357 TCG_REG_R2,
34ef7676
RH		 358
359 /* V8-V15 are call saved, and omitted. */
360 TCG_REG_V0,
361 TCG_REG_V1,
362 TCG_REG_V2,
363 TCG_REG_V3,
364 TCG_REG_V4,
365 TCG_REG_V5,
366 TCG_REG_V6,
367 TCG_REG_V7,
368 TCG_REG_V16,
369 TCG_REG_V17,
370 TCG_REG_V18,
371 TCG_REG_V19,
372 TCG_REG_V20,
373 TCG_REG_V21,
374 TCG_REG_V22,
375 TCG_REG_V23,
376 TCG_REG_V24,
377 TCG_REG_V25,
378 TCG_REG_V26,
379 TCG_REG_V27,
380 TCG_REG_V28,
381 TCG_REG_V29,
382 TCG_REG_V30,
383 TCG_REG_V31,
2827822e
AG		 384};
385
386static const int tcg_target_call_iarg_regs[] = {
48bb3750
RH		 387 TCG_REG_R2,
388 TCG_REG_R3,
389 TCG_REG_R4,
390 TCG_REG_R5,
391 TCG_REG_R6,
2827822e
AG		 392};
393
5e3d0c19
RH		 394static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
395{
396 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
397 tcg_debug_assert(slot == 0);
398 return TCG_REG_R2;
399}
48bb3750
RH		 400
401#define S390_CC_EQ 8
402#define S390_CC_LT 4
403#define S390_CC_GT 2
404#define S390_CC_OV 1
405#define S390_CC_NE (S390_CC_LT | S390_CC_GT)
406#define S390_CC_LE (S390_CC_LT | S390_CC_EQ)
407#define S390_CC_GE (S390_CC_GT | S390_CC_EQ)
408#define S390_CC_NEVER 0
409#define S390_CC_ALWAYS 15
410
411/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
0aed257f 412static const uint8_t tcg_cond_to_s390_cond[] = {
48bb3750
RH		 413 [TCG_COND_EQ] = S390_CC_EQ,
414 [TCG_COND_NE] = S390_CC_NE,
415 [TCG_COND_LT] = S390_CC_LT,
416 [TCG_COND_LE] = S390_CC_LE,
417 [TCG_COND_GT] = S390_CC_GT,
418 [TCG_COND_GE] = S390_CC_GE,
419 [TCG_COND_LTU] = S390_CC_LT,
420 [TCG_COND_LEU] = S390_CC_LE,
421 [TCG_COND_GTU] = S390_CC_GT,
422 [TCG_COND_GEU] = S390_CC_GE,
423};
424
425/* Condition codes that result from a LOAD AND TEST. Here, we have no
426 unsigned instruction variation, however since the test is vs zero we
427 can re-map the outcomes appropriately. */
0aed257f 428static const uint8_t tcg_cond_to_ltr_cond[] = {
48bb3750
RH		 429 [TCG_COND_EQ] = S390_CC_EQ,
430 [TCG_COND_NE] = S390_CC_NE,
431 [TCG_COND_LT] = S390_CC_LT,
432 [TCG_COND_LE] = S390_CC_LE,
433 [TCG_COND_GT] = S390_CC_GT,
434 [TCG_COND_GE] = S390_CC_GE,
435 [TCG_COND_LTU] = S390_CC_NEVER,
436 [TCG_COND_LEU] = S390_CC_EQ,
437 [TCG_COND_GTU] = S390_CC_NE,
438 [TCG_COND_GEU] = S390_CC_ALWAYS,
439};
440
79dae4dd 441static const tcg_insn_unit *tb_ret_addr;
34ef7676 442uint64_t s390_facilities[3];
2827822e 443
2dabf742
RH		 444static inline bool is_general_reg(TCGReg r)
445{
446 return r <= TCG_REG_R15;
447}
448
449static inline bool is_vector_reg(TCGReg r)
450{
451 return r >= TCG_REG_V0 && r <= TCG_REG_V31;
452}
453
79dae4dd 454static bool patch_reloc(tcg_insn_unit *src_rw, int type,
2ba7fae2 455 intptr_t value, intptr_t addend)
2827822e 456{
79dae4dd 457 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
e692a349 458 intptr_t pcrel2;
28eef8aa 459 uint32_t old;
e692a349
RH		 460
461 value += addend;
79dae4dd 462 pcrel2 = (tcg_insn_unit *)value - src_rx;
48bb3750
RH		 463
464 switch (type) {
465 case R_390_PC16DBL:
55dfd8fe 466 if (pcrel2 == (int16_t)pcrel2) {
79dae4dd 467 tcg_patch16(src_rw, pcrel2);
55dfd8fe
RH		 468 return true;
469 }
48bb3750
RH		 470 break;
471 case R_390_PC32DBL:
55dfd8fe 472 if (pcrel2 == (int32_t)pcrel2) {
79dae4dd 473 tcg_patch32(src_rw, pcrel2);
55dfd8fe
RH		 474 return true;
475 }
48bb3750 476 break;
28eef8aa 477 case R_390_20:
55dfd8fe 478 if (value == sextract64(value, 0, 20)) {
79dae4dd 479 old = *(uint32_t *)src_rw & 0xf00000ff;
55dfd8fe 480 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4);
79dae4dd 481 tcg_patch32(src_rw, old);
55dfd8fe
RH		 482 return true;
483 }
28eef8aa 484 break;
48bb3750 485 default:
e692a349 486 g_assert_not_reached();
48bb3750 487 }
55dfd8fe 488 return false;
2827822e
AG		 489}
490
b2509acc
RH		 491static int is_const_p16(uint64_t val)
492{
493 for (int i = 0; i < 4; ++i) {
494 uint64_t mask = 0xffffull << (i * 16);
495 if ((val & ~mask) == 0) {
496 return i;
497 }
498 }
499 return -1;
500}
501
502static int is_const_p32(uint64_t val)
503{
504 if ((val & 0xffffffff00000000ull) == 0) {
505 return 0;
506 }
507 if ((val & 0x00000000ffffffffull) == 0) {
508 return 1;
509 }
510 return -1;
511}
512
4134083f
RH		 513/*
514 * Accept bit patterns like these:
515 * 0....01....1
516 * 1....10....0
517 * 1..10..01..1
518 * 0..01..10..0
519 * Copied from gcc sources.
520 */
521static bool risbg_mask(uint64_t c)
522{
523 uint64_t lsb;
524 /* We don't change the number of transitions by inverting,
525 so make sure we start with the LSB zero. */
526 if (c & 1) {
527 c = ~c;
528 }
529 /* Reject all zeros or all ones. */
530 if (c == 0) {
531 return false;
532 }
533 /* Find the first transition. */
534 lsb = c & -c;
535 /* Invert to look for a second transition. */
536 c = ~c;
537 /* Erase the first transition. */
538 c &= -lsb;
539 /* Find the second transition, if any. */
540 lsb = c & -c;
541 /* Match if all the bits are 1's, or if c is zero. */
542 return c == -lsb;
543}
544
2827822e 545/* Test if a constant matches the constraint. */
a4fbbd77 546static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
2827822e 547{
48bb3750
RH		 548 if (ct & TCG_CT_CONST) {
549 return 1;
550 }
551
671c835b 552 if (type == TCG_TYPE_I32) {
48bb3750
RH		 553 val = (int32_t)val;
554 }
555
556 /* The following are mutually exclusive. */
a8f0269e
RH		 557 if (ct & TCG_CT_CONST_S16) {
558 return val == (int16_t)val;
559 } else if (ct & TCG_CT_CONST_S32) {
560 return val == (int32_t)val;
ba18b07d
RH		 561 } else if (ct & TCG_CT_CONST_S33) {
562 return val >= -0xffffffffll && val <= 0xffffffffll;
752b1be9
RH		 563 } else if (ct & TCG_CT_CONST_ZERO) {
564 return val == 0;
48bb3750
RH		 565 }
566
4134083f
RH		 567 if (ct & TCG_CT_CONST_INV) {
568 val = ~val;
569 }
b2509acc
RH		 570 /*
571 * Note that is_const_p16 is a subset of is_const_p32,
572 * so we don't need both constraints.
573 */
574 if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) {
575 return true;
576 }
4134083f
RH		 577 if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) {
578 return true;
579 }
b2509acc 580
2827822e
AG		 581 return 0;
582}
583
48bb3750
RH		 584/* Emit instructions according to the given instruction format. */
585
586static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2)
587{
588 tcg_out16(s, (op << 8) | (r1 << 4) | r2);
589}
590
591static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
592 TCGReg r1, TCGReg r2)
593{
594 tcg_out32(s, (op << 16) | (r1 << 4) | r2);
595}
596
0bbf0f7a 597/* RRF-a without the m4 field */
1dd06b1a
RH		 598static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op,
599 TCGReg r1, TCGReg r2, TCGReg r3)
600{
601 tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2);
602}
603
0bbf0f7a
RH		 604/* RRF-a with the m4 field */
605static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op,
606 TCGReg r1, TCGReg r2, TCGReg r3, int m4)
607{
608 tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2);
609}
610
1dd06b1a
RH		 611static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op,
612 TCGReg r1, TCGReg r2, int m3)
96a9f093
RH		 613{
614 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
615}
616
48bb3750
RH		 617static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
618{
619 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
620}
621
d84ca804 622static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1,
7af525af
RH		 623 int i2, int m3)
624{
625 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
626 tcg_out32(s, (i2 << 16) | (op & 0xff));
627}
628
48bb3750
RH		 629static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
630{
631 tcg_out16(s, op | (r1 << 4));
632 tcg_out32(s, i2);
633}
634
635static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1,
636 TCGReg b2, TCGReg r3, int disp)
637{
638 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12)
639 | (disp & 0xfff));
640}
641
642static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
643 TCGReg b2, TCGReg r3, int disp)
644{
645 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3);
646 tcg_out32(s, (op & 0xff) | (b2 << 28)
647 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4));
648}
649
650#define tcg_out_insn_RX tcg_out_insn_RS
651#define tcg_out_insn_RXY tcg_out_insn_RSY
652
2dabf742
RH		 653static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
654{
655 /*
656 * Shift bit 4 of each regno to its corresponding bit of RXB.
657 * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4
658 * is the left-shift of the 4th operand.
659 */
660 return ((v1 & 0x10) << (4 + 3))
661 | ((v2 & 0x10) << (4 + 2))
662 | ((v3 & 0x10) << (4 + 1))
663 | ((v4 & 0x10) << (4 + 0));
664}
665
79cada86
RH		 666static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op,
667 TCGReg v1, uint16_t i2, int m3)
668{
669 tcg_debug_assert(is_vector_reg(v1));
670 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4));
671 tcg_out16(s, i2);
672 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12));
673}
674
675static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op,
676 TCGReg v1, uint8_t i2, uint8_t i3, int m4)
677{
678 tcg_debug_assert(is_vector_reg(v1));
679 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4));
680 tcg_out16(s, (i2 << 8) | (i3 & 0xff));
681 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
682}
683
684static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op,
685 TCGReg v1, uint16_t i2, TCGReg v3, int m4)
686{
687 tcg_debug_assert(is_vector_reg(v1));
688 tcg_debug_assert(is_vector_reg(v3));
689 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
690 tcg_out16(s, i2);
691 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
692}
693
b33ce725
RH		 694static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
695 TCGReg v1, TCGReg v2, int m3)
696{
697 tcg_debug_assert(is_vector_reg(v1));
698 tcg_debug_assert(is_vector_reg(v2));
699 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
700 tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12));
701}
702
a429ee29
RH		 703static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op,
704 TCGReg v1, TCGReg v2, TCGReg v3, int m4)
705{
706 tcg_debug_assert(is_vector_reg(v1));
707 tcg_debug_assert(is_vector_reg(v2));
708 tcg_debug_assert(is_vector_reg(v3));
709 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
710 tcg_out16(s, v3 << 12);
711 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12));
712}
713
9bca986d
RH		 714static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op,
715 TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
716{
717 tcg_debug_assert(is_vector_reg(v1));
718 tcg_debug_assert(is_vector_reg(v2));
719 tcg_debug_assert(is_vector_reg(v3));
720 tcg_debug_assert(is_vector_reg(v4));
721 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
722 tcg_out16(s, v3 << 12);
723 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12));
724}
725
79cada86
RH		 726static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
727 TCGReg v1, TCGReg r2, TCGReg r3)
728{
729 tcg_debug_assert(is_vector_reg(v1));
730 tcg_debug_assert(is_general_reg(r2));
731 tcg_debug_assert(is_general_reg(r3));
732 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2);
733 tcg_out16(s, r3 << 12);
734 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0));
735}
736
22cb37b4
RH		 737static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1,
738 intptr_t d2, TCGReg b2, TCGReg v3, int m4)
739{
740 tcg_debug_assert(is_vector_reg(v1));
741 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
742 tcg_debug_assert(is_general_reg(b2));
743 tcg_debug_assert(is_vector_reg(v3));
744 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
745 tcg_out16(s, b2 << 12 | d2);
746 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
747}
748
b33ce725
RH		 749static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
750 intptr_t d2, TCGReg b2, TCGReg r3, int m4)
751{
752 tcg_debug_assert(is_vector_reg(v1));
753 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
754 tcg_debug_assert(is_general_reg(b2));
755 tcg_debug_assert(is_general_reg(r3));
756 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3);
757 tcg_out16(s, b2 << 12 | d2);
758 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
759}
760
761static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1,
762 intptr_t d2, TCGReg b2, TCGReg v3, int m4)
763{
764 tcg_debug_assert(is_general_reg(r1));
765 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
766 tcg_debug_assert(is_general_reg(b2));
767 tcg_debug_assert(is_vector_reg(v3));
768 tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf));
769 tcg_out16(s, b2 << 12 | d2);
770 tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12));
771}
772
2dabf742
RH		 773static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1,
774 TCGReg b2, TCGReg x2, intptr_t d2, int m3)
775{
776 tcg_debug_assert(is_vector_reg(v1));
777 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
778 tcg_debug_assert(is_general_reg(x2));
779 tcg_debug_assert(is_general_reg(b2));
780 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2);
781 tcg_out16(s, (b2 << 12) | d2);
782 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12));
783}
784
48bb3750
RH		 785/* Emit an opcode with "type-checking" of the format. */
786#define tcg_out_insn(S, FMT, OP, ...) \
787 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
788
789
790/* emit 64-bit shifts */
791static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest,
792 TCGReg src, TCGReg sh_reg, int sh_imm)
793{
794 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm);
795}
796
797/* emit 32-bit shifts */
798static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
799 TCGReg sh_reg, int sh_imm)
800{
801 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
802}
803
78113e83 804static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
48bb3750 805{
b33ce725
RH		 806 if (src == dst) {
807 return true;
808 }
809 switch (type) {
810 case TCG_TYPE_I32:
811 if (likely(is_general_reg(dst) && is_general_reg(src))) {
48bb3750 812 tcg_out_insn(s, RR, LR, dst, src);
b33ce725 813 break;
48bb3750 814 }
b33ce725
RH		 815 /* fallthru */
816
817 case TCG_TYPE_I64:
818 if (likely(is_general_reg(dst))) {
819 if (likely(is_general_reg(src))) {
820 tcg_out_insn(s, RRE, LGR, dst, src);
821 } else {
822 tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3);
823 }
824 break;
825 } else if (is_general_reg(src)) {
826 tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3);
827 break;
828 }
829 /* fallthru */
830
831 case TCG_TYPE_V64:
832 case TCG_TYPE_V128:
833 tcg_out_insn(s, VRRa, VLR, dst, src, 0);
834 break;
835
836 default:
837 g_assert_not_reached();
48bb3750 838 }
78113e83 839 return true;
48bb3750
RH		 840}
841
1818c71b 842static const S390Opcode li_insns[4] = {
28eef8aa
RH		 843 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
844};
90497e03
RH		 845static const S390Opcode oi_insns[4] = {
846 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
847};
1818c71b
RH		 848static const S390Opcode lif_insns[2] = {
849 RIL_LLILF, RIL_LLIHF,
850};
48bb3750 851
1818c71b
RH		 852/* load a register with an immediate value */
853static void tcg_out_movi(TCGContext *s, TCGType type,
854 TCGReg ret, tcg_target_long sval)
28eef8aa 855{
48bb3750 856 tcg_target_ulong uval = sval;
1818c71b 857 ptrdiff_t pc_off;
48bb3750
RH		 858 int i;
859
860 if (type == TCG_TYPE_I32) {
861 uval = (uint32_t)sval;
862 sval = (int32_t)sval;
863 }
864
865 /* Try all 32-bit insns that can load it in one go. */
866 if (sval >= -0x8000 && sval < 0x8000) {
867 tcg_out_insn(s, RI, LGHI, ret, sval);
28eef8aa
RH		 868 return;
869 }
870
1818c71b
RH		 871 i = is_const_p16(uval);
872 if (i >= 0) {
873 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16));
874 return;
28eef8aa
RH		 875 }
876
48bb3750 877 /* Try all 48-bit insns that can load it in one go. */
3e25f7da
RH		 878 if (sval == (int32_t)sval) {
879 tcg_out_insn(s, RIL, LGFI, ret, sval);
880 return;
881 }
1818c71b
RH		 882
883 i = is_const_p32(uval);
884 if (i >= 0) {
885 tcg_out_insn_RIL(s, lif_insns[i], ret, uval >> (i * 32));
3e25f7da 886 return;
48bb3750
RH		 887 }
888
1b74cf6e
RH		 889 /* Try for PC-relative address load. For odd addresses, add one. */
890 pc_off = tcg_pcrel_diff(s, (void *)sval) >> 1;
891 if (pc_off == (int32_t)pc_off) {
892 tcg_out_insn(s, RIL, LARL, ret, pc_off);
893 if (sval & 1) {
894 tcg_out_insn(s, RI, AGHI, ret, 1);
48bb3750 895 }
1b74cf6e 896 return;
48bb3750
RH		 897 }
898
90497e03
RH		 899 /* Otherwise, load it by parts. */
900 i = is_const_p16((uint32_t)uval);
901 if (i >= 0) {
902 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16));
903 } else {
904 tcg_out_insn(s, RIL, LLILF, ret, uval);
905 }
906 uval >>= 32;
907 i = is_const_p16(uval);
908 if (i >= 0) {
909 tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16));
910 } else {
911 tcg_out_insn(s, RIL, OIHF, ret, uval);
912 }
48bb3750
RH		 913}
914
48bb3750
RH		 915/* Emit a load/store type instruction. Inputs are:
916 DATA: The register to be loaded or stored.
917 BASE+OFS: The effective address.
918 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0.
919 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */
920
921static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
922 TCGReg data, TCGReg base, TCGReg index,
923 tcg_target_long ofs)
924{
925 if (ofs < -0x80000 || ofs >= 0x80000) {
78c9f7c5
RH		 926 /* Combine the low 20 bits of the offset with the actual load insn;
927 the high 44 bits must come from an immediate load. */
928 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000;
929 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low);
930 ofs = low;
48bb3750
RH		 931
932 /* If we were already given an index register, add it in. */
933 if (index != TCG_REG_NONE) {
934 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
935 }
936 index = TCG_TMP0;
937 }
938
939 if (opc_rx && ofs >= 0 && ofs < 0x1000) {
940 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs);
941 } else {
942 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs);
943 }
2827822e
AG		 944}
945
2dabf742
RH		 946static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx,
947 TCGReg data, TCGReg base, TCGReg index,
948 tcg_target_long ofs, int m3)
949{
950 if (ofs < 0 || ofs >= 0x1000) {
951 if (ofs >= -0x80000 && ofs < 0x80000) {
952 tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs);
953 base = TCG_TMP0;
954 index = TCG_REG_NONE;
955 ofs = 0;
956 } else {
957 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs);
958 if (index != TCG_REG_NONE) {
959 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
960 }
961 index = TCG_TMP0;
962 ofs = 0;
963 }
964 }
965 tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3);
966}
48bb3750 967
2827822e 968/* load data without address translation or endianness conversion */
2dabf742
RH		 969static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
970 TCGReg base, intptr_t ofs)
2827822e 971{
2dabf742
RH		 972 switch (type) {
973 case TCG_TYPE_I32:
974 if (likely(is_general_reg(data))) {
975 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
976 break;
977 }
978 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32);
979 break;
980
981 case TCG_TYPE_I64:
982 if (likely(is_general_reg(data))) {
983 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
984 break;
985 }
986 /* fallthru */
987
988 case TCG_TYPE_V64:
989 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64);
990 break;
991
992 case TCG_TYPE_V128:
993 /* Hint quadword aligned. */
994 tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4);
995 break;
996
997 default:
998 g_assert_not_reached();
48bb3750 999 }
2827822e
AG		 1000}
1001
2dabf742
RH		 1002static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
1003 TCGReg base, intptr_t ofs)
2827822e 1004{
2dabf742
RH		 1005 switch (type) {
1006 case TCG_TYPE_I32:
1007 if (likely(is_general_reg(data))) {
1008 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
1009 } else {
1010 tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1);
1011 }
1012 break;
1013
1014 case TCG_TYPE_I64:
1015 if (likely(is_general_reg(data))) {
1016 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
1017 break;
1018 }
1019 /* fallthru */
1020
1021 case TCG_TYPE_V64:
1022 tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0);
1023 break;
1024
1025 case TCG_TYPE_V128:
1026 /* Hint quadword aligned. */
1027 tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4);
1028 break;
1029
1030 default:
1031 g_assert_not_reached();
48bb3750
RH		 1032 }
1033}
1034
59d7c14e
RH		 1035static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
1036 TCGReg base, intptr_t ofs)
1037{
1038 return false;
1039}
1040
767c2503
RH		 1041static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
1042{
1043 return false;
1044}
1045
6a6d772e
RH		 1046static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
1047 tcg_target_long imm)
1048{
1049 /* This function is only used for passing structs by reference. */
1050 tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm);
1051}
1052
f0bffc27
RH		 1053static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
1054 int msb, int lsb, int ofs, int z)
1055{
1056 /* Format RIE-f */
d84ca804 1057 tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src);
f0bffc27 1058 tcg_out16(s, (msb << 8) | (z << 7) | lsb);
d84ca804 1059 tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff));
f0bffc27
RH		 1060}
1061
678155b2 1062static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
48bb3750 1063{
3e25f7da 1064 tcg_out_insn(s, RRE, LGBR, dest, src);
48bb3750
RH		 1065}
1066
d0e66c89 1067static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src)
48bb3750 1068{
3e25f7da 1069 tcg_out_insn(s, RRE, LLGCR, dest, src);
48bb3750
RH		 1070}
1071
753e42ea 1072static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
48bb3750 1073{
3e25f7da 1074 tcg_out_insn(s, RRE, LGHR, dest, src);
48bb3750
RH		 1075}
1076
379afdff 1077static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src)
48bb3750 1078{
3e25f7da 1079 tcg_out_insn(s, RRE, LLGHR, dest, src);
48bb3750
RH		 1080}
1081
52bf3398 1082static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
48bb3750
RH		 1083{
1084 tcg_out_insn(s, RRE, LGFR, dest, src);
1085}
1086
9ecf5f61 1087static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
48bb3750
RH		 1088{
1089 tcg_out_insn(s, RRE, LLGFR, dest, src);
1090}
1091
9c6aa274
RH		 1092static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src)
1093{
1094 tcg_out_ext32s(s, dest, src);
1095}
1096
b9bfe000
RH		 1097static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src)
1098{
1099 tcg_out_ext32u(s, dest, src);
1100}
1101
b8b94ac6
RH		 1102static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src)
1103{
1104 tcg_out_mov(s, TCG_TYPE_I32, dest, src);
1105}
1106
547ec121
RH		 1107static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val)
1108{
1109 int msb, lsb;
1110 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
1111 /* Achieve wraparound by swapping msb and lsb. */
1112 msb = 64 - ctz64(~val);
1113 lsb = clz64(~val) - 1;
1114 } else {
1115 msb = clz64(val);
1116 lsb = 63 - ctz64(val);
1117 }
1118 tcg_out_risbg(s, out, in, msb, lsb, 0, 1);
1119}
1120
07ff7983 1121static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
48bb3750
RH		 1122{
1123 static const S390Opcode ni_insns[4] = {
1124 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
1125 };
1126 static const S390Opcode nif_insns[2] = {
1127 RIL_NILF, RIL_NIHF
1128 };
07ff7983 1129 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull);
48bb3750
RH		 1130 int i;
1131
48bb3750 1132 /* Look for the zero-extensions. */
07ff7983 1133 if ((val & valid) == 0xffffffff) {
9ecf5f61 1134 tcg_out_ext32u(s, dest, dest);
48bb3750
RH		 1135 return;
1136 }
3e25f7da 1137 if ((val & valid) == 0xff) {
d0e66c89 1138 tcg_out_ext8u(s, dest, dest);
3e25f7da
RH		 1139 return;
1140 }
1141 if ((val & valid) == 0xffff) {
379afdff 1142 tcg_out_ext16u(s, dest, dest);
3e25f7da 1143 return;
07ff7983 1144 }
48bb3750 1145
4134083f
RH		 1146 i = is_const_p16(~val & valid);
1147 if (i >= 0) {
1148 tcg_out_insn_RI(s, ni_insns[i], dest, val >> (i * 16));
1149 return;
07ff7983 1150 }
48bb3750 1151
4134083f
RH		 1152 i = is_const_p32(~val & valid);
1153 tcg_debug_assert(i == 0 || type != TCG_TYPE_I32);
1154 if (i >= 0) {
1155 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> (i * 32));
1156 return;
07ff7983 1157 }
4134083f 1158
9c3bfb79 1159 if (risbg_mask(val)) {
547ec121 1160 tgen_andi_risbg(s, dest, dest, val);
f0bffc27
RH		 1161 return;
1162 }
48bb3750 1163
4134083f 1164 g_assert_not_reached();
48bb3750
RH		 1165}
1166
b2509acc 1167static void tgen_ori(TCGContext *s, TCGReg dest, uint64_t val)
48bb3750 1168{
4046d9ca 1169 static const S390Opcode oif_insns[2] = {
48bb3750
RH		 1170 RIL_OILF, RIL_OIHF
1171 };
1172
1173 int i;
1174
b2509acc
RH		 1175 i = is_const_p16(val);
1176 if (i >= 0) {
1177 tcg_out_insn_RI(s, oi_insns[i], dest, val >> (i * 16));
48bb3750
RH		 1178 return;
1179 }
1180
b2509acc
RH		 1181 i = is_const_p32(val);
1182 if (i >= 0) {
1183 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> (i * 32));
1184 return;
4046d9ca 1185 }
48bb3750 1186
b2509acc 1187 g_assert_not_reached();
48bb3750
RH		 1188}
1189
b2509acc 1190static void tgen_xori(TCGContext *s, TCGReg dest, uint64_t val)
48bb3750 1191{
b2509acc
RH		 1192 switch (is_const_p32(val)) {
1193 case 0:
3e25f7da 1194 tcg_out_insn(s, RIL, XILF, dest, val);
b2509acc
RH		 1195 break;
1196 case 1:
3e25f7da 1197 tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
b2509acc
RH		 1198 break;
1199 default:
1200 g_assert_not_reached();
48bb3750
RH		 1201 }
1202}
1203
5c837bbc
RH		 1204static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
1205 TCGArg c2, bool c2const, bool need_carry, int *inv_cc)
48bb3750 1206{
bcc66562 1207 bool is_unsigned = is_unsigned_cond(c);
5c837bbc 1208 TCGCond inv_c = tcg_invert_cond(c);
a534bb15
RH		 1209 S390Opcode op;
1210
48bb3750
RH		 1211 if (c2const) {
1212 if (c2 == 0) {
65839b56
RH		 1213 if (!(is_unsigned && need_carry)) {
1214 if (type == TCG_TYPE_I32) {
1215 tcg_out_insn(s, RR, LTR, r1, r1);
1216 } else {
1217 tcg_out_insn(s, RRE, LTGR, r1, r1);
1218 }
5c837bbc 1219 *inv_cc = tcg_cond_to_ltr_cond[inv_c];
65839b56
RH		 1220 return tcg_cond_to_ltr_cond[c];
1221 }
65839b56 1222 }
a534bb15
RH		 1223
1224 if (!is_unsigned && c2 == (int16_t)c2) {
1225 op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI);
1226 tcg_out_insn_RI(s, op, r1, c2);
1227 goto exit;
1228 }
1229
3e25f7da
RH		 1230 if (type == TCG_TYPE_I32) {
1231 op = (is_unsigned ? RIL_CLFI : RIL_CFI);
1232 tcg_out_insn_RIL(s, op, r1, c2);
1233 goto exit;
1234 }
32c256ed
RH		 1235
1236 /*
1237 * Constraints are for a signed 33-bit operand, which is a
1238 * convenient superset of this signed/unsigned test.
1239 */
3e25f7da
RH		 1240 if (c2 == (is_unsigned ? (TCGArg)(uint32_t)c2 : (TCGArg)(int32_t)c2)) {
1241 op = (is_unsigned ? RIL_CLGFI : RIL_CGFI);
1242 tcg_out_insn_RIL(s, op, r1, c2);
1243 goto exit;
48bb3750 1244 }
a534bb15 1245
32c256ed
RH		 1246 /* Load everything else into a register. */
1247 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, c2);
1248 c2 = TCG_TMP0;
48bb3750 1249 }
a534bb15
RH		 1250
1251 if (type == TCG_TYPE_I32) {
1252 op = (is_unsigned ? RR_CLR : RR_CR);
1253 tcg_out_insn_RR(s, op, r1, c2);
1254 } else {
1255 op = (is_unsigned ? RRE_CLGR : RRE_CGR);
1256 tcg_out_insn_RRE(s, op, r1, c2);
1257 }
1258
1259 exit:
5c837bbc 1260 *inv_cc = tcg_cond_to_s390_cond[inv_c];
48bb3750
RH		 1261 return tcg_cond_to_s390_cond[c];
1262}
1263
5c837bbc
RH		 1264static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
1265 TCGArg c2, bool c2const, bool need_carry)
1266{
1267 int inv_cc;
1268 return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc);
1269}
1270
7b7066b1 1271static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
96a9f093 1272 TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
48bb3750 1273{
7b7066b1
RH		 1274 int cc;
1275
7af525af 1276 /* With LOC2, we can always emit the minimum 3 insns. */
748b7f3e 1277 if (HAVE_FACILITY(LOAD_ON_COND2)) {
7af525af
RH		 1278 /* Emit: d = 0, d = (cc ? 1 : d). */
1279 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
1280 tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
d84ca804 1281 tcg_out_insn(s, RIEg, LOCGHI, dest, 1, cc);
7af525af
RH		 1282 return;
1283 }
1284
4609190b 1285 restart:
7b7066b1 1286 switch (cond) {
4609190b
RH		 1287 case TCG_COND_NE:
1288 /* X != 0 is X > 0. */
1289 if (c2const && c2 == 0) {
1290 cond = TCG_COND_GTU;
1291 } else {
1292 break;
1293 }
1294 /* fallthru */
1295
7b7066b1
RH		 1296 case TCG_COND_GTU:
1297 case TCG_COND_GT:
7b7066b1
RH		 1298 /* The result of a compare has CC=2 for GT and CC=3 unused.
1299 ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */
65839b56 1300 tgen_cmp(s, type, cond, c1, c2, c2const, true);
7b7066b1
RH		 1301 tcg_out_movi(s, type, dest, 0);
1302 tcg_out_insn(s, RRE, ALCGR, dest, dest);
1303 return;
1304
4609190b
RH		 1305 case TCG_COND_EQ:
1306 /* X == 0 is X <= 0. */
1307 if (c2const && c2 == 0) {
1308 cond = TCG_COND_LEU;
7b7066b1 1309 } else {
4609190b 1310 break;
7b7066b1 1311 }
4609190b 1312 /* fallthru */
7b7066b1
RH		 1313
1314 case TCG_COND_LEU:
4609190b
RH		 1315 case TCG_COND_LE:
1316 /* As above, but we're looking for borrow, or !carry.
1317 The second insn computes d - d - borrow, or -1 for true
1318 and 0 for false. So we must mask to 1 bit afterward. */
1319 tgen_cmp(s, type, cond, c1, c2, c2const, true);
1320 tcg_out_insn(s, RRE, SLBGR, dest, dest);
1321 tgen_andi(s, type, dest, 1);
1322 return;
1323
1324 case TCG_COND_GEU:
7b7066b1
RH		 1325 case TCG_COND_LTU:
1326 case TCG_COND_LT:
4609190b
RH		 1327 case TCG_COND_GE:
1328 /* Swap operands so that we can use LEU/GTU/GT/LE. */
c68d5b7a 1329 if (!c2const) {
7b7066b1
RH		 1330 TCGReg t = c1;
1331 c1 = c2;
1332 c2 = t;
c68d5b7a
RH		 1333 cond = tcg_swap_cond(cond);
1334 goto restart;
7b7066b1 1335 }
c68d5b7a 1336 break;
48bb3750 1337
7b7066b1 1338 default:
4609190b 1339 g_assert_not_reached();
7b7066b1
RH		 1340 }
1341
65839b56 1342 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
c68d5b7a
RH		 1343 /* Emit: d = 0, t = 1, d = (cc ? t : d). */
1344 tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
1345 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
1dd06b1a 1346 tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc);
48bb3750
RH		 1347}
1348
23d1394a
RH		 1349static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest,
1350 TCGArg v3, int v3const, TCGReg v4,
1351 int cc, int inv_cc)
1352{
1353 TCGReg src;
1354
1355 if (v3const) {
1356 if (dest == v4) {
1357 if (HAVE_FACILITY(LOAD_ON_COND2)) {
1358 /* Emit: if (cc) dest = v3. */
1359 tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc);
1360 return;
1361 }
1362 tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3);
1363 src = TCG_TMP0;
1364 } else {
1365 /* LGR+LOCGHI is larger than LGHI+LOCGR. */
1366 tcg_out_insn(s, RI, LGHI, dest, v3);
1367 cc = inv_cc;
1368 src = v4;
1369 }
1370 } else {
0bbf0f7a
RH		 1371 if (HAVE_FACILITY(MISC_INSN_EXT3)) {
1372 /* Emit: dest = cc ? v3 : v4. */
1373 tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc);
1374 return;
1375 }
23d1394a
RH		 1376 if (dest == v4) {
1377 src = v3;
1378 } else {
1379 tcg_out_mov(s, type, dest, v3);
1380 cc = inv_cc;
1381 src = v4;
1382 }
1383 }
1384
1385 /* Emit: if (cc) dest = src. */
1386 tcg_out_insn(s, RRFc, LOCGR, dest, src, cc);
1387}
1388
96a9f093 1389static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
7af525af 1390 TCGReg c1, TCGArg c2, int c2const,
23d1394a 1391 TCGArg v3, int v3const, TCGReg v4)
96a9f093 1392{
5c837bbc
RH		 1393 int cc, inv_cc;
1394
1395 cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc);
23d1394a 1396 tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc);
96a9f093
RH		 1397}
1398
ce411066
RH		 1399static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
1400 TCGArg a2, int a2const)
1401{
1402 /* Since this sets both R and R+1, we have no choice but to store the
1403 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */
1404 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
1405 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1);
1406
1407 if (a2const && a2 == 64) {
1408 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
bfff8518 1409 return;
ce411066 1410 }
bfff8518
RH		 1411
1412 /*
1413 * Conditions from FLOGR are:
1414 * 2 -> one bit found
1415 * 8 -> no one bit found
1416 */
1417 tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2);
ce411066
RH		 1418}
1419
29a5ea73
RH		 1420static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
1421{
1422 /* With MIE3, and bit 0 of m4 set, we get the complete result. */
1423 if (HAVE_FACILITY(MISC_INSN_EXT3)) {
1424 if (type == TCG_TYPE_I32) {
9ecf5f61 1425 tcg_out_ext32u(s, dest, src);
29a5ea73
RH		 1426 src = dest;
1427 }
1428 tcg_out_insn(s, RRFc, POPCNT, dest, src, 8);
1429 return;
1430 }
1431
1432 /* Without MIE3, each byte gets the count of bits for the byte. */
1433 tcg_out_insn(s, RRFc, POPCNT, dest, src, 0);
1434
1435 /* Multiply to sum each byte at the top of the word. */
1436 if (type == TCG_TYPE_I32) {
1437 tcg_out_insn(s, RIL, MSFI, dest, 0x01010101);
1438 tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24);
1439 } else {
1440 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull);
1441 tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0);
1442 tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56);
1443 }
1444}
1445
d5690ea4 1446static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
752b1be9 1447 int ofs, int len, int z)
d5690ea4
RH		 1448{
1449 int lsb = (63 - ofs);
1450 int msb = lsb - (len - 1);
752b1be9 1451 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z);
d5690ea4
RH		 1452}
1453
b0bf5fe8
RH		 1454static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
1455 int ofs, int len)
1456{
1457 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
1458}
1459
ffd0e507 1460static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest)
48bb3750 1461{
79dae4dd 1462 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1;
8c081b18 1463 if (off == (int16_t)off) {
48bb3750
RH		 1464 tcg_out_insn(s, RI, BRC, cc, off);
1465 } else if (off == (int32_t)off) {
1466 tcg_out_insn(s, RIL, BRCL, cc, off);
1467 } else {
8c081b18 1468 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
48bb3750
RH		 1469 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0);
1470 }
1471}
1472
bec16311 1473static void tgen_branch(TCGContext *s, int cc, TCGLabel *l)
48bb3750 1474{
48bb3750 1475 if (l->has_value) {
8c081b18 1476 tgen_gotoi(s, cc, l->u.value_ptr);
48bb3750
RH		 1477 } else {
1478 tcg_out16(s, RI_BRC | (cc << 4));
e692a349 1479 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2);
8c081b18 1480 s->code_ptr += 1;
48bb3750
RH		 1481 }
1482}
1483
1484static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
bec16311 1485 TCGReg r1, TCGReg r2, TCGLabel *l)
48bb3750 1486{
79dae4dd 1487 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
d84ca804 1488 /* Format RIE-b */
48bb3750 1489 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
79dae4dd 1490 tcg_out16(s, 0);
48bb3750
RH		 1491 tcg_out16(s, cc << 12 | (opc & 0xff));
1492}
1493
1494static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
bec16311 1495 TCGReg r1, int i2, TCGLabel *l)
48bb3750 1496{
79dae4dd 1497 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
d84ca804 1498 /* Format RIE-c */
48bb3750 1499 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
79dae4dd 1500 tcg_out16(s, 0);
48bb3750
RH		 1501 tcg_out16(s, (i2 << 8) | (opc & 0xff));
1502}
1503
1504static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
bec16311 1505 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l)
48bb3750
RH		 1506{
1507 int cc;
9c3bfb79
RH		 1508 bool is_unsigned = is_unsigned_cond(c);
1509 bool in_range;
1510 S390Opcode opc;
48bb3750 1511
9c3bfb79 1512 cc = tcg_cond_to_s390_cond[c];
48bb3750 1513
9c3bfb79
RH		 1514 if (!c2const) {
1515 opc = (type == TCG_TYPE_I32
d84ca804
RH		 1516 ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ)
1517 : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ));
9c3bfb79
RH		 1518 tgen_compare_branch(s, opc, cc, r1, c2, l);
1519 return;
1520 }
48bb3750 1521
9c3bfb79
RH		 1522 /*
1523 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
1524 * If the immediate we've been given does not fit that range, we'll
1525 * fall back to separate compare and branch instructions using the
1526 * larger comparison range afforded by COMPARE IMMEDIATE.
1527 */
1528 if (type == TCG_TYPE_I32) {
1529 if (is_unsigned) {
d84ca804 1530 opc = RIEc_CLIJ;
9c3bfb79 1531 in_range = (uint32_t)c2 == (uint8_t)c2;
48bb3750 1532 } else {
d84ca804 1533 opc = RIEc_CIJ;
9c3bfb79 1534 in_range = (int32_t)c2 == (int8_t)c2;
48bb3750 1535 }
9c3bfb79
RH		 1536 } else {
1537 if (is_unsigned) {
d84ca804 1538 opc = RIEc_CLGIJ;
9c3bfb79
RH		 1539 in_range = (uint64_t)c2 == (uint8_t)c2;
1540 } else {
d84ca804 1541 opc = RIEc_CGIJ;
9c3bfb79 1542 in_range = (int64_t)c2 == (int8_t)c2;
48bb3750
RH		 1543 }
1544 }
9c3bfb79
RH		 1545 if (in_range) {
1546 tgen_compare_imm_branch(s, opc, cc, r1, c2, l);
1547 return;
1548 }
48bb3750 1549
65839b56 1550 cc = tgen_cmp(s, type, c, r1, c2, c2const, false);
bec16311 1551 tgen_branch(s, cc, l);
48bb3750
RH		 1552}
1553
cee44b03 1554static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest)
48bb3750 1555{
79dae4dd 1556 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1;
48bb3750
RH		 1557 if (off == (int32_t)off) {
1558 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off);
1559 } else {
8c081b18 1560 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
48bb3750
RH		 1561 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0);
1562 }
1563}
1564
cee44b03
RH		 1565static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest,
1566 const TCGHelperInfo *info)
1567{
1568 tcg_out_call_int(s, dest);
1569}
1570
03654748
RH		 1571typedef struct {
1572 TCGReg base;
1573 TCGReg index;
1574 int disp;
1575} HostAddress;
1576
14776ab5 1577static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
03654748 1578 HostAddress h)
48bb3750 1579{
3c8691f5 1580 switch (opc & (MO_SSIZE | MO_BSWAP)) {
a5a04f28 1581 case MO_UB:
03654748 1582 tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp);
48bb3750 1583 break;
a5a04f28 1584 case MO_SB:
03654748 1585 tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp);
48bb3750 1586 break;
b8dd88b8
RH		 1587
1588 case MO_UW | MO_BSWAP:
1589 /* swapped unsigned halfword load with upper bits zeroed */
03654748 1590 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp);
379afdff 1591 tcg_out_ext16u(s, data, data);
b8dd88b8 1592 break;
a5a04f28 1593 case MO_UW:
03654748 1594 tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp);
b8dd88b8
RH		 1595 break;
1596
1597 case MO_SW | MO_BSWAP:
1598 /* swapped sign-extended halfword load */
03654748 1599 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp);
753e42ea 1600 tcg_out_ext16s(s, TCG_TYPE_REG, data, data);
48bb3750 1601 break;
a5a04f28 1602 case MO_SW:
03654748 1603 tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp);
b8dd88b8
RH		 1604 break;
1605
1606 case MO_UL | MO_BSWAP:
1607 /* swapped unsigned int load with upper bits zeroed */
03654748 1608 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp);
9ecf5f61 1609 tcg_out_ext32u(s, data, data);
48bb3750 1610 break;
a5a04f28 1611 case MO_UL:
03654748 1612 tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp);
b8dd88b8
RH		 1613 break;
1614
1615 case MO_SL | MO_BSWAP:
1616 /* swapped sign-extended int load */
03654748 1617 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp);
52bf3398 1618 tcg_out_ext32s(s, data, data);
48bb3750 1619 break;
a5a04f28 1620 case MO_SL:
03654748 1621 tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp);
b8dd88b8
RH		 1622 break;
1623
fc313c64 1624 case MO_UQ | MO_BSWAP:
03654748 1625 tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp);
48bb3750 1626 break;
fc313c64 1627 case MO_UQ:
03654748 1628 tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp);
48bb3750 1629 break;
b8dd88b8 1630
48bb3750 1631 default:
732e89f4 1632 g_assert_not_reached();
48bb3750
RH		 1633 }
1634}
1635
14776ab5 1636static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
03654748 1637 HostAddress h)
48bb3750 1638{
3c8691f5 1639 switch (opc & (MO_SIZE | MO_BSWAP)) {
a5a04f28 1640 case MO_UB:
03654748
RH		 1641 if (h.disp >= 0 && h.disp < 0x1000) {
1642 tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp);
48bb3750 1643 } else {
03654748 1644 tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp);
48bb3750
RH		 1645 }
1646 break;
b8dd88b8
RH		 1647
1648 case MO_UW | MO_BSWAP:
03654748 1649 tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp);
b8dd88b8 1650 break;
a5a04f28 1651 case MO_UW:
03654748
RH		 1652 if (h.disp >= 0 && h.disp < 0x1000) {
1653 tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp);
48bb3750 1654 } else {
03654748 1655 tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp);
48bb3750
RH		 1656 }
1657 break;
b8dd88b8
RH		 1658
1659 case MO_UL | MO_BSWAP:
03654748 1660 tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp);
b8dd88b8 1661 break;
a5a04f28 1662 case MO_UL:
03654748
RH		 1663 if (h.disp >= 0 && h.disp < 0x1000) {
1664 tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp);
48bb3750 1665 } else {
03654748 1666 tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp);
48bb3750
RH		 1667 }
1668 break;
b8dd88b8 1669
fc313c64 1670 case MO_UQ | MO_BSWAP:
03654748 1671 tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp);
b8dd88b8 1672 break;
fc313c64 1673 case MO_UQ:
03654748 1674 tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp);
48bb3750 1675 break;
b8dd88b8 1676
48bb3750 1677 default:
732e89f4 1678 g_assert_not_reached();
48bb3750
RH		 1679 }
1680}
1681
eb491329
RH		 1682static const TCGLdstHelperParam ldst_helper_param = {
1683 .ntmp = 1, .tmp = { TCG_TMP0 }
1684};
1685
aeee05f5 1686static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
fb596415 1687{
eb491329 1688 MemOp opc = get_memop(lb->oi);
48bb3750 1689
aeee05f5 1690 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
79dae4dd 1691 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
aeee05f5
RH		 1692 return false;
1693 }
48bb3750 1694
eb491329 1695 tcg_out_ld_helper_args(s, lb, &ldst_helper_param);
0cadc1ed 1696 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]);
eb491329 1697 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param);
65a62a75 1698
fb596415 1699 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
aeee05f5 1700 return true;
48bb3750
RH		 1701}
1702
aeee05f5 1703static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
48bb3750 1704{
eb491329 1705 MemOp opc = get_memop(lb->oi);
fb596415 1706
aeee05f5 1707 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
79dae4dd 1708 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
aeee05f5
RH		 1709 return false;
1710 }
fb596415 1711
eb491329 1712 tcg_out_st_helper_args(s, lb, &ldst_helper_param);
0cadc1ed 1713 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]);
fb596415
RH		 1714
1715 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
aeee05f5 1716 return true;
48bb3750 1717}
1cd49868 1718
0741b25e
RH		 1719/*
1720 * For softmmu, perform the TLB load and compare.
1721 * For useronly, perform any required alignment tests.
1722 * In both cases, return a TCGLabelQemuLdst structure if the slow path
1723 * is required and fill in @h with the host address for the fast path.
1724 */
1725static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1726 TCGReg addr_reg, MemOpIdx oi,
1727 bool is_ld)
48bb3750 1728{
0741b25e
RH		 1729 TCGLabelQemuLdst *ldst = NULL;
1730 MemOp opc = get_memop(oi);
1731 unsigned a_bits = get_alignment_bits(opc);
1732 unsigned a_mask = (1u << a_bits) - 1;
1733
1734#ifdef CONFIG_SOFTMMU
1735 unsigned s_bits = opc & MO_SIZE;
1736 unsigned s_mask = (1 << s_bits) - 1;
1737 int mem_index = get_mmuidx(oi);
1738 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1739 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1740 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1741 int ofs, a_off;
1742 uint64_t tlb_mask;
1743
1744 ldst = new_ldst_label(s);
1745 ldst->is_ld = is_ld;
1746 ldst->oi = oi;
1747 ldst->addrlo_reg = addr_reg;
1748
94901422 1749 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE,
0741b25e
RH		 1750 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1751
1752 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1753 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
94901422
RH		 1754 tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off);
1755 tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off);
0741b25e
RH		 1756
1757 /*
1758 * For aligned accesses, we check the first byte and include the alignment
1759 * bits within the address. For unaligned access, we check that we don't
1760 * cross pages using the address of the last byte of the access.
1761 */
1762 a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask);
1763 tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
1764 if (a_off == 0) {
94901422 1765 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask);
0741b25e 1766 } else {
94901422
RH		 1767 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off);
1768 tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask);
0741b25e 1769 }
03654748 1770
0741b25e
RH		 1771 if (is_ld) {
1772 ofs = offsetof(CPUTLBEntry, addr_read);
1773 } else {
1774 ofs = offsetof(CPUTLBEntry, addr_write);
1775 }
1776 if (TARGET_LONG_BITS == 32) {
94901422 1777 tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs);
0741b25e 1778 } else {
94901422 1779 tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs);
0741b25e
RH		 1780 }
1781
1782 tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
1783 ldst->label_ptr[0] = s->code_ptr++;
1784
94901422
RH		 1785 h->index = TCG_TMP0;
1786 tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE,
0741b25e
RH		 1787 offsetof(CPUTLBEntry, addend));
1788
0741b25e 1789 if (TARGET_LONG_BITS == 32) {
8b1b4597
RH		 1790 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg);
1791 h->base = TCG_REG_NONE;
1792 } else {
1793 h->base = addr_reg;
0741b25e
RH		 1794 }
1795 h->disp = 0;
1796#else
1797 if (a_mask) {
1798 ldst = new_ldst_label(s);
1799 ldst->is_ld = is_ld;
1800 ldst->oi = oi;
1801 ldst->addrlo_reg = addr_reg;
1802
1803 /* We are expecting a_bits to max out at 7, much lower than TMLL. */
1804 tcg_debug_assert(a_bits < 16);
1805 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask);
1806
1807 tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */
1808 ldst->label_ptr[0] = s->code_ptr++;
1809 }
1810
1811 h->base = addr_reg;
48bb3750 1812 if (TARGET_LONG_BITS == 32) {
03654748 1813 tcg_out_ext32u(s, TCG_TMP0, addr_reg);
0741b25e 1814 h->base = TCG_TMP0;
48bb3750 1815 }
b76f21a7 1816 if (guest_base < 0x80000) {
0741b25e
RH		 1817 h->index = TCG_REG_NONE;
1818 h->disp = guest_base;
48bb3750 1819 } else {
0741b25e
RH		 1820 h->index = TCG_GUEST_BASE_REG;
1821 h->disp = 0;
48bb3750 1822 }
0741b25e
RH		 1823#endif
1824
1825 return ldst;
48bb3750 1826}
48bb3750 1827
f24efee4 1828static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
01a3b5de 1829 MemOpIdx oi, TCGType data_type)
48bb3750 1830{
0741b25e 1831 TCGLabelQemuLdst *ldst;
03654748
RH		 1832 HostAddress h;
1833
0741b25e
RH		 1834 ldst = prepare_host_addr(s, &h, addr_reg, oi, true);
1835 tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h);
fb596415 1836
0741b25e
RH		 1837 if (ldst) {
1838 ldst->type = data_type;
1839 ldst->datalo_reg = data_reg;
1840 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1cd49868 1841 }
48bb3750
RH		 1842}
1843
f24efee4 1844static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
01a3b5de 1845 MemOpIdx oi, TCGType data_type)
48bb3750 1846{
0741b25e 1847 TCGLabelQemuLdst *ldst;
03654748
RH		 1848 HostAddress h;
1849
0741b25e
RH		 1850 ldst = prepare_host_addr(s, &h, addr_reg, oi, false);
1851 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h);
48bb3750 1852
0741b25e
RH		 1853 if (ldst) {
1854 ldst->type = data_type;
1855 ldst->datalo_reg = data_reg;
1856 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1cd49868 1857 }
2827822e
AG		 1858}
1859
b55a8d9d
RH		 1860static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1861{
1862 /* Reuse the zeroing that exists for goto_ptr. */
1863 if (a0 == 0) {
1864 tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue);
1865 } else {
1866 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0);
1867 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr);
1868 }
1869}
1870
cf7d6b8e
RH		 1871static void tcg_out_goto_tb(TCGContext *s, int which)
1872{
1873 /*
1874 * Branch displacement must be aligned for atomic patching;
1875 * see if we need to add extra nop before branch
1876 */
1877 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {
1878 tcg_out16(s, NOP);
1879 }
1880 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));
1881 set_jmp_insn_offset(s, which);
1882 s->code_ptr += 2;
1883 set_jmp_reset_offset(s, which);
1884}
1885
0fe1c98d
RH		 1886void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1887 uintptr_t jmp_rx, uintptr_t jmp_rw)
1888{
2fd2e78d
RH		 1889 if (!HAVE_FACILITY(GEN_INST_EXT)) {
1890 return;
1891 }
0fe1c98d
RH		 1892 /* patch the branch destination */
1893 uintptr_t addr = tb->jmp_target_addr[n];
1894 intptr_t disp = addr - (jmp_rx - 2);
1895 qatomic_set((int32_t *)jmp_rw, disp / 2);
1896 /* no need to flush icache explicitly */
1897}
1898
48bb3750
RH		 1899# define OP_32_64(x) \
1900 case glue(glue(INDEX_op_,x),_i32): \
1901 case glue(glue(INDEX_op_,x),_i64)
48bb3750 1902
a9751609 1903static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
5e8892db
MR		 1904 const TCGArg args[TCG_MAX_OP_ARGS],
1905 const int const_args[TCG_MAX_OP_ARGS])
2827822e 1906{
c2097136 1907 S390Opcode op, op2;
0db921e6 1908 TCGArg a0, a1, a2;
48bb3750
RH		 1909
1910 switch (opc) {
46644483 1911 case INDEX_op_goto_ptr:
829e1376 1912 a0 = args[0];
829e1376 1913 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);
46644483
RH		 1914 break;
1915
48bb3750
RH		 1916 OP_32_64(ld8u):
1917 /* ??? LLC (RXY format) is only present with the extended-immediate
1918 facility, whereas LLGC is always present. */
1919 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]);
1920 break;
1921
1922 OP_32_64(ld8s):
1923 /* ??? LB is no smaller than LGB, so no point to using it. */
1924 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]);
1925 break;
1926
1927 OP_32_64(ld16u):
1928 /* ??? LLH (RXY format) is only present with the extended-immediate
1929 facility, whereas LLGH is always present. */
1930 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]);
1931 break;
1932
1933 case INDEX_op_ld16s_i32:
1934 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]);
1935 break;
1936
1937 case INDEX_op_ld_i32:
1938 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1939 break;
1940
1941 OP_32_64(st8):
1942 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1],
1943 TCG_REG_NONE, args[2]);
1944 break;
1945
1946 OP_32_64(st16):
1947 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1],
1948 TCG_REG_NONE, args[2]);
1949 break;
1950
1951 case INDEX_op_st_i32:
1952 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1953 break;
1954
1955 case INDEX_op_add_i32:
0db921e6 1956 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
48bb3750 1957 if (const_args[2]) {
0db921e6
RH		 1958 do_addi_32:
1959 if (a0 == a1) {
1960 if (a2 == (int16_t)a2) {
1961 tcg_out_insn(s, RI, AHI, a0, a2);
1962 break;
1963 }
3e25f7da
RH		 1964 tcg_out_insn(s, RIL, AFI, a0, a2);
1965 break;
0db921e6
RH		 1966 }
1967 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
1968 } else if (a0 == a1) {
1969 tcg_out_insn(s, RR, AR, a0, a2);
48bb3750 1970 } else {
0db921e6 1971 tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
48bb3750
RH		 1972 }
1973 break;
1974 case INDEX_op_sub_i32:
0db921e6 1975 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
48bb3750 1976 if (const_args[2]) {
0db921e6
RH		 1977 a2 = -a2;
1978 goto do_addi_32;
c2097136
RH		 1979 } else if (a0 == a1) {
1980 tcg_out_insn(s, RR, SR, a0, a2);
1981 } else {
1dd06b1a 1982 tcg_out_insn(s, RRFa, SRK, a0, a1, a2);
48bb3750
RH		 1983 }
1984 break;
1985
1986 case INDEX_op_and_i32:
c2097136 1987 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
48bb3750 1988 if (const_args[2]) {
c2097136
RH		 1989 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1990 tgen_andi(s, TCG_TYPE_I32, a0, a2);
1991 } else if (a0 == a1) {
1992 tcg_out_insn(s, RR, NR, a0, a2);
48bb3750 1993 } else {
1dd06b1a 1994 tcg_out_insn(s, RRFa, NRK, a0, a1, a2);
48bb3750
RH		 1995 }
1996 break;
1997 case INDEX_op_or_i32:
c2097136 1998 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
48bb3750 1999 if (const_args[2]) {
c2097136 2000 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
b2509acc 2001 tgen_ori(s, a0, a2);
c2097136
RH		 2002 } else if (a0 == a1) {
2003 tcg_out_insn(s, RR, OR, a0, a2);
48bb3750 2004 } else {
1dd06b1a 2005 tcg_out_insn(s, RRFa, ORK, a0, a1, a2);
48bb3750
RH		 2006 }
2007 break;
2008 case INDEX_op_xor_i32:
c2097136 2009 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
48bb3750 2010 if (const_args[2]) {
c2097136 2011 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
a0332aca 2012 tcg_out_insn(s, RIL, XILF, a0, a2);
c2097136 2013 } else if (a0 == a1) {
48bb3750 2014 tcg_out_insn(s, RR, XR, args[0], args[2]);
c2097136 2015 } else {
1dd06b1a 2016 tcg_out_insn(s, RRFa, XRK, a0, a1, a2);
48bb3750
RH		 2017 }
2018 break;
2019
6c9b5c0f
RH		 2020 case INDEX_op_andc_i32:
2021 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
2022 if (const_args[2]) {
2023 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
2024 tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2);
2025 } else {
2026 tcg_out_insn(s, RRFa, NCRK, a0, a1, a2);
2027 }
2028 break;
2029 case INDEX_op_orc_i32:
2030 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
2031 if (const_args[2]) {
2032 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
2033 tgen_ori(s, a0, (uint32_t)~a2);
2034 } else {
2035 tcg_out_insn(s, RRFa, OCRK, a0, a1, a2);
2036 }
2037 break;
2038 case INDEX_op_eqv_i32:
2039 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
2040 if (const_args[2]) {
2041 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
2042 tcg_out_insn(s, RIL, XILF, a0, ~a2);
2043 } else {
2044 tcg_out_insn(s, RRFa, NXRK, a0, a1, a2);
2045 }
2046 break;
2047 case INDEX_op_nand_i32:
2048 tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]);
2049 break;
2050 case INDEX_op_nor_i32:
2051 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[2]);
2052 break;
2053
48bb3750
RH		 2054 case INDEX_op_neg_i32:
2055 tcg_out_insn(s, RR, LCR, args[0], args[1]);
2056 break;
6c9b5c0f
RH		 2057 case INDEX_op_not_i32:
2058 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[1]);
2059 break;
48bb3750
RH		 2060
2061 case INDEX_op_mul_i32:
92c89a07 2062 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
48bb3750 2063 if (const_args[2]) {
92c89a07
RH		 2064 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
2065 if (a2 == (int16_t)a2) {
2066 tcg_out_insn(s, RI, MHI, a0, a2);
48bb3750 2067 } else {
92c89a07 2068 tcg_out_insn(s, RIL, MSFI, a0, a2);
48bb3750 2069 }
92c89a07
RH		 2070 } else if (a0 == a1) {
2071 tcg_out_insn(s, RRE, MSR, a0, a2);
48bb3750 2072 } else {
92c89a07 2073 tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2);
48bb3750
RH		 2074 }
2075 break;
2076
2077 case INDEX_op_div2_i32:
4143f78d
RH		 2078 tcg_debug_assert(args[0] == args[2]);
2079 tcg_debug_assert(args[1] == args[3]);
2080 tcg_debug_assert((args[1] & 1) == 0);
2081 tcg_debug_assert(args[0] == args[1] + 1);
2082 tcg_out_insn(s, RR, DR, args[1], args[4]);
48bb3750
RH		 2083 break;
2084 case INDEX_op_divu2_i32:
4143f78d
RH		 2085 tcg_debug_assert(args[0] == args[2]);
2086 tcg_debug_assert(args[1] == args[3]);
2087 tcg_debug_assert((args[1] & 1) == 0);
2088 tcg_debug_assert(args[0] == args[1] + 1);
2089 tcg_out_insn(s, RRE, DLR, args[1], args[4]);
48bb3750
RH		 2090 break;
2091
2092 case INDEX_op_shl_i32:
2093 op = RS_SLL;
c2097136 2094 op2 = RSY_SLLK;
48bb3750 2095 do_shift32:
c2097136
RH		 2096 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
2097 if (a0 == a1) {
2098 if (const_args[2]) {
2099 tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2);
2100 } else {
2101 tcg_out_sh32(s, op, a0, a2, 0);
2102 }
48bb3750 2103 } else {
c2097136
RH		 2104 /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */
2105 if (const_args[2]) {
2106 tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2);
2107 } else {
2108 tcg_out_sh64(s, op2, a0, a1, a2, 0);
2109 }
48bb3750
RH		 2110 }
2111 break;
2112 case INDEX_op_shr_i32:
2113 op = RS_SRL;
c2097136 2114 op2 = RSY_SRLK;
48bb3750
RH		 2115 goto do_shift32;
2116 case INDEX_op_sar_i32:
2117 op = RS_SRA;
c2097136 2118 op2 = RSY_SRAK;
48bb3750
RH		 2119 goto do_shift32;
2120
2121 case INDEX_op_rotl_i32:
2122 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */
2123 if (const_args[2]) {
2124 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]);
2125 } else {
2126 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0);
2127 }
2128 break;
2129 case INDEX_op_rotr_i32:
2130 if (const_args[2]) {
2131 tcg_out_sh64(s, RSY_RLL, args[0], args[1],
2132 TCG_REG_NONE, (32 - args[2]) & 31);
2133 } else {
2134 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
2135 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0);
2136 }
2137 break;
2138
1619ee9e
RH		 2139 case INDEX_op_bswap16_i32:
2140 a0 = args[0], a1 = args[1], a2 = args[2];
2141 tcg_out_insn(s, RRE, LRVR, a0, a1);
2142 if (a2 & TCG_BSWAP_OS) {
2143 tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16);
2144 } else {
2145 tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16);
2146 }
48bb3750 2147 break;
1619ee9e
RH		 2148 case INDEX_op_bswap16_i64:
2149 a0 = args[0], a1 = args[1], a2 = args[2];
2150 tcg_out_insn(s, RRE, LRVGR, a0, a1);
2151 if (a2 & TCG_BSWAP_OS) {
2152 tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48);
2153 } else {
2154 tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48);
2155 }
2156 break;
2157
2158 case INDEX_op_bswap32_i32:
48bb3750
RH		 2159 tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
2160 break;
1619ee9e
RH		 2161 case INDEX_op_bswap32_i64:
2162 a0 = args[0], a1 = args[1], a2 = args[2];
2163 tcg_out_insn(s, RRE, LRVR, a0, a1);
2164 if (a2 & TCG_BSWAP_OS) {
52bf3398 2165 tcg_out_ext32s(s, a0, a0);
1619ee9e 2166 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
9ecf5f61 2167 tcg_out_ext32u(s, a0, a0);
1619ee9e
RH		 2168 }
2169 break;
48bb3750 2170
3790b918 2171 case INDEX_op_add2_i32:
ad19b358
RH		 2172 if (const_args[4]) {
2173 tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
2174 } else {
2175 tcg_out_insn(s, RR, ALR, args[0], args[4]);
2176 }
3790b918
RH		 2177 tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
2178 break;
2179 case INDEX_op_sub2_i32:
ad19b358
RH		 2180 if (const_args[4]) {
2181 tcg_out_insn(s, RIL, SLFI, args[0], args[4]);
2182 } else {
2183 tcg_out_insn(s, RR, SLR, args[0], args[4]);
2184 }
3790b918
RH		 2185 tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
2186 break;
2187
48bb3750 2188 case INDEX_op_br:
bec16311 2189 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0]));
48bb3750
RH		 2190 break;
2191
2192 case INDEX_op_brcond_i32:
2193 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0],
bec16311 2194 args[1], const_args[1], arg_label(args[3]));
48bb3750
RH		 2195 break;
2196 case INDEX_op_setcond_i32:
2197 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1],
2198 args[2], const_args[2]);
2199 break;
96a9f093
RH		 2200 case INDEX_op_movcond_i32:
2201 tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1],
23d1394a 2202 args[2], const_args[2], args[3], const_args[3], args[4]);
96a9f093 2203 break;
48bb3750 2204
f24efee4 2205 case INDEX_op_qemu_ld_i32:
01a3b5de
RH		 2206 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32);
2207 break;
f24efee4 2208 case INDEX_op_qemu_ld_i64:
01a3b5de 2209 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64);
48bb3750 2210 break;
f24efee4 2211 case INDEX_op_qemu_st_i32:
01a3b5de
RH		 2212 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32);
2213 break;
f24efee4 2214 case INDEX_op_qemu_st_i64:
01a3b5de 2215 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64);
48bb3750
RH		 2216 break;
2217
48bb3750
RH		 2218 case INDEX_op_ld16s_i64:
2219 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]);
2220 break;
2221 case INDEX_op_ld32u_i64:
2222 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]);
2223 break;
2224 case INDEX_op_ld32s_i64:
2225 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]);
2226 break;
2227 case INDEX_op_ld_i64:
2228 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
2229 break;
2230
2231 case INDEX_op_st32_i64:
2232 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
2233 break;
2234 case INDEX_op_st_i64:
2235 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
2236 break;
2237
2238 case INDEX_op_add_i64:
0db921e6 2239 a0 = args[0], a1 = args[1], a2 = args[2];
48bb3750 2240 if (const_args[2]) {
0db921e6
RH		 2241 do_addi_64:
2242 if (a0 == a1) {
2243 if (a2 == (int16_t)a2) {
2244 tcg_out_insn(s, RI, AGHI, a0, a2);
2245 break;
2246 }
3e25f7da
RH		 2247 if (a2 == (int32_t)a2) {
2248 tcg_out_insn(s, RIL, AGFI, a0, a2);
2249 break;
2250 }
2251 if (a2 == (uint32_t)a2) {
2252 tcg_out_insn(s, RIL, ALGFI, a0, a2);
2253 break;
2254 }
2255 if (-a2 == (uint32_t)-a2) {
2256 tcg_out_insn(s, RIL, SLGFI, a0, -a2);
2257 break;
0db921e6
RH		 2258 }
2259 }
2260 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
2261 } else if (a0 == a1) {
2262 tcg_out_insn(s, RRE, AGR, a0, a2);
48bb3750 2263 } else {
0db921e6 2264 tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
48bb3750
RH		 2265 }
2266 break;
2267 case INDEX_op_sub_i64:
0db921e6 2268 a0 = args[0], a1 = args[1], a2 = args[2];
48bb3750 2269 if (const_args[2]) {
0db921e6
RH		 2270 a2 = -a2;
2271 goto do_addi_64;
48bb3750 2272 } else {
1dd06b1a 2273 tcg_out_insn(s, RRFa, SGRK, a0, a1, a2);
48bb3750
RH		 2274 }
2275 break;
2276
2277 case INDEX_op_and_i64:
c2097136 2278 a0 = args[0], a1 = args[1], a2 = args[2];
48bb3750 2279 if (const_args[2]) {
c2097136 2280 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
07ff7983 2281 tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
c2097136 2282 } else {
1dd06b1a 2283 tcg_out_insn(s, RRFa, NGRK, a0, a1, a2);
48bb3750
RH		 2284 }
2285 break;
2286 case INDEX_op_or_i64:
c2097136 2287 a0 = args[0], a1 = args[1], a2 = args[2];
48bb3750 2288 if (const_args[2]) {
c2097136 2289 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
b2509acc 2290 tgen_ori(s, a0, a2);
48bb3750 2291 } else {
1dd06b1a 2292 tcg_out_insn(s, RRFa, OGRK, a0, a1, a2);
48bb3750
RH		 2293 }
2294 break;
2295 case INDEX_op_xor_i64:
c2097136 2296 a0 = args[0], a1 = args[1], a2 = args[2];
48bb3750 2297 if (const_args[2]) {
c2097136 2298 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
b2509acc 2299 tgen_xori(s, a0, a2);
48bb3750 2300 } else {
1dd06b1a 2301 tcg_out_insn(s, RRFa, XGRK, a0, a1, a2);
48bb3750
RH		 2302 }
2303 break;
2304
6c9b5c0f
RH		 2305 case INDEX_op_andc_i64:
2306 a0 = args[0], a1 = args[1], a2 = args[2];
2307 if (const_args[2]) {
2308 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2309 tgen_andi(s, TCG_TYPE_I64, a0, ~a2);
2310 } else {
2311 tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2);
2312 }
2313 break;
2314 case INDEX_op_orc_i64:
2315 a0 = args[0], a1 = args[1], a2 = args[2];
2316 if (const_args[2]) {
2317 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2318 tgen_ori(s, a0, ~a2);
2319 } else {
2320 tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2);
2321 }
2322 break;
2323 case INDEX_op_eqv_i64:
2324 a0 = args[0], a1 = args[1], a2 = args[2];
2325 if (const_args[2]) {
2326 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2327 tgen_xori(s, a0, ~a2);
2328 } else {
2329 tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2);
2330 }
2331 break;
2332 case INDEX_op_nand_i64:
2333 tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]);
2334 break;
2335 case INDEX_op_nor_i64:
2336 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[2]);
2337 break;
2338
48bb3750
RH		 2339 case INDEX_op_neg_i64:
2340 tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
2341 break;
6c9b5c0f
RH		 2342 case INDEX_op_not_i64:
2343 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[1]);
2344 break;
48bb3750
RH		 2345 case INDEX_op_bswap64_i64:
2346 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
2347 break;
2348
2349 case INDEX_op_mul_i64:
92c89a07 2350 a0 = args[0], a1 = args[1], a2 = args[2];
48bb3750 2351 if (const_args[2]) {
92c89a07
RH		 2352 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2353 if (a2 == (int16_t)a2) {
2354 tcg_out_insn(s, RI, MGHI, a0, a2);
48bb3750 2355 } else {
92c89a07 2356 tcg_out_insn(s, RIL, MSGFI, a0, a2);
48bb3750 2357 }
92c89a07
RH		 2358 } else if (a0 == a1) {
2359 tcg_out_insn(s, RRE, MSGR, a0, a2);
48bb3750 2360 } else {
92c89a07 2361 tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2);
48bb3750
RH		 2362 }
2363 break;
2364
2365 case INDEX_op_div2_i64:
4143f78d
RH		 2366 /*
2367 * ??? We get an unnecessary sign-extension of the dividend
2368 * into op0 with this definition, but as we do in fact always
2369 * produce both quotient and remainder using INDEX_op_div_i64
2370 * instead requires jumping through even more hoops.
2371 */
2372 tcg_debug_assert(args[0] == args[2]);
2373 tcg_debug_assert(args[1] == args[3]);
2374 tcg_debug_assert((args[1] & 1) == 0);
2375 tcg_debug_assert(args[0] == args[1] + 1);
2376 tcg_out_insn(s, RRE, DSGR, args[1], args[4]);
48bb3750
RH		 2377 break;
2378 case INDEX_op_divu2_i64:
4143f78d
RH		 2379 tcg_debug_assert(args[0] == args[2]);
2380 tcg_debug_assert(args[1] == args[3]);
2381 tcg_debug_assert((args[1] & 1) == 0);
2382 tcg_debug_assert(args[0] == args[1] + 1);
2383 tcg_out_insn(s, RRE, DLGR, args[1], args[4]);
48bb3750 2384 break;
36017dc6 2385 case INDEX_op_mulu2_i64:
4143f78d
RH		 2386 tcg_debug_assert(args[0] == args[2]);
2387 tcg_debug_assert((args[1] & 1) == 0);
2388 tcg_debug_assert(args[0] == args[1] + 1);
2389 tcg_out_insn(s, RRE, MLGR, args[1], args[3]);
36017dc6 2390 break;
668ce343
RH		 2391 case INDEX_op_muls2_i64:
2392 tcg_debug_assert((args[1] & 1) == 0);
2393 tcg_debug_assert(args[0] == args[1] + 1);
2394 tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]);
2395 break;
48bb3750
RH		 2396
2397 case INDEX_op_shl_i64:
2398 op = RSY_SLLG;
2399 do_shift64:
2400 if (const_args[2]) {
2401 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]);
2402 } else {
2403 tcg_out_sh64(s, op, args[0], args[1], args[2], 0);
2404 }
2405 break;
2406 case INDEX_op_shr_i64:
2407 op = RSY_SRLG;
2408 goto do_shift64;
2409 case INDEX_op_sar_i64:
2410 op = RSY_SRAG;
2411 goto do_shift64;
2412
2413 case INDEX_op_rotl_i64:
2414 if (const_args[2]) {
2415 tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
2416 TCG_REG_NONE, args[2]);
2417 } else {
2418 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0);
2419 }
2420 break;
2421 case INDEX_op_rotr_i64:
2422 if (const_args[2]) {
2423 tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
2424 TCG_REG_NONE, (64 - args[2]) & 63);
2425 } else {
2426 /* We can use the smaller 32-bit negate because only the
2427 low 6 bits are examined for the rotate. */
2428 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
2429 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0);
2430 }
2431 break;
2432
3790b918 2433 case INDEX_op_add2_i64:
ad19b358
RH		 2434 if (const_args[4]) {
2435 if ((int64_t)args[4] >= 0) {
2436 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]);
2437 } else {
2438 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]);
2439 }
2440 } else {
2441 tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
2442 }
3790b918
RH		 2443 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
2444 break;
2445 case INDEX_op_sub2_i64:
ad19b358
RH		 2446 if (const_args[4]) {
2447 if ((int64_t)args[4] >= 0) {
2448 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]);
2449 } else {
2450 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]);
2451 }
2452 } else {
2453 tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
2454 }
3790b918
RH		 2455 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
2456 break;
2457
48bb3750
RH		 2458 case INDEX_op_brcond_i64:
2459 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0],
bec16311 2460 args[1], const_args[1], arg_label(args[3]));
48bb3750
RH		 2461 break;
2462 case INDEX_op_setcond_i64:
2463 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1],
2464 args[2], const_args[2]);
2465 break;
96a9f093
RH		 2466 case INDEX_op_movcond_i64:
2467 tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1],
23d1394a 2468 args[2], const_args[2], args[3], const_args[3], args[4]);
96a9f093 2469 break;
48bb3750 2470
d5690ea4 2471 OP_32_64(deposit):
752b1be9
RH		 2472 a0 = args[0], a1 = args[1], a2 = args[2];
2473 if (const_args[1]) {
2474 tgen_deposit(s, a0, a2, args[3], args[4], 1);
2475 } else {
2476 /* Since we can't support "0Z" as a constraint, we allow a1 in
2477 any register. Fix things up as if a matching constraint. */
2478 if (a0 != a1) {
2479 TCGType type = (opc == INDEX_op_deposit_i64);
2480 if (a0 == a2) {
2481 tcg_out_mov(s, type, TCG_TMP0, a2);
2482 a2 = TCG_TMP0;
2483 }
2484 tcg_out_mov(s, type, a0, a1);
2485 }
2486 tgen_deposit(s, a0, a2, args[3], args[4], 0);
2487 }
d5690ea4 2488 break;
752b1be9 2489
b0bf5fe8
RH		 2490 OP_32_64(extract):
2491 tgen_extract(s, args[0], args[1], args[2], args[3]);
2492 break;
d5690ea4 2493
ce411066
RH		 2494 case INDEX_op_clz_i64:
2495 tgen_clz(s, args[0], args[1], args[2], const_args[2]);
2496 break;
2497
29a5ea73
RH		 2498 case INDEX_op_ctpop_i32:
2499 tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]);
2500 break;
2501 case INDEX_op_ctpop_i64:
2502 tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]);
2503 break;
2504
c9314d61
PK		 2505 case INDEX_op_mb:
2506 /* The host memory model is quite strong, we simply need to
2507 serialize the instruction stream. */
2508 if (args[0] & TCG_MO_ST_LD) {
e62d5752
RH		 2509 /* fast-bcr-serialization facility (45) is present */
2510 tcg_out_insn(s, RR, BCR, 14, 0);
c9314d61
PK		 2511 }
2512 break;
2513
96d0ee7f
RH		 2514 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2515 case INDEX_op_mov_i64:
96d0ee7f 2516 case INDEX_op_call: /* Always emitted via tcg_out_call. */
b55a8d9d 2517 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
cf7d6b8e 2518 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
678155b2
RH		 2519 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
2520 case INDEX_op_ext8s_i64:
d0e66c89
RH		 2521 case INDEX_op_ext8u_i32:
2522 case INDEX_op_ext8u_i64:
753e42ea
RH		 2523 case INDEX_op_ext16s_i32:
2524 case INDEX_op_ext16s_i64:
379afdff
RH		 2525 case INDEX_op_ext16u_i32:
2526 case INDEX_op_ext16u_i64:
52bf3398 2527 case INDEX_op_ext32s_i64:
9ecf5f61 2528 case INDEX_op_ext32u_i64:
9c6aa274 2529 case INDEX_op_ext_i32_i64:
b9bfe000 2530 case INDEX_op_extu_i32_i64:
b8b94ac6 2531 case INDEX_op_extrl_i64_i32:
48bb3750 2532 default:
732e89f4 2533 g_assert_not_reached();
48bb3750 2534 }
2827822e
AG		 2535}
2536
34ef7676
RH		 2537static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
2538 TCGReg dst, TCGReg src)
2539{
79cada86
RH		 2540 if (is_general_reg(src)) {
2541 /* Replicate general register into two MO_64. */
2542 tcg_out_insn(s, VRRf, VLVGP, dst, src, src);
2543 if (vece == MO_64) {
2544 return true;
2545 }
6e591a85 2546 src = dst;
79cada86
RH		 2547 }
2548
2549 /*
2550 * Recall that the "standard" integer, within a vector, is the
2551 * rightmost element of the leftmost doubleword, a-la VLLEZ.
2552 */
2553 tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece);
2554 return true;
34ef7676
RH		 2555}
2556
2557static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
2558 TCGReg dst, TCGReg base, intptr_t offset)
2559{
79cada86
RH		 2560 tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece);
2561 return true;
34ef7676
RH		 2562}
2563
2564static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
2565 TCGReg dst, int64_t val)
2566{
79cada86
RH		 2567 int i, mask, msb, lsb;
2568
2569 /* Look for int16_t elements. */
2570 if (vece <= MO_16 ||
2571 (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) {
2572 tcg_out_insn(s, VRIa, VREPI, dst, val, vece);
2573 return;
2574 }
2575
2576 /* Look for bit masks. */
2577 if (vece == MO_32) {
2578 if (risbg_mask((int32_t)val)) {
2579 /* Handle wraparound by swapping msb and lsb. */
2580 if ((val & 0x80000001u) == 0x80000001u) {
2581 msb = 32 - ctz32(~val);
2582 lsb = clz32(~val) - 1;
2583 } else {
2584 msb = clz32(val);
2585 lsb = 31 - ctz32(val);
2586 }
a66669c9 2587 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32);
79cada86
RH		 2588 return;
2589 }
2590 } else {
2591 if (risbg_mask(val)) {
2592 /* Handle wraparound by swapping msb and lsb. */
2593 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
2594 /* Handle wraparound by swapping msb and lsb. */
2595 msb = 64 - ctz64(~val);
2596 lsb = clz64(~val) - 1;
2597 } else {
2598 msb = clz64(val);
2599 lsb = 63 - ctz64(val);
2600 }
a66669c9 2601 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64);
79cada86
RH		 2602 return;
2603 }
2604 }
2605
2606 /* Look for all bytes 0x00 or 0xff. */
2607 for (i = mask = 0; i < 8; i++) {
2608 uint8_t byte = val >> (i * 8);
2609 if (byte == 0xff) {
2610 mask |= 1 << i;
2611 } else if (byte != 0) {
2612 break;
2613 }
2614 }
2615 if (i == 8) {
2616 tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0);
2617 return;
2618 }
2619
2620 /* Otherwise, stuff it in the constant pool. */
2621 tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0);
2622 new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2);
2623 tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64);
34ef7676
RH		 2624}
2625
2626static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
2627 unsigned vecl, unsigned vece,
d58f0173
MR		 2628 const TCGArg args[TCG_MAX_OP_ARGS],
2629 const int const_args[TCG_MAX_OP_ARGS])
34ef7676 2630{
a429ee29
RH		 2631 TCGType type = vecl + TCG_TYPE_V64;
2632 TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
2633
2634 switch (opc) {
2635 case INDEX_op_ld_vec:
2636 tcg_out_ld(s, type, a0, a1, a2);
2637 break;
2638 case INDEX_op_st_vec:
2639 tcg_out_st(s, type, a0, a1, a2);
2640 break;
2641 case INDEX_op_dupm_vec:
2642 tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
2643 break;
2644
ae77bbe5
RH		 2645 case INDEX_op_abs_vec:
2646 tcg_out_insn(s, VRRa, VLP, a0, a1, vece);
2647 break;
2648 case INDEX_op_neg_vec:
2649 tcg_out_insn(s, VRRa, VLC, a0, a1, vece);
2650 break;
2651 case INDEX_op_not_vec:
2652 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0);
2653 break;
2654
a429ee29
RH		 2655 case INDEX_op_add_vec:
2656 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece);
2657 break;
2658 case INDEX_op_sub_vec:
2659 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece);
2660 break;
2661 case INDEX_op_and_vec:
2662 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0);
2663 break;
ae77bbe5
RH		 2664 case INDEX_op_andc_vec:
2665 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0);
2666 break;
479b61cb
RH		 2667 case INDEX_op_mul_vec:
2668 tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece);
2669 break;
a429ee29
RH		 2670 case INDEX_op_or_vec:
2671 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0);
2672 break;
ae77bbe5
RH		 2673 case INDEX_op_orc_vec:
2674 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0);
2675 break;
a429ee29
RH		 2676 case INDEX_op_xor_vec:
2677 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
2678 break;
21eab5bf
RH		 2679 case INDEX_op_nand_vec:
2680 tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0);
2681 break;
2682 case INDEX_op_nor_vec:
2683 tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0);
2684 break;
2685 case INDEX_op_eqv_vec:
2686 tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0);
2687 break;
a429ee29 2688
22cb37b4
RH		 2689 case INDEX_op_shli_vec:
2690 tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece);
2691 break;
2692 case INDEX_op_shri_vec:
2693 tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece);
2694 break;
2695 case INDEX_op_sari_vec:
2696 tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece);
2697 break;
2698 case INDEX_op_rotli_vec:
2699 tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece);
2700 break;
2701 case INDEX_op_shls_vec:
2702 tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece);
2703 break;
2704 case INDEX_op_shrs_vec:
2705 tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece);
2706 break;
2707 case INDEX_op_sars_vec:
2708 tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece);
2709 break;
2710 case INDEX_op_rotls_vec:
2711 tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece);
2712 break;
2713 case INDEX_op_shlv_vec:
2714 tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece);
2715 break;
2716 case INDEX_op_shrv_vec:
2717 tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece);
2718 break;
2719 case INDEX_op_sarv_vec:
2720 tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece);
2721 break;
2722 case INDEX_op_rotlv_vec:
2723 tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece);
2724 break;
2725
220db7a6
RH		 2726 case INDEX_op_smin_vec:
2727 tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece);
2728 break;
2729 case INDEX_op_smax_vec:
2730 tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece);
2731 break;
2732 case INDEX_op_umin_vec:
2733 tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece);
2734 break;
2735 case INDEX_op_umax_vec:
2736 tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece);
2737 break;
2738
9bca986d 2739 case INDEX_op_bitsel_vec:
6e5f9fb7 2740 tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1);
9bca986d
RH		 2741 break;
2742
a429ee29
RH		 2743 case INDEX_op_cmp_vec:
2744 switch ((TCGCond)args[3]) {
2745 case TCG_COND_EQ:
2746 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece);
2747 break;
2748 case TCG_COND_GT:
2749 tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece);
2750 break;
2751 case TCG_COND_GTU:
2752 tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece);
2753 break;
2754 default:
2755 g_assert_not_reached();
2756 }
2757 break;
2758
4223c9c1
RH		 2759 case INDEX_op_s390_vuph_vec:
2760 tcg_out_insn(s, VRRa, VUPH, a0, a1, vece);
2761 break;
2762 case INDEX_op_s390_vupl_vec:
2763 tcg_out_insn(s, VRRa, VUPL, a0, a1, vece);
2764 break;
2765 case INDEX_op_s390_vpks_vec:
2766 tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece);
2767 break;
2768
a429ee29
RH		 2769 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
2770 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
2771 default:
2772 g_assert_not_reached();
2773 }
34ef7676
RH		 2774}
2775
2776int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
2777{
a429ee29 2778 switch (opc) {
ae77bbe5 2779 case INDEX_op_abs_vec:
a429ee29
RH		 2780 case INDEX_op_add_vec:
2781 case INDEX_op_and_vec:
ae77bbe5 2782 case INDEX_op_andc_vec:
9bca986d 2783 case INDEX_op_bitsel_vec:
21eab5bf
RH		 2784 case INDEX_op_eqv_vec:
2785 case INDEX_op_nand_vec:
ae77bbe5 2786 case INDEX_op_neg_vec:
21eab5bf 2787 case INDEX_op_nor_vec:
ae77bbe5 2788 case INDEX_op_not_vec:
a429ee29 2789 case INDEX_op_or_vec:
ae77bbe5 2790 case INDEX_op_orc_vec:
22cb37b4
RH		 2791 case INDEX_op_rotli_vec:
2792 case INDEX_op_rotls_vec:
2793 case INDEX_op_rotlv_vec:
2794 case INDEX_op_sari_vec:
2795 case INDEX_op_sars_vec:
2796 case INDEX_op_sarv_vec:
2797 case INDEX_op_shli_vec:
2798 case INDEX_op_shls_vec:
2799 case INDEX_op_shlv_vec:
2800 case INDEX_op_shri_vec:
2801 case INDEX_op_shrs_vec:
2802 case INDEX_op_shrv_vec:
220db7a6
RH		 2803 case INDEX_op_smax_vec:
2804 case INDEX_op_smin_vec:
a429ee29 2805 case INDEX_op_sub_vec:
220db7a6
RH		 2806 case INDEX_op_umax_vec:
2807 case INDEX_op_umin_vec:
a429ee29
RH		 2808 case INDEX_op_xor_vec:
2809 return 1;
2810 case INDEX_op_cmp_vec:
ea3f2af8 2811 case INDEX_op_cmpsel_vec:
22cb37b4 2812 case INDEX_op_rotrv_vec:
a429ee29 2813 return -1;
479b61cb
RH		 2814 case INDEX_op_mul_vec:
2815 return vece < MO_64;
4223c9c1
RH		 2816 case INDEX_op_ssadd_vec:
2817 case INDEX_op_sssub_vec:
2818 return vece < MO_64 ? -1 : 0;
a429ee29
RH		 2819 default:
2820 return 0;
2821 }
2822}
2823
2824static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
2825 TCGv_vec v1, TCGv_vec v2, TCGCond cond)
2826{
2827 bool need_swap = false, need_inv = false;
2828
2829 switch (cond) {
2830 case TCG_COND_EQ:
2831 case TCG_COND_GT:
2832 case TCG_COND_GTU:
2833 break;
2834 case TCG_COND_NE:
2835 case TCG_COND_LE:
2836 case TCG_COND_LEU:
2837 need_inv = true;
2838 break;
2839 case TCG_COND_LT:
2840 case TCG_COND_LTU:
2841 need_swap = true;
2842 break;
2843 case TCG_COND_GE:
2844 case TCG_COND_GEU:
2845 need_swap = need_inv = true;
2846 break;
2847 default:
2848 g_assert_not_reached();
2849 }
2850
2851 if (need_inv) {
2852 cond = tcg_invert_cond(cond);
2853 }
2854 if (need_swap) {
2855 TCGv_vec t1;
2856 t1 = v1, v1 = v2, v2 = t1;
2857 cond = tcg_swap_cond(cond);
2858 }
2859
2860 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
2861 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
2862
2863 return need_inv;
2864}
2865
2866static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
2867 TCGv_vec v1, TCGv_vec v2, TCGCond cond)
2868{
2869 if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) {
2870 tcg_gen_not_vec(vece, v0, v0);
2871 }
34ef7676
RH		 2872}
2873
ea3f2af8
RH		 2874static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0,
2875 TCGv_vec c1, TCGv_vec c2,
2876 TCGv_vec v3, TCGv_vec v4, TCGCond cond)
2877{
2878 TCGv_vec t = tcg_temp_new_vec(type);
2879
2880 if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) {
2881 /* Invert the sense of the compare by swapping arguments. */
2882 tcg_gen_bitsel_vec(vece, v0, t, v4, v3);
2883 } else {
2884 tcg_gen_bitsel_vec(vece, v0, t, v3, v4);
2885 }
2886 tcg_temp_free_vec(t);
2887}
2888
4223c9c1
RH		 2889static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0,
2890 TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc)
2891{
2892 TCGv_vec h1 = tcg_temp_new_vec(type);
2893 TCGv_vec h2 = tcg_temp_new_vec(type);
2894 TCGv_vec l1 = tcg_temp_new_vec(type);
2895 TCGv_vec l2 = tcg_temp_new_vec(type);
2896
2897 tcg_debug_assert (vece < MO_64);
2898
2899 /* Unpack with sign-extension. */
2900 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece,
2901 tcgv_vec_arg(h1), tcgv_vec_arg(v1));
2902 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece,
2903 tcgv_vec_arg(h2), tcgv_vec_arg(v2));
2904
2905 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece,
2906 tcgv_vec_arg(l1), tcgv_vec_arg(v1));
2907 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece,
2908 tcgv_vec_arg(l2), tcgv_vec_arg(v2));
2909
2910 /* Arithmetic on a wider element size. */
2911 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1),
2912 tcgv_vec_arg(h1), tcgv_vec_arg(h2));
2913 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1),
2914 tcgv_vec_arg(l1), tcgv_vec_arg(l2));
2915
2916 /* Pack with saturation. */
2917 vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1,
2918 tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1));
2919
2920 tcg_temp_free_vec(h1);
2921 tcg_temp_free_vec(h2);
2922 tcg_temp_free_vec(l1);
2923 tcg_temp_free_vec(l2);
2924}
2925
34ef7676
RH		 2926void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
2927 TCGArg a0, ...)
2928{
a429ee29 2929 va_list va;
ea3f2af8 2930 TCGv_vec v0, v1, v2, v3, v4, t0;
a429ee29
RH		 2931
2932 va_start(va, a0);
2933 v0 = temp_tcgv_vec(arg_temp(a0));
2934 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
2935 v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
2936
2937 switch (opc) {
2938 case INDEX_op_cmp_vec:
2939 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
2940 break;
2941
ea3f2af8
RH		 2942 case INDEX_op_cmpsel_vec:
2943 v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
2944 v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
2945 expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg));
2946 break;
2947
22cb37b4
RH		 2948 case INDEX_op_rotrv_vec:
2949 t0 = tcg_temp_new_vec(type);
2950 tcg_gen_neg_vec(vece, t0, v2);
2951 tcg_gen_rotlv_vec(vece, v0, v1, t0);
2952 tcg_temp_free_vec(t0);
2953 break;
2954
4223c9c1
RH		 2955 case INDEX_op_ssadd_vec:
2956 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec);
2957 break;
2958 case INDEX_op_sssub_vec:
2959 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec);
2960 break;
2961
a429ee29
RH		 2962 default:
2963 g_assert_not_reached();
2964 }
2965 va_end(va);
34ef7676
RH		 2966}
2967
d1c36a90 2968static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
f69d277e 2969{
9b5500b6
RH		 2970 switch (op) {
2971 case INDEX_op_goto_ptr:
d1c36a90 2972 return C_O0_I1(r);
9b5500b6
RH		 2973
2974 case INDEX_op_ld8u_i32:
2975 case INDEX_op_ld8u_i64:
2976 case INDEX_op_ld8s_i32:
2977 case INDEX_op_ld8s_i64:
2978 case INDEX_op_ld16u_i32:
2979 case INDEX_op_ld16u_i64:
2980 case INDEX_op_ld16s_i32:
2981 case INDEX_op_ld16s_i64:
2982 case INDEX_op_ld_i32:
2983 case INDEX_op_ld32u_i64:
2984 case INDEX_op_ld32s_i64:
2985 case INDEX_op_ld_i64:
d1c36a90
RH		 2986 return C_O1_I1(r, r);
2987
9b5500b6
RH		 2988 case INDEX_op_st8_i32:
2989 case INDEX_op_st8_i64:
2990 case INDEX_op_st16_i32:
2991 case INDEX_op_st16_i64:
2992 case INDEX_op_st_i32:
2993 case INDEX_op_st32_i64:
2994 case INDEX_op_st_i64:
d1c36a90 2995 return C_O0_I2(r, r);
9b5500b6
RH		 2996
2997 case INDEX_op_add_i32:
2998 case INDEX_op_add_i64:
d1c36a90
RH		 2999 case INDEX_op_shl_i64:
3000 case INDEX_op_shr_i64:
3001 case INDEX_op_sar_i64:
3002 case INDEX_op_rotl_i32:
3003 case INDEX_op_rotl_i64:
3004 case INDEX_op_rotr_i32:
3005 case INDEX_op_rotr_i64:
d1c36a90 3006 case INDEX_op_setcond_i32:
d1c36a90 3007 return C_O1_I2(r, r, ri);
32c256ed
RH		 3008 case INDEX_op_setcond_i64:
3009 return C_O1_I2(r, r, rA);
d1c36a90 3010
bfff8518
RH		 3011 case INDEX_op_clz_i64:
3012 return C_O1_I2(r, r, rI);
3013
9b5500b6
RH		 3014 case INDEX_op_sub_i32:
3015 case INDEX_op_sub_i64:
bdcd5d19 3016 case INDEX_op_and_i32:
4046d9ca 3017 case INDEX_op_or_i32:
5bf67a92 3018 case INDEX_op_xor_i32:
238da1c9 3019 return C_O1_I2(r, r, ri);
4134083f
RH		 3020 case INDEX_op_and_i64:
3021 return C_O1_I2(r, r, rNKR);
b2509acc
RH		 3022 case INDEX_op_or_i64:
3023 case INDEX_op_xor_i64:
3024 return C_O1_I2(r, r, rK);
a8f0269e 3025
6c9b5c0f
RH		 3026 case INDEX_op_andc_i32:
3027 case INDEX_op_orc_i32:
3028 case INDEX_op_eqv_i32:
3029 return C_O1_I2(r, r, ri);
3030 case INDEX_op_andc_i64:
3031 return C_O1_I2(r, r, rKR);
3032 case INDEX_op_orc_i64:
3033 case INDEX_op_eqv_i64:
3034 return C_O1_I2(r, r, rNK);
3035
3036 case INDEX_op_nand_i32:
3037 case INDEX_op_nand_i64:
3038 case INDEX_op_nor_i32:
3039 case INDEX_op_nor_i64:
3040 return C_O1_I2(r, r, r);
3041
9b5500b6 3042 case INDEX_op_mul_i32:
92c89a07
RH		 3043 return (HAVE_FACILITY(MISC_INSN_EXT2)
3044 ? C_O1_I2(r, r, ri)
3045 : C_O1_I2(r, 0, ri));
9b5500b6 3046 case INDEX_op_mul_i64:
92c89a07
RH		 3047 return (HAVE_FACILITY(MISC_INSN_EXT2)
3048 ? C_O1_I2(r, r, rJ)
3049 : C_O1_I2(r, 0, rJ));
a8f0269e 3050
9b5500b6
RH		 3051 case INDEX_op_shl_i32:
3052 case INDEX_op_shr_i32:
3053 case INDEX_op_sar_i32:
238da1c9 3054 return C_O1_I2(r, r, ri);
9b5500b6
RH		 3055
3056 case INDEX_op_brcond_i32:
d1c36a90 3057 return C_O0_I2(r, ri);
32c256ed
RH		 3058 case INDEX_op_brcond_i64:
3059 return C_O0_I2(r, rA);
9b5500b6
RH		 3060
3061 case INDEX_op_bswap16_i32:
3062 case INDEX_op_bswap16_i64:
3063 case INDEX_op_bswap32_i32:
3064 case INDEX_op_bswap32_i64:
3065 case INDEX_op_bswap64_i64:
3066 case INDEX_op_neg_i32:
3067 case INDEX_op_neg_i64:
6c9b5c0f
RH		 3068 case INDEX_op_not_i32:
3069 case INDEX_op_not_i64:
9b5500b6
RH		 3070 case INDEX_op_ext8s_i32:
3071 case INDEX_op_ext8s_i64:
3072 case INDEX_op_ext8u_i32:
3073 case INDEX_op_ext8u_i64:
3074 case INDEX_op_ext16s_i32:
3075 case INDEX_op_ext16s_i64:
3076 case INDEX_op_ext16u_i32:
3077 case INDEX_op_ext16u_i64:
3078 case INDEX_op_ext32s_i64:
3079 case INDEX_op_ext32u_i64:
3080 case INDEX_op_ext_i32_i64:
3081 case INDEX_op_extu_i32_i64:
3082 case INDEX_op_extract_i32:
3083 case INDEX_op_extract_i64:
29a5ea73
RH		 3084 case INDEX_op_ctpop_i32:
3085 case INDEX_op_ctpop_i64:
d1c36a90 3086 return C_O1_I1(r, r);
9b5500b6
RH		 3087
3088 case INDEX_op_qemu_ld_i32:
3089 case INDEX_op_qemu_ld_i64:
94901422 3090 return C_O1_I1(r, r);
9b5500b6
RH		 3091 case INDEX_op_qemu_st_i64:
3092 case INDEX_op_qemu_st_i32:
94901422 3093 return C_O0_I2(r, r);
f69d277e 3094
9b5500b6
RH		 3095 case INDEX_op_deposit_i32:
3096 case INDEX_op_deposit_i64:
d1c36a90
RH		 3097 return C_O1_I2(r, rZ, r);
3098
9b5500b6 3099 case INDEX_op_movcond_i32:
23d1394a 3100 return C_O1_I4(r, r, ri, rI, r);
32c256ed
RH		 3101 case INDEX_op_movcond_i64:
3102 return C_O1_I4(r, r, rA, rI, r);
d1c36a90 3103
9b5500b6
RH		 3104 case INDEX_op_div2_i32:
3105 case INDEX_op_div2_i64:
3106 case INDEX_op_divu2_i32:
3107 case INDEX_op_divu2_i64:
4143f78d 3108 return C_O2_I3(o, m, 0, 1, r);
d1c36a90 3109
9b5500b6 3110 case INDEX_op_mulu2_i64:
4143f78d 3111 return C_O2_I2(o, m, 0, r);
668ce343
RH		 3112 case INDEX_op_muls2_i64:
3113 return C_O2_I2(o, m, r, r);
ba18b07d 3114
9b5500b6 3115 case INDEX_op_add2_i32:
9b5500b6 3116 case INDEX_op_sub2_i32:
3e25f7da 3117 return C_O2_I4(r, r, 0, 1, ri, r);
d1c36a90 3118
ba18b07d 3119 case INDEX_op_add2_i64:
9b5500b6 3120 case INDEX_op_sub2_i64:
3e25f7da 3121 return C_O2_I4(r, r, 0, 1, rA, r);
9b5500b6 3122
34ef7676
RH		 3123 case INDEX_op_st_vec:
3124 return C_O0_I2(v, r);
3125 case INDEX_op_ld_vec:
3126 case INDEX_op_dupm_vec:
3127 return C_O1_I1(v, r);
3128 case INDEX_op_dup_vec:
3129 return C_O1_I1(v, vr);
ae77bbe5
RH		 3130 case INDEX_op_abs_vec:
3131 case INDEX_op_neg_vec:
3132 case INDEX_op_not_vec:
22cb37b4
RH		 3133 case INDEX_op_rotli_vec:
3134 case INDEX_op_sari_vec:
3135 case INDEX_op_shli_vec:
3136 case INDEX_op_shri_vec:
4223c9c1
RH		 3137 case INDEX_op_s390_vuph_vec:
3138 case INDEX_op_s390_vupl_vec:
ae77bbe5 3139 return C_O1_I1(v, v);
34ef7676
RH		 3140 case INDEX_op_add_vec:
3141 case INDEX_op_sub_vec:
3142 case INDEX_op_and_vec:
ae77bbe5 3143 case INDEX_op_andc_vec:
34ef7676 3144 case INDEX_op_or_vec:
ae77bbe5 3145 case INDEX_op_orc_vec:
34ef7676 3146 case INDEX_op_xor_vec:
21eab5bf
RH		 3147 case INDEX_op_nand_vec:
3148 case INDEX_op_nor_vec:
3149 case INDEX_op_eqv_vec:
34ef7676 3150 case INDEX_op_cmp_vec:
479b61cb 3151 case INDEX_op_mul_vec:
22cb37b4
RH		 3152 case INDEX_op_rotlv_vec:
3153 case INDEX_op_rotrv_vec:
3154 case INDEX_op_shlv_vec:
3155 case INDEX_op_shrv_vec:
3156 case INDEX_op_sarv_vec:
220db7a6
RH		 3157 case INDEX_op_smax_vec:
3158 case INDEX_op_smin_vec:
3159 case INDEX_op_umax_vec:
3160 case INDEX_op_umin_vec:
4223c9c1 3161 case INDEX_op_s390_vpks_vec:
34ef7676 3162 return C_O1_I2(v, v, v);
22cb37b4
RH		 3163 case INDEX_op_rotls_vec:
3164 case INDEX_op_shls_vec:
3165 case INDEX_op_shrs_vec:
3166 case INDEX_op_sars_vec:
3167 return C_O1_I2(v, v, r);
9bca986d
RH		 3168 case INDEX_op_bitsel_vec:
3169 return C_O1_I3(v, v, v, v);
34ef7676 3170
9b5500b6 3171 default:
d1c36a90 3172 g_assert_not_reached();
f69d277e 3173 }
f69d277e
RH		 3174}
3175
34ef7676
RH		 3176/*
3177 * Mainline glibc added HWCAP_S390_VX before it was kernel abi.
3178 * Some distros have fixed this up locally, others have not.
3179 */
3180#ifndef HWCAP_S390_VXRS
3181#define HWCAP_S390_VXRS 2048
3182#endif
3183
b2c98d9d 3184static void query_s390_facilities(void)
48bb3750 3185{
c9baa30f 3186 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
761ea522 3187 const char *which;
48bb3750 3188
c9baa30f
RH		 3189 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this
3190 is present on all 64-bit systems, but let's check for it anyway. */
3191 if (hwcap & HWCAP_S390_STFLE) {
748b7f3e
RH		 3192 register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1;
3193 register void *r1 __asm__("1") = s390_facilities;
48bb3750 3194
c9baa30f 3195 /* stfle 0(%r1) */
c9baa30f 3196 asm volatile(".word 0xb2b0,0x1000"
748b7f3e 3197 : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc");
48bb3750 3198 }
34ef7676
RH		 3199
3200 /*
3201 * Use of vector registers requires os support beyond the facility bit.
3202 * If the kernel does not advertise support, disable the facility bits.
3203 * There is nothing else we currently care about in the 3rd word, so
3204 * disable VECTOR with one store.
3205 */
a429ee29 3206 if (!(hwcap & HWCAP_S390_VXRS)) {
34ef7676
RH		 3207 s390_facilities[2] = 0;
3208 }
761ea522
RH		 3209
3210 /*
c68d5b7a 3211 * Minimum supported cpu revision is z196.
761ea522
RH		 3212 * Check for all required facilities.
3213 * ZARCH_ACTIVE is done via preprocessor check for 64-bit.
3214 */
3215 if (!HAVE_FACILITY(LONG_DISP)) {
3216 which = "long-displacement";
3217 goto fail;
3218 }
3e25f7da
RH		 3219 if (!HAVE_FACILITY(EXT_IMM)) {
3220 which = "extended-immediate";
3221 goto fail;
3222 }
9c3bfb79
RH		 3223 if (!HAVE_FACILITY(GEN_INST_EXT)) {
3224 which = "general-instructions-extension";
3225 goto fail;
3226 }
c68d5b7a
RH		 3227 /*
3228 * Facility 45 is a big bin that contains: distinct-operands,
3229 * fast-BCR-serialization, high-word, population-count,
3230 * interlocked-access-1, and load/store-on-condition-1
3231 */
3232 if (!HAVE_FACILITY(45)) {
3233 which = "45";
3234 goto fail;
3235 }
761ea522
RH		 3236 return;
3237
3238 fail:
3239 error_report("%s: missing required facility %s", __func__, which);
3240 exit(EXIT_FAILURE);
48bb3750
RH		 3241}
3242
3243static void tcg_target_init(TCGContext *s)
2827822e 3244{
b2c98d9d 3245 query_s390_facilities();
48bb3750 3246
f46934df
RH		 3247 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
3248 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
34ef7676
RH		 3249 if (HAVE_FACILITY(VECTOR)) {
3250 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3251 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
3252 }
48bb3750 3253
ccb1bb66 3254 tcg_target_call_clobber_regs = 0;
48bb3750
RH		 3255 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
3256 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
3257 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
3258 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
3259 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
3260 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
f24efee4
RH		 3261 /* The r6 register is technically call-saved, but it's also a parameter
3262 register, so it can get killed by setup for the qemu_st helper. */
3263 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
48bb3750
RH		 3264 /* The return register can be considered call-clobbered. */
3265 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
3266
34ef7676
RH		 3267 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
3268 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
3269 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
3270 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
3271 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
3272 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
3273 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
3274 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
3275 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
3276 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
3277 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
3278 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
3279 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20);
3280 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21);
3281 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22);
3282 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23);
3283 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24);
3284 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
3285 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26);
3286 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27);
3287 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28);
3288 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29);
3289 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30);
3290 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31);
3291
ccb1bb66 3292 s->reserved_regs = 0;
48bb3750
RH		 3293 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
3294 /* XXX many insns can't be used with R0, so we better avoid it for now */
3295 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
3296 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
2827822e
AG		 3297}
3298
f167dc37
RH		 3299#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \
3300 + TCG_STATIC_CALL_ARGS_SIZE \
3301 + CPU_TEMP_BUF_NLONGS * sizeof(long)))
3302
48bb3750 3303static void tcg_target_qemu_prologue(TCGContext *s)
2827822e 3304{
48bb3750
RH		 3305 /* stmg %r6,%r15,48(%r15) (save registers) */
3306 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48);
3307
a4924e8b 3308 /* aghi %r15,-frame_size */
f167dc37 3309 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE);
a4924e8b
RH		 3310
3311 tcg_set_frame(s, TCG_REG_CALL_STACK,
3312 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
3313 CPU_TEMP_BUF_NLONGS * sizeof(long));
48bb3750 3314
090d0bfd 3315#ifndef CONFIG_SOFTMMU
b76f21a7 3316 if (guest_base >= 0x80000) {
ccbecb44 3317 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
48bb3750
RH		 3318 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
3319 }
090d0bfd 3320#endif
48bb3750 3321
cea5f9a2 3322 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
829e1376 3323
cea5f9a2
BS		 3324 /* br %r3 (go to TB) */
3325 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);
48bb3750 3326
46644483
RH		 3327 /*
3328 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
3329 * and fall through to the rest of the epilogue.
3330 */
c8bc1168 3331 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
46644483
RH		 3332 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0);
3333
3334 /* TB epilogue */
79dae4dd 3335 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
48bb3750 3336
a4924e8b
RH		 3337 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */
3338 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
f167dc37 3339 FRAME_SIZE + 48);
48bb3750
RH		 3340
3341 /* br %r14 (return) */
3342 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);
2827822e 3343}
f167dc37 3344
28eef8aa
RH		 3345static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
3346{
3347 memset(p, 0x07, count * sizeof(tcg_insn_unit));
3348}
3349
f167dc37 3350typedef struct {
d2e16f2c 3351 DebugFrameHeader h;
f167dc37
RH		 3352 uint8_t fde_def_cfa[4];
3353 uint8_t fde_reg_ofs[18];
3354} DebugFrame;
3355
3356/* We're expecting a 2 byte uleb128 encoded value. */
3357QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
3358
3359#define ELF_HOST_MACHINE EM_S390
3360
d2e16f2c
RH		 3361static const DebugFrame debug_frame = {
3362 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
3363 .h.cie.id = -1,
3364 .h.cie.version = 1,
3365 .h.cie.code_align = 1,
3366 .h.cie.data_align = 8, /* sleb128 8 */
3367 .h.cie.return_column = TCG_REG_R14,
f167dc37
RH		 3368
3369 /* Total FDE size does not include the "len" member. */
d2e16f2c 3370 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
f167dc37
RH		 3371
3372 .fde_def_cfa = {
3373 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */
3374 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
3375 (FRAME_SIZE >> 7)
3376 },
3377 .fde_reg_ofs = {
3378 0x86, 6, /* DW_CFA_offset, %r6, 48 */
3379 0x87, 7, /* DW_CFA_offset, %r7, 56 */
3380 0x88, 8, /* DW_CFA_offset, %r8, 64 */
3381 0x89, 9, /* DW_CFA_offset, %r92, 72 */
3382 0x8a, 10, /* DW_CFA_offset, %r10, 80 */
3383 0x8b, 11, /* DW_CFA_offset, %r11, 88 */
3384 0x8c, 12, /* DW_CFA_offset, %r12, 96 */
3385 0x8d, 13, /* DW_CFA_offset, %r13, 104 */
3386 0x8e, 14, /* DW_CFA_offset, %r14, 112 */
3387 }
3388};
3389
755bf9e5 3390void tcg_register_jit(const void *buf, size_t buf_size)
f167dc37 3391{
f167dc37
RH		 3392 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
3393}
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