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8289b279
BS		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
26 "%g0",
27 "%g1",
28 "%g2",
29 "%g3",
30 "%g4",
31 "%g5",
32 "%g6",
33 "%g7",
34 "%o0",
35 "%o1",
36 "%o2",
37 "%o3",
38 "%o4",
39 "%o5",
40 "%o6",
41 "%o7",
42 "%l0",
43 "%l1",
44 "%l2",
45 "%l3",
46 "%l4",
47 "%l5",
48 "%l6",
49 "%l7",
50 "%i0",
51 "%i1",
52 "%i2",
53 "%i3",
54 "%i4",
55 "%i5",
56 "%i6",
57 "%i7",
58};
59
0954d0d9 60static const int tcg_target_reg_alloc_order[] = {
8289b279
BS		 61 TCG_REG_L0,
62 TCG_REG_L1,
63 TCG_REG_L2,
64 TCG_REG_L3,
65 TCG_REG_L4,
66 TCG_REG_L5,
67 TCG_REG_L6,
68 TCG_REG_L7,
69 TCG_REG_I0,
70 TCG_REG_I1,
71 TCG_REG_I2,
72 TCG_REG_I3,
73 TCG_REG_I4,
8289b279
BS		 74};
75
76static const int tcg_target_call_iarg_regs[6] = {
77 TCG_REG_O0,
78 TCG_REG_O1,
79 TCG_REG_O2,
80 TCG_REG_O3,
81 TCG_REG_O4,
82 TCG_REG_O5,
83};
84
85static const int tcg_target_call_oarg_regs[2] = {
86 TCG_REG_O0,
87 TCG_REG_O1,
88};
89
57e49b40 90static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
f5ef6aac 91{
57e49b40
BS		 92 return (val << ((sizeof(tcg_target_long) * 8 - bits))
93 >> (sizeof(tcg_target_long) * 8 - bits)) == val;
94}
95
96static inline int check_fit_i32(uint32_t val, unsigned int bits)
97{
98 return ((val << (32 - bits)) >> (32 - bits)) == val;
f5ef6aac
BS		 99}
100
8289b279 101static void patch_reloc(uint8_t *code_ptr, int type,
f54b3f92 102 tcg_target_long value, tcg_target_long addend)
8289b279 103{
f54b3f92 104 value += addend;
8289b279
BS		 105 switch (type) {
106 case R_SPARC_32:
107 if (value != (uint32_t)value)
108 tcg_abort();
109 *(uint32_t *)code_ptr = value;
110 break;
f5ef6aac
BS		 111 case R_SPARC_WDISP22:
112 value -= (long)code_ptr;
113 value >>= 2;
57e49b40 114 if (!check_fit_tl(value, 22))
f5ef6aac
BS		 115 tcg_abort();
116 *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
117 break;
8289b279
BS		 118 default:
119 tcg_abort();
120 }
121}
122
123/* maximum number of register used for input function arguments */
124static inline int tcg_target_get_call_iarg_regs_count(int flags)
125{
126 return 6;
127}
128
129/* parse target specific constraints */
130static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
131{
132 const char *ct_str;
133
134 ct_str = *pct_str;
135 switch (ct_str[0]) {
136 case 'r':
137 case 'L': /* qemu_ld/st constraint */
138 ct->ct |= TCG_CT_REG;
139 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
53c37487
BS		 140 // Helper args
141 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
142 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
143 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
8289b279
BS		 144 break;
145 case 'I':
146 ct->ct |= TCG_CT_CONST_S11;
147 break;
148 case 'J':
149 ct->ct |= TCG_CT_CONST_S13;
150 break;
151 default:
152 return -1;
153 }
154 ct_str++;
155 *pct_str = ct_str;
156 return 0;
157}
158
8289b279
BS		 159/* test if a constant matches the constraint */
160static inline int tcg_target_const_match(tcg_target_long val,
161 const TCGArgConstraint *arg_ct)
162{
163 int ct;
164
165 ct = arg_ct->ct;
166 if (ct & TCG_CT_CONST)
167 return 1;
57e49b40 168 else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
8289b279 169 return 1;
57e49b40 170 else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
8289b279
BS		 171 return 1;
172 else
173 return 0;
174}
175
176#define INSN_OP(x) ((x) << 30)
177#define INSN_OP2(x) ((x) << 22)
178#define INSN_OP3(x) ((x) << 19)
179#define INSN_OPF(x) ((x) << 5)
180#define INSN_RD(x) ((x) << 25)
181#define INSN_RS1(x) ((x) << 14)
182#define INSN_RS2(x) (x)
8384dd67 183#define INSN_ASI(x) ((x) << 5)
8289b279
BS		 184
185#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
b3db8758 186#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
8289b279 187
b3db8758 188#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
cf7c2ca5
BS		 189#define COND_N 0x0
190#define COND_E 0x1
191#define COND_LE 0x2
192#define COND_L 0x3
193#define COND_LEU 0x4
194#define COND_CS 0x5
195#define COND_NEG 0x6
196#define COND_VS 0x7
b3db8758 197#define COND_A 0x8
cf7c2ca5
BS		 198#define COND_NE 0x9
199#define COND_G 0xa
200#define COND_GE 0xb
201#define COND_GU 0xc
202#define COND_CC 0xd
203#define COND_POS 0xe
204#define COND_VC 0xf
b3db8758 205#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
8289b279
BS		 206
207#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
208#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
209#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
9a7f3228 210#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
8289b279 211#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
f5ef6aac
BS		 212#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
213#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
8289b279
BS		 214#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
215#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
216#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
217#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
218#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
219#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
220#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
221#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
222
223#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
224#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
225#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
226
227#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
228#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
229#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
230
231#define WRY (INSN_OP(2) | INSN_OP3(0x30))
232#define JMPL (INSN_OP(2) | INSN_OP3(0x38))
233#define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
234#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
235#define SETHI (INSN_OP(0) | INSN_OP2(0x4))
236#define CALL INSN_OP(1)
237#define LDUB (INSN_OP(3) | INSN_OP3(0x01))
238#define LDSB (INSN_OP(3) | INSN_OP3(0x09))
239#define LDUH (INSN_OP(3) | INSN_OP3(0x02))
240#define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
241#define LDUW (INSN_OP(3) | INSN_OP3(0x00))
242#define LDSW (INSN_OP(3) | INSN_OP3(0x08))
243#define LDX (INSN_OP(3) | INSN_OP3(0x0b))
244#define STB (INSN_OP(3) | INSN_OP3(0x05))
245#define STH (INSN_OP(3) | INSN_OP3(0x06))
246#define STW (INSN_OP(3) | INSN_OP3(0x04))
247#define STX (INSN_OP(3) | INSN_OP3(0x0e))
8384dd67
BS		 248#define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
249#define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
250#define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
251#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
252#define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
253#define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
254#define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
255#define STBA (INSN_OP(3) | INSN_OP3(0x15))
256#define STHA (INSN_OP(3) | INSN_OP3(0x16))
257#define STWA (INSN_OP(3) | INSN_OP3(0x14))
258#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
259
260#ifndef ASI_PRIMARY_LITTLE
261#define ASI_PRIMARY_LITTLE 0x88
262#endif
8289b279 263
26cc915c
BS		 264static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
265 int op)
266{
267 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
268 INSN_RS2(rs2));
269}
270
6f41b777
BS		 271static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1,
272 uint32_t offset, int op)
26cc915c
BS		 273{
274 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
275 INSN_IMM13(offset));
276}
277
8289b279
BS		 278static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
279{
26cc915c
BS		 280 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
281}
282
283static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
284{
285 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
8289b279
BS		 286}
287
b101234a
BS		 288static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
289{
290 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
291}
292
293static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
8289b279 294{
6f41b777 295 if (check_fit_tl(arg, 12))
b101234a 296 tcg_out_movi_imm13(s, ret, arg);
8289b279 297 else {
26cc915c 298 tcg_out_sethi(s, ret, arg);
8289b279 299 if (arg & 0x3ff)
b101234a 300 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
8289b279
BS		 301 }
302}
303
b101234a
BS		 304static inline void tcg_out_movi(TCGContext *s, TCGType type,
305 int ret, tcg_target_long arg)
306{
307#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
308 if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) {
d795eb86
BS		 309 tcg_out_movi_imm32(s, TCG_REG_I4, arg >> 32);
310 tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
b101234a 311 tcg_out_movi_imm32(s, ret, arg);
d795eb86 312 tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
6f41b777
BS		 313 } else if (check_fit_tl(arg, 12))
314 tcg_out_movi_imm13(s, ret, arg);
315 else {
316 tcg_out_sethi(s, ret, arg);
317 if (arg & 0x3ff)
318 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
319 }
320#else
321 tcg_out_movi_imm32(s, ret, arg);
b101234a 322#endif
b101234a
BS		 323}
324
8289b279
BS		 325static inline void tcg_out_ld_raw(TCGContext *s, int ret,
326 tcg_target_long arg)
327{
26cc915c 328 tcg_out_sethi(s, ret, arg);
8289b279
BS		 329 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
330 INSN_IMM13(arg & 0x3ff));
331}
332
b3db8758
BS		 333static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
334 tcg_target_long arg)
335{
b101234a
BS		 336 if (!check_fit_tl(arg, 10))
337 tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
b3db8758 338#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
b3db8758
BS		 339 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
340 INSN_IMM13(arg & 0x3ff));
341#else
b101234a
BS		 342 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
343 INSN_IMM13(arg & 0x3ff));
b3db8758
BS		 344#endif
345}
346
8289b279
BS		 347static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
348{
57e49b40 349 if (check_fit_tl(offset, 13))
8289b279
BS		 350 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
351 INSN_IMM13(offset));
cf7c2ca5
BS		 352 else {
353 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
354 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
355 INSN_RS2(addr));
356 }
8289b279
BS		 357}
358
8384dd67
BS		 359static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
360 int offset, int op, int asi)
361{
362 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
363 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
364 INSN_ASI(asi) | INSN_RS2(addr));
365}
366
e4d5434c 367static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
8289b279
BS		 368 int arg1, tcg_target_long arg2)
369{
7d551702
BS		 370 if (type == TCG_TYPE_I32)
371 tcg_out_ldst(s, ret, arg1, arg2, LDUW);
372 else
373 tcg_out_ldst(s, ret, arg1, arg2, LDX);
8289b279
BS		 374}
375
e4d5434c 376static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
8289b279
BS		 377 int arg1, tcg_target_long arg2)
378{
7d551702
BS		 379 if (type == TCG_TYPE_I32)
380 tcg_out_ldst(s, arg, arg1, arg2, STW);
381 else
382 tcg_out_ldst(s, arg, arg1, arg2, STX);
8289b279
BS		 383}
384
8289b279
BS		 385static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
386{
387 if (val == 0 || val == -1)
388 tcg_out32(s, WRY | INSN_IMM13(val));
389 else
390 fprintf(stderr, "unimplemented sety %ld\n", (long)val);
391}
392
393static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
394{
395 if (val != 0) {
57e49b40 396 if (check_fit_tl(val, 13))
8289b279 397 tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
f5ef6aac
BS		 398 else {
399 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
400 tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
401 }
8289b279
BS		 402 }
403}
404
53c37487
BS		 405static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
406{
407 if (val != 0) {
408 if (check_fit_tl(val, 13))
409 tcg_out_arithi(s, reg, reg, val, ARITH_AND);
410 else {
411 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
412 tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
413 }
414 }
415}
416
8289b279
BS		 417static inline void tcg_out_nop(TCGContext *s)
418{
26cc915c 419 tcg_out_sethi(s, TCG_REG_G0, 0);
8289b279
BS		 420}
421
cf7c2ca5
BS		 422static void tcg_out_branch(TCGContext *s, int opc, int label_index)
423{
424 int32_t val;
425 TCGLabel *l = &s->labels[label_index];
426
427 if (l->has_value) {
428 val = l->u.value - (tcg_target_long)s->code_ptr;
f5ef6aac 429 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
cf7c2ca5 430 | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
f5ef6aac
BS		 431 } else {
432 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
433 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
434 }
cf7c2ca5
BS		 435}
436
437static const uint8_t tcg_cond_to_bcond[10] = {
438 [TCG_COND_EQ] = COND_E,
439 [TCG_COND_NE] = COND_NE,
440 [TCG_COND_LT] = COND_L,
441 [TCG_COND_GE] = COND_GE,
442 [TCG_COND_LE] = COND_LE,
443 [TCG_COND_GT] = COND_G,
444 [TCG_COND_LTU] = COND_CS,
445 [TCG_COND_GEU] = COND_CC,
446 [TCG_COND_LEU] = COND_LEU,
447 [TCG_COND_GTU] = COND_GU,
448};
449
450static void tcg_out_brcond(TCGContext *s, int cond,
451 TCGArg arg1, TCGArg arg2, int const_arg2,
452 int label_index)
453{
454 if (const_arg2 && arg2 == 0)
26cc915c 455 /* orcc %g0, r, %g0 */
9a7f3228 456 tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC);
cf7c2ca5
BS		 457 else
458 /* subcc r1, r2, %g0 */
459 tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC);
460 tcg_out_branch(s, tcg_cond_to_bcond[cond], label_index);
461 tcg_out_nop(s);
462}
463
7d551702
BS		 464/* Generate global QEMU prologue and epilogue code */
465void tcg_target_qemu_prologue(TCGContext *s)
b3db8758
BS		 466{
467 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
468 INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
cf7c2ca5 469 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
7d551702
BS		 470 INSN_RS2(TCG_REG_G0));
471 tcg_out_nop(s);
b3db8758
BS		 472}
473
f5ef6aac 474#if defined(CONFIG_SOFTMMU)
f5ef6aac 475
79383c9c 476#include "../../softmmu_defs.h"
f5ef6aac 477
9a7f3228 478static const void * const qemu_ld_helpers[4] = {
f5ef6aac
BS		 479 __ldb_mmu,
480 __ldw_mmu,
481 __ldl_mmu,
482 __ldq_mmu,
483};
484
9a7f3228 485static const void * const qemu_st_helpers[4] = {
f5ef6aac
BS		 486 __stb_mmu,
487 __stw_mmu,
488 __stl_mmu,
489 __stq_mmu,
490};
491#endif
492
bffe1431
BS		 493#if TARGET_LONG_BITS == 32
494#define TARGET_LD_OP LDUW
495#else
496#define TARGET_LD_OP LDX
497#endif
498
9d0efc88
BS		 499#if TARGET_PHYS_ADDR_BITS == 32
500#define TARGET_ADDEND_LD_OP LDUW
501#else
502#define TARGET_ADDEND_LD_OP LDX
503#endif
504
bffe1431
BS		 505#ifdef __arch64__
506#define HOST_LD_OP LDX
507#define HOST_ST_OP STX
508#define HOST_SLL_OP SHIFT_SLLX
509#define HOST_SRA_OP SHIFT_SRAX
510#else
511#define HOST_LD_OP LDUW
512#define HOST_ST_OP STW
513#define HOST_SLL_OP SHIFT_SLL
514#define HOST_SRA_OP SHIFT_SRA
515#endif
516
f5ef6aac
BS		 517static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
518 int opc)
519{
56fc64df 520 int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
f5ef6aac 521#if defined(CONFIG_SOFTMMU)
53c37487 522 uint32_t *label1_ptr, *label2_ptr;
f5ef6aac
BS		 523#endif
524
525 data_reg = *args++;
526 addr_reg = *args++;
527 mem_index = *args;
528 s_bits = opc & 3;
529
53c37487
BS		 530 arg0 = TCG_REG_O0;
531 arg1 = TCG_REG_O1;
56fc64df 532 arg2 = TCG_REG_O2;
f5ef6aac 533
f5ef6aac 534#if defined(CONFIG_SOFTMMU)
56fc64df
BS		 535 /* srl addr_reg, x, arg1 */
536 tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
f5ef6aac 537 SHIFT_SRL);
56fc64df
BS		 538 /* and addr_reg, x, arg0 */
539 tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
f5ef6aac
BS		 540 ARITH_AND);
541
56fc64df
BS		 542 /* and arg1, x, arg1 */
543 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
f5ef6aac 544
56fc64df
BS		 545 /* add arg1, x, arg1 */
546 tcg_out_addi(s, arg1, offsetof(CPUState,
547 tlb_table[mem_index][0].addr_read));
53c37487 548
56fc64df
BS		 549 /* add env, arg1, arg1 */
550 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
f5ef6aac 551
56fc64df 552 /* ld [arg1], arg2 */
bffe1431 553 tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
56fc64df 554 INSN_RS2(TCG_REG_G0));
f5ef6aac 555
56fc64df
BS		 556 /* subcc arg0, arg2, %g0 */
557 tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
f5ef6aac
BS		 558
559 /* will become:
560 be label1 */
53c37487 561 label1_ptr = (uint32_t *)s->code_ptr;
f5ef6aac
BS		 562 tcg_out32(s, 0);
563
53c37487
BS		 564 /* mov (delay slot) */
565 tcg_out_mov(s, arg0, addr_reg);
f5ef6aac 566
bffe1431
BS		 567 /* mov */
568 tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
569
f5ef6aac 570 /* XXX: move that code at the end of the TB */
53c37487 571 /* qemu_ld_helper[s_bits](arg0, arg1) */
f5ef6aac
BS		 572 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
573 - (tcg_target_ulong)s->code_ptr) >> 2)
574 & 0x3fffffff));
bffe1431
BS		 575 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
576 global registers */
577 // delay slot
578 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
579 TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_ST_OP);
580 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
581 TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_LD_OP);
f5ef6aac 582
53c37487 583 /* data_reg = sign_extend(arg0) */
f5ef6aac
BS		 584 switch(opc) {
585 case 0 | 4:
53c37487 586 /* sll arg0, 24/56, data_reg */
56fc64df 587 tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
bffe1431 588 HOST_SLL_OP);
53c37487 589 /* sra data_reg, 24/56, data_reg */
56fc64df 590 tcg_out_arithi(s, data_reg, data_reg,
bffe1431 591 (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
f5ef6aac
BS		 592 break;
593 case 1 | 4:
53c37487 594 /* sll arg0, 16/48, data_reg */
56fc64df 595 tcg_out_arithi(s, data_reg, arg0,
bffe1431 596 (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
53c37487 597 /* sra data_reg, 16/48, data_reg */
56fc64df 598 tcg_out_arithi(s, data_reg, data_reg,
bffe1431 599 (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
f5ef6aac
BS		 600 break;
601 case 2 | 4:
53c37487 602 /* sll arg0, 32, data_reg */
bffe1431 603 tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
53c37487 604 /* sra data_reg, 32, data_reg */
bffe1431 605 tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
f5ef6aac
BS		 606 break;
607 case 0:
608 case 1:
609 case 2:
610 case 3:
611 default:
612 /* mov */
53c37487 613 tcg_out_mov(s, data_reg, arg0);
f5ef6aac
BS		 614 break;
615 }
616
617 /* will become:
618 ba label2 */
53c37487 619 label2_ptr = (uint32_t *)s->code_ptr;
f5ef6aac
BS		 620 tcg_out32(s, 0);
621
53c37487
BS		 622 /* nop (delay slot */
623 tcg_out_nop(s);
624
f5ef6aac 625 /* label1: */
53c37487
BS		 626 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
627 INSN_OFF22((unsigned long)s->code_ptr -
628 (unsigned long)label1_ptr));
f5ef6aac 629
56fc64df
BS		 630 /* ld [arg1 + x], arg1 */
631 tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
9d0efc88 632 offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
90cbed46
BS		 633
634#if TARGET_LONG_BITS == 32
635 /* and addr_reg, x, arg0 */
636 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
637 tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
638 /* add arg0, arg1, arg0 */
639 tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
640#else
56fc64df
BS		 641 /* add addr_reg, arg1, arg0 */
642 tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
90cbed46
BS		 643#endif
644
f5ef6aac 645#else
56fc64df 646 arg0 = addr_reg;
f5ef6aac
BS		 647#endif
648
f5ef6aac
BS		 649 switch(opc) {
650 case 0:
56fc64df
BS		 651 /* ldub [arg0], data_reg */
652 tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
f5ef6aac
BS		 653 break;
654 case 0 | 4:
56fc64df
BS		 655 /* ldsb [arg0], data_reg */
656 tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
f5ef6aac
BS		 657 break;
658 case 1:
8384dd67 659#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 660 /* lduh [arg0], data_reg */
661 tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
8384dd67 662#else
56fc64df
BS		 663 /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
664 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
8384dd67 665#endif
f5ef6aac
BS		 666 break;
667 case 1 | 4:
8384dd67 668#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 669 /* ldsh [arg0], data_reg */
670 tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
8384dd67 671#else
56fc64df
BS		 672 /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
673 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
8384dd67 674#endif
f5ef6aac
BS		 675 break;
676 case 2:
8384dd67 677#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 678 /* lduw [arg0], data_reg */
679 tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
8384dd67 680#else
56fc64df
BS		 681 /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
682 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
8384dd67 683#endif
f5ef6aac
BS		 684 break;
685 case 2 | 4:
8384dd67 686#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 687 /* ldsw [arg0], data_reg */
688 tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
8384dd67 689#else
56fc64df
BS		 690 /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
691 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
8384dd67 692#endif
f5ef6aac
BS		 693 break;
694 case 3:
8384dd67 695#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 696 /* ldx [arg0], data_reg */
697 tcg_out_ldst(s, data_reg, arg0, 0, LDX);
8384dd67 698#else
56fc64df
BS		 699 /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
700 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
8384dd67 701#endif
f5ef6aac
BS		 702 break;
703 default:
704 tcg_abort();
705 }
706
707#if defined(CONFIG_SOFTMMU)
708 /* label2: */
9a7f3228 709 *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
53c37487
BS		 710 INSN_OFF22((unsigned long)s->code_ptr -
711 (unsigned long)label2_ptr));
f5ef6aac
BS		 712#endif
713}
714
715static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
716 int opc)
717{
56fc64df 718 int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
f5ef6aac 719#if defined(CONFIG_SOFTMMU)
53c37487 720 uint32_t *label1_ptr, *label2_ptr;
f5ef6aac
BS		 721#endif
722
723 data_reg = *args++;
724 addr_reg = *args++;
725 mem_index = *args;
726
727 s_bits = opc;
728
53c37487
BS		 729 arg0 = TCG_REG_O0;
730 arg1 = TCG_REG_O1;
731 arg2 = TCG_REG_O2;
f5ef6aac 732
f5ef6aac 733#if defined(CONFIG_SOFTMMU)
56fc64df
BS		 734 /* srl addr_reg, x, arg1 */
735 tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
f5ef6aac 736 SHIFT_SRL);
53c37487 737
56fc64df
BS		 738 /* and addr_reg, x, arg0 */
739 tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
f5ef6aac
BS		 740 ARITH_AND);
741
56fc64df
BS		 742 /* and arg1, x, arg1 */
743 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
f5ef6aac 744
56fc64df
BS		 745 /* add arg1, x, arg1 */
746 tcg_out_addi(s, arg1, offsetof(CPUState,
747 tlb_table[mem_index][0].addr_write));
f5ef6aac 748
56fc64df
BS		 749 /* add env, arg1, arg1 */
750 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
f5ef6aac 751
56fc64df 752 /* ld [arg1], arg2 */
bffe1431 753 tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
56fc64df 754 INSN_RS2(TCG_REG_G0));
53c37487 755
56fc64df
BS		 756 /* subcc arg0, arg2, %g0 */
757 tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
f5ef6aac
BS		 758
759 /* will become:
760 be label1 */
53c37487 761 label1_ptr = (uint32_t *)s->code_ptr;
f5ef6aac 762 tcg_out32(s, 0);
f5ef6aac 763
53c37487
BS		 764 /* mov (delay slot) */
765 tcg_out_mov(s, arg0, addr_reg);
766
53c37487 767 /* mov */
56fc64df 768 tcg_out_mov(s, arg1, data_reg);
53c37487 769
bffe1431
BS		 770 /* mov */
771 tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
772
53c37487
BS		 773 /* XXX: move that code at the end of the TB */
774 /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
f5ef6aac
BS		 775 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
776 - (tcg_target_ulong)s->code_ptr) >> 2)
777 & 0x3fffffff));
bffe1431
BS		 778 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
779 global registers */
780 // delay slot
781 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
782 TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_ST_OP);
783 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
784 TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_LD_OP);
f5ef6aac
BS		 785
786 /* will become:
787 ba label2 */
53c37487 788 label2_ptr = (uint32_t *)s->code_ptr;
f5ef6aac
BS		 789 tcg_out32(s, 0);
790
53c37487
BS		 791 /* nop (delay slot) */
792 tcg_out_nop(s);
793
f5ef6aac 794 /* label1: */
53c37487
BS		 795 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
796 INSN_OFF22((unsigned long)s->code_ptr -
797 (unsigned long)label1_ptr));
f5ef6aac 798
56fc64df
BS		 799 /* ld [arg1 + x], arg1 */
800 tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
9d0efc88 801 offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
53c37487 802
90cbed46
BS		 803#if TARGET_LONG_BITS == 32
804 /* and addr_reg, x, arg0 */
805 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
806 tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
807 /* add arg0, arg1, arg0 */
808 tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
809#else
56fc64df
BS		 810 /* add addr_reg, arg1, arg0 */
811 tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
90cbed46
BS		 812#endif
813
f5ef6aac 814#else
56fc64df 815 arg0 = addr_reg;
f5ef6aac
BS		 816#endif
817
f5ef6aac
BS		 818 switch(opc) {
819 case 0:
56fc64df
BS		 820 /* stb data_reg, [arg0] */
821 tcg_out_ldst(s, data_reg, arg0, 0, STB);
f5ef6aac
BS		 822 break;
823 case 1:
8384dd67 824#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 825 /* sth data_reg, [arg0] */
826 tcg_out_ldst(s, data_reg, arg0, 0, STH);
8384dd67 827#else
56fc64df
BS		 828 /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
829 tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
8384dd67 830#endif
f5ef6aac
BS		 831 break;
832 case 2:
8384dd67 833#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 834 /* stw data_reg, [arg0] */
835 tcg_out_ldst(s, data_reg, arg0, 0, STW);
8384dd67 836#else
56fc64df
BS		 837 /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
838 tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
8384dd67 839#endif
f5ef6aac
BS		 840 break;
841 case 3:
8384dd67 842#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 843 /* stx data_reg, [arg0] */
844 tcg_out_ldst(s, data_reg, arg0, 0, STX);
8384dd67 845#else
56fc64df
BS		 846 /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
847 tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
8384dd67 848#endif
f5ef6aac
BS		 849 break;
850 default:
851 tcg_abort();
852 }
853
854#if defined(CONFIG_SOFTMMU)
855 /* label2: */
9a7f3228 856 *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
53c37487
BS		 857 INSN_OFF22((unsigned long)s->code_ptr -
858 (unsigned long)label2_ptr));
f5ef6aac
BS		 859#endif
860}
861
8289b279
BS		 862static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
863 const int *const_args)
864{
865 int c;
866
867 switch (opc) {
868 case INDEX_op_exit_tb:
b3db8758
BS		 869 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
870 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
8289b279 871 INSN_IMM13(8));
b3db8758
BS		 872 tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
873 INSN_RS2(TCG_REG_G0));
8289b279
BS		 874 break;
875 case INDEX_op_goto_tb:
876 if (s->tb_jmp_offset) {
877 /* direct jump method */
26cc915c 878 tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
cf7c2ca5
BS		 879 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
880 INSN_IMM13((args[0] & 0x1fff)));
8289b279 881 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
8289b279
BS		 882 } else {
883 /* indirect jump method */
b3db8758
BS		 884 tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
885 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
886 INSN_RS2(TCG_REG_G0));
8289b279 887 }
53cd9273 888 tcg_out_nop(s);
8289b279
BS		 889 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
890 break;
891 case INDEX_op_call:
bffe1431
BS		 892 if (const_args[0])
893 tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
894 - (tcg_target_ulong)s->code_ptr) >> 2)
895 & 0x3fffffff));
896 else {
897 tcg_out_ld_ptr(s, TCG_REG_I5,
898 (tcg_target_long)(s->tb_next + args[0]));
899 tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
900 INSN_RS2(TCG_REG_G0));
8289b279 901 }
bffe1431
BS		 902 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
903 global registers */
904 // delay slot
905 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
906 TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_ST_OP);
907 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
908 TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_LD_OP);
8289b279
BS		 909 break;
910 case INDEX_op_jmp:
8289b279 911 case INDEX_op_br:
f5ef6aac
BS		 912 tcg_out_branch(s, COND_A, args[0]);
913 tcg_out_nop(s);
8289b279
BS		 914 break;
915 case INDEX_op_movi_i32:
916 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
917 break;
918
919#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
920#define OP_32_64(x) \
921 glue(glue(case INDEX_op_, x), _i32:) \
922 glue(glue(case INDEX_op_, x), _i64:)
923#else
924#define OP_32_64(x) \
925 glue(glue(case INDEX_op_, x), _i32:)
926#endif
927 OP_32_64(ld8u);
928 tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
929 break;
930 OP_32_64(ld8s);
931 tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
932 break;
933 OP_32_64(ld16u);
934 tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
935 break;
936 OP_32_64(ld16s);
937 tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
938 break;
939 case INDEX_op_ld_i32:
940#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
53cd9273 941 case INDEX_op_ld32u_i64:
8289b279
BS		 942#endif
943 tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
944 break;
945 OP_32_64(st8);
946 tcg_out_ldst(s, args[0], args[1], args[2], STB);
947 break;
948 OP_32_64(st16);
949 tcg_out_ldst(s, args[0], args[1], args[2], STH);
950 break;
951 case INDEX_op_st_i32:
952#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
53cd9273 953 case INDEX_op_st32_i64:
8289b279
BS		 954#endif
955 tcg_out_ldst(s, args[0], args[1], args[2], STW);
956 break;
53cd9273
BS		 957 OP_32_64(add);
958 c = ARITH_ADD;
959 goto gen_arith32;
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BS		 960 OP_32_64(sub);
961 c = ARITH_SUB;
962 goto gen_arith32;
963 OP_32_64(and);
964 c = ARITH_AND;
965 goto gen_arith32;
966 OP_32_64(or);
967 c = ARITH_OR;
968 goto gen_arith32;
969 OP_32_64(xor);
970 c = ARITH_XOR;
971 goto gen_arith32;
972 case INDEX_op_shl_i32:
973 c = SHIFT_SLL;
974 goto gen_arith32;
975 case INDEX_op_shr_i32:
976 c = SHIFT_SRL;
977 goto gen_arith32;
978 case INDEX_op_sar_i32:
979 c = SHIFT_SRA;
980 goto gen_arith32;
981 case INDEX_op_mul_i32:
982 c = ARITH_UMUL;
983 goto gen_arith32;
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BS		 984 case INDEX_op_div2_i32:
985#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
986 c = ARITH_SDIVX;
987 goto gen_arith32;
988#else
989 tcg_out_sety(s, 0);
990 c = ARITH_SDIV;
991 goto gen_arith32;
992#endif
993 case INDEX_op_divu2_i32:
994#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
995 c = ARITH_UDIVX;
996 goto gen_arith32;
997#else
998 tcg_out_sety(s, 0);
999 c = ARITH_UDIV;
1000 goto gen_arith32;
1001#endif
1002
1003 case INDEX_op_brcond_i32:
cf7c2ca5
BS		 1004 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1005 args[3]);
8289b279
BS		 1006 break;
1007
1008 case INDEX_op_qemu_ld8u:
f5ef6aac 1009 tcg_out_qemu_ld(s, args, 0);
8289b279
BS		 1010 break;
1011 case INDEX_op_qemu_ld8s:
f5ef6aac 1012 tcg_out_qemu_ld(s, args, 0 | 4);
8289b279
BS		 1013 break;
1014 case INDEX_op_qemu_ld16u:
f5ef6aac 1015 tcg_out_qemu_ld(s, args, 1);
8289b279
BS		 1016 break;
1017 case INDEX_op_qemu_ld16s:
f5ef6aac 1018 tcg_out_qemu_ld(s, args, 1 | 4);
8289b279
BS		 1019 break;
1020 case INDEX_op_qemu_ld32u:
f5ef6aac 1021 tcg_out_qemu_ld(s, args, 2);
8289b279
BS		 1022 break;
1023 case INDEX_op_qemu_ld32s:
f5ef6aac 1024 tcg_out_qemu_ld(s, args, 2 | 4);
8289b279
BS		 1025 break;
1026 case INDEX_op_qemu_st8:
f5ef6aac 1027 tcg_out_qemu_st(s, args, 0);
8289b279
BS		 1028 break;
1029 case INDEX_op_qemu_st16:
f5ef6aac 1030 tcg_out_qemu_st(s, args, 1);
8289b279
BS		 1031 break;
1032 case INDEX_op_qemu_st32:
f5ef6aac 1033 tcg_out_qemu_st(s, args, 2);
8289b279
BS		 1034 break;
1035
1036#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1037 case INDEX_op_movi_i64:
1038 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1039 break;
53cd9273
BS		 1040 case INDEX_op_ld32s_i64:
1041 tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1042 break;
8289b279
BS		 1043 case INDEX_op_ld_i64:
1044 tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1045 break;
1046 case INDEX_op_st_i64:
1047 tcg_out_ldst(s, args[0], args[1], args[2], STX);
1048 break;
1049 case INDEX_op_shl_i64:
1050 c = SHIFT_SLLX;
1051 goto gen_arith32;
1052 case INDEX_op_shr_i64:
1053 c = SHIFT_SRLX;
1054 goto gen_arith32;
1055 case INDEX_op_sar_i64:
1056 c = SHIFT_SRAX;
1057 goto gen_arith32;
1058 case INDEX_op_mul_i64:
1059 c = ARITH_MULX;
1060 goto gen_arith32;
1061 case INDEX_op_div2_i64:
53cd9273 1062 c = ARITH_SDIVX;
8289b279
BS		 1063 goto gen_arith32;
1064 case INDEX_op_divu2_i64:
1065 c = ARITH_UDIVX;
1066 goto gen_arith32;
1067
1068 case INDEX_op_brcond_i64:
f5ef6aac
BS		 1069 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1070 args[3]);
8289b279
BS		 1071 break;
1072 case INDEX_op_qemu_ld64:
f5ef6aac 1073 tcg_out_qemu_ld(s, args, 3);
8289b279
BS		 1074 break;
1075 case INDEX_op_qemu_st64:
f5ef6aac 1076 tcg_out_qemu_st(s, args, 3);
8289b279
BS		 1077 break;
1078
1079#endif
53cd9273
BS		 1080 gen_arith32:
1081 if (const_args[2]) {
1082 tcg_out_arithi(s, args[0], args[1], args[2], c);
1083 } else {
1084 tcg_out_arith(s, args[0], args[1], args[2], c);
1085 }
1086 break;
1087
8289b279
BS		 1088 default:
1089 fprintf(stderr, "unknown opcode 0x%x\n", opc);
1090 tcg_abort();
1091 }
1092}
1093
1094static const TCGTargetOpDef sparc_op_defs[] = {
1095 { INDEX_op_exit_tb, { } },
b3db8758 1096 { INDEX_op_goto_tb, { } },
8289b279
BS		 1097 { INDEX_op_call, { "ri" } },
1098 { INDEX_op_jmp, { "ri" } },
1099 { INDEX_op_br, { } },
1100
1101 { INDEX_op_mov_i32, { "r", "r" } },
1102 { INDEX_op_movi_i32, { "r" } },
1103 { INDEX_op_ld8u_i32, { "r", "r" } },
1104 { INDEX_op_ld8s_i32, { "r", "r" } },
1105 { INDEX_op_ld16u_i32, { "r", "r" } },
1106 { INDEX_op_ld16s_i32, { "r", "r" } },
1107 { INDEX_op_ld_i32, { "r", "r" } },
1108 { INDEX_op_st8_i32, { "r", "r" } },
1109 { INDEX_op_st16_i32, { "r", "r" } },
1110 { INDEX_op_st_i32, { "r", "r" } },
1111
53cd9273
BS		 1112 { INDEX_op_add_i32, { "r", "r", "rJ" } },
1113 { INDEX_op_mul_i32, { "r", "r", "rJ" } },
8289b279
BS		 1114 { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
1115 { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
53cd9273
BS		 1116 { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1117 { INDEX_op_and_i32, { "r", "r", "rJ" } },
1118 { INDEX_op_or_i32, { "r", "r", "rJ" } },
1119 { INDEX_op_xor_i32, { "r", "r", "rJ" } },
8289b279 1120
53cd9273
BS		 1121 { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1122 { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1123 { INDEX_op_sar_i32, { "r", "r", "rJ" } },
8289b279
BS		 1124
1125 { INDEX_op_brcond_i32, { "r", "ri" } },
1126
1127 { INDEX_op_qemu_ld8u, { "r", "L" } },
1128 { INDEX_op_qemu_ld8s, { "r", "L" } },
1129 { INDEX_op_qemu_ld16u, { "r", "L" } },
1130 { INDEX_op_qemu_ld16s, { "r", "L" } },
1131 { INDEX_op_qemu_ld32u, { "r", "L" } },
1132 { INDEX_op_qemu_ld32s, { "r", "L" } },
1133
1134 { INDEX_op_qemu_st8, { "L", "L" } },
1135 { INDEX_op_qemu_st16, { "L", "L" } },
1136 { INDEX_op_qemu_st32, { "L", "L" } },
1137
1138#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1139 { INDEX_op_mov_i64, { "r", "r" } },
1140 { INDEX_op_movi_i64, { "r" } },
1141 { INDEX_op_ld8u_i64, { "r", "r" } },
1142 { INDEX_op_ld8s_i64, { "r", "r" } },
1143 { INDEX_op_ld16u_i64, { "r", "r" } },
1144 { INDEX_op_ld16s_i64, { "r", "r" } },
1145 { INDEX_op_ld32u_i64, { "r", "r" } },
1146 { INDEX_op_ld32s_i64, { "r", "r" } },
1147 { INDEX_op_ld_i64, { "r", "r" } },
1148 { INDEX_op_st8_i64, { "r", "r" } },
1149 { INDEX_op_st16_i64, { "r", "r" } },
1150 { INDEX_op_st32_i64, { "r", "r" } },
1151 { INDEX_op_st_i64, { "r", "r" } },
56fc64df
BS		 1152 { INDEX_op_qemu_ld64, { "L", "L" } },
1153 { INDEX_op_qemu_st64, { "L", "L" } },
8289b279 1154
53cd9273
BS		 1155 { INDEX_op_add_i64, { "r", "r", "rJ" } },
1156 { INDEX_op_mul_i64, { "r", "r", "rJ" } },
8289b279
BS		 1157 { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
1158 { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
53cd9273
BS		 1159 { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1160 { INDEX_op_and_i64, { "r", "r", "rJ" } },
1161 { INDEX_op_or_i64, { "r", "r", "rJ" } },
1162 { INDEX_op_xor_i64, { "r", "r", "rJ" } },
8289b279 1163
53cd9273
BS		 1164 { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1165 { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1166 { INDEX_op_sar_i64, { "r", "r", "rJ" } },
8289b279
BS		 1167
1168 { INDEX_op_brcond_i64, { "r", "ri" } },
1169#endif
1170 { -1 },
1171};
1172
1173void tcg_target_init(TCGContext *s)
1174{
1175 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1176#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1177 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1178#endif
1179 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
b3db8758
BS		 1180 (1 << TCG_REG_G1) |
1181 (1 << TCG_REG_G2) |
1182 (1 << TCG_REG_G3) |
1183 (1 << TCG_REG_G4) |
1184 (1 << TCG_REG_G5) |
1185 (1 << TCG_REG_G6) |
1186 (1 << TCG_REG_G7) |
8289b279
BS		 1187 (1 << TCG_REG_O0) |
1188 (1 << TCG_REG_O1) |
1189 (1 << TCG_REG_O2) |
1190 (1 << TCG_REG_O3) |
1191 (1 << TCG_REG_O4) |
1192 (1 << TCG_REG_O5) |
8289b279
BS		 1193 (1 << TCG_REG_O7));
1194
1195 tcg_regset_clear(s->reserved_regs);
1196 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
d795eb86
BS		 1197#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1198 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1199#endif
53cd9273 1200 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
8289b279
BS		 1201 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1202 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1203 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1204 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1205 tcg_add_target_add_op_defs(sparc_op_defs);
1206}
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