]>
Commit | Line | Data |
---|---|---|
8289b279 BS |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
cb9c377f | 24 | #ifndef TCG_TARGET_SPARC |
8289b279 BS |
25 | #define TCG_TARGET_SPARC 1 |
26 | ||
8289b279 BS |
27 | #define TCG_TARGET_WORDS_BIGENDIAN |
28 | ||
29 | #define TCG_TARGET_NB_REGS 32 | |
30 | ||
771142c2 | 31 | typedef enum { |
8289b279 BS |
32 | TCG_REG_G0 = 0, |
33 | TCG_REG_G1, | |
34 | TCG_REG_G2, | |
35 | TCG_REG_G3, | |
36 | TCG_REG_G4, | |
37 | TCG_REG_G5, | |
38 | TCG_REG_G6, | |
39 | TCG_REG_G7, | |
40 | TCG_REG_O0, | |
41 | TCG_REG_O1, | |
42 | TCG_REG_O2, | |
43 | TCG_REG_O3, | |
44 | TCG_REG_O4, | |
45 | TCG_REG_O5, | |
46 | TCG_REG_O6, | |
47 | TCG_REG_O7, | |
48 | TCG_REG_L0, | |
49 | TCG_REG_L1, | |
50 | TCG_REG_L2, | |
51 | TCG_REG_L3, | |
52 | TCG_REG_L4, | |
53 | TCG_REG_L5, | |
54 | TCG_REG_L6, | |
55 | TCG_REG_L7, | |
56 | TCG_REG_I0, | |
57 | TCG_REG_I1, | |
58 | TCG_REG_I2, | |
59 | TCG_REG_I3, | |
60 | TCG_REG_I4, | |
61 | TCG_REG_I5, | |
62 | TCG_REG_I6, | |
63 | TCG_REG_I7, | |
771142c2 | 64 | } TCGReg; |
8289b279 | 65 | |
89269f6c RH |
66 | #define TCG_CT_CONST_S11 0x100 |
67 | #define TCG_CT_CONST_S13 0x200 | |
68 | #define TCG_CT_CONST_ZERO 0x400 | |
8289b279 BS |
69 | |
70 | /* used for function call generation */ | |
4c3204cb | 71 | #define TCG_REG_CALL_STACK TCG_REG_O6 |
9b9c37c3 RH |
72 | |
73 | #if TCG_TARGET_REG_BITS == 64 | |
4c3204cb RH |
74 | #define TCG_TARGET_STACK_BIAS 2047 |
75 | #define TCG_TARGET_STACK_ALIGN 16 | |
76 | #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) | |
b3db8758 | 77 | #else |
4c3204cb RH |
78 | #define TCG_TARGET_STACK_BIAS 0 |
79 | #define TCG_TARGET_STACK_ALIGN 8 | |
80 | #define TCG_TARGET_CALL_STACK_OFFSET (64 + 4 + 6*4) | |
b3db8758 BS |
81 | #endif |
82 | ||
9b9c37c3 | 83 | #if TCG_TARGET_REG_BITS == 64 |
2bece2c8 RH |
84 | #define TCG_TARGET_EXTEND_ARGS 1 |
85 | #endif | |
86 | ||
8289b279 | 87 | /* optional instructions */ |
25c4d9cc RH |
88 | #define TCG_TARGET_HAS_div_i32 1 |
89 | #define TCG_TARGET_HAS_rot_i32 0 | |
90 | #define TCG_TARGET_HAS_ext8s_i32 0 | |
91 | #define TCG_TARGET_HAS_ext16s_i32 0 | |
92 | #define TCG_TARGET_HAS_ext8u_i32 0 | |
93 | #define TCG_TARGET_HAS_ext16u_i32 0 | |
94 | #define TCG_TARGET_HAS_bswap16_i32 0 | |
95 | #define TCG_TARGET_HAS_bswap32_i32 0 | |
96 | #define TCG_TARGET_HAS_neg_i32 1 | |
97 | #define TCG_TARGET_HAS_not_i32 1 | |
98 | #define TCG_TARGET_HAS_andc_i32 1 | |
99 | #define TCG_TARGET_HAS_orc_i32 1 | |
100 | #define TCG_TARGET_HAS_eqv_i32 0 | |
101 | #define TCG_TARGET_HAS_nand_i32 0 | |
102 | #define TCG_TARGET_HAS_nor_i32 0 | |
103 | #define TCG_TARGET_HAS_deposit_i32 0 | |
ded37f0d | 104 | #define TCG_TARGET_HAS_movcond_i32 1 |
4b5a85c1 | 105 | |
cc6dfecf | 106 | #if TCG_TARGET_REG_BITS == 64 |
25c4d9cc RH |
107 | #define TCG_TARGET_HAS_div_i64 1 |
108 | #define TCG_TARGET_HAS_rot_i64 0 | |
109 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
110 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
111 | #define TCG_TARGET_HAS_ext32s_i64 1 | |
112 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
113 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
114 | #define TCG_TARGET_HAS_ext32u_i64 1 | |
115 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
116 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
117 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
118 | #define TCG_TARGET_HAS_neg_i64 1 | |
119 | #define TCG_TARGET_HAS_not_i64 1 | |
120 | #define TCG_TARGET_HAS_andc_i64 1 | |
121 | #define TCG_TARGET_HAS_orc_i64 1 | |
122 | #define TCG_TARGET_HAS_eqv_i64 0 | |
123 | #define TCG_TARGET_HAS_nand_i64 0 | |
124 | #define TCG_TARGET_HAS_nor_i64 0 | |
125 | #define TCG_TARGET_HAS_deposit_i64 0 | |
ded37f0d | 126 | #define TCG_TARGET_HAS_movcond_i64 1 |
cc6dfecf RH |
127 | #endif |
128 | ||
0c554161 | 129 | #define TCG_AREG0 TCG_REG_I0 |
8289b279 | 130 | |
dba4f1bc SW |
131 | static inline void flush_icache_range(tcg_target_ulong start, |
132 | tcg_target_ulong stop) | |
8289b279 BS |
133 | { |
134 | unsigned long p; | |
135 | ||
136 | p = start & ~(8UL - 1UL); | |
137 | stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL); | |
138 | ||
139 | for (; p < stop; p += 8) | |
140 | __asm__ __volatile__("flush\t%0" : : "r" (p)); | |
141 | } | |
cb9c377f PB |
142 | |
143 | #endif |