[mirror_qemu.git] / tcg / sparc / tcg-target.h

/*
 * Tiny Code Generator for QEMU
 *
 * Copyright (c) 2008 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#define TCG_TARGET_SPARC 1

#define TCG_TARGET_WORDS_BIGENDIAN

#define TCG_TARGET_NB_REGS 32

enum {
    TCG_REG_G0 = 0,
    TCG_REG_G1,
    TCG_REG_G2,
    TCG_REG_G3,
    TCG_REG_G4,
    TCG_REG_G5,
    TCG_REG_G6,
    TCG_REG_G7,
    TCG_REG_O0,
    TCG_REG_O1,
    TCG_REG_O2,
    TCG_REG_O3,
    TCG_REG_O4,
    TCG_REG_O5,
    TCG_REG_O6,
    TCG_REG_O7,
    TCG_REG_L0,
    TCG_REG_L1,
    TCG_REG_L2,
    TCG_REG_L3,
    TCG_REG_L4,
    TCG_REG_L5,
    TCG_REG_L6,
    TCG_REG_L7,
    TCG_REG_I0,
    TCG_REG_I1,
    TCG_REG_I2,
    TCG_REG_I3,
    TCG_REG_I4,
    TCG_REG_I5,
    TCG_REG_I6,
    TCG_REG_I7,
};

#define TCG_CT_CONST_S11 0x100
#define TCG_CT_CONST_S13 0x200

/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_I6
#ifdef __arch64__
// Reserve space for AREG0
#define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \
                                   TCG_STATIC_CALL_ARGS_SIZE)
#define TCG_TARGET_CALL_STACK_OFFSET (2047 - 16)
#define TCG_TARGET_STACK_ALIGN 16
#else
// AREG0 + one word for alignment
#define TCG_TARGET_STACK_MINFRAME (92 + (2 + 1) * (int)sizeof(long) + \
                                   TCG_STATIC_CALL_ARGS_SIZE)
#define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME
#define TCG_TARGET_STACK_ALIGN 8
#endif

#ifdef __arch64__
#define TCG_TARGET_EXTEND_ARGS 1
#endif

/* optional instructions */
#define TCG_TARGET_HAS_div_i32		1
#define TCG_TARGET_HAS_rot_i32          0
#define TCG_TARGET_HAS_ext8s_i32        0
#define TCG_TARGET_HAS_ext16s_i32       0
#define TCG_TARGET_HAS_ext8u_i32        0
#define TCG_TARGET_HAS_ext16u_i32       0
#define TCG_TARGET_HAS_bswap16_i32      0
#define TCG_TARGET_HAS_bswap32_i32      0
#define TCG_TARGET_HAS_neg_i32          1
#define TCG_TARGET_HAS_not_i32          1
#define TCG_TARGET_HAS_andc_i32         1
#define TCG_TARGET_HAS_orc_i32          1
#define TCG_TARGET_HAS_eqv_i32          0
#define TCG_TARGET_HAS_nand_i32         0
#define TCG_TARGET_HAS_nor_i32          0
#define TCG_TARGET_HAS_deposit_i32      0

#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div_i64          1
#define TCG_TARGET_HAS_rot_i64          0
#define TCG_TARGET_HAS_ext8s_i64        0
#define TCG_TARGET_HAS_ext16s_i64       0
#define TCG_TARGET_HAS_ext32s_i64       1
#define TCG_TARGET_HAS_ext8u_i64        0
#define TCG_TARGET_HAS_ext16u_i64       0
#define TCG_TARGET_HAS_ext32u_i64       1
#define TCG_TARGET_HAS_bswap16_i64      0
#define TCG_TARGET_HAS_bswap32_i64      0
#define TCG_TARGET_HAS_bswap64_i64      0
#define TCG_TARGET_HAS_neg_i64          1
#define TCG_TARGET_HAS_not_i64          1
#define TCG_TARGET_HAS_andc_i64         1
#define TCG_TARGET_HAS_orc_i64          1
#define TCG_TARGET_HAS_eqv_i64          0
#define TCG_TARGET_HAS_nand_i64         0
#define TCG_TARGET_HAS_nor_i64          0
#define TCG_TARGET_HAS_deposit_i64      0
#endif

/* Note: must be synced with dyngen-exec.h */
#ifdef CONFIG_SOLARIS
#define TCG_AREG0 TCG_REG_G2
#elif defined(__sparc_v9__)
#define TCG_AREG0 TCG_REG_G5
#else
#define TCG_AREG0 TCG_REG_G6
#endif

static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
    unsigned long p;

    p = start & ~(8UL - 1UL);
    stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);

    for (; p < stop; p += 8)
        __asm__ __volatile__("flush\t%0" : : "r" (p));
}
Commit	Line	Data
8289b279 BS	1	/*
	2	* Tiny Code Generator for QEMU
	3	*
	4	* Copyright (c) 2008 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#define TCG_TARGET_SPARC 1
	25
8289b279 BS	26	#define TCG_TARGET_WORDS_BIGENDIAN
	27
	28	#define TCG_TARGET_NB_REGS 32
	29
	30	enum {
	31	TCG_REG_G0 = 0,
	32	TCG_REG_G1,
	33	TCG_REG_G2,
	34	TCG_REG_G3,
	35	TCG_REG_G4,
	36	TCG_REG_G5,
	37	TCG_REG_G6,
	38	TCG_REG_G7,
	39	TCG_REG_O0,
	40	TCG_REG_O1,
	41	TCG_REG_O2,
	42	TCG_REG_O3,
	43	TCG_REG_O4,
	44	TCG_REG_O5,
	45	TCG_REG_O6,
	46	TCG_REG_O7,
	47	TCG_REG_L0,
	48	TCG_REG_L1,
	49	TCG_REG_L2,
	50	TCG_REG_L3,
	51	TCG_REG_L4,
	52	TCG_REG_L5,
	53	TCG_REG_L6,
	54	TCG_REG_L7,
	55	TCG_REG_I0,
	56	TCG_REG_I1,
	57	TCG_REG_I2,
	58	TCG_REG_I3,
	59	TCG_REG_I4,
	60	TCG_REG_I5,
	61	TCG_REG_I6,
	62	TCG_REG_I7,
	63	};
	64
	65	#define TCG_CT_CONST_S11 0x100
	66	#define TCG_CT_CONST_S13 0x200
	67
	68	/* used for function call generation */
e97b640d	69	#define TCG_REG_CALL_STACK TCG_REG_I6
64e3257c	70	#ifdef __arch64__
e97b640d	71	// Reserve space for AREG0
f843e528 BS	72	#define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \
	73	TCG_STATIC_CALL_ARGS_SIZE)
	74	#define TCG_TARGET_CALL_STACK_OFFSET (2047 - 16)
77fcd093	75	#define TCG_TARGET_STACK_ALIGN 16
b3db8758	76	#else
baf8cc52	77	// AREG0 + one word for alignment
f843e528 BS	78	#define TCG_TARGET_STACK_MINFRAME (92 + (2 + 1) * (int)sizeof(long) + \
f843e528 BS	79	TCG_STATIC_CALL_ARGS_SIZE)
e97b640d	80	#define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME
77fcd093	81	#define TCG_TARGET_STACK_ALIGN 8
b3db8758 BS	82	#endif
b3db8758 BS	83
2bece2c8 RH	84	#ifdef __arch64__
	85	#define TCG_TARGET_EXTEND_ARGS 1
	86	#endif
	87
8289b279	88	/* optional instructions */
25c4d9cc RH	89	#define TCG_TARGET_HAS_div_i32 1
	90	#define TCG_TARGET_HAS_rot_i32 0
	91	#define TCG_TARGET_HAS_ext8s_i32 0
	92	#define TCG_TARGET_HAS_ext16s_i32 0
	93	#define TCG_TARGET_HAS_ext8u_i32 0
	94	#define TCG_TARGET_HAS_ext16u_i32 0
	95	#define TCG_TARGET_HAS_bswap16_i32 0
	96	#define TCG_TARGET_HAS_bswap32_i32 0
	97	#define TCG_TARGET_HAS_neg_i32 1
	98	#define TCG_TARGET_HAS_not_i32 1
	99	#define TCG_TARGET_HAS_andc_i32 1
	100	#define TCG_TARGET_HAS_orc_i32 1
	101	#define TCG_TARGET_HAS_eqv_i32 0
	102	#define TCG_TARGET_HAS_nand_i32 0
	103	#define TCG_TARGET_HAS_nor_i32 0
	104	#define TCG_TARGET_HAS_deposit_i32 0
4b5a85c1	105
cc6dfecf	106	#if TCG_TARGET_REG_BITS == 64
25c4d9cc RH	107	#define TCG_TARGET_HAS_div_i64 1
	108	#define TCG_TARGET_HAS_rot_i64 0
	109	#define TCG_TARGET_HAS_ext8s_i64 0
	110	#define TCG_TARGET_HAS_ext16s_i64 0
	111	#define TCG_TARGET_HAS_ext32s_i64 1
	112	#define TCG_TARGET_HAS_ext8u_i64 0
	113	#define TCG_TARGET_HAS_ext16u_i64 0
	114	#define TCG_TARGET_HAS_ext32u_i64 1
	115	#define TCG_TARGET_HAS_bswap16_i64 0
	116	#define TCG_TARGET_HAS_bswap32_i64 0
	117	#define TCG_TARGET_HAS_bswap64_i64 0
	118	#define TCG_TARGET_HAS_neg_i64 1
	119	#define TCG_TARGET_HAS_not_i64 1
	120	#define TCG_TARGET_HAS_andc_i64 1
	121	#define TCG_TARGET_HAS_orc_i64 1
	122	#define TCG_TARGET_HAS_eqv_i64 0
	123	#define TCG_TARGET_HAS_nand_i64 0
	124	#define TCG_TARGET_HAS_nor_i64 0
	125	#define TCG_TARGET_HAS_deposit_i64 0
cc6dfecf RH	126	#endif
cc6dfecf RH	127
a63b5829	128	/* Note: must be synced with dyngen-exec.h */
dfe5fff3	129	#ifdef CONFIG_SOLARIS
8289b279	130	#define TCG_AREG0 TCG_REG_G2
8289b279	131	#elif defined(__sparc_v9__)
e97b640d	132	#define TCG_AREG0 TCG_REG_G5
8289b279 BS	133	#else
8289b279 BS	134	#define TCG_AREG0 TCG_REG_G6
8289b279 BS	135	#endif
	136
	137	static inline void flush_icache_range(unsigned long start, unsigned long stop)
	138	{
	139	unsigned long p;
	140
	141	p = start & ~(8UL - 1UL);
	142	stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
	143
	144	for (; p < stop; p += 8)
	145	__asm__ __volatile__("flush\t%0" : : "r" (p));
	146	}