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8289b279 BS |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
3a5f6805 RH |
25 | /* We only support generating code for 64-bit mode. */ |
26 | #ifndef __arch64__ | |
27 | #error "unsupported code generation mode" | |
28 | #endif | |
29 | ||
29086503 | 30 | #include "../tcg-ldst.c.inc" |
139c1837 | 31 | #include "../tcg-pool.c.inc" |
e9823b4c | 32 | |
8d8fdbae | 33 | #ifdef CONFIG_DEBUG_TCG |
8289b279 BS |
34 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
35 | "%g0", | |
36 | "%g1", | |
37 | "%g2", | |
38 | "%g3", | |
39 | "%g4", | |
40 | "%g5", | |
41 | "%g6", | |
42 | "%g7", | |
43 | "%o0", | |
44 | "%o1", | |
45 | "%o2", | |
46 | "%o3", | |
47 | "%o4", | |
48 | "%o5", | |
49 | "%o6", | |
50 | "%o7", | |
51 | "%l0", | |
52 | "%l1", | |
53 | "%l2", | |
54 | "%l3", | |
55 | "%l4", | |
56 | "%l5", | |
57 | "%l6", | |
58 | "%l7", | |
59 | "%i0", | |
60 | "%i1", | |
61 | "%i2", | |
62 | "%i3", | |
63 | "%i4", | |
64 | "%i5", | |
65 | "%i6", | |
66 | "%i7", | |
67 | }; | |
d4a9eb1f | 68 | #endif |
8289b279 | 69 | |
77f268e8 RH |
70 | #define TCG_CT_CONST_S11 0x100 |
71 | #define TCG_CT_CONST_S13 0x200 | |
72 | #define TCG_CT_CONST_ZERO 0x400 | |
73 | ||
29086503 | 74 | #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) |
34b1a49c | 75 | |
33982b89 | 76 | /* Define some temporary registers. T3 is used for constant generation. */ |
375816f8 | 77 | #define TCG_REG_T1 TCG_REG_G1 |
33982b89 RH |
78 | #define TCG_REG_T2 TCG_REG_G2 |
79 | #define TCG_REG_T3 TCG_REG_O7 | |
375816f8 | 80 | |
4cbea598 | 81 | #ifndef CONFIG_SOFTMMU |
375816f8 | 82 | # define TCG_GUEST_BASE_REG TCG_REG_I5 |
c6f7e4fb | 83 | #endif |
e141ab52 | 84 | |
ab20bdc1 | 85 | #define TCG_REG_TB TCG_REG_I1 |
ab20bdc1 | 86 | |
0954d0d9 | 87 | static const int tcg_target_reg_alloc_order[] = { |
8289b279 BS |
88 | TCG_REG_L0, |
89 | TCG_REG_L1, | |
90 | TCG_REG_L2, | |
91 | TCG_REG_L3, | |
92 | TCG_REG_L4, | |
93 | TCG_REG_L5, | |
94 | TCG_REG_L6, | |
95 | TCG_REG_L7, | |
26adfb75 | 96 | |
8289b279 BS |
97 | TCG_REG_I0, |
98 | TCG_REG_I1, | |
99 | TCG_REG_I2, | |
100 | TCG_REG_I3, | |
101 | TCG_REG_I4, | |
375816f8 | 102 | TCG_REG_I5, |
26adfb75 | 103 | |
26adfb75 RH |
104 | TCG_REG_G3, |
105 | TCG_REG_G4, | |
106 | TCG_REG_G5, | |
107 | ||
108 | TCG_REG_O0, | |
109 | TCG_REG_O1, | |
110 | TCG_REG_O2, | |
111 | TCG_REG_O3, | |
112 | TCG_REG_O4, | |
113 | TCG_REG_O5, | |
8289b279 BS |
114 | }; |
115 | ||
116 | static const int tcg_target_call_iarg_regs[6] = { | |
117 | TCG_REG_O0, | |
118 | TCG_REG_O1, | |
119 | TCG_REG_O2, | |
120 | TCG_REG_O3, | |
121 | TCG_REG_O4, | |
122 | TCG_REG_O5, | |
123 | }; | |
124 | ||
5e3d0c19 RH |
125 | static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) |
126 | { | |
127 | tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); | |
128 | tcg_debug_assert(slot >= 0 && slot <= 3); | |
129 | return TCG_REG_O0 + slot; | |
130 | } | |
8289b279 | 131 | |
8289b279 BS |
132 | #define INSN_OP(x) ((x) << 30) |
133 | #define INSN_OP2(x) ((x) << 22) | |
134 | #define INSN_OP3(x) ((x) << 19) | |
135 | #define INSN_OPF(x) ((x) << 5) | |
136 | #define INSN_RD(x) ((x) << 25) | |
137 | #define INSN_RS1(x) ((x) << 14) | |
138 | #define INSN_RS2(x) (x) | |
8384dd67 | 139 | #define INSN_ASI(x) ((x) << 5) |
8289b279 | 140 | |
203342d8 | 141 | #define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) |
dbfe80e1 | 142 | #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) |
8289b279 | 143 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
ab1339b9 | 144 | #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) |
1da92db2 | 145 | #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) |
a115f3ea | 146 | #define INSN_COND(x) ((x) << 25) |
8289b279 | 147 | |
cf7c2ca5 BS |
148 | #define COND_N 0x0 |
149 | #define COND_E 0x1 | |
150 | #define COND_LE 0x2 | |
151 | #define COND_L 0x3 | |
152 | #define COND_LEU 0x4 | |
153 | #define COND_CS 0x5 | |
154 | #define COND_NEG 0x6 | |
155 | #define COND_VS 0x7 | |
b3db8758 | 156 | #define COND_A 0x8 |
cf7c2ca5 BS |
157 | #define COND_NE 0x9 |
158 | #define COND_G 0xa | |
159 | #define COND_GE 0xb | |
160 | #define COND_GU 0xc | |
161 | #define COND_CC 0xd | |
162 | #define COND_POS 0xe | |
163 | #define COND_VC 0xf | |
a115f3ea | 164 | #define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) |
8289b279 | 165 | |
ab1339b9 RH |
166 | #define RCOND_Z 1 |
167 | #define RCOND_LEZ 2 | |
168 | #define RCOND_LZ 3 | |
169 | #define RCOND_NZ 5 | |
170 | #define RCOND_GZ 6 | |
171 | #define RCOND_GEZ 7 | |
172 | ||
dbfe80e1 RH |
173 | #define MOVCC_ICC (1 << 18) |
174 | #define MOVCC_XCC (1 << 18 | 1 << 12) | |
175 | ||
a115f3ea RH |
176 | #define BPCC_ICC 0 |
177 | #define BPCC_XCC (2 << 20) | |
178 | #define BPCC_PT (1 << 19) | |
179 | #define BPCC_PN 0 | |
180 | #define BPCC_A (1 << 29) | |
181 | ||
ab1339b9 RH |
182 | #define BPR_PT BPCC_PT |
183 | ||
8289b279 | 184 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
7a3766f3 | 185 | #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) |
8289b279 | 186 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
321dbde3 | 187 | #define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11)) |
dc69960d | 188 | #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) |
8289b279 | 189 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
9a7f3228 | 190 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
be6551b1 | 191 | #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) |
8289b279 | 192 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
f5ef6aac BS |
193 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
194 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) | |
c470b663 RH |
195 | #define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) |
196 | #define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) | |
8289b279 | 197 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
f4c16661 | 198 | #define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) |
8289b279 BS |
199 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
200 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) | |
201 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) | |
202 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) | |
203 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) | |
dbfe80e1 | 204 | #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) |
203342d8 | 205 | #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) |
8289b279 | 206 | |
90379ca8 | 207 | #define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) |
de8301e5 | 208 | #define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) |
90379ca8 | 209 | |
8289b279 BS |
210 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
211 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) | |
212 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) | |
213 | ||
214 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) | |
215 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) | |
216 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) | |
217 | ||
7a3766f3 | 218 | #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) |
583d1215 | 219 | #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) |
8289b279 | 220 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
8b66eefe | 221 | #define RETURN (INSN_OP(2) | INSN_OP3(0x39)) |
8289b279 BS |
222 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
223 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) | |
224 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) | |
225 | #define CALL INSN_OP(1) | |
226 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) | |
227 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) | |
228 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) | |
229 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) | |
230 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) | |
231 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) | |
232 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) | |
233 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) | |
234 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) | |
235 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) | |
236 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) | |
8384dd67 BS |
237 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
238 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) | |
239 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) | |
240 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) | |
241 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) | |
242 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) | |
243 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) | |
244 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) | |
245 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) | |
246 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) | |
247 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) | |
248 | ||
f8f03b37 PK |
249 | #define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) |
250 | ||
ab20bdc1 RH |
251 | #define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) |
252 | ||
8384dd67 BS |
253 | #ifndef ASI_PRIMARY_LITTLE |
254 | #define ASI_PRIMARY_LITTLE 0x88 | |
255 | #endif | |
8289b279 | 256 | |
a0ce341a RH |
257 | #define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
258 | #define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
259 | #define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
260 | #define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
261 | #define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
262 | ||
263 | #define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
264 | #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
265 | #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
266 | ||
90379ca8 RH |
267 | #ifndef use_vis3_instructions |
268 | bool use_vis3_instructions; | |
269 | #endif | |
270 | ||
897fd616 | 271 | static bool check_fit_i64(int64_t val, unsigned int bits) |
a115f3ea | 272 | { |
425532d7 | 273 | return val == sextract64(val, 0, bits); |
a115f3ea RH |
274 | } |
275 | ||
897fd616 | 276 | static bool check_fit_i32(int32_t val, unsigned int bits) |
a115f3ea | 277 | { |
425532d7 | 278 | return val == sextract32(val, 0, bits); |
a115f3ea RH |
279 | } |
280 | ||
425532d7 | 281 | #define check_fit_tl check_fit_i64 |
3a5f6805 | 282 | #define check_fit_ptr check_fit_i64 |
425532d7 | 283 | |
0d8b6191 | 284 | static bool patch_reloc(tcg_insn_unit *src_rw, int type, |
2ba7fae2 | 285 | intptr_t value, intptr_t addend) |
a115f3ea | 286 | { |
0d8b6191 RH |
287 | const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); |
288 | uint32_t insn = *src_rw; | |
e9823b4c | 289 | intptr_t pcrel; |
abce5964 | 290 | |
e9823b4c | 291 | value += addend; |
0d8b6191 | 292 | pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, src_rx); |
abce5964 | 293 | |
a115f3ea | 294 | switch (type) { |
ab1339b9 | 295 | case R_SPARC_WDISP16: |
6a6bfa3c RH |
296 | if (!check_fit_ptr(pcrel >> 2, 16)) { |
297 | return false; | |
298 | } | |
ab1339b9 | 299 | insn &= ~INSN_OFF16(-1); |
e9823b4c | 300 | insn |= INSN_OFF16(pcrel); |
ab1339b9 | 301 | break; |
a115f3ea | 302 | case R_SPARC_WDISP19: |
6a6bfa3c RH |
303 | if (!check_fit_ptr(pcrel >> 2, 19)) { |
304 | return false; | |
305 | } | |
a115f3ea | 306 | insn &= ~INSN_OFF19(-1); |
e9823b4c RH |
307 | insn |= INSN_OFF19(pcrel); |
308 | break; | |
c834b8d8 RH |
309 | case R_SPARC_13: |
310 | if (!check_fit_ptr(value, 13)) { | |
311 | return false; | |
312 | } | |
313 | insn &= ~INSN_IMM13(-1); | |
314 | insn |= INSN_IMM13(value); | |
315 | break; | |
a115f3ea | 316 | default: |
e9823b4c | 317 | g_assert_not_reached(); |
a115f3ea | 318 | } |
e9823b4c | 319 | |
0d8b6191 | 320 | *src_rw = insn; |
6ac17786 | 321 | return true; |
a115f3ea RH |
322 | } |
323 | ||
a115f3ea | 324 | /* test if a constant matches the constraint */ |
a4fbbd77 | 325 | static bool tcg_target_const_match(int64_t val, TCGType type, int ct) |
a115f3ea | 326 | { |
a115f3ea RH |
327 | if (ct & TCG_CT_CONST) { |
328 | return 1; | |
4b304cfa RH |
329 | } |
330 | ||
331 | if (type == TCG_TYPE_I32) { | |
332 | val = (int32_t)val; | |
333 | } | |
334 | ||
335 | if ((ct & TCG_CT_CONST_ZERO) && val == 0) { | |
a115f3ea RH |
336 | return 1; |
337 | } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { | |
338 | return 1; | |
339 | } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { | |
340 | return 1; | |
341 | } else { | |
342 | return 0; | |
343 | } | |
344 | } | |
345 | ||
220b2da7 RH |
346 | static void tcg_out_nop(TCGContext *s) |
347 | { | |
348 | tcg_out32(s, NOP); | |
349 | } | |
350 | ||
897fd616 RH |
351 | static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, |
352 | TCGReg rs2, int op) | |
26cc915c | 353 | { |
35e2da15 | 354 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); |
26cc915c BS |
355 | } |
356 | ||
897fd616 RH |
357 | static void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, |
358 | int32_t offset, int op) | |
26cc915c | 359 | { |
35e2da15 | 360 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); |
26cc915c BS |
361 | } |
362 | ||
35e2da15 RH |
363 | static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, |
364 | int32_t val2, int val2const, int op) | |
ba225198 RH |
365 | { |
366 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
367 | | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); | |
368 | } | |
369 | ||
897fd616 | 370 | static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) |
8289b279 | 371 | { |
dda73c78 RH |
372 | if (ret != arg) { |
373 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); | |
374 | } | |
78113e83 | 375 | return true; |
26cc915c BS |
376 | } |
377 | ||
220b2da7 RH |
378 | static void tcg_out_mov_delay(TCGContext *s, TCGReg ret, TCGReg arg) |
379 | { | |
380 | if (ret != arg) { | |
381 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); | |
382 | } else { | |
383 | tcg_out_nop(s); | |
384 | } | |
385 | } | |
386 | ||
897fd616 | 387 | static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) |
26cc915c BS |
388 | { |
389 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); | |
8289b279 BS |
390 | } |
391 | ||
8b14f862 RH |
392 | /* A 13-bit constant sign-extended to 64 bits. */ |
393 | static void tcg_out_movi_s13(TCGContext *s, TCGReg ret, int32_t arg) | |
b101234a BS |
394 | { |
395 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); | |
396 | } | |
397 | ||
1a42d9d4 RH |
398 | /* A 32-bit constant sign-extended to 64 bits. */ |
399 | static void tcg_out_movi_s32(TCGContext *s, TCGReg ret, int32_t arg) | |
400 | { | |
401 | tcg_out_sethi(s, ret, ~arg); | |
402 | tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); | |
403 | } | |
404 | ||
2cb3f794 RH |
405 | /* A 32-bit constant zero-extended to 64 bits. */ |
406 | static void tcg_out_movi_u32(TCGContext *s, TCGReg ret, uint32_t arg) | |
c71929c3 | 407 | { |
ca0681c9 RH |
408 | tcg_out_sethi(s, ret, arg); |
409 | if (arg & 0x3ff) { | |
410 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); | |
c71929c3 RH |
411 | } |
412 | } | |
413 | ||
ab20bdc1 | 414 | static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, |
92840d06 RH |
415 | tcg_target_long arg, bool in_prologue, |
416 | TCGReg scratch) | |
8289b279 | 417 | { |
425532d7 | 418 | tcg_target_long hi, lo = (int32_t)arg; |
ab20bdc1 | 419 | tcg_target_long test, lsb; |
a9c7d27b RH |
420 | |
421 | /* A 13-bit constant sign-extended to 64-bits. */ | |
422 | if (check_fit_tl(arg, 13)) { | |
8b14f862 | 423 | tcg_out_movi_s13(s, ret, arg); |
a9c7d27b | 424 | return; |
8289b279 | 425 | } |
8289b279 | 426 | |
ca0681c9 RH |
427 | /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ |
428 | if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { | |
2cb3f794 | 429 | tcg_out_movi_u32(s, ret, arg); |
ca0681c9 RH |
430 | return; |
431 | } | |
432 | ||
f6823cbe | 433 | /* A 13-bit constant relative to the TB. */ |
1e42b4f8 | 434 | if (!in_prologue) { |
47c2206b | 435 | test = tcg_tbrel_diff(s, (void *)arg); |
f6823cbe RH |
436 | if (check_fit_ptr(test, 13)) { |
437 | tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); | |
438 | return; | |
439 | } | |
440 | } | |
441 | ||
a9c7d27b | 442 | /* A 32-bit constant sign-extended to 64-bits. */ |
425532d7 | 443 | if (arg == lo) { |
1a42d9d4 | 444 | tcg_out_movi_s32(s, ret, arg); |
a9c7d27b RH |
445 | return; |
446 | } | |
447 | ||
684db2a0 | 448 | /* A 32-bit constant, shifted. */ |
ab20bdc1 RH |
449 | lsb = ctz64(arg); |
450 | test = (tcg_target_long)arg >> lsb; | |
684db2a0 | 451 | if (lsb > 10 && test == extract64(test, 0, 21)) { |
ab20bdc1 RH |
452 | tcg_out_sethi(s, ret, test << 10); |
453 | tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); | |
454 | return; | |
684db2a0 RH |
455 | } else if (test == (uint32_t)test || test == (int32_t)test) { |
456 | tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); | |
457 | tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); | |
458 | return; | |
ab20bdc1 RH |
459 | } |
460 | ||
c834b8d8 | 461 | /* Use the constant pool, if possible. */ |
1e42b4f8 | 462 | if (!in_prologue) { |
c834b8d8 RH |
463 | new_pool_label(s, arg, R_SPARC_13, s->code_ptr, |
464 | tcg_tbrel_diff(s, NULL)); | |
465 | tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); | |
466 | return; | |
467 | } | |
468 | ||
a9c7d27b | 469 | /* A 64-bit constant decomposed into 2 32-bit pieces. */ |
425532d7 | 470 | if (check_fit_i32(lo, 13)) { |
34b1a49c | 471 | hi = (arg - lo) >> 32; |
2cb3f794 | 472 | tcg_out_movi_u32(s, ret, hi); |
a9c7d27b RH |
473 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); |
474 | tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); | |
43172207 | 475 | } else { |
34b1a49c | 476 | hi = arg >> 32; |
2cb3f794 RH |
477 | tcg_out_movi_u32(s, ret, hi); |
478 | tcg_out_movi_u32(s, scratch, lo); | |
375816f8 | 479 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); |
92840d06 | 480 | tcg_out_arith(s, ret, ret, scratch, ARITH_OR); |
6f41b777 | 481 | } |
b101234a BS |
482 | } |
483 | ||
897fd616 RH |
484 | static void tcg_out_movi(TCGContext *s, TCGType type, |
485 | TCGReg ret, tcg_target_long arg) | |
ab20bdc1 | 486 | { |
33982b89 RH |
487 | tcg_debug_assert(ret != TCG_REG_T3); |
488 | tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3); | |
ab20bdc1 RH |
489 | } |
490 | ||
678155b2 RH |
491 | static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) |
492 | { | |
493 | g_assert_not_reached(); | |
494 | } | |
495 | ||
753e42ea RH |
496 | static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) |
497 | { | |
498 | g_assert_not_reached(); | |
499 | } | |
500 | ||
d0e66c89 RH |
501 | static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) |
502 | { | |
503 | tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); | |
504 | } | |
505 | ||
379afdff RH |
506 | static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) |
507 | { | |
508 | tcg_out_arithi(s, rd, rs, 16, SHIFT_SLL); | |
509 | tcg_out_arithi(s, rd, rd, 16, SHIFT_SRL); | |
510 | } | |
511 | ||
52bf3398 RH |
512 | static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) |
513 | { | |
514 | tcg_out_arithi(s, rd, rs, 0, SHIFT_SRA); | |
515 | } | |
516 | ||
9ecf5f61 RH |
517 | static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) |
518 | { | |
519 | tcg_out_arithi(s, rd, rs, 0, SHIFT_SRL); | |
520 | } | |
521 | ||
9c6aa274 RH |
522 | static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) |
523 | { | |
524 | tcg_out_ext32s(s, rd, rs); | |
525 | } | |
526 | ||
b9bfe000 RH |
527 | static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) |
528 | { | |
529 | tcg_out_ext32u(s, rd, rs); | |
530 | } | |
531 | ||
b8b94ac6 RH |
532 | static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) |
533 | { | |
534 | tcg_out_mov(s, TCG_TYPE_I32, rd, rs); | |
535 | } | |
536 | ||
767c2503 RH |
537 | static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) |
538 | { | |
539 | return false; | |
540 | } | |
541 | ||
6a6d772e RH |
542 | static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, |
543 | tcg_target_long imm) | |
544 | { | |
545 | /* This function is only used for passing structs by reference. */ | |
546 | g_assert_not_reached(); | |
547 | } | |
548 | ||
897fd616 RH |
549 | static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, |
550 | TCGReg a2, int op) | |
8289b279 | 551 | { |
a0ce341a | 552 | tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); |
8289b279 BS |
553 | } |
554 | ||
35e2da15 RH |
555 | static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, |
556 | intptr_t offset, int op) | |
8289b279 | 557 | { |
425532d7 | 558 | if (check_fit_ptr(offset, 13)) { |
8289b279 BS |
559 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
560 | INSN_IMM13(offset)); | |
a0ce341a | 561 | } else { |
375816f8 RH |
562 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); |
563 | tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); | |
cf7c2ca5 | 564 | } |
8289b279 BS |
565 | } |
566 | ||
897fd616 RH |
567 | static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, |
568 | TCGReg arg1, intptr_t arg2) | |
8289b279 | 569 | { |
a0ce341a | 570 | tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); |
8289b279 BS |
571 | } |
572 | ||
897fd616 RH |
573 | static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
574 | TCGReg arg1, intptr_t arg2) | |
8289b279 | 575 | { |
a0ce341a RH |
576 | tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); |
577 | } | |
578 | ||
897fd616 RH |
579 | static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, |
580 | TCGReg base, intptr_t ofs) | |
59d7c14e RH |
581 | { |
582 | if (val == 0) { | |
583 | tcg_out_st(s, type, TCG_REG_G0, base, ofs); | |
584 | return true; | |
585 | } | |
586 | return false; | |
587 | } | |
588 | ||
897fd616 | 589 | static void tcg_out_sety(TCGContext *s, TCGReg rs) |
8289b279 | 590 | { |
583d1215 | 591 | tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); |
8289b279 BS |
592 | } |
593 | ||
35e2da15 RH |
594 | static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, |
595 | int32_t val2, int val2const, int uns) | |
583d1215 RH |
596 | { |
597 | /* Load Y with the sign/zero extension of RS1 to 64-bits. */ | |
598 | if (uns) { | |
599 | tcg_out_sety(s, TCG_REG_G0); | |
600 | } else { | |
375816f8 RH |
601 | tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); |
602 | tcg_out_sety(s, TCG_REG_T1); | |
583d1215 RH |
603 | } |
604 | ||
605 | tcg_out_arithc(s, rd, rs1, val2, val2const, | |
606 | uns ? ARITH_UDIV : ARITH_SDIV); | |
607 | } | |
608 | ||
0aed257f | 609 | static const uint8_t tcg_cond_to_bcond[] = { |
cf7c2ca5 BS |
610 | [TCG_COND_EQ] = COND_E, |
611 | [TCG_COND_NE] = COND_NE, | |
612 | [TCG_COND_LT] = COND_L, | |
613 | [TCG_COND_GE] = COND_GE, | |
614 | [TCG_COND_LE] = COND_LE, | |
615 | [TCG_COND_GT] = COND_G, | |
616 | [TCG_COND_LTU] = COND_CS, | |
617 | [TCG_COND_GEU] = COND_CC, | |
618 | [TCG_COND_LEU] = COND_LEU, | |
619 | [TCG_COND_GTU] = COND_GU, | |
620 | }; | |
621 | ||
ab1339b9 RH |
622 | static const uint8_t tcg_cond_to_rcond[] = { |
623 | [TCG_COND_EQ] = RCOND_Z, | |
624 | [TCG_COND_NE] = RCOND_NZ, | |
625 | [TCG_COND_LT] = RCOND_LZ, | |
626 | [TCG_COND_GT] = RCOND_GZ, | |
627 | [TCG_COND_LE] = RCOND_LEZ, | |
628 | [TCG_COND_GE] = RCOND_GEZ | |
629 | }; | |
630 | ||
a115f3ea RH |
631 | static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) |
632 | { | |
633 | tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); | |
634 | } | |
635 | ||
bec16311 | 636 | static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) |
a115f3ea | 637 | { |
791645f0 | 638 | int off19 = 0; |
a115f3ea RH |
639 | |
640 | if (l->has_value) { | |
abce5964 | 641 | off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); |
a115f3ea | 642 | } else { |
bec16311 | 643 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); |
a115f3ea RH |
644 | } |
645 | tcg_out_bpcc0(s, scond, flags, off19); | |
646 | } | |
647 | ||
35e2da15 | 648 | static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const) |
56f4927e | 649 | { |
ba225198 | 650 | tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); |
56f4927e RH |
651 | } |
652 | ||
35e2da15 | 653 | static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 654 | int32_t arg2, int const_arg2, TCGLabel *l) |
cf7c2ca5 | 655 | { |
56f4927e | 656 | tcg_out_cmp(s, arg1, arg2, const_arg2); |
bec16311 | 657 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); |
cf7c2ca5 BS |
658 | tcg_out_nop(s); |
659 | } | |
660 | ||
35e2da15 RH |
661 | static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret, |
662 | int32_t v1, int v1const) | |
ded37f0d RH |
663 | { |
664 | tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) | |
665 | | INSN_RS1(tcg_cond_to_bcond[cond]) | |
666 | | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); | |
667 | } | |
668 | ||
35e2da15 RH |
669 | static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, |
670 | TCGReg c1, int32_t c2, int c2const, | |
671 | int32_t v1, int v1const) | |
ded37f0d RH |
672 | { |
673 | tcg_out_cmp(s, c1, c2, c2const); | |
674 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); | |
675 | } | |
676 | ||
35e2da15 | 677 | static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 678 | int32_t arg2, int const_arg2, TCGLabel *l) |
1da92db2 | 679 | { |
ab1339b9 RH |
680 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ |
681 | if (arg2 == 0 && !is_unsigned_cond(cond)) { | |
791645f0 | 682 | int off16 = 0; |
ab1339b9 RH |
683 | |
684 | if (l->has_value) { | |
abce5964 | 685 | off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); |
ab1339b9 | 686 | } else { |
bec16311 | 687 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); |
ab1339b9 RH |
688 | } |
689 | tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) | |
690 | | INSN_COND(tcg_cond_to_rcond[cond]) | off16); | |
691 | } else { | |
692 | tcg_out_cmp(s, arg1, arg2, const_arg2); | |
bec16311 | 693 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); |
ab1339b9 | 694 | } |
1da92db2 BS |
695 | tcg_out_nop(s); |
696 | } | |
ded37f0d | 697 | |
35e2da15 RH |
698 | static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1, |
699 | int32_t v1, int v1const) | |
203342d8 RH |
700 | { |
701 | tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) | |
702 | | (tcg_cond_to_rcond[cond] << 10) | |
703 | | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); | |
704 | } | |
705 | ||
35e2da15 RH |
706 | static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, |
707 | TCGReg c1, int32_t c2, int c2const, | |
708 | int32_t v1, int v1const) | |
ded37f0d | 709 | { |
203342d8 RH |
710 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. |
711 | Note that the immediate range is one bit smaller, so we must check | |
712 | for that as well. */ | |
713 | if (c2 == 0 && !is_unsigned_cond(cond) | |
35e2da15 | 714 | && (!v1const || check_fit_i32(v1, 10))) { |
203342d8 RH |
715 | tcg_out_movr(s, cond, ret, c1, v1, v1const); |
716 | } else { | |
717 | tcg_out_cmp(s, c1, c2, c2const); | |
718 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); | |
719 | } | |
ded37f0d | 720 | } |
1da92db2 | 721 | |
35e2da15 RH |
722 | static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, |
723 | TCGReg c1, int32_t c2, int c2const) | |
dbfe80e1 | 724 | { |
c470b663 | 725 | /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ |
dbfe80e1 | 726 | switch (cond) { |
7d458a75 RH |
727 | case TCG_COND_LTU: |
728 | case TCG_COND_GEU: | |
729 | /* The result of the comparison is in the carry bit. */ | |
730 | break; | |
731 | ||
dbfe80e1 RH |
732 | case TCG_COND_EQ: |
733 | case TCG_COND_NE: | |
7d458a75 | 734 | /* For equality, we can transform to inequality vs zero. */ |
dbfe80e1 | 735 | if (c2 != 0) { |
321b6c05 RH |
736 | tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); |
737 | c2 = TCG_REG_T1; | |
738 | } else { | |
739 | c2 = c1; | |
dbfe80e1 | 740 | } |
321b6c05 | 741 | c1 = TCG_REG_G0, c2const = 0; |
7d458a75 | 742 | cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); |
dbfe80e1 RH |
743 | break; |
744 | ||
745 | case TCG_COND_GTU: | |
dbfe80e1 | 746 | case TCG_COND_LEU: |
7d458a75 RH |
747 | /* If we don't need to load a constant into a register, we can |
748 | swap the operands on GTU/LEU. There's no benefit to loading | |
749 | the constant into a temporary register. */ | |
750 | if (!c2const || c2 == 0) { | |
35e2da15 | 751 | TCGReg t = c1; |
7d458a75 RH |
752 | c1 = c2; |
753 | c2 = t; | |
754 | c2const = 0; | |
755 | cond = tcg_swap_cond(cond); | |
756 | break; | |
757 | } | |
758 | /* FALLTHRU */ | |
dbfe80e1 RH |
759 | |
760 | default: | |
761 | tcg_out_cmp(s, c1, c2, c2const); | |
8b14f862 | 762 | tcg_out_movi_s13(s, ret, 0); |
ded37f0d | 763 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1); |
dbfe80e1 RH |
764 | return; |
765 | } | |
766 | ||
767 | tcg_out_cmp(s, c1, c2, c2const); | |
768 | if (cond == TCG_COND_LTU) { | |
c470b663 | 769 | tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); |
dbfe80e1 | 770 | } else { |
c470b663 | 771 | tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); |
dbfe80e1 RH |
772 | } |
773 | } | |
774 | ||
35e2da15 RH |
775 | static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, |
776 | TCGReg c1, int32_t c2, int c2const) | |
dbfe80e1 | 777 | { |
9d6a7a85 RH |
778 | if (use_vis3_instructions) { |
779 | switch (cond) { | |
780 | case TCG_COND_NE: | |
781 | if (c2 != 0) { | |
782 | break; | |
783 | } | |
784 | c2 = c1, c2const = 0, c1 = TCG_REG_G0; | |
785 | /* FALLTHRU */ | |
786 | case TCG_COND_LTU: | |
787 | tcg_out_cmp(s, c1, c2, c2const); | |
788 | tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); | |
789 | return; | |
790 | default: | |
791 | break; | |
792 | } | |
793 | } | |
794 | ||
203342d8 RH |
795 | /* For 64-bit signed comparisons vs zero, we can avoid the compare |
796 | if the input does not overlap the output. */ | |
797 | if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { | |
8b14f862 | 798 | tcg_out_movi_s13(s, ret, 0); |
203342d8 RH |
799 | tcg_out_movr(s, cond, ret, c1, 1, 1); |
800 | } else { | |
801 | tcg_out_cmp(s, c1, c2, c2const); | |
8b14f862 | 802 | tcg_out_movi_s13(s, ret, 0); |
203342d8 RH |
803 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); |
804 | } | |
dbfe80e1 | 805 | } |
4ec28e25 | 806 | |
609ac1e1 RH |
807 | static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, |
808 | TCGReg al, TCGReg ah, int32_t bl, int blconst, | |
809 | int32_t bh, int bhconst, int opl, int oph) | |
4ec28e25 | 810 | { |
35e2da15 | 811 | TCGReg tmp = TCG_REG_T1; |
4ec28e25 RH |
812 | |
813 | /* Note that the low parts are fully consumed before tmp is set. */ | |
814 | if (rl != ah && (bhconst || rl != bh)) { | |
815 | tmp = rl; | |
816 | } | |
817 | ||
818 | tcg_out_arithc(s, tmp, al, bl, blconst, opl); | |
819 | tcg_out_arithc(s, rh, ah, bh, bhconst, oph); | |
820 | tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); | |
821 | } | |
dbfe80e1 | 822 | |
609ac1e1 RH |
823 | static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, |
824 | TCGReg al, TCGReg ah, int32_t bl, int blconst, | |
825 | int32_t bh, int bhconst, bool is_sub) | |
826 | { | |
827 | TCGReg tmp = TCG_REG_T1; | |
828 | ||
829 | /* Note that the low parts are fully consumed before tmp is set. */ | |
830 | if (rl != ah && (bhconst || rl != bh)) { | |
831 | tmp = rl; | |
832 | } | |
833 | ||
834 | tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC); | |
835 | ||
90379ca8 RH |
836 | if (use_vis3_instructions && !is_sub) { |
837 | /* Note that ADDXC doesn't accept immediates. */ | |
838 | if (bhconst && bh != 0) { | |
8b14f862 | 839 | tcg_out_movi_s13(s, TCG_REG_T2, bh); |
90379ca8 RH |
840 | bh = TCG_REG_T2; |
841 | } | |
842 | tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); | |
843 | } else if (bh == TCG_REG_G0) { | |
609ac1e1 RH |
844 | /* If we have a zero, we can perform the operation in two insns, |
845 | with the arithmetic first, and a conditional move into place. */ | |
846 | if (rh == ah) { | |
847 | tcg_out_arithi(s, TCG_REG_T2, ah, 1, | |
848 | is_sub ? ARITH_SUB : ARITH_ADD); | |
849 | tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); | |
850 | } else { | |
851 | tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); | |
852 | tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); | |
853 | } | |
854 | } else { | |
414399b6 RH |
855 | /* |
856 | * Otherwise adjust BH as if there is carry into T2. | |
857 | * Note that constant BH is constrained to 11 bits for the MOVCC, | |
858 | * so the adjustment fits 12 bits. | |
859 | */ | |
609ac1e1 | 860 | if (bhconst) { |
8b14f862 | 861 | tcg_out_movi_s13(s, TCG_REG_T2, bh + (is_sub ? -1 : 1)); |
609ac1e1 RH |
862 | } else { |
863 | tcg_out_arithi(s, TCG_REG_T2, bh, 1, | |
864 | is_sub ? ARITH_SUB : ARITH_ADD); | |
865 | } | |
866 | /* ... smoosh T2 back to original BH if carry is clear ... */ | |
867 | tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); | |
868 | /* ... and finally perform the arithmetic with the new operand. */ | |
869 | tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); | |
870 | } | |
871 | ||
872 | tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); | |
873 | } | |
874 | ||
e01d60f2 RH |
875 | static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest, |
876 | bool in_prologue, bool tail_call) | |
877 | { | |
878 | uintptr_t desti = (uintptr_t)dest; | |
879 | ||
e01d60f2 | 880 | tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, |
33982b89 | 881 | desti & ~0xfff, in_prologue, TCG_REG_T2); |
e01d60f2 RH |
882 | tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, |
883 | TCG_REG_T1, desti & 0xfff, JMPL); | |
884 | } | |
885 | ||
2be7d76b | 886 | static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, |
ab20bdc1 | 887 | bool in_prologue) |
aad2f06a | 888 | { |
abce5964 | 889 | ptrdiff_t disp = tcg_pcrel_diff(s, dest); |
aad2f06a RH |
890 | |
891 | if (disp == (int32_t)disp) { | |
892 | tcg_out32(s, CALL | (uint32_t)disp >> 2); | |
893 | } else { | |
e01d60f2 | 894 | tcg_out_jmpl_const(s, dest, in_prologue, false); |
aad2f06a RH |
895 | } |
896 | } | |
897 | ||
cee44b03 RH |
898 | static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, |
899 | const TCGHelperInfo *info) | |
4e9cf840 | 900 | { |
ab20bdc1 | 901 | tcg_out_call_nodelay(s, dest, false); |
4e9cf840 RH |
902 | tcg_out_nop(s); |
903 | } | |
904 | ||
f8f03b37 PK |
905 | static void tcg_out_mb(TCGContext *s, TCGArg a0) |
906 | { | |
907 | /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ | |
908 | tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); | |
909 | } | |
910 | ||
7d551702 | 911 | /* Generate global QEMU prologue and epilogue code */ |
e4d58b41 | 912 | static void tcg_target_qemu_prologue(TCGContext *s) |
b3db8758 | 913 | { |
4c3204cb RH |
914 | int tmp_buf_size, frame_size; |
915 | ||
9defd1bd RH |
916 | /* |
917 | * The TCG temp buffer is at the top of the frame, immediately | |
918 | * below the frame pointer. Use the logical (aligned) offset here; | |
919 | * the stack bias is applied in temp_allocate_frame(). | |
920 | */ | |
4c3204cb | 921 | tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); |
9defd1bd | 922 | tcg_set_frame(s, TCG_REG_I6, -tmp_buf_size, tmp_buf_size); |
4c3204cb | 923 | |
9defd1bd RH |
924 | /* |
925 | * TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is | |
926 | * otherwise the minimal frame usable by callees. | |
927 | */ | |
4c3204cb RH |
928 | frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; |
929 | frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; | |
930 | frame_size += TCG_TARGET_STACK_ALIGN - 1; | |
931 | frame_size &= -TCG_TARGET_STACK_ALIGN; | |
b3db8758 | 932 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
4c3204cb | 933 | INSN_IMM13(-frame_size)); |
c6f7e4fb | 934 | |
4cbea598 | 935 | #ifndef CONFIG_SOFTMMU |
b76f21a7 | 936 | if (guest_base != 0) { |
92840d06 RH |
937 | tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, |
938 | guest_base, true, TCG_REG_T1); | |
c6f7e4fb RH |
939 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); |
940 | } | |
941 | #endif | |
942 | ||
ab20bdc1 | 943 | /* We choose TCG_REG_TB such that no move is required. */ |
1e42b4f8 RH |
944 | QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); |
945 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); | |
ab20bdc1 | 946 | |
aad2f06a | 947 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); |
0c554161 RH |
948 | /* delay slot */ |
949 | tcg_out_nop(s); | |
4c3204cb | 950 | |
38f81dc5 | 951 | /* Epilogue for goto_ptr. */ |
c8bc1168 | 952 | tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); |
38f81dc5 RH |
953 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); |
954 | /* delay slot */ | |
8b14f862 | 955 | tcg_out_movi_s13(s, TCG_REG_O0, 0); |
b3db8758 BS |
956 | } |
957 | ||
e9823b4c RH |
958 | static void tcg_out_nop_fill(tcg_insn_unit *p, int count) |
959 | { | |
960 | int i; | |
961 | for (i = 0; i < count; ++i) { | |
962 | p[i] = NOP; | |
963 | } | |
964 | } | |
965 | ||
29086503 RH |
966 | static const TCGLdstHelperParam ldst_helper_param = { |
967 | .ntmp = 1, .tmp = { TCG_REG_T1 } | |
968 | }; | |
a0ce341a | 969 | |
29086503 | 970 | static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) |
a0ce341a | 971 | { |
29086503 RH |
972 | MemOp opc = get_memop(lb->oi); |
973 | MemOp sgn; | |
17ff9f78 | 974 | |
29086503 RH |
975 | if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, |
976 | (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { | |
977 | return false; | |
978 | } | |
a0ce341a | 979 | |
29086503 RH |
980 | /* Use inline tcg_out_ext32s; otherwise let the helper sign-extend. */ |
981 | sgn = (opc & MO_SIZE) < MO_32 ? MO_SIGN : 0; | |
17ff9f78 | 982 | |
29086503 RH |
983 | tcg_out_ld_helper_args(s, lb, &ldst_helper_param); |
984 | tcg_out_call(s, qemu_ld_helpers[opc & (MO_SIZE | sgn)], NULL); | |
985 | tcg_out_ld_helper_ret(s, lb, sgn, &ldst_helper_param); | |
17ff9f78 | 986 | |
29086503 RH |
987 | tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); |
988 | return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, | |
989 | (intptr_t)lb->raddr, 0); | |
990 | } | |
a0ce341a | 991 | |
29086503 RH |
992 | static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) |
993 | { | |
994 | MemOp opc = get_memop(lb->oi); | |
a0ce341a | 995 | |
29086503 RH |
996 | if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, |
997 | (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { | |
998 | return false; | |
a0ce341a | 999 | } |
9d0efc88 | 1000 | |
29086503 RH |
1001 | tcg_out_st_helper_args(s, lb, &ldst_helper_param); |
1002 | tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE], NULL); | |
eef0d9e7 | 1003 | |
29086503 RH |
1004 | tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); |
1005 | return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, | |
1006 | (intptr_t)lb->raddr, 0); | |
1007 | } | |
eef0d9e7 | 1008 | |
29086503 RH |
1009 | typedef struct { |
1010 | TCGReg base; | |
1011 | TCGReg index; | |
9ca63431 | 1012 | TCGAtomAlign aa; |
29086503 | 1013 | } HostAddress; |
bffe1431 | 1014 | |
7b880107 RH |
1015 | bool tcg_target_has_memory_bswap(MemOp memop) |
1016 | { | |
1017 | return true; | |
1018 | } | |
1019 | ||
29086503 RH |
1020 | /* |
1021 | * For softmmu, perform the TLB load and compare. | |
1022 | * For useronly, perform any required alignment tests. | |
1023 | * In both cases, return a TCGLabelQemuLdst structure if the slow path | |
1024 | * is required and fill in @h with the host address for the fast path. | |
1025 | */ | |
1026 | static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, | |
1027 | TCGReg addr_reg, MemOpIdx oi, | |
1028 | bool is_ld) | |
f5ef6aac | 1029 | { |
29086503 RH |
1030 | TCGLabelQemuLdst *ldst = NULL; |
1031 | MemOp opc = get_memop(oi); | |
9ca63431 | 1032 | MemOp s_bits = opc & MO_SIZE; |
29086503 | 1033 | unsigned a_mask; |
321dbde3 | 1034 | |
29086503 | 1035 | /* We don't support unaligned accesses. */ |
9ca63431 RH |
1036 | h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); |
1037 | h->aa.align = MAX(h->aa.align, s_bits); | |
1038 | a_mask = (1u << h->aa.align) - 1; | |
f5ef6aac | 1039 | |
29086503 RH |
1040 | #ifdef CONFIG_SOFTMMU |
1041 | int mem_index = get_mmuidx(oi); | |
1042 | int fast_off = TLB_MASK_TABLE_OFS(mem_index); | |
1043 | int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); | |
1044 | int table_off = fast_off + offsetof(CPUTLBDescFast, table); | |
1045 | int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) | |
1046 | : offsetof(CPUTLBEntry, addr_write); | |
1047 | int add_off = offsetof(CPUTLBEntry, addend); | |
1048 | int compare_mask; | |
1049 | int cc; | |
a0ce341a | 1050 | |
29086503 RH |
1051 | /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ |
1052 | QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); | |
1053 | QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); | |
1054 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T2, TCG_AREG0, mask_off); | |
1055 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T3, TCG_AREG0, table_off); | |
a0ce341a | 1056 | |
29086503 RH |
1057 | /* Extract the page index, shifted into place for tlb index. */ |
1058 | tcg_out_arithi(s, TCG_REG_T1, addr_reg, | |
aece72b7 | 1059 | s->page_bits - CPU_TLB_ENTRY_BITS, SHIFT_SRL); |
29086503 | 1060 | tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_AND); |
53c37487 | 1061 | |
29086503 RH |
1062 | /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ |
1063 | tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); | |
f5ef6aac | 1064 | |
29086503 RH |
1065 | /* Load the tlb comparator and the addend. */ |
1066 | tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_T2, TCG_REG_T1, cmp_off); | |
1067 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); | |
1068 | h->base = TCG_REG_T1; | |
f5ef6aac | 1069 | |
29086503 | 1070 | /* Mask out the page offset, except for the required alignment. */ |
aece72b7 | 1071 | compare_mask = s->page_mask | a_mask; |
29086503 RH |
1072 | if (check_fit_tl(compare_mask, 13)) { |
1073 | tcg_out_arithi(s, TCG_REG_T3, addr_reg, compare_mask, ARITH_AND); | |
7ea5d725 | 1074 | } else { |
29086503 RH |
1075 | tcg_out_movi_s32(s, TCG_REG_T3, compare_mask); |
1076 | tcg_out_arith(s, TCG_REG_T3, addr_reg, TCG_REG_T3, ARITH_AND); | |
7ea5d725 | 1077 | } |
29086503 | 1078 | tcg_out_cmp(s, TCG_REG_T2, TCG_REG_T3, 0); |
3a5f6805 | 1079 | |
29086503 RH |
1080 | ldst = new_ldst_label(s); |
1081 | ldst->is_ld = is_ld; | |
1082 | ldst->oi = oi; | |
1083 | ldst->addrlo_reg = addr_reg; | |
1084 | ldst->label_ptr[0] = s->code_ptr; | |
f5ef6aac | 1085 | |
29086503 RH |
1086 | /* bne,pn %[xi]cc, label0 */ |
1087 | cc = TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC; | |
1088 | tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); | |
90cbed46 | 1089 | #else |
9ca63431 RH |
1090 | /* |
1091 | * If the size equals the required alignment, we can skip the test | |
1092 | * and allow host SIGBUS to deliver SIGBUS to the guest. | |
1093 | * Otherwise, test for at least natural alignment and defer | |
1094 | * everything else to the helper functions. | |
1095 | */ | |
1096 | if (s_bits != get_alignment_bits(opc)) { | |
29086503 RH |
1097 | tcg_debug_assert(check_fit_tl(a_mask, 13)); |
1098 | tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); | |
321dbde3 | 1099 | |
29086503 RH |
1100 | ldst = new_ldst_label(s); |
1101 | ldst->is_ld = is_ld; | |
1102 | ldst->oi = oi; | |
1103 | ldst->addrlo_reg = addr_reg; | |
1104 | ldst->label_ptr[0] = s->code_ptr; | |
321dbde3 | 1105 | |
29086503 RH |
1106 | /* bne,pn %icc, label0 */ |
1107 | tcg_out_bpcc0(s, COND_NE, BPCC_PN | BPCC_ICC, 0); | |
321dbde3 | 1108 | } |
29086503 RH |
1109 | h->base = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0; |
1110 | #endif | |
321dbde3 | 1111 | |
29086503 RH |
1112 | /* If the guest address must be zero-extended, do in the delay slot. */ |
1113 | if (TARGET_LONG_BITS == 32) { | |
1114 | tcg_out_ext32u(s, TCG_REG_T2, addr_reg); | |
1115 | h->index = TCG_REG_T2; | |
321dbde3 | 1116 | } else { |
29086503 RH |
1117 | if (ldst) { |
1118 | tcg_out_nop(s); | |
321dbde3 | 1119 | } |
29086503 | 1120 | h->index = addr_reg; |
321dbde3 | 1121 | } |
29086503 RH |
1122 | return ldst; |
1123 | } | |
321dbde3 | 1124 | |
29086503 RH |
1125 | static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, |
1126 | MemOpIdx oi, TCGType data_type) | |
1127 | { | |
1128 | static const int ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = { | |
1129 | [MO_UB] = LDUB, | |
1130 | [MO_SB] = LDSB, | |
1131 | [MO_UB | MO_LE] = LDUB, | |
1132 | [MO_SB | MO_LE] = LDSB, | |
1133 | ||
1134 | [MO_BEUW] = LDUH, | |
1135 | [MO_BESW] = LDSH, | |
1136 | [MO_BEUL] = LDUW, | |
1137 | [MO_BESL] = LDSW, | |
1138 | [MO_BEUQ] = LDX, | |
1139 | [MO_BESQ] = LDX, | |
1140 | ||
1141 | [MO_LEUW] = LDUH_LE, | |
1142 | [MO_LESW] = LDSH_LE, | |
1143 | [MO_LEUL] = LDUW_LE, | |
1144 | [MO_LESL] = LDSW_LE, | |
1145 | [MO_LEUQ] = LDX_LE, | |
1146 | [MO_LESQ] = LDX_LE, | |
1147 | }; | |
1148 | ||
1149 | TCGLabelQemuLdst *ldst; | |
1150 | HostAddress h; | |
1151 | ||
1152 | ldst = prepare_host_addr(s, &h, addr, oi, true); | |
1153 | ||
1154 | tcg_out_ldst_rr(s, data, h.base, h.index, | |
1155 | ld_opc[get_memop(oi) & (MO_BSWAP | MO_SSIZE)]); | |
1156 | ||
1157 | if (ldst) { | |
1158 | ldst->type = data_type; | |
1159 | ldst->datalo_reg = data; | |
1160 | ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); | |
1161 | } | |
f5ef6aac BS |
1162 | } |
1163 | ||
34b1a49c | 1164 | static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, |
b3dfd5fc | 1165 | MemOpIdx oi, TCGType data_type) |
f5ef6aac | 1166 | { |
29086503 RH |
1167 | static const int st_opc[(MO_SIZE | MO_BSWAP) + 1] = { |
1168 | [MO_UB] = STB, | |
321dbde3 | 1169 | |
29086503 RH |
1170 | [MO_BEUW] = STH, |
1171 | [MO_BEUL] = STW, | |
1172 | [MO_BEUQ] = STX, | |
a0ce341a | 1173 | |
29086503 RH |
1174 | [MO_LEUW] = STH_LE, |
1175 | [MO_LEUL] = STW_LE, | |
1176 | [MO_LEUQ] = STX_LE, | |
1177 | }; | |
a0ce341a | 1178 | |
29086503 RH |
1179 | TCGLabelQemuLdst *ldst; |
1180 | HostAddress h; | |
53c37487 | 1181 | |
29086503 | 1182 | ldst = prepare_host_addr(s, &h, addr, oi, false); |
f5ef6aac | 1183 | |
29086503 RH |
1184 | tcg_out_ldst_rr(s, data, h.base, h.index, |
1185 | st_opc[get_memop(oi) & (MO_BSWAP | MO_SIZE)]); | |
321dbde3 | 1186 | |
29086503 RH |
1187 | if (ldst) { |
1188 | ldst->type = data_type; | |
1189 | ldst->datalo_reg = data; | |
1190 | ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); | |
321dbde3 | 1191 | } |
f5ef6aac BS |
1192 | } |
1193 | ||
b55a8d9d RH |
1194 | static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) |
1195 | { | |
1196 | if (check_fit_ptr(a0, 13)) { | |
1197 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); | |
8b14f862 | 1198 | tcg_out_movi_s13(s, TCG_REG_O0, a0); |
b55a8d9d | 1199 | return; |
1e42b4f8 | 1200 | } else { |
b55a8d9d RH |
1201 | intptr_t tb_diff = tcg_tbrel_diff(s, (void *)a0); |
1202 | if (check_fit_ptr(tb_diff, 13)) { | |
1203 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); | |
1204 | /* Note that TCG_REG_TB has been unwound to O1. */ | |
1205 | tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); | |
1206 | return; | |
1207 | } | |
1208 | } | |
1209 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); | |
1210 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); | |
1211 | tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); | |
1212 | } | |
1213 | ||
cf7d6b8e RH |
1214 | static void tcg_out_goto_tb(TCGContext *s, int which) |
1215 | { | |
a228ae3e | 1216 | ptrdiff_t off = tcg_tbrel_diff(s, (void *)get_jmp_target_addr(s, which)); |
1e42b4f8 | 1217 | |
1ffbe5d6 | 1218 | /* Load link and indirect branch. */ |
1e42b4f8 | 1219 | set_jmp_insn_offset(s, which); |
a228ae3e | 1220 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, TCG_REG_TB, off); |
1ffbe5d6 RH |
1221 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); |
1222 | /* delay slot */ | |
1223 | tcg_out_nop(s); | |
cf7d6b8e RH |
1224 | set_jmp_reset_offset(s, which); |
1225 | ||
1226 | /* | |
1227 | * For the unlinked path of goto_tb, we need to reset TCG_REG_TB | |
1228 | * to the beginning of this TB. | |
1229 | */ | |
a228ae3e RH |
1230 | off = -tcg_current_code_size(s); |
1231 | if (check_fit_i32(off, 13)) { | |
1232 | tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, off, ARITH_ADD); | |
1e42b4f8 | 1233 | } else { |
a228ae3e | 1234 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, off); |
1e42b4f8 | 1235 | tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); |
cf7d6b8e RH |
1236 | } |
1237 | } | |
1238 | ||
a228ae3e RH |
1239 | void tb_target_set_jmp_target(const TranslationBlock *tb, int n, |
1240 | uintptr_t jmp_rx, uintptr_t jmp_rw) | |
1241 | { | |
a228ae3e RH |
1242 | } |
1243 | ||
b357f902 RH |
1244 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, |
1245 | const TCGArg args[TCG_MAX_OP_ARGS], | |
1246 | const int const_args[TCG_MAX_OP_ARGS]) | |
8289b279 | 1247 | { |
b357f902 RH |
1248 | TCGArg a0, a1, a2; |
1249 | int c, c2; | |
1250 | ||
1251 | /* Hoist the loads of the most common arguments. */ | |
1252 | a0 = args[0]; | |
1253 | a1 = args[1]; | |
1254 | a2 = args[2]; | |
1255 | c2 = const_args[2]; | |
8289b279 BS |
1256 | |
1257 | switch (opc) { | |
38f81dc5 RH |
1258 | case INDEX_op_goto_ptr: |
1259 | tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); | |
1e42b4f8 | 1260 | tcg_out_mov_delay(s, TCG_REG_TB, a0); |
38f81dc5 | 1261 | break; |
8289b279 | 1262 | case INDEX_op_br: |
bec16311 | 1263 | tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); |
f5ef6aac | 1264 | tcg_out_nop(s); |
8289b279 | 1265 | break; |
8289b279 | 1266 | |
8289b279 | 1267 | #define OP_32_64(x) \ |
ba225198 RH |
1268 | glue(glue(case INDEX_op_, x), _i32): \ |
1269 | glue(glue(case INDEX_op_, x), _i64) | |
34b1a49c | 1270 | |
ba225198 | 1271 | OP_32_64(ld8u): |
b357f902 | 1272 | tcg_out_ldst(s, a0, a1, a2, LDUB); |
8289b279 | 1273 | break; |
ba225198 | 1274 | OP_32_64(ld8s): |
b357f902 | 1275 | tcg_out_ldst(s, a0, a1, a2, LDSB); |
8289b279 | 1276 | break; |
ba225198 | 1277 | OP_32_64(ld16u): |
b357f902 | 1278 | tcg_out_ldst(s, a0, a1, a2, LDUH); |
8289b279 | 1279 | break; |
ba225198 | 1280 | OP_32_64(ld16s): |
b357f902 | 1281 | tcg_out_ldst(s, a0, a1, a2, LDSH); |
8289b279 BS |
1282 | break; |
1283 | case INDEX_op_ld_i32: | |
53cd9273 | 1284 | case INDEX_op_ld32u_i64: |
b357f902 | 1285 | tcg_out_ldst(s, a0, a1, a2, LDUW); |
8289b279 | 1286 | break; |
ba225198 | 1287 | OP_32_64(st8): |
b357f902 | 1288 | tcg_out_ldst(s, a0, a1, a2, STB); |
8289b279 | 1289 | break; |
ba225198 | 1290 | OP_32_64(st16): |
b357f902 | 1291 | tcg_out_ldst(s, a0, a1, a2, STH); |
8289b279 BS |
1292 | break; |
1293 | case INDEX_op_st_i32: | |
53cd9273 | 1294 | case INDEX_op_st32_i64: |
b357f902 | 1295 | tcg_out_ldst(s, a0, a1, a2, STW); |
8289b279 | 1296 | break; |
ba225198 | 1297 | OP_32_64(add): |
53cd9273 | 1298 | c = ARITH_ADD; |
ba225198 RH |
1299 | goto gen_arith; |
1300 | OP_32_64(sub): | |
8289b279 | 1301 | c = ARITH_SUB; |
ba225198 RH |
1302 | goto gen_arith; |
1303 | OP_32_64(and): | |
8289b279 | 1304 | c = ARITH_AND; |
ba225198 | 1305 | goto gen_arith; |
dc69960d RH |
1306 | OP_32_64(andc): |
1307 | c = ARITH_ANDN; | |
1308 | goto gen_arith; | |
ba225198 | 1309 | OP_32_64(or): |
8289b279 | 1310 | c = ARITH_OR; |
ba225198 | 1311 | goto gen_arith; |
18c8f7a3 RH |
1312 | OP_32_64(orc): |
1313 | c = ARITH_ORN; | |
1314 | goto gen_arith; | |
ba225198 | 1315 | OP_32_64(xor): |
8289b279 | 1316 | c = ARITH_XOR; |
ba225198 | 1317 | goto gen_arith; |
8289b279 BS |
1318 | case INDEX_op_shl_i32: |
1319 | c = SHIFT_SLL; | |
1fd95946 RH |
1320 | do_shift32: |
1321 | /* Limit immediate shift count lest we create an illegal insn. */ | |
b357f902 | 1322 | tcg_out_arithc(s, a0, a1, a2 & 31, c2, c); |
1fd95946 | 1323 | break; |
8289b279 BS |
1324 | case INDEX_op_shr_i32: |
1325 | c = SHIFT_SRL; | |
1fd95946 | 1326 | goto do_shift32; |
8289b279 BS |
1327 | case INDEX_op_sar_i32: |
1328 | c = SHIFT_SRA; | |
1fd95946 | 1329 | goto do_shift32; |
8289b279 BS |
1330 | case INDEX_op_mul_i32: |
1331 | c = ARITH_UMUL; | |
ba225198 | 1332 | goto gen_arith; |
583d1215 | 1333 | |
4b5a85c1 RH |
1334 | OP_32_64(neg): |
1335 | c = ARITH_SUB; | |
1336 | goto gen_arith1; | |
be6551b1 RH |
1337 | OP_32_64(not): |
1338 | c = ARITH_ORN; | |
1339 | goto gen_arith1; | |
4b5a85c1 | 1340 | |
583d1215 | 1341 | case INDEX_op_div_i32: |
b357f902 | 1342 | tcg_out_div32(s, a0, a1, a2, c2, 0); |
583d1215 RH |
1343 | break; |
1344 | case INDEX_op_divu_i32: | |
b357f902 | 1345 | tcg_out_div32(s, a0, a1, a2, c2, 1); |
583d1215 RH |
1346 | break; |
1347 | ||
8289b279 | 1348 | case INDEX_op_brcond_i32: |
bec16311 | 1349 | tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); |
8289b279 | 1350 | break; |
dbfe80e1 | 1351 | case INDEX_op_setcond_i32: |
b357f902 | 1352 | tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2); |
dbfe80e1 | 1353 | break; |
ded37f0d | 1354 | case INDEX_op_movcond_i32: |
b357f902 | 1355 | tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); |
ded37f0d | 1356 | break; |
dbfe80e1 | 1357 | |
7a3766f3 | 1358 | case INDEX_op_add2_i32: |
609ac1e1 RH |
1359 | tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], |
1360 | args[4], const_args[4], args[5], const_args[5], | |
c470b663 | 1361 | ARITH_ADDCC, ARITH_ADDC); |
7a3766f3 RH |
1362 | break; |
1363 | case INDEX_op_sub2_i32: | |
609ac1e1 RH |
1364 | tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], |
1365 | args[4], const_args[4], args[5], const_args[5], | |
c470b663 | 1366 | ARITH_SUBCC, ARITH_SUBC); |
7a3766f3 RH |
1367 | break; |
1368 | case INDEX_op_mulu2_i32: | |
f4c16661 RH |
1369 | c = ARITH_UMUL; |
1370 | goto do_mul2; | |
1371 | case INDEX_op_muls2_i32: | |
1372 | c = ARITH_SMUL; | |
1373 | do_mul2: | |
3a5f6805 | 1374 | /* The 32-bit multiply insns produce a full 64-bit result. */ |
b357f902 | 1375 | tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); |
3a5f6805 | 1376 | tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); |
7a3766f3 | 1377 | break; |
8289b279 | 1378 | |
fecccfcc RH |
1379 | case INDEX_op_qemu_ld_a32_i32: |
1380 | case INDEX_op_qemu_ld_a64_i32: | |
e2adae3f | 1381 | tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); |
8289b279 | 1382 | break; |
fecccfcc RH |
1383 | case INDEX_op_qemu_ld_a32_i64: |
1384 | case INDEX_op_qemu_ld_a64_i64: | |
e2adae3f | 1385 | tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); |
8289b279 | 1386 | break; |
fecccfcc RH |
1387 | case INDEX_op_qemu_st_a32_i32: |
1388 | case INDEX_op_qemu_st_a64_i32: | |
b3dfd5fc RH |
1389 | tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); |
1390 | break; | |
fecccfcc RH |
1391 | case INDEX_op_qemu_st_a32_i64: |
1392 | case INDEX_op_qemu_st_a64_i64: | |
b3dfd5fc | 1393 | tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); |
a0ce341a | 1394 | break; |
8289b279 | 1395 | |
53cd9273 | 1396 | case INDEX_op_ld32s_i64: |
b357f902 | 1397 | tcg_out_ldst(s, a0, a1, a2, LDSW); |
53cd9273 | 1398 | break; |
8289b279 | 1399 | case INDEX_op_ld_i64: |
b357f902 | 1400 | tcg_out_ldst(s, a0, a1, a2, LDX); |
8289b279 BS |
1401 | break; |
1402 | case INDEX_op_st_i64: | |
b357f902 | 1403 | tcg_out_ldst(s, a0, a1, a2, STX); |
8289b279 BS |
1404 | break; |
1405 | case INDEX_op_shl_i64: | |
1406 | c = SHIFT_SLLX; | |
1fd95946 RH |
1407 | do_shift64: |
1408 | /* Limit immediate shift count lest we create an illegal insn. */ | |
b357f902 | 1409 | tcg_out_arithc(s, a0, a1, a2 & 63, c2, c); |
1fd95946 | 1410 | break; |
8289b279 BS |
1411 | case INDEX_op_shr_i64: |
1412 | c = SHIFT_SRLX; | |
1fd95946 | 1413 | goto do_shift64; |
8289b279 BS |
1414 | case INDEX_op_sar_i64: |
1415 | c = SHIFT_SRAX; | |
1fd95946 | 1416 | goto do_shift64; |
8289b279 BS |
1417 | case INDEX_op_mul_i64: |
1418 | c = ARITH_MULX; | |
ba225198 | 1419 | goto gen_arith; |
583d1215 | 1420 | case INDEX_op_div_i64: |
53cd9273 | 1421 | c = ARITH_SDIVX; |
ba225198 | 1422 | goto gen_arith; |
583d1215 | 1423 | case INDEX_op_divu_i64: |
8289b279 | 1424 | c = ARITH_UDIVX; |
ba225198 | 1425 | goto gen_arith; |
609ad705 RH |
1426 | case INDEX_op_extrh_i64_i32: |
1427 | tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX); | |
a24fba93 | 1428 | break; |
8289b279 BS |
1429 | |
1430 | case INDEX_op_brcond_i64: | |
bec16311 | 1431 | tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); |
8289b279 | 1432 | break; |
dbfe80e1 | 1433 | case INDEX_op_setcond_i64: |
b357f902 | 1434 | tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2); |
dbfe80e1 | 1435 | break; |
ded37f0d | 1436 | case INDEX_op_movcond_i64: |
b357f902 | 1437 | tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); |
ded37f0d | 1438 | break; |
609ac1e1 RH |
1439 | case INDEX_op_add2_i64: |
1440 | tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], | |
1441 | const_args[4], args[5], const_args[5], false); | |
1442 | break; | |
1443 | case INDEX_op_sub2_i64: | |
1444 | tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], | |
1445 | const_args[4], args[5], const_args[5], true); | |
1446 | break; | |
de8301e5 RH |
1447 | case INDEX_op_muluh_i64: |
1448 | tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); | |
1449 | break; | |
34b1a49c | 1450 | |
ba225198 | 1451 | gen_arith: |
b357f902 | 1452 | tcg_out_arithc(s, a0, a1, a2, c2, c); |
53cd9273 BS |
1453 | break; |
1454 | ||
4b5a85c1 | 1455 | gen_arith1: |
b357f902 | 1456 | tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); |
4b5a85c1 RH |
1457 | break; |
1458 | ||
f8f03b37 PK |
1459 | case INDEX_op_mb: |
1460 | tcg_out_mb(s, a0); | |
1461 | break; | |
1462 | ||
96d0ee7f | 1463 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ |
98b90bab | 1464 | case INDEX_op_mov_i64: |
96d0ee7f | 1465 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ |
b55a8d9d | 1466 | case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ |
cf7d6b8e | 1467 | case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ |
678155b2 RH |
1468 | case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ |
1469 | case INDEX_op_ext8s_i64: | |
d0e66c89 RH |
1470 | case INDEX_op_ext8u_i32: |
1471 | case INDEX_op_ext8u_i64: | |
753e42ea RH |
1472 | case INDEX_op_ext16s_i32: |
1473 | case INDEX_op_ext16s_i64: | |
379afdff RH |
1474 | case INDEX_op_ext16u_i32: |
1475 | case INDEX_op_ext16u_i64: | |
52bf3398 | 1476 | case INDEX_op_ext32s_i64: |
9ecf5f61 | 1477 | case INDEX_op_ext32u_i64: |
9c6aa274 | 1478 | case INDEX_op_ext_i32_i64: |
b9bfe000 | 1479 | case INDEX_op_extu_i32_i64: |
b8b94ac6 | 1480 | case INDEX_op_extrl_i64_i32: |
8289b279 | 1481 | default: |
732e89f4 | 1482 | g_assert_not_reached(); |
8289b279 BS |
1483 | } |
1484 | } | |
1485 | ||
0d11dc7c | 1486 | static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) |
f69d277e | 1487 | { |
9be44a16 RH |
1488 | switch (op) { |
1489 | case INDEX_op_goto_ptr: | |
0d11dc7c | 1490 | return C_O0_I1(r); |
f69d277e | 1491 | |
9be44a16 | 1492 | case INDEX_op_ld8u_i32: |
a59a2931 | 1493 | case INDEX_op_ld8u_i64: |
9be44a16 | 1494 | case INDEX_op_ld8s_i32: |
a59a2931 | 1495 | case INDEX_op_ld8s_i64: |
9be44a16 | 1496 | case INDEX_op_ld16u_i32: |
a59a2931 | 1497 | case INDEX_op_ld16u_i64: |
9be44a16 | 1498 | case INDEX_op_ld16s_i32: |
a59a2931 | 1499 | case INDEX_op_ld16s_i64: |
9be44a16 | 1500 | case INDEX_op_ld_i32: |
a59a2931 RH |
1501 | case INDEX_op_ld32u_i64: |
1502 | case INDEX_op_ld32s_i64: | |
1503 | case INDEX_op_ld_i64: | |
9be44a16 | 1504 | case INDEX_op_neg_i32: |
a59a2931 | 1505 | case INDEX_op_neg_i64: |
9be44a16 | 1506 | case INDEX_op_not_i32: |
a59a2931 RH |
1507 | case INDEX_op_not_i64: |
1508 | case INDEX_op_ext32s_i64: | |
1509 | case INDEX_op_ext32u_i64: | |
1510 | case INDEX_op_ext_i32_i64: | |
1511 | case INDEX_op_extu_i32_i64: | |
1512 | case INDEX_op_extrl_i64_i32: | |
1513 | case INDEX_op_extrh_i64_i32: | |
fecccfcc RH |
1514 | case INDEX_op_qemu_ld_a32_i32: |
1515 | case INDEX_op_qemu_ld_a64_i32: | |
1516 | case INDEX_op_qemu_ld_a32_i64: | |
1517 | case INDEX_op_qemu_ld_a64_i64: | |
0d11dc7c | 1518 | return C_O1_I1(r, r); |
9be44a16 RH |
1519 | |
1520 | case INDEX_op_st8_i32: | |
a59a2931 | 1521 | case INDEX_op_st8_i64: |
9be44a16 | 1522 | case INDEX_op_st16_i32: |
a59a2931 | 1523 | case INDEX_op_st16_i64: |
9be44a16 | 1524 | case INDEX_op_st_i32: |
a59a2931 RH |
1525 | case INDEX_op_st32_i64: |
1526 | case INDEX_op_st_i64: | |
fecccfcc RH |
1527 | case INDEX_op_qemu_st_a32_i32: |
1528 | case INDEX_op_qemu_st_a64_i32: | |
1529 | case INDEX_op_qemu_st_a32_i64: | |
1530 | case INDEX_op_qemu_st_a64_i64: | |
0d11dc7c | 1531 | return C_O0_I2(rZ, r); |
9be44a16 RH |
1532 | |
1533 | case INDEX_op_add_i32: | |
a59a2931 | 1534 | case INDEX_op_add_i64: |
9be44a16 | 1535 | case INDEX_op_mul_i32: |
a59a2931 | 1536 | case INDEX_op_mul_i64: |
9be44a16 | 1537 | case INDEX_op_div_i32: |
a59a2931 | 1538 | case INDEX_op_div_i64: |
9be44a16 | 1539 | case INDEX_op_divu_i32: |
a59a2931 | 1540 | case INDEX_op_divu_i64: |
9be44a16 | 1541 | case INDEX_op_sub_i32: |
a59a2931 | 1542 | case INDEX_op_sub_i64: |
9be44a16 | 1543 | case INDEX_op_and_i32: |
a59a2931 | 1544 | case INDEX_op_and_i64: |
9be44a16 | 1545 | case INDEX_op_andc_i32: |
a59a2931 | 1546 | case INDEX_op_andc_i64: |
9be44a16 | 1547 | case INDEX_op_or_i32: |
a59a2931 | 1548 | case INDEX_op_or_i64: |
9be44a16 | 1549 | case INDEX_op_orc_i32: |
a59a2931 | 1550 | case INDEX_op_orc_i64: |
9be44a16 | 1551 | case INDEX_op_xor_i32: |
a59a2931 | 1552 | case INDEX_op_xor_i64: |
9be44a16 | 1553 | case INDEX_op_shl_i32: |
a59a2931 | 1554 | case INDEX_op_shl_i64: |
9be44a16 | 1555 | case INDEX_op_shr_i32: |
a59a2931 | 1556 | case INDEX_op_shr_i64: |
9be44a16 | 1557 | case INDEX_op_sar_i32: |
a59a2931 | 1558 | case INDEX_op_sar_i64: |
9be44a16 | 1559 | case INDEX_op_setcond_i32: |
a59a2931 | 1560 | case INDEX_op_setcond_i64: |
0d11dc7c | 1561 | return C_O1_I2(r, rZ, rJ); |
9be44a16 RH |
1562 | |
1563 | case INDEX_op_brcond_i32: | |
a59a2931 | 1564 | case INDEX_op_brcond_i64: |
0d11dc7c | 1565 | return C_O0_I2(rZ, rJ); |
9be44a16 | 1566 | case INDEX_op_movcond_i32: |
a59a2931 | 1567 | case INDEX_op_movcond_i64: |
0d11dc7c | 1568 | return C_O1_I4(r, rZ, rJ, rI, 0); |
9be44a16 | 1569 | case INDEX_op_add2_i32: |
a59a2931 | 1570 | case INDEX_op_add2_i64: |
9be44a16 | 1571 | case INDEX_op_sub2_i32: |
a59a2931 | 1572 | case INDEX_op_sub2_i64: |
0d11dc7c | 1573 | return C_O2_I4(r, r, rZ, rZ, rJ, rJ); |
9be44a16 RH |
1574 | case INDEX_op_mulu2_i32: |
1575 | case INDEX_op_muls2_i32: | |
0d11dc7c | 1576 | return C_O2_I2(r, r, rZ, rJ); |
9be44a16 | 1577 | case INDEX_op_muluh_i64: |
a59a2931 | 1578 | return C_O1_I2(r, r, r); |
9be44a16 | 1579 | |
9be44a16 | 1580 | default: |
0d11dc7c | 1581 | g_assert_not_reached(); |
f69d277e | 1582 | } |
f69d277e RH |
1583 | } |
1584 | ||
e4d58b41 | 1585 | static void tcg_target_init(TCGContext *s) |
8289b279 | 1586 | { |
a4761232 PMD |
1587 | /* |
1588 | * Only probe for the platform and capabilities if we haven't already | |
1589 | * determined maximum values at compile time. | |
1590 | */ | |
90379ca8 RH |
1591 | #ifndef use_vis3_instructions |
1592 | { | |
1593 | unsigned long hwcap = qemu_getauxval(AT_HWCAP); | |
1594 | use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; | |
1595 | } | |
1596 | #endif | |
1597 | ||
77f268e8 | 1598 | tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; |
a59a2931 | 1599 | tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; |
f46934df RH |
1600 | |
1601 | tcg_target_call_clobber_regs = 0; | |
1602 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); | |
1603 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); | |
1604 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); | |
1605 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); | |
1606 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); | |
1607 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); | |
1608 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); | |
1609 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); | |
1610 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); | |
1611 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); | |
1612 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); | |
1613 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); | |
1614 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); | |
1615 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); | |
1616 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); | |
8289b279 | 1617 | |
ccb1bb66 | 1618 | s->reserved_regs = 0; |
375816f8 RH |
1619 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ |
1620 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ | |
1621 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ | |
1622 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ | |
1623 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ | |
1624 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ | |
1625 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ | |
1626 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ | |
33982b89 | 1627 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T3); /* for internal use */ |
8289b279 | 1628 | } |
cb1977d3 | 1629 | |
3a5f6805 | 1630 | #define ELF_HOST_MACHINE EM_SPARCV9 |
cb1977d3 | 1631 | |
cb1977d3 | 1632 | typedef struct { |
ae18b28d | 1633 | DebugFrameHeader h; |
3a5f6805 | 1634 | uint8_t fde_def_cfa[4]; |
497a22eb RH |
1635 | uint8_t fde_win_save; |
1636 | uint8_t fde_ret_save[3]; | |
cb1977d3 RH |
1637 | } DebugFrame; |
1638 | ||
ae18b28d RH |
1639 | static const DebugFrame debug_frame = { |
1640 | .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ | |
1641 | .h.cie.id = -1, | |
1642 | .h.cie.version = 1, | |
1643 | .h.cie.code_align = 1, | |
1644 | .h.cie.data_align = -sizeof(void *) & 0x7f, | |
1645 | .h.cie.return_column = 15, /* o7 */ | |
cb1977d3 | 1646 | |
497a22eb | 1647 | /* Total FDE size does not include the "len" member. */ |
ae18b28d | 1648 | .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), |
497a22eb RH |
1649 | |
1650 | .fde_def_cfa = { | |
cb1977d3 RH |
1651 | 12, 30, /* DW_CFA_def_cfa i6, 2047 */ |
1652 | (2047 & 0x7f) | 0x80, (2047 >> 7) | |
cb1977d3 | 1653 | }, |
497a22eb RH |
1654 | .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ |
1655 | .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ | |
cb1977d3 RH |
1656 | }; |
1657 | ||
755bf9e5 | 1658 | void tcg_register_jit(const void *buf, size_t buf_size) |
cb1977d3 | 1659 | { |
cb1977d3 RH |
1660 | tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); |
1661 | } |