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db432672 RH |
1 | /* |
2 | * Generic vector operation expansion | |
3 | * | |
4 | * Copyright (c) 2018 Linaro | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
fb0343d5 | 9 | * version 2.1 of the License, or (at your option) any later version. |
db432672 RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
dcb32f1d | 21 | #include "tcg/tcg.h" |
47f7313d | 22 | #include "tcg/tcg-temp-internal.h" |
ad3d0e4d | 23 | #include "tcg/tcg-op-common.h" |
447ca1cb | 24 | #include "tcg/tcg-op-gvec-common.h" |
dcb32f1d | 25 | #include "tcg/tcg-gvec-desc.h" |
db432672 RH |
26 | |
27 | #define MAX_UNROLL 4 | |
28 | ||
53229a77 RH |
29 | #ifdef CONFIG_DEBUG_TCG |
30 | static const TCGOpcode vecop_list_empty[1] = { 0 }; | |
31 | #else | |
32 | #define vecop_list_empty NULL | |
33 | #endif | |
34 | ||
35 | ||
db432672 RH |
36 | /* Verify vector size and alignment rules. OFS should be the OR of all |
37 | of the operand offsets so that we can check them all at once. */ | |
38 | static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs) | |
39 | { | |
e2e7168a RH |
40 | uint32_t max_align; |
41 | ||
42 | switch (oprsz) { | |
43 | case 8: | |
44 | case 16: | |
45 | case 32: | |
46 | tcg_debug_assert(oprsz <= maxsz); | |
47 | break; | |
48 | default: | |
49 | tcg_debug_assert(oprsz == maxsz); | |
50 | break; | |
51 | } | |
52 | tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS)); | |
53 | ||
54 | max_align = maxsz >= 16 ? 15 : 7; | |
db432672 RH |
55 | tcg_debug_assert((maxsz & max_align) == 0); |
56 | tcg_debug_assert((ofs & max_align) == 0); | |
57 | } | |
58 | ||
59 | /* Verify vector overlap rules for two operands. */ | |
60 | static void check_overlap_2(uint32_t d, uint32_t a, uint32_t s) | |
61 | { | |
62 | tcg_debug_assert(d == a || d + s <= a || a + s <= d); | |
63 | } | |
64 | ||
65 | /* Verify vector overlap rules for three operands. */ | |
66 | static void check_overlap_3(uint32_t d, uint32_t a, uint32_t b, uint32_t s) | |
67 | { | |
68 | check_overlap_2(d, a, s); | |
69 | check_overlap_2(d, b, s); | |
70 | check_overlap_2(a, b, s); | |
71 | } | |
72 | ||
73 | /* Verify vector overlap rules for four operands. */ | |
74 | static void check_overlap_4(uint32_t d, uint32_t a, uint32_t b, | |
75 | uint32_t c, uint32_t s) | |
76 | { | |
77 | check_overlap_2(d, a, s); | |
78 | check_overlap_2(d, b, s); | |
79 | check_overlap_2(d, c, s); | |
80 | check_overlap_2(a, b, s); | |
81 | check_overlap_2(a, c, s); | |
82 | check_overlap_2(b, c, s); | |
83 | } | |
84 | ||
85 | /* Create a descriptor from components. */ | |
86 | uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data) | |
87 | { | |
88 | uint32_t desc = 0; | |
89 | ||
e2e7168a RH |
90 | check_size_align(oprsz, maxsz, 0); |
91 | tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS)); | |
db432672 RH |
92 | |
93 | oprsz = (oprsz / 8) - 1; | |
94 | maxsz = (maxsz / 8) - 1; | |
e2e7168a RH |
95 | |
96 | /* | |
97 | * We have just asserted in check_size_align that either | |
98 | * oprsz is {8,16,32} or matches maxsz. Encode the final | |
99 | * case with '2', as that would otherwise map to 24. | |
100 | */ | |
101 | if (oprsz == maxsz) { | |
102 | oprsz = 2; | |
103 | } | |
104 | ||
db432672 RH |
105 | desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz); |
106 | desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz); | |
107 | desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data); | |
108 | ||
109 | return desc; | |
110 | } | |
111 | ||
112 | /* Generate a call to a gvec-style helper with two vector operands. */ | |
113 | void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, | |
114 | uint32_t oprsz, uint32_t maxsz, int32_t data, | |
115 | gen_helper_gvec_2 *fn) | |
116 | { | |
117 | TCGv_ptr a0, a1; | |
88d4005b | 118 | TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); |
db432672 | 119 | |
5dd48602 RH |
120 | a0 = tcg_temp_ebb_new_ptr(); |
121 | a1 = tcg_temp_ebb_new_ptr(); | |
db432672 RH |
122 | |
123 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
124 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
125 | ||
126 | fn(a0, a1, desc); | |
127 | ||
128 | tcg_temp_free_ptr(a0); | |
129 | tcg_temp_free_ptr(a1); | |
db432672 RH |
130 | } |
131 | ||
22fc3527 RH |
132 | /* Generate a call to a gvec-style helper with two vector operands |
133 | and one scalar operand. */ | |
134 | void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, | |
135 | uint32_t oprsz, uint32_t maxsz, int32_t data, | |
136 | gen_helper_gvec_2i *fn) | |
137 | { | |
138 | TCGv_ptr a0, a1; | |
88d4005b | 139 | TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); |
22fc3527 | 140 | |
5dd48602 RH |
141 | a0 = tcg_temp_ebb_new_ptr(); |
142 | a1 = tcg_temp_ebb_new_ptr(); | |
22fc3527 RH |
143 | |
144 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
145 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
146 | ||
147 | fn(a0, a1, c, desc); | |
148 | ||
149 | tcg_temp_free_ptr(a0); | |
150 | tcg_temp_free_ptr(a1); | |
22fc3527 RH |
151 | } |
152 | ||
db432672 RH |
153 | /* Generate a call to a gvec-style helper with three vector operands. */ |
154 | void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
155 | uint32_t oprsz, uint32_t maxsz, int32_t data, | |
156 | gen_helper_gvec_3 *fn) | |
157 | { | |
158 | TCGv_ptr a0, a1, a2; | |
88d4005b | 159 | TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); |
db432672 | 160 | |
5dd48602 RH |
161 | a0 = tcg_temp_ebb_new_ptr(); |
162 | a1 = tcg_temp_ebb_new_ptr(); | |
163 | a2 = tcg_temp_ebb_new_ptr(); | |
db432672 RH |
164 | |
165 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
166 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
167 | tcg_gen_addi_ptr(a2, cpu_env, bofs); | |
168 | ||
169 | fn(a0, a1, a2, desc); | |
170 | ||
171 | tcg_temp_free_ptr(a0); | |
172 | tcg_temp_free_ptr(a1); | |
173 | tcg_temp_free_ptr(a2); | |
db432672 RH |
174 | } |
175 | ||
176 | /* Generate a call to a gvec-style helper with four vector operands. */ | |
177 | void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
178 | uint32_t cofs, uint32_t oprsz, uint32_t maxsz, | |
179 | int32_t data, gen_helper_gvec_4 *fn) | |
180 | { | |
181 | TCGv_ptr a0, a1, a2, a3; | |
88d4005b | 182 | TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); |
db432672 | 183 | |
5dd48602 RH |
184 | a0 = tcg_temp_ebb_new_ptr(); |
185 | a1 = tcg_temp_ebb_new_ptr(); | |
186 | a2 = tcg_temp_ebb_new_ptr(); | |
187 | a3 = tcg_temp_ebb_new_ptr(); | |
db432672 RH |
188 | |
189 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
190 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
191 | tcg_gen_addi_ptr(a2, cpu_env, bofs); | |
192 | tcg_gen_addi_ptr(a3, cpu_env, cofs); | |
193 | ||
194 | fn(a0, a1, a2, a3, desc); | |
195 | ||
196 | tcg_temp_free_ptr(a0); | |
197 | tcg_temp_free_ptr(a1); | |
198 | tcg_temp_free_ptr(a2); | |
199 | tcg_temp_free_ptr(a3); | |
db432672 RH |
200 | } |
201 | ||
202 | /* Generate a call to a gvec-style helper with five vector operands. */ | |
203 | void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
204 | uint32_t cofs, uint32_t xofs, uint32_t oprsz, | |
205 | uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn) | |
206 | { | |
207 | TCGv_ptr a0, a1, a2, a3, a4; | |
88d4005b | 208 | TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); |
db432672 | 209 | |
5dd48602 RH |
210 | a0 = tcg_temp_ebb_new_ptr(); |
211 | a1 = tcg_temp_ebb_new_ptr(); | |
212 | a2 = tcg_temp_ebb_new_ptr(); | |
213 | a3 = tcg_temp_ebb_new_ptr(); | |
214 | a4 = tcg_temp_ebb_new_ptr(); | |
db432672 RH |
215 | |
216 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
217 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
218 | tcg_gen_addi_ptr(a2, cpu_env, bofs); | |
219 | tcg_gen_addi_ptr(a3, cpu_env, cofs); | |
220 | tcg_gen_addi_ptr(a4, cpu_env, xofs); | |
221 | ||
222 | fn(a0, a1, a2, a3, a4, desc); | |
223 | ||
224 | tcg_temp_free_ptr(a0); | |
225 | tcg_temp_free_ptr(a1); | |
226 | tcg_temp_free_ptr(a2); | |
227 | tcg_temp_free_ptr(a3); | |
228 | tcg_temp_free_ptr(a4); | |
db432672 RH |
229 | } |
230 | ||
231 | /* Generate a call to a gvec-style helper with three vector operands | |
232 | and an extra pointer operand. */ | |
233 | void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, | |
234 | TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, | |
235 | int32_t data, gen_helper_gvec_2_ptr *fn) | |
236 | { | |
237 | TCGv_ptr a0, a1; | |
88d4005b | 238 | TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); |
db432672 | 239 | |
5dd48602 RH |
240 | a0 = tcg_temp_ebb_new_ptr(); |
241 | a1 = tcg_temp_ebb_new_ptr(); | |
db432672 RH |
242 | |
243 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
244 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
245 | ||
246 | fn(a0, a1, ptr, desc); | |
247 | ||
248 | tcg_temp_free_ptr(a0); | |
249 | tcg_temp_free_ptr(a1); | |
db432672 RH |
250 | } |
251 | ||
252 | /* Generate a call to a gvec-style helper with three vector operands | |
253 | and an extra pointer operand. */ | |
254 | void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
255 | TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, | |
256 | int32_t data, gen_helper_gvec_3_ptr *fn) | |
257 | { | |
258 | TCGv_ptr a0, a1, a2; | |
88d4005b | 259 | TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); |
db432672 | 260 | |
5dd48602 RH |
261 | a0 = tcg_temp_ebb_new_ptr(); |
262 | a1 = tcg_temp_ebb_new_ptr(); | |
263 | a2 = tcg_temp_ebb_new_ptr(); | |
db432672 RH |
264 | |
265 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
266 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
267 | tcg_gen_addi_ptr(a2, cpu_env, bofs); | |
268 | ||
269 | fn(a0, a1, a2, ptr, desc); | |
270 | ||
271 | tcg_temp_free_ptr(a0); | |
272 | tcg_temp_free_ptr(a1); | |
273 | tcg_temp_free_ptr(a2); | |
db432672 RH |
274 | } |
275 | ||
276 | /* Generate a call to a gvec-style helper with four vector operands | |
277 | and an extra pointer operand. */ | |
278 | void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
279 | uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz, | |
280 | uint32_t maxsz, int32_t data, | |
281 | gen_helper_gvec_4_ptr *fn) | |
282 | { | |
283 | TCGv_ptr a0, a1, a2, a3; | |
88d4005b | 284 | TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); |
db432672 | 285 | |
5dd48602 RH |
286 | a0 = tcg_temp_ebb_new_ptr(); |
287 | a1 = tcg_temp_ebb_new_ptr(); | |
288 | a2 = tcg_temp_ebb_new_ptr(); | |
289 | a3 = tcg_temp_ebb_new_ptr(); | |
db432672 RH |
290 | |
291 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
292 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
293 | tcg_gen_addi_ptr(a2, cpu_env, bofs); | |
294 | tcg_gen_addi_ptr(a3, cpu_env, cofs); | |
295 | ||
296 | fn(a0, a1, a2, a3, ptr, desc); | |
297 | ||
298 | tcg_temp_free_ptr(a0); | |
299 | tcg_temp_free_ptr(a1); | |
300 | tcg_temp_free_ptr(a2); | |
301 | tcg_temp_free_ptr(a3); | |
db432672 RH |
302 | } |
303 | ||
24459716 RH |
304 | /* Generate a call to a gvec-style helper with five vector operands |
305 | and an extra pointer operand. */ | |
306 | void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
307 | uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, | |
308 | uint32_t oprsz, uint32_t maxsz, int32_t data, | |
309 | gen_helper_gvec_5_ptr *fn) | |
310 | { | |
311 | TCGv_ptr a0, a1, a2, a3, a4; | |
88d4005b | 312 | TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); |
24459716 | 313 | |
5dd48602 RH |
314 | a0 = tcg_temp_ebb_new_ptr(); |
315 | a1 = tcg_temp_ebb_new_ptr(); | |
316 | a2 = tcg_temp_ebb_new_ptr(); | |
317 | a3 = tcg_temp_ebb_new_ptr(); | |
318 | a4 = tcg_temp_ebb_new_ptr(); | |
24459716 RH |
319 | |
320 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
321 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
322 | tcg_gen_addi_ptr(a2, cpu_env, bofs); | |
323 | tcg_gen_addi_ptr(a3, cpu_env, cofs); | |
324 | tcg_gen_addi_ptr(a4, cpu_env, eofs); | |
325 | ||
326 | fn(a0, a1, a2, a3, a4, ptr, desc); | |
327 | ||
328 | tcg_temp_free_ptr(a0); | |
329 | tcg_temp_free_ptr(a1); | |
330 | tcg_temp_free_ptr(a2); | |
331 | tcg_temp_free_ptr(a3); | |
332 | tcg_temp_free_ptr(a4); | |
24459716 RH |
333 | } |
334 | ||
db432672 RH |
335 | /* Return true if we want to implement something of OPRSZ bytes |
336 | in units of LNSZ. This limits the expansion of inline code. */ | |
337 | static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz) | |
338 | { | |
f47db80c RH |
339 | uint32_t q, r; |
340 | ||
341 | if (oprsz < lnsz) { | |
342 | return false; | |
343 | } | |
344 | ||
345 | q = oprsz / lnsz; | |
346 | r = oprsz % lnsz; | |
347 | tcg_debug_assert((r & 7) == 0); | |
348 | ||
349 | if (lnsz < 16) { | |
350 | /* For sizes below 16, accept no remainder. */ | |
351 | if (r != 0) { | |
352 | return false; | |
353 | } | |
354 | } else { | |
355 | /* | |
356 | * Recall that ARM SVE allows vector sizes that are not a | |
357 | * power of 2, but always a multiple of 16. The intent is | |
358 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
359 | * In addition, expand_clr needs to handle a multiple of 8. | |
360 | * Thus we can handle the tail with one more operation per | |
361 | * diminishing power of 2. | |
362 | */ | |
363 | q += ctpop32(r); | |
499748d7 | 364 | } |
f47db80c RH |
365 | |
366 | return q <= MAX_UNROLL; | |
db432672 RH |
367 | } |
368 | ||
369 | static void expand_clr(uint32_t dofs, uint32_t maxsz); | |
370 | ||
371 | /* Duplicate C as per VECE. */ | |
372 | uint64_t (dup_const)(unsigned vece, uint64_t c) | |
373 | { | |
374 | switch (vece) { | |
375 | case MO_8: | |
376 | return 0x0101010101010101ull * (uint8_t)c; | |
377 | case MO_16: | |
378 | return 0x0001000100010001ull * (uint16_t)c; | |
379 | case MO_32: | |
380 | return 0x0000000100000001ull * (uint32_t)c; | |
381 | case MO_64: | |
382 | return c; | |
383 | default: | |
384 | g_assert_not_reached(); | |
385 | } | |
386 | } | |
387 | ||
388 | /* Duplicate IN into OUT as per VECE. */ | |
614dd4f3 | 389 | void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in) |
db432672 RH |
390 | { |
391 | switch (vece) { | |
392 | case MO_8: | |
393 | tcg_gen_ext8u_i32(out, in); | |
394 | tcg_gen_muli_i32(out, out, 0x01010101); | |
395 | break; | |
396 | case MO_16: | |
397 | tcg_gen_deposit_i32(out, in, in, 16, 16); | |
398 | break; | |
399 | case MO_32: | |
400 | tcg_gen_mov_i32(out, in); | |
401 | break; | |
402 | default: | |
403 | g_assert_not_reached(); | |
404 | } | |
405 | } | |
406 | ||
614dd4f3 | 407 | void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in) |
db432672 RH |
408 | { |
409 | switch (vece) { | |
410 | case MO_8: | |
411 | tcg_gen_ext8u_i64(out, in); | |
412 | tcg_gen_muli_i64(out, out, 0x0101010101010101ull); | |
413 | break; | |
414 | case MO_16: | |
415 | tcg_gen_ext16u_i64(out, in); | |
416 | tcg_gen_muli_i64(out, out, 0x0001000100010001ull); | |
417 | break; | |
418 | case MO_32: | |
419 | tcg_gen_deposit_i64(out, in, in, 32, 32); | |
420 | break; | |
421 | case MO_64: | |
422 | tcg_gen_mov_i64(out, in); | |
423 | break; | |
424 | default: | |
425 | g_assert_not_reached(); | |
426 | } | |
427 | } | |
428 | ||
adb196cb RH |
429 | /* Select a supported vector type for implementing an operation on SIZE |
430 | * bytes. If OP is 0, assume that the real operation to be performed is | |
431 | * required by all backends. Otherwise, make sure than OP can be performed | |
432 | * on elements of size VECE in the selected type. Do not select V64 if | |
433 | * PREFER_I64 is true. Return 0 if no vector type is selected. | |
434 | */ | |
53229a77 RH |
435 | static TCGType choose_vector_type(const TCGOpcode *list, unsigned vece, |
436 | uint32_t size, bool prefer_i64) | |
adb196cb | 437 | { |
f47db80c RH |
438 | /* |
439 | * Recall that ARM SVE allows vector sizes that are not a | |
440 | * power of 2, but always a multiple of 16. The intent is | |
441 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
442 | * It is hard to imagine a case in which v256 is supported | |
443 | * but v128 is not, but check anyway. | |
444 | * In addition, expand_clr needs to handle a multiple of 8. | |
445 | */ | |
446 | if (TCG_TARGET_HAS_v256 && | |
447 | check_size_impl(size, 32) && | |
448 | tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece) && | |
449 | (!(size & 16) || | |
450 | (TCG_TARGET_HAS_v128 && | |
451 | tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) && | |
452 | (!(size & 8) || | |
453 | (TCG_TARGET_HAS_v64 && | |
454 | tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { | |
455 | return TCG_TYPE_V256; | |
adb196cb | 456 | } |
f47db80c RH |
457 | if (TCG_TARGET_HAS_v128 && |
458 | check_size_impl(size, 16) && | |
459 | tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece) && | |
460 | (!(size & 8) || | |
461 | (TCG_TARGET_HAS_v64 && | |
462 | tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { | |
adb196cb RH |
463 | return TCG_TYPE_V128; |
464 | } | |
465 | if (TCG_TARGET_HAS_v64 && !prefer_i64 && check_size_impl(size, 8) | |
53229a77 | 466 | && tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)) { |
adb196cb RH |
467 | return TCG_TYPE_V64; |
468 | } | |
469 | return 0; | |
470 | } | |
471 | ||
37ee55a0 RH |
472 | static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz, |
473 | uint32_t maxsz, TCGv_vec t_vec) | |
474 | { | |
475 | uint32_t i = 0; | |
476 | ||
f47db80c RH |
477 | tcg_debug_assert(oprsz >= 8); |
478 | ||
479 | /* | |
480 | * This may be expand_clr for the tail of an operation, e.g. | |
481 | * oprsz == 8 && maxsz == 64. The first 8 bytes of this store | |
482 | * are misaligned wrt the maximum vector size, so do that first. | |
483 | */ | |
484 | if (dofs & 8) { | |
485 | tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); | |
486 | i += 8; | |
487 | } | |
488 | ||
37ee55a0 RH |
489 | switch (type) { |
490 | case TCG_TYPE_V256: | |
491 | /* | |
492 | * Recall that ARM SVE allows vector sizes that are not a | |
493 | * power of 2, but always a multiple of 16. The intent is | |
494 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
495 | */ | |
496 | for (; i + 32 <= oprsz; i += 32) { | |
497 | tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); | |
498 | } | |
499 | /* fallthru */ | |
500 | case TCG_TYPE_V128: | |
501 | for (; i + 16 <= oprsz; i += 16) { | |
502 | tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); | |
503 | } | |
504 | break; | |
505 | case TCG_TYPE_V64: | |
506 | for (; i < oprsz; i += 8) { | |
507 | tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); | |
508 | } | |
509 | break; | |
510 | default: | |
511 | g_assert_not_reached(); | |
512 | } | |
513 | ||
514 | if (oprsz < maxsz) { | |
515 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
516 | } | |
517 | } | |
518 | ||
db432672 RH |
519 | /* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C. |
520 | * Only one of IN_32 or IN_64 may be set; | |
521 | * IN_C is used if IN_32 and IN_64 are unset. | |
522 | */ | |
523 | static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, | |
524 | uint32_t maxsz, TCGv_i32 in_32, TCGv_i64 in_64, | |
525 | uint64_t in_c) | |
526 | { | |
527 | TCGType type; | |
528 | TCGv_i64 t_64; | |
529 | TCGv_i32 t_32, t_desc; | |
530 | TCGv_ptr t_ptr; | |
531 | uint32_t i; | |
532 | ||
533 | assert(vece <= (in_32 ? MO_32 : MO_64)); | |
534 | assert(in_32 == NULL || in_64 == NULL); | |
535 | ||
536 | /* If we're storing 0, expand oprsz to maxsz. */ | |
537 | if (in_32 == NULL && in_64 == NULL) { | |
538 | in_c = dup_const(vece, in_c); | |
539 | if (in_c == 0) { | |
540 | oprsz = maxsz; | |
6d3ef048 RH |
541 | vece = MO_8; |
542 | } else if (in_c == dup_const(MO_8, in_c)) { | |
543 | vece = MO_8; | |
db432672 RH |
544 | } |
545 | } | |
546 | ||
adb196cb RH |
547 | /* Implement inline with a vector type, if possible. |
548 | * Prefer integer when 64-bit host and no variable dup. | |
549 | */ | |
53229a77 | 550 | type = choose_vector_type(NULL, vece, oprsz, |
adb196cb RH |
551 | (TCG_TARGET_REG_BITS == 64 && in_32 == NULL |
552 | && (in_64 == NULL || vece == MO_64))); | |
db432672 RH |
553 | if (type != 0) { |
554 | TCGv_vec t_vec = tcg_temp_new_vec(type); | |
555 | ||
556 | if (in_32) { | |
557 | tcg_gen_dup_i32_vec(vece, t_vec, in_32); | |
558 | } else if (in_64) { | |
559 | tcg_gen_dup_i64_vec(vece, t_vec, in_64); | |
560 | } else { | |
37ee55a0 | 561 | tcg_gen_dupi_vec(vece, t_vec, in_c); |
db432672 | 562 | } |
37ee55a0 | 563 | do_dup_store(type, dofs, oprsz, maxsz, t_vec); |
db432672 | 564 | tcg_temp_free_vec(t_vec); |
37ee55a0 | 565 | return; |
db432672 RH |
566 | } |
567 | ||
568 | /* Otherwise, inline with an integer type, unless "large". */ | |
569 | if (check_size_impl(oprsz, TCG_TARGET_REG_BITS / 8)) { | |
570 | t_64 = NULL; | |
571 | t_32 = NULL; | |
572 | ||
573 | if (in_32) { | |
574 | /* We are given a 32-bit variable input. For a 64-bit host, | |
575 | use a 64-bit operation unless the 32-bit operation would | |
576 | be simple enough. */ | |
577 | if (TCG_TARGET_REG_BITS == 64 | |
578 | && (vece != MO_32 || !check_size_impl(oprsz, 4))) { | |
5dd48602 | 579 | t_64 = tcg_temp_ebb_new_i64(); |
db432672 | 580 | tcg_gen_extu_i32_i64(t_64, in_32); |
614dd4f3 | 581 | tcg_gen_dup_i64(vece, t_64, t_64); |
db432672 | 582 | } else { |
5dd48602 | 583 | t_32 = tcg_temp_ebb_new_i32(); |
614dd4f3 | 584 | tcg_gen_dup_i32(vece, t_32, in_32); |
db432672 RH |
585 | } |
586 | } else if (in_64) { | |
587 | /* We are given a 64-bit variable input. */ | |
5dd48602 | 588 | t_64 = tcg_temp_ebb_new_i64(); |
614dd4f3 | 589 | tcg_gen_dup_i64(vece, t_64, in_64); |
db432672 RH |
590 | } else { |
591 | /* We are given a constant input. */ | |
592 | /* For 64-bit hosts, use 64-bit constants for "simple" constants | |
593 | or when we'd need too many 32-bit stores, or when a 64-bit | |
594 | constant is really required. */ | |
595 | if (vece == MO_64 | |
596 | || (TCG_TARGET_REG_BITS == 64 | |
597 | && (in_c == 0 || in_c == -1 | |
598 | || !check_size_impl(oprsz, 4)))) { | |
88d4005b | 599 | t_64 = tcg_constant_i64(in_c); |
db432672 | 600 | } else { |
88d4005b | 601 | t_32 = tcg_constant_i32(in_c); |
db432672 RH |
602 | } |
603 | } | |
604 | ||
605 | /* Implement inline if we picked an implementation size above. */ | |
606 | if (t_32) { | |
607 | for (i = 0; i < oprsz; i += 4) { | |
608 | tcg_gen_st_i32(t_32, cpu_env, dofs + i); | |
609 | } | |
610 | tcg_temp_free_i32(t_32); | |
611 | goto done; | |
612 | } | |
613 | if (t_64) { | |
614 | for (i = 0; i < oprsz; i += 8) { | |
615 | tcg_gen_st_i64(t_64, cpu_env, dofs + i); | |
616 | } | |
617 | tcg_temp_free_i64(t_64); | |
618 | goto done; | |
adb196cb | 619 | } |
db432672 RH |
620 | } |
621 | ||
622 | /* Otherwise implement out of line. */ | |
5dd48602 | 623 | t_ptr = tcg_temp_ebb_new_ptr(); |
db432672 | 624 | tcg_gen_addi_ptr(t_ptr, cpu_env, dofs); |
6d3ef048 RH |
625 | |
626 | /* | |
627 | * This may be expand_clr for the tail of an operation, e.g. | |
628 | * oprsz == 8 && maxsz == 64. The size of the clear is misaligned | |
629 | * wrt simd_desc and will assert. Simply pass all replicated byte | |
630 | * stores through to memset. | |
631 | */ | |
632 | if (oprsz == maxsz && vece == MO_8) { | |
e1986410 | 633 | TCGv_ptr t_size = tcg_constant_ptr(oprsz); |
6d3ef048 RH |
634 | TCGv_i32 t_val; |
635 | ||
636 | if (in_32) { | |
637 | t_val = in_32; | |
638 | } else if (in_64) { | |
5dd48602 | 639 | t_val = tcg_temp_ebb_new_i32(); |
6d3ef048 RH |
640 | tcg_gen_extrl_i64_i32(t_val, in_64); |
641 | } else { | |
88d4005b | 642 | t_val = tcg_constant_i32(in_c); |
6d3ef048 RH |
643 | } |
644 | gen_helper_memset(t_ptr, t_ptr, t_val, t_size); | |
645 | ||
88d4005b | 646 | if (in_64) { |
6d3ef048 RH |
647 | tcg_temp_free_i32(t_val); |
648 | } | |
6d3ef048 RH |
649 | tcg_temp_free_ptr(t_ptr); |
650 | return; | |
651 | } | |
652 | ||
88d4005b | 653 | t_desc = tcg_constant_i32(simd_desc(oprsz, maxsz, 0)); |
db432672 RH |
654 | |
655 | if (vece == MO_64) { | |
656 | if (in_64) { | |
657 | gen_helper_gvec_dup64(t_ptr, t_desc, in_64); | |
658 | } else { | |
88d4005b | 659 | t_64 = tcg_constant_i64(in_c); |
db432672 | 660 | gen_helper_gvec_dup64(t_ptr, t_desc, t_64); |
db432672 RH |
661 | } |
662 | } else { | |
663 | typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32); | |
664 | static dup_fn * const fns[3] = { | |
665 | gen_helper_gvec_dup8, | |
666 | gen_helper_gvec_dup16, | |
667 | gen_helper_gvec_dup32 | |
668 | }; | |
669 | ||
670 | if (in_32) { | |
671 | fns[vece](t_ptr, t_desc, in_32); | |
88d4005b | 672 | } else if (in_64) { |
5dd48602 | 673 | t_32 = tcg_temp_ebb_new_i32(); |
88d4005b RH |
674 | tcg_gen_extrl_i64_i32(t_32, in_64); |
675 | fns[vece](t_ptr, t_desc, t_32); | |
676 | tcg_temp_free_i32(t_32); | |
677 | } else { | |
678 | if (vece == MO_8) { | |
679 | in_c &= 0xff; | |
db432672 | 680 | } else if (vece == MO_16) { |
88d4005b | 681 | in_c &= 0xffff; |
db432672 | 682 | } |
88d4005b | 683 | t_32 = tcg_constant_i32(in_c); |
db432672 | 684 | fns[vece](t_ptr, t_desc, t_32); |
db432672 RH |
685 | } |
686 | } | |
687 | ||
688 | tcg_temp_free_ptr(t_ptr); | |
db432672 RH |
689 | return; |
690 | ||
691 | done: | |
692 | if (oprsz < maxsz) { | |
693 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
694 | } | |
695 | } | |
696 | ||
697 | /* Likewise, but with zero. */ | |
698 | static void expand_clr(uint32_t dofs, uint32_t maxsz) | |
699 | { | |
700 | do_dup(MO_8, dofs, maxsz, maxsz, NULL, NULL, 0); | |
701 | } | |
702 | ||
703 | /* Expand OPSZ bytes worth of two-operand operations using i32 elements. */ | |
704 | static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, | |
ac09ae62 | 705 | bool load_dest, void (*fni)(TCGv_i32, TCGv_i32)) |
db432672 RH |
706 | { |
707 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
ac09ae62 | 708 | TCGv_i32 t1 = tcg_temp_new_i32(); |
db432672 RH |
709 | uint32_t i; |
710 | ||
711 | for (i = 0; i < oprsz; i += 4) { | |
712 | tcg_gen_ld_i32(t0, cpu_env, aofs + i); | |
ac09ae62 RH |
713 | if (load_dest) { |
714 | tcg_gen_ld_i32(t1, cpu_env, dofs + i); | |
715 | } | |
716 | fni(t1, t0); | |
717 | tcg_gen_st_i32(t1, cpu_env, dofs + i); | |
db432672 RH |
718 | } |
719 | tcg_temp_free_i32(t0); | |
ac09ae62 | 720 | tcg_temp_free_i32(t1); |
db432672 RH |
721 | } |
722 | ||
d0ec9796 RH |
723 | static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, |
724 | int32_t c, bool load_dest, | |
725 | void (*fni)(TCGv_i32, TCGv_i32, int32_t)) | |
726 | { | |
727 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
728 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
729 | uint32_t i; | |
730 | ||
731 | for (i = 0; i < oprsz; i += 4) { | |
732 | tcg_gen_ld_i32(t0, cpu_env, aofs + i); | |
733 | if (load_dest) { | |
734 | tcg_gen_ld_i32(t1, cpu_env, dofs + i); | |
735 | } | |
736 | fni(t1, t0, c); | |
737 | tcg_gen_st_i32(t1, cpu_env, dofs + i); | |
738 | } | |
739 | tcg_temp_free_i32(t0); | |
740 | tcg_temp_free_i32(t1); | |
741 | } | |
742 | ||
22fc3527 RH |
743 | static void expand_2s_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, |
744 | TCGv_i32 c, bool scalar_first, | |
745 | void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32)) | |
746 | { | |
747 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
748 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
749 | uint32_t i; | |
750 | ||
751 | for (i = 0; i < oprsz; i += 4) { | |
752 | tcg_gen_ld_i32(t0, cpu_env, aofs + i); | |
753 | if (scalar_first) { | |
754 | fni(t1, c, t0); | |
755 | } else { | |
756 | fni(t1, t0, c); | |
757 | } | |
758 | tcg_gen_st_i32(t1, cpu_env, dofs + i); | |
759 | } | |
760 | tcg_temp_free_i32(t0); | |
761 | tcg_temp_free_i32(t1); | |
762 | } | |
763 | ||
db432672 RH |
764 | /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ |
765 | static void expand_3_i32(uint32_t dofs, uint32_t aofs, | |
766 | uint32_t bofs, uint32_t oprsz, bool load_dest, | |
767 | void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32)) | |
768 | { | |
769 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
770 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
771 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
772 | uint32_t i; | |
773 | ||
774 | for (i = 0; i < oprsz; i += 4) { | |
775 | tcg_gen_ld_i32(t0, cpu_env, aofs + i); | |
776 | tcg_gen_ld_i32(t1, cpu_env, bofs + i); | |
777 | if (load_dest) { | |
778 | tcg_gen_ld_i32(t2, cpu_env, dofs + i); | |
779 | } | |
780 | fni(t2, t0, t1); | |
781 | tcg_gen_st_i32(t2, cpu_env, dofs + i); | |
782 | } | |
783 | tcg_temp_free_i32(t2); | |
784 | tcg_temp_free_i32(t1); | |
785 | tcg_temp_free_i32(t0); | |
786 | } | |
787 | ||
e1227bb6 DH |
788 | static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, |
789 | uint32_t oprsz, int32_t c, bool load_dest, | |
790 | void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t)) | |
791 | { | |
792 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
793 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
794 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
795 | uint32_t i; | |
796 | ||
797 | for (i = 0; i < oprsz; i += 4) { | |
798 | tcg_gen_ld_i32(t0, cpu_env, aofs + i); | |
799 | tcg_gen_ld_i32(t1, cpu_env, bofs + i); | |
800 | if (load_dest) { | |
801 | tcg_gen_ld_i32(t2, cpu_env, dofs + i); | |
802 | } | |
803 | fni(t2, t0, t1, c); | |
804 | tcg_gen_st_i32(t2, cpu_env, dofs + i); | |
805 | } | |
806 | tcg_temp_free_i32(t0); | |
807 | tcg_temp_free_i32(t1); | |
808 | tcg_temp_free_i32(t2); | |
809 | } | |
810 | ||
db432672 RH |
811 | /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ |
812 | static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
5d6acdd4 | 813 | uint32_t cofs, uint32_t oprsz, bool write_aofs, |
db432672 RH |
814 | void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32)) |
815 | { | |
816 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
817 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
818 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
819 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
820 | uint32_t i; | |
821 | ||
822 | for (i = 0; i < oprsz; i += 4) { | |
823 | tcg_gen_ld_i32(t1, cpu_env, aofs + i); | |
824 | tcg_gen_ld_i32(t2, cpu_env, bofs + i); | |
825 | tcg_gen_ld_i32(t3, cpu_env, cofs + i); | |
826 | fni(t0, t1, t2, t3); | |
827 | tcg_gen_st_i32(t0, cpu_env, dofs + i); | |
5d6acdd4 RH |
828 | if (write_aofs) { |
829 | tcg_gen_st_i32(t1, cpu_env, aofs + i); | |
830 | } | |
db432672 RH |
831 | } |
832 | tcg_temp_free_i32(t3); | |
833 | tcg_temp_free_i32(t2); | |
834 | tcg_temp_free_i32(t1); | |
835 | tcg_temp_free_i32(t0); | |
836 | } | |
837 | ||
9620ae01 MF |
838 | static void expand_4i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, |
839 | uint32_t cofs, uint32_t oprsz, int32_t c, | |
840 | void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32, | |
841 | int32_t)) | |
842 | { | |
843 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
844 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
845 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
846 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
847 | uint32_t i; | |
848 | ||
849 | for (i = 0; i < oprsz; i += 4) { | |
850 | tcg_gen_ld_i32(t1, cpu_env, aofs + i); | |
851 | tcg_gen_ld_i32(t2, cpu_env, bofs + i); | |
852 | tcg_gen_ld_i32(t3, cpu_env, cofs + i); | |
853 | fni(t0, t1, t2, t3, c); | |
854 | tcg_gen_st_i32(t0, cpu_env, dofs + i); | |
855 | } | |
856 | tcg_temp_free_i32(t3); | |
857 | tcg_temp_free_i32(t2); | |
858 | tcg_temp_free_i32(t1); | |
859 | tcg_temp_free_i32(t0); | |
860 | } | |
861 | ||
db432672 RH |
862 | /* Expand OPSZ bytes worth of two-operand operations using i64 elements. */ |
863 | static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, | |
ac09ae62 | 864 | bool load_dest, void (*fni)(TCGv_i64, TCGv_i64)) |
db432672 RH |
865 | { |
866 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
ac09ae62 | 867 | TCGv_i64 t1 = tcg_temp_new_i64(); |
db432672 RH |
868 | uint32_t i; |
869 | ||
870 | for (i = 0; i < oprsz; i += 8) { | |
871 | tcg_gen_ld_i64(t0, cpu_env, aofs + i); | |
ac09ae62 RH |
872 | if (load_dest) { |
873 | tcg_gen_ld_i64(t1, cpu_env, dofs + i); | |
874 | } | |
875 | fni(t1, t0); | |
876 | tcg_gen_st_i64(t1, cpu_env, dofs + i); | |
db432672 RH |
877 | } |
878 | tcg_temp_free_i64(t0); | |
ac09ae62 | 879 | tcg_temp_free_i64(t1); |
db432672 RH |
880 | } |
881 | ||
d0ec9796 RH |
882 | static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, |
883 | int64_t c, bool load_dest, | |
884 | void (*fni)(TCGv_i64, TCGv_i64, int64_t)) | |
885 | { | |
886 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
887 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
888 | uint32_t i; | |
889 | ||
890 | for (i = 0; i < oprsz; i += 8) { | |
891 | tcg_gen_ld_i64(t0, cpu_env, aofs + i); | |
892 | if (load_dest) { | |
893 | tcg_gen_ld_i64(t1, cpu_env, dofs + i); | |
894 | } | |
895 | fni(t1, t0, c); | |
896 | tcg_gen_st_i64(t1, cpu_env, dofs + i); | |
897 | } | |
898 | tcg_temp_free_i64(t0); | |
899 | tcg_temp_free_i64(t1); | |
900 | } | |
901 | ||
22fc3527 RH |
902 | static void expand_2s_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, |
903 | TCGv_i64 c, bool scalar_first, | |
904 | void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64)) | |
905 | { | |
906 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
907 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
908 | uint32_t i; | |
909 | ||
910 | for (i = 0; i < oprsz; i += 8) { | |
911 | tcg_gen_ld_i64(t0, cpu_env, aofs + i); | |
912 | if (scalar_first) { | |
913 | fni(t1, c, t0); | |
914 | } else { | |
915 | fni(t1, t0, c); | |
916 | } | |
917 | tcg_gen_st_i64(t1, cpu_env, dofs + i); | |
918 | } | |
919 | tcg_temp_free_i64(t0); | |
920 | tcg_temp_free_i64(t1); | |
921 | } | |
922 | ||
db432672 RH |
923 | /* Expand OPSZ bytes worth of three-operand operations using i64 elements. */ |
924 | static void expand_3_i64(uint32_t dofs, uint32_t aofs, | |
925 | uint32_t bofs, uint32_t oprsz, bool load_dest, | |
926 | void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64)) | |
927 | { | |
928 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
929 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
930 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
931 | uint32_t i; | |
932 | ||
933 | for (i = 0; i < oprsz; i += 8) { | |
934 | tcg_gen_ld_i64(t0, cpu_env, aofs + i); | |
935 | tcg_gen_ld_i64(t1, cpu_env, bofs + i); | |
936 | if (load_dest) { | |
937 | tcg_gen_ld_i64(t2, cpu_env, dofs + i); | |
938 | } | |
939 | fni(t2, t0, t1); | |
940 | tcg_gen_st_i64(t2, cpu_env, dofs + i); | |
941 | } | |
942 | tcg_temp_free_i64(t2); | |
943 | tcg_temp_free_i64(t1); | |
944 | tcg_temp_free_i64(t0); | |
945 | } | |
946 | ||
e1227bb6 DH |
947 | static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, |
948 | uint32_t oprsz, int64_t c, bool load_dest, | |
949 | void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t)) | |
950 | { | |
951 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
952 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
953 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
954 | uint32_t i; | |
955 | ||
956 | for (i = 0; i < oprsz; i += 8) { | |
957 | tcg_gen_ld_i64(t0, cpu_env, aofs + i); | |
958 | tcg_gen_ld_i64(t1, cpu_env, bofs + i); | |
959 | if (load_dest) { | |
960 | tcg_gen_ld_i64(t2, cpu_env, dofs + i); | |
961 | } | |
962 | fni(t2, t0, t1, c); | |
963 | tcg_gen_st_i64(t2, cpu_env, dofs + i); | |
964 | } | |
965 | tcg_temp_free_i64(t0); | |
966 | tcg_temp_free_i64(t1); | |
967 | tcg_temp_free_i64(t2); | |
968 | } | |
969 | ||
db432672 RH |
970 | /* Expand OPSZ bytes worth of three-operand operations using i64 elements. */ |
971 | static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
5d6acdd4 | 972 | uint32_t cofs, uint32_t oprsz, bool write_aofs, |
db432672 RH |
973 | void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) |
974 | { | |
975 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
976 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
977 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
978 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
979 | uint32_t i; | |
980 | ||
981 | for (i = 0; i < oprsz; i += 8) { | |
982 | tcg_gen_ld_i64(t1, cpu_env, aofs + i); | |
983 | tcg_gen_ld_i64(t2, cpu_env, bofs + i); | |
984 | tcg_gen_ld_i64(t3, cpu_env, cofs + i); | |
985 | fni(t0, t1, t2, t3); | |
986 | tcg_gen_st_i64(t0, cpu_env, dofs + i); | |
5d6acdd4 RH |
987 | if (write_aofs) { |
988 | tcg_gen_st_i64(t1, cpu_env, aofs + i); | |
989 | } | |
db432672 RH |
990 | } |
991 | tcg_temp_free_i64(t3); | |
992 | tcg_temp_free_i64(t2); | |
993 | tcg_temp_free_i64(t1); | |
994 | tcg_temp_free_i64(t0); | |
995 | } | |
996 | ||
9620ae01 MF |
997 | static void expand_4i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, |
998 | uint32_t cofs, uint32_t oprsz, int64_t c, | |
999 | void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, | |
1000 | int64_t)) | |
1001 | { | |
1002 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1003 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1004 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1005 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1006 | uint32_t i; | |
1007 | ||
1008 | for (i = 0; i < oprsz; i += 8) { | |
1009 | tcg_gen_ld_i64(t1, cpu_env, aofs + i); | |
1010 | tcg_gen_ld_i64(t2, cpu_env, bofs + i); | |
1011 | tcg_gen_ld_i64(t3, cpu_env, cofs + i); | |
1012 | fni(t0, t1, t2, t3, c); | |
1013 | tcg_gen_st_i64(t0, cpu_env, dofs + i); | |
1014 | } | |
1015 | tcg_temp_free_i64(t3); | |
1016 | tcg_temp_free_i64(t2); | |
1017 | tcg_temp_free_i64(t1); | |
1018 | tcg_temp_free_i64(t0); | |
1019 | } | |
1020 | ||
db432672 RH |
1021 | /* Expand OPSZ bytes worth of two-operand operations using host vectors. */ |
1022 | static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs, | |
1023 | uint32_t oprsz, uint32_t tysz, TCGType type, | |
ac09ae62 | 1024 | bool load_dest, |
db432672 RH |
1025 | void (*fni)(unsigned, TCGv_vec, TCGv_vec)) |
1026 | { | |
1027 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
ac09ae62 | 1028 | TCGv_vec t1 = tcg_temp_new_vec(type); |
db432672 RH |
1029 | uint32_t i; |
1030 | ||
1031 | for (i = 0; i < oprsz; i += tysz) { | |
1032 | tcg_gen_ld_vec(t0, cpu_env, aofs + i); | |
ac09ae62 RH |
1033 | if (load_dest) { |
1034 | tcg_gen_ld_vec(t1, cpu_env, dofs + i); | |
1035 | } | |
1036 | fni(vece, t1, t0); | |
1037 | tcg_gen_st_vec(t1, cpu_env, dofs + i); | |
db432672 RH |
1038 | } |
1039 | tcg_temp_free_vec(t0); | |
ac09ae62 | 1040 | tcg_temp_free_vec(t1); |
db432672 RH |
1041 | } |
1042 | ||
d0ec9796 RH |
1043 | /* Expand OPSZ bytes worth of two-vector operands and an immediate operand |
1044 | using host vectors. */ | |
1045 | static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, | |
1046 | uint32_t oprsz, uint32_t tysz, TCGType type, | |
1047 | int64_t c, bool load_dest, | |
1048 | void (*fni)(unsigned, TCGv_vec, TCGv_vec, int64_t)) | |
1049 | { | |
1050 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
1051 | TCGv_vec t1 = tcg_temp_new_vec(type); | |
1052 | uint32_t i; | |
1053 | ||
1054 | for (i = 0; i < oprsz; i += tysz) { | |
1055 | tcg_gen_ld_vec(t0, cpu_env, aofs + i); | |
1056 | if (load_dest) { | |
1057 | tcg_gen_ld_vec(t1, cpu_env, dofs + i); | |
1058 | } | |
1059 | fni(vece, t1, t0, c); | |
1060 | tcg_gen_st_vec(t1, cpu_env, dofs + i); | |
1061 | } | |
1062 | tcg_temp_free_vec(t0); | |
1063 | tcg_temp_free_vec(t1); | |
1064 | } | |
1065 | ||
22fc3527 RH |
1066 | static void expand_2s_vec(unsigned vece, uint32_t dofs, uint32_t aofs, |
1067 | uint32_t oprsz, uint32_t tysz, TCGType type, | |
1068 | TCGv_vec c, bool scalar_first, | |
1069 | void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec)) | |
1070 | { | |
1071 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
1072 | TCGv_vec t1 = tcg_temp_new_vec(type); | |
1073 | uint32_t i; | |
1074 | ||
1075 | for (i = 0; i < oprsz; i += tysz) { | |
1076 | tcg_gen_ld_vec(t0, cpu_env, aofs + i); | |
1077 | if (scalar_first) { | |
1078 | fni(vece, t1, c, t0); | |
1079 | } else { | |
1080 | fni(vece, t1, t0, c); | |
1081 | } | |
1082 | tcg_gen_st_vec(t1, cpu_env, dofs + i); | |
1083 | } | |
1084 | tcg_temp_free_vec(t0); | |
1085 | tcg_temp_free_vec(t1); | |
1086 | } | |
1087 | ||
db432672 RH |
1088 | /* Expand OPSZ bytes worth of three-operand operations using host vectors. */ |
1089 | static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs, | |
1090 | uint32_t bofs, uint32_t oprsz, | |
1091 | uint32_t tysz, TCGType type, bool load_dest, | |
1092 | void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec)) | |
1093 | { | |
1094 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
1095 | TCGv_vec t1 = tcg_temp_new_vec(type); | |
1096 | TCGv_vec t2 = tcg_temp_new_vec(type); | |
1097 | uint32_t i; | |
1098 | ||
1099 | for (i = 0; i < oprsz; i += tysz) { | |
1100 | tcg_gen_ld_vec(t0, cpu_env, aofs + i); | |
1101 | tcg_gen_ld_vec(t1, cpu_env, bofs + i); | |
1102 | if (load_dest) { | |
1103 | tcg_gen_ld_vec(t2, cpu_env, dofs + i); | |
1104 | } | |
1105 | fni(vece, t2, t0, t1); | |
1106 | tcg_gen_st_vec(t2, cpu_env, dofs + i); | |
1107 | } | |
1108 | tcg_temp_free_vec(t2); | |
1109 | tcg_temp_free_vec(t1); | |
1110 | tcg_temp_free_vec(t0); | |
1111 | } | |
1112 | ||
e1227bb6 DH |
1113 | /* |
1114 | * Expand OPSZ bytes worth of three-vector operands and an immediate operand | |
1115 | * using host vectors. | |
1116 | */ | |
1117 | static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, | |
1118 | uint32_t bofs, uint32_t oprsz, uint32_t tysz, | |
1119 | TCGType type, int64_t c, bool load_dest, | |
1120 | void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, | |
1121 | int64_t)) | |
1122 | { | |
1123 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
1124 | TCGv_vec t1 = tcg_temp_new_vec(type); | |
1125 | TCGv_vec t2 = tcg_temp_new_vec(type); | |
1126 | uint32_t i; | |
1127 | ||
1128 | for (i = 0; i < oprsz; i += tysz) { | |
1129 | tcg_gen_ld_vec(t0, cpu_env, aofs + i); | |
1130 | tcg_gen_ld_vec(t1, cpu_env, bofs + i); | |
1131 | if (load_dest) { | |
1132 | tcg_gen_ld_vec(t2, cpu_env, dofs + i); | |
1133 | } | |
1134 | fni(vece, t2, t0, t1, c); | |
1135 | tcg_gen_st_vec(t2, cpu_env, dofs + i); | |
1136 | } | |
1137 | tcg_temp_free_vec(t0); | |
1138 | tcg_temp_free_vec(t1); | |
1139 | tcg_temp_free_vec(t2); | |
1140 | } | |
1141 | ||
db432672 RH |
1142 | /* Expand OPSZ bytes worth of four-operand operations using host vectors. */ |
1143 | static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs, | |
1144 | uint32_t bofs, uint32_t cofs, uint32_t oprsz, | |
5d6acdd4 | 1145 | uint32_t tysz, TCGType type, bool write_aofs, |
db432672 RH |
1146 | void (*fni)(unsigned, TCGv_vec, TCGv_vec, |
1147 | TCGv_vec, TCGv_vec)) | |
1148 | { | |
1149 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
1150 | TCGv_vec t1 = tcg_temp_new_vec(type); | |
1151 | TCGv_vec t2 = tcg_temp_new_vec(type); | |
1152 | TCGv_vec t3 = tcg_temp_new_vec(type); | |
1153 | uint32_t i; | |
1154 | ||
1155 | for (i = 0; i < oprsz; i += tysz) { | |
1156 | tcg_gen_ld_vec(t1, cpu_env, aofs + i); | |
1157 | tcg_gen_ld_vec(t2, cpu_env, bofs + i); | |
1158 | tcg_gen_ld_vec(t3, cpu_env, cofs + i); | |
1159 | fni(vece, t0, t1, t2, t3); | |
1160 | tcg_gen_st_vec(t0, cpu_env, dofs + i); | |
5d6acdd4 RH |
1161 | if (write_aofs) { |
1162 | tcg_gen_st_vec(t1, cpu_env, aofs + i); | |
1163 | } | |
db432672 RH |
1164 | } |
1165 | tcg_temp_free_vec(t3); | |
1166 | tcg_temp_free_vec(t2); | |
1167 | tcg_temp_free_vec(t1); | |
1168 | tcg_temp_free_vec(t0); | |
1169 | } | |
1170 | ||
9620ae01 MF |
1171 | /* |
1172 | * Expand OPSZ bytes worth of four-vector operands and an immediate operand | |
1173 | * using host vectors. | |
1174 | */ | |
1175 | static void expand_4i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, | |
1176 | uint32_t bofs, uint32_t cofs, uint32_t oprsz, | |
1177 | uint32_t tysz, TCGType type, int64_t c, | |
1178 | void (*fni)(unsigned, TCGv_vec, TCGv_vec, | |
1179 | TCGv_vec, TCGv_vec, int64_t)) | |
1180 | { | |
1181 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
1182 | TCGv_vec t1 = tcg_temp_new_vec(type); | |
1183 | TCGv_vec t2 = tcg_temp_new_vec(type); | |
1184 | TCGv_vec t3 = tcg_temp_new_vec(type); | |
1185 | uint32_t i; | |
1186 | ||
1187 | for (i = 0; i < oprsz; i += tysz) { | |
1188 | tcg_gen_ld_vec(t1, cpu_env, aofs + i); | |
1189 | tcg_gen_ld_vec(t2, cpu_env, bofs + i); | |
1190 | tcg_gen_ld_vec(t3, cpu_env, cofs + i); | |
1191 | fni(vece, t0, t1, t2, t3, c); | |
1192 | tcg_gen_st_vec(t0, cpu_env, dofs + i); | |
1193 | } | |
1194 | tcg_temp_free_vec(t3); | |
1195 | tcg_temp_free_vec(t2); | |
1196 | tcg_temp_free_vec(t1); | |
1197 | tcg_temp_free_vec(t0); | |
1198 | } | |
1199 | ||
db432672 RH |
1200 | /* Expand a vector two-operand operation. */ |
1201 | void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, | |
1202 | uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g) | |
1203 | { | |
53229a77 RH |
1204 | const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; |
1205 | const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); | |
adb196cb RH |
1206 | TCGType type; |
1207 | uint32_t some; | |
1208 | ||
db432672 RH |
1209 | check_size_align(oprsz, maxsz, dofs | aofs); |
1210 | check_overlap_2(dofs, aofs, maxsz); | |
1211 | ||
adb196cb RH |
1212 | type = 0; |
1213 | if (g->fniv) { | |
53229a77 | 1214 | type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); |
adb196cb RH |
1215 | } |
1216 | switch (type) { | |
1217 | case TCG_TYPE_V256: | |
1218 | /* Recall that ARM SVE allows vector sizes that are not a | |
1219 | * power of 2, but always a multiple of 16. The intent is | |
1220 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
1221 | */ | |
1222 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
ac09ae62 RH |
1223 | expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, |
1224 | g->load_dest, g->fniv); | |
db432672 | 1225 | if (some == oprsz) { |
adb196cb | 1226 | break; |
db432672 RH |
1227 | } |
1228 | dofs += some; | |
1229 | aofs += some; | |
1230 | oprsz -= some; | |
1231 | maxsz -= some; | |
adb196cb RH |
1232 | /* fallthru */ |
1233 | case TCG_TYPE_V128: | |
ac09ae62 RH |
1234 | expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, |
1235 | g->load_dest, g->fniv); | |
adb196cb RH |
1236 | break; |
1237 | case TCG_TYPE_V64: | |
ac09ae62 RH |
1238 | expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, |
1239 | g->load_dest, g->fniv); | |
adb196cb RH |
1240 | break; |
1241 | ||
1242 | case 0: | |
1243 | if (g->fni8 && check_size_impl(oprsz, 8)) { | |
ac09ae62 | 1244 | expand_2_i64(dofs, aofs, oprsz, g->load_dest, g->fni8); |
adb196cb | 1245 | } else if (g->fni4 && check_size_impl(oprsz, 4)) { |
ac09ae62 | 1246 | expand_2_i32(dofs, aofs, oprsz, g->load_dest, g->fni4); |
adb196cb RH |
1247 | } else { |
1248 | assert(g->fno != NULL); | |
1249 | tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno); | |
53229a77 | 1250 | oprsz = maxsz; |
adb196cb RH |
1251 | } |
1252 | break; | |
1253 | ||
1254 | default: | |
1255 | g_assert_not_reached(); | |
db432672 | 1256 | } |
53229a77 | 1257 | tcg_swap_vecop_list(hold_list); |
db432672 | 1258 | |
db432672 RH |
1259 | if (oprsz < maxsz) { |
1260 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1261 | } | |
1262 | } | |
1263 | ||
22fc3527 | 1264 | /* Expand a vector operation with two vectors and an immediate. */ |
d0ec9796 RH |
1265 | void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, |
1266 | uint32_t maxsz, int64_t c, const GVecGen2i *g) | |
1267 | { | |
53229a77 RH |
1268 | const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; |
1269 | const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); | |
adb196cb RH |
1270 | TCGType type; |
1271 | uint32_t some; | |
1272 | ||
d0ec9796 RH |
1273 | check_size_align(oprsz, maxsz, dofs | aofs); |
1274 | check_overlap_2(dofs, aofs, maxsz); | |
1275 | ||
adb196cb RH |
1276 | type = 0; |
1277 | if (g->fniv) { | |
53229a77 | 1278 | type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); |
adb196cb RH |
1279 | } |
1280 | switch (type) { | |
1281 | case TCG_TYPE_V256: | |
1282 | /* Recall that ARM SVE allows vector sizes that are not a | |
1283 | * power of 2, but always a multiple of 16. The intent is | |
1284 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
1285 | */ | |
1286 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
d0ec9796 RH |
1287 | expand_2i_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, |
1288 | c, g->load_dest, g->fniv); | |
1289 | if (some == oprsz) { | |
adb196cb | 1290 | break; |
d0ec9796 RH |
1291 | } |
1292 | dofs += some; | |
1293 | aofs += some; | |
1294 | oprsz -= some; | |
1295 | maxsz -= some; | |
adb196cb RH |
1296 | /* fallthru */ |
1297 | case TCG_TYPE_V128: | |
d0ec9796 RH |
1298 | expand_2i_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, |
1299 | c, g->load_dest, g->fniv); | |
adb196cb RH |
1300 | break; |
1301 | case TCG_TYPE_V64: | |
d0ec9796 RH |
1302 | expand_2i_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, |
1303 | c, g->load_dest, g->fniv); | |
adb196cb RH |
1304 | break; |
1305 | ||
1306 | case 0: | |
1307 | if (g->fni8 && check_size_impl(oprsz, 8)) { | |
1308 | expand_2i_i64(dofs, aofs, oprsz, c, g->load_dest, g->fni8); | |
1309 | } else if (g->fni4 && check_size_impl(oprsz, 4)) { | |
1310 | expand_2i_i32(dofs, aofs, oprsz, c, g->load_dest, g->fni4); | |
22fc3527 | 1311 | } else { |
adb196cb RH |
1312 | if (g->fno) { |
1313 | tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno); | |
1314 | } else { | |
88d4005b | 1315 | TCGv_i64 tcg_c = tcg_constant_i64(c); |
adb196cb RH |
1316 | tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz, |
1317 | maxsz, c, g->fnoi); | |
adb196cb | 1318 | } |
53229a77 | 1319 | oprsz = maxsz; |
22fc3527 | 1320 | } |
adb196cb RH |
1321 | break; |
1322 | ||
1323 | default: | |
1324 | g_assert_not_reached(); | |
d0ec9796 | 1325 | } |
53229a77 | 1326 | tcg_swap_vecop_list(hold_list); |
d0ec9796 | 1327 | |
d0ec9796 RH |
1328 | if (oprsz < maxsz) { |
1329 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1330 | } | |
1331 | } | |
1332 | ||
22fc3527 RH |
1333 | /* Expand a vector operation with two vectors and a scalar. */ |
1334 | void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, | |
1335 | uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g) | |
1336 | { | |
1337 | TCGType type; | |
1338 | ||
1339 | check_size_align(oprsz, maxsz, dofs | aofs); | |
1340 | check_overlap_2(dofs, aofs, maxsz); | |
1341 | ||
1342 | type = 0; | |
1343 | if (g->fniv) { | |
53229a77 | 1344 | type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); |
22fc3527 RH |
1345 | } |
1346 | if (type != 0) { | |
53229a77 RH |
1347 | const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; |
1348 | const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); | |
22fc3527 | 1349 | TCGv_vec t_vec = tcg_temp_new_vec(type); |
adb196cb | 1350 | uint32_t some; |
22fc3527 RH |
1351 | |
1352 | tcg_gen_dup_i64_vec(g->vece, t_vec, c); | |
1353 | ||
22fc3527 RH |
1354 | switch (type) { |
1355 | case TCG_TYPE_V256: | |
adb196cb RH |
1356 | /* Recall that ARM SVE allows vector sizes that are not a |
1357 | * power of 2, but always a multiple of 16. The intent is | |
1358 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
1359 | */ | |
1360 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
1361 | expand_2s_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, | |
1362 | t_vec, g->scalar_first, g->fniv); | |
1363 | if (some == oprsz) { | |
1364 | break; | |
22fc3527 | 1365 | } |
adb196cb RH |
1366 | dofs += some; |
1367 | aofs += some; | |
1368 | oprsz -= some; | |
1369 | maxsz -= some; | |
22fc3527 RH |
1370 | /* fallthru */ |
1371 | ||
1372 | case TCG_TYPE_V128: | |
1373 | expand_2s_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, | |
1374 | t_vec, g->scalar_first, g->fniv); | |
1375 | break; | |
1376 | ||
1377 | case TCG_TYPE_V64: | |
1378 | expand_2s_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, | |
1379 | t_vec, g->scalar_first, g->fniv); | |
1380 | break; | |
1381 | ||
1382 | default: | |
1383 | g_assert_not_reached(); | |
1384 | } | |
1385 | tcg_temp_free_vec(t_vec); | |
53229a77 | 1386 | tcg_swap_vecop_list(hold_list); |
22fc3527 RH |
1387 | } else if (g->fni8 && check_size_impl(oprsz, 8)) { |
1388 | TCGv_i64 t64 = tcg_temp_new_i64(); | |
1389 | ||
614dd4f3 | 1390 | tcg_gen_dup_i64(g->vece, t64, c); |
22fc3527 RH |
1391 | expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8); |
1392 | tcg_temp_free_i64(t64); | |
1393 | } else if (g->fni4 && check_size_impl(oprsz, 4)) { | |
1394 | TCGv_i32 t32 = tcg_temp_new_i32(); | |
1395 | ||
1396 | tcg_gen_extrl_i64_i32(t32, c); | |
614dd4f3 | 1397 | tcg_gen_dup_i32(g->vece, t32, t32); |
22fc3527 RH |
1398 | expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4); |
1399 | tcg_temp_free_i32(t32); | |
1400 | } else { | |
1401 | tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, 0, g->fno); | |
1402 | return; | |
1403 | } | |
1404 | ||
1405 | if (oprsz < maxsz) { | |
1406 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1407 | } | |
1408 | } | |
1409 | ||
db432672 RH |
1410 | /* Expand a vector three-operand operation. */ |
1411 | void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
1412 | uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g) | |
1413 | { | |
53229a77 RH |
1414 | const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; |
1415 | const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); | |
adb196cb RH |
1416 | TCGType type; |
1417 | uint32_t some; | |
1418 | ||
db432672 RH |
1419 | check_size_align(oprsz, maxsz, dofs | aofs | bofs); |
1420 | check_overlap_3(dofs, aofs, bofs, maxsz); | |
1421 | ||
adb196cb RH |
1422 | type = 0; |
1423 | if (g->fniv) { | |
53229a77 | 1424 | type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); |
adb196cb RH |
1425 | } |
1426 | switch (type) { | |
1427 | case TCG_TYPE_V256: | |
1428 | /* Recall that ARM SVE allows vector sizes that are not a | |
1429 | * power of 2, but always a multiple of 16. The intent is | |
1430 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
1431 | */ | |
1432 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
db432672 RH |
1433 | expand_3_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, |
1434 | g->load_dest, g->fniv); | |
1435 | if (some == oprsz) { | |
adb196cb | 1436 | break; |
db432672 RH |
1437 | } |
1438 | dofs += some; | |
1439 | aofs += some; | |
1440 | bofs += some; | |
1441 | oprsz -= some; | |
1442 | maxsz -= some; | |
adb196cb RH |
1443 | /* fallthru */ |
1444 | case TCG_TYPE_V128: | |
db432672 RH |
1445 | expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, |
1446 | g->load_dest, g->fniv); | |
adb196cb RH |
1447 | break; |
1448 | case TCG_TYPE_V64: | |
db432672 RH |
1449 | expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, |
1450 | g->load_dest, g->fniv); | |
adb196cb RH |
1451 | break; |
1452 | ||
1453 | case 0: | |
1454 | if (g->fni8 && check_size_impl(oprsz, 8)) { | |
1455 | expand_3_i64(dofs, aofs, bofs, oprsz, g->load_dest, g->fni8); | |
1456 | } else if (g->fni4 && check_size_impl(oprsz, 4)) { | |
1457 | expand_3_i32(dofs, aofs, bofs, oprsz, g->load_dest, g->fni4); | |
1458 | } else { | |
1459 | assert(g->fno != NULL); | |
1460 | tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, | |
1461 | maxsz, g->data, g->fno); | |
53229a77 | 1462 | oprsz = maxsz; |
adb196cb RH |
1463 | } |
1464 | break; | |
1465 | ||
1466 | default: | |
1467 | g_assert_not_reached(); | |
db432672 | 1468 | } |
53229a77 | 1469 | tcg_swap_vecop_list(hold_list); |
db432672 | 1470 | |
db432672 RH |
1471 | if (oprsz < maxsz) { |
1472 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1473 | } | |
1474 | } | |
1475 | ||
e1227bb6 DH |
1476 | /* Expand a vector operation with three vectors and an immediate. */ |
1477 | void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
1478 | uint32_t oprsz, uint32_t maxsz, int64_t c, | |
1479 | const GVecGen3i *g) | |
1480 | { | |
53229a77 RH |
1481 | const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; |
1482 | const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); | |
e1227bb6 DH |
1483 | TCGType type; |
1484 | uint32_t some; | |
1485 | ||
1486 | check_size_align(oprsz, maxsz, dofs | aofs | bofs); | |
1487 | check_overlap_3(dofs, aofs, bofs, maxsz); | |
1488 | ||
1489 | type = 0; | |
1490 | if (g->fniv) { | |
53229a77 | 1491 | type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); |
e1227bb6 DH |
1492 | } |
1493 | switch (type) { | |
1494 | case TCG_TYPE_V256: | |
1495 | /* | |
1496 | * Recall that ARM SVE allows vector sizes that are not a | |
1497 | * power of 2, but always a multiple of 16. The intent is | |
1498 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
1499 | */ | |
1500 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
1501 | expand_3i_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, | |
1502 | c, g->load_dest, g->fniv); | |
1503 | if (some == oprsz) { | |
1504 | break; | |
1505 | } | |
1506 | dofs += some; | |
1507 | aofs += some; | |
1508 | bofs += some; | |
1509 | oprsz -= some; | |
1510 | maxsz -= some; | |
1511 | /* fallthru */ | |
1512 | case TCG_TYPE_V128: | |
1513 | expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, | |
1514 | c, g->load_dest, g->fniv); | |
1515 | break; | |
1516 | case TCG_TYPE_V64: | |
1517 | expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, | |
1518 | c, g->load_dest, g->fniv); | |
1519 | break; | |
1520 | ||
1521 | case 0: | |
1522 | if (g->fni8 && check_size_impl(oprsz, 8)) { | |
1523 | expand_3i_i64(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni8); | |
1524 | } else if (g->fni4 && check_size_impl(oprsz, 4)) { | |
1525 | expand_3i_i32(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni4); | |
1526 | } else { | |
1527 | assert(g->fno != NULL); | |
1528 | tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno); | |
53229a77 | 1529 | oprsz = maxsz; |
e1227bb6 DH |
1530 | } |
1531 | break; | |
1532 | ||
1533 | default: | |
1534 | g_assert_not_reached(); | |
1535 | } | |
53229a77 | 1536 | tcg_swap_vecop_list(hold_list); |
e1227bb6 DH |
1537 | |
1538 | if (oprsz < maxsz) { | |
1539 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1540 | } | |
1541 | } | |
1542 | ||
db432672 RH |
1543 | /* Expand a vector four-operand operation. */ |
1544 | void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, | |
1545 | uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g) | |
1546 | { | |
53229a77 RH |
1547 | const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; |
1548 | const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); | |
adb196cb RH |
1549 | TCGType type; |
1550 | uint32_t some; | |
1551 | ||
db432672 RH |
1552 | check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs); |
1553 | check_overlap_4(dofs, aofs, bofs, cofs, maxsz); | |
1554 | ||
adb196cb RH |
1555 | type = 0; |
1556 | if (g->fniv) { | |
53229a77 | 1557 | type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); |
adb196cb RH |
1558 | } |
1559 | switch (type) { | |
1560 | case TCG_TYPE_V256: | |
1561 | /* Recall that ARM SVE allows vector sizes that are not a | |
1562 | * power of 2, but always a multiple of 16. The intent is | |
1563 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
1564 | */ | |
1565 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
db432672 | 1566 | expand_4_vec(g->vece, dofs, aofs, bofs, cofs, some, |
5d6acdd4 | 1567 | 32, TCG_TYPE_V256, g->write_aofs, g->fniv); |
db432672 | 1568 | if (some == oprsz) { |
adb196cb | 1569 | break; |
db432672 RH |
1570 | } |
1571 | dofs += some; | |
1572 | aofs += some; | |
1573 | bofs += some; | |
1574 | cofs += some; | |
1575 | oprsz -= some; | |
1576 | maxsz -= some; | |
adb196cb RH |
1577 | /* fallthru */ |
1578 | case TCG_TYPE_V128: | |
db432672 | 1579 | expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, |
5d6acdd4 | 1580 | 16, TCG_TYPE_V128, g->write_aofs, g->fniv); |
adb196cb RH |
1581 | break; |
1582 | case TCG_TYPE_V64: | |
db432672 | 1583 | expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, |
5d6acdd4 | 1584 | 8, TCG_TYPE_V64, g->write_aofs, g->fniv); |
adb196cb RH |
1585 | break; |
1586 | ||
1587 | case 0: | |
1588 | if (g->fni8 && check_size_impl(oprsz, 8)) { | |
5d6acdd4 RH |
1589 | expand_4_i64(dofs, aofs, bofs, cofs, oprsz, |
1590 | g->write_aofs, g->fni8); | |
adb196cb | 1591 | } else if (g->fni4 && check_size_impl(oprsz, 4)) { |
5d6acdd4 RH |
1592 | expand_4_i32(dofs, aofs, bofs, cofs, oprsz, |
1593 | g->write_aofs, g->fni4); | |
adb196cb RH |
1594 | } else { |
1595 | assert(g->fno != NULL); | |
1596 | tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs, | |
1597 | oprsz, maxsz, g->data, g->fno); | |
53229a77 | 1598 | oprsz = maxsz; |
adb196cb RH |
1599 | } |
1600 | break; | |
1601 | ||
1602 | default: | |
1603 | g_assert_not_reached(); | |
db432672 | 1604 | } |
53229a77 | 1605 | tcg_swap_vecop_list(hold_list); |
db432672 | 1606 | |
db432672 RH |
1607 | if (oprsz < maxsz) { |
1608 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1609 | } | |
1610 | } | |
1611 | ||
9620ae01 MF |
1612 | /* Expand a vector four-operand operation. */ |
1613 | void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, | |
1614 | uint32_t oprsz, uint32_t maxsz, int64_t c, | |
1615 | const GVecGen4i *g) | |
1616 | { | |
1617 | const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; | |
1618 | const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); | |
1619 | TCGType type; | |
1620 | uint32_t some; | |
1621 | ||
1622 | check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs); | |
1623 | check_overlap_4(dofs, aofs, bofs, cofs, maxsz); | |
1624 | ||
1625 | type = 0; | |
1626 | if (g->fniv) { | |
1627 | type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); | |
1628 | } | |
1629 | switch (type) { | |
1630 | case TCG_TYPE_V256: | |
1631 | /* | |
1632 | * Recall that ARM SVE allows vector sizes that are not a | |
1633 | * power of 2, but always a multiple of 16. The intent is | |
1634 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
1635 | */ | |
1636 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
1637 | expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, some, | |
1638 | 32, TCG_TYPE_V256, c, g->fniv); | |
1639 | if (some == oprsz) { | |
1640 | break; | |
1641 | } | |
1642 | dofs += some; | |
1643 | aofs += some; | |
1644 | bofs += some; | |
1645 | cofs += some; | |
1646 | oprsz -= some; | |
1647 | maxsz -= some; | |
1648 | /* fallthru */ | |
1649 | case TCG_TYPE_V128: | |
1650 | expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, | |
1651 | 16, TCG_TYPE_V128, c, g->fniv); | |
1652 | break; | |
1653 | case TCG_TYPE_V64: | |
1654 | expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, | |
1655 | 8, TCG_TYPE_V64, c, g->fniv); | |
1656 | break; | |
1657 | ||
1658 | case 0: | |
1659 | if (g->fni8 && check_size_impl(oprsz, 8)) { | |
1660 | expand_4i_i64(dofs, aofs, bofs, cofs, oprsz, c, g->fni8); | |
1661 | } else if (g->fni4 && check_size_impl(oprsz, 4)) { | |
1662 | expand_4i_i32(dofs, aofs, bofs, cofs, oprsz, c, g->fni4); | |
1663 | } else { | |
1664 | assert(g->fno != NULL); | |
1665 | tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs, | |
1666 | oprsz, maxsz, c, g->fno); | |
1667 | oprsz = maxsz; | |
1668 | } | |
1669 | break; | |
1670 | ||
1671 | default: | |
1672 | g_assert_not_reached(); | |
1673 | } | |
1674 | tcg_swap_vecop_list(hold_list); | |
1675 | ||
1676 | if (oprsz < maxsz) { | |
1677 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1678 | } | |
1679 | } | |
1680 | ||
db432672 RH |
1681 | /* |
1682 | * Expand specific vector operations. | |
1683 | */ | |
1684 | ||
1685 | static void vec_mov2(unsigned vece, TCGv_vec a, TCGv_vec b) | |
1686 | { | |
1687 | tcg_gen_mov_vec(a, b); | |
1688 | } | |
1689 | ||
1690 | void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs, | |
1691 | uint32_t oprsz, uint32_t maxsz) | |
1692 | { | |
1693 | static const GVecGen2 g = { | |
1694 | .fni8 = tcg_gen_mov_i64, | |
1695 | .fniv = vec_mov2, | |
1696 | .fno = gen_helper_gvec_mov, | |
1697 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1698 | }; | |
1699 | if (dofs != aofs) { | |
1700 | tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g); | |
1701 | } else { | |
1702 | check_size_align(oprsz, maxsz, dofs); | |
1703 | if (oprsz < maxsz) { | |
1704 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1705 | } | |
1706 | } | |
1707 | } | |
1708 | ||
1709 | void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz, | |
1710 | uint32_t maxsz, TCGv_i32 in) | |
1711 | { | |
1712 | check_size_align(oprsz, maxsz, dofs); | |
1713 | tcg_debug_assert(vece <= MO_32); | |
1714 | do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0); | |
1715 | } | |
1716 | ||
1717 | void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz, | |
1718 | uint32_t maxsz, TCGv_i64 in) | |
1719 | { | |
1720 | check_size_align(oprsz, maxsz, dofs); | |
1721 | tcg_debug_assert(vece <= MO_64); | |
1722 | do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0); | |
1723 | } | |
1724 | ||
1725 | void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, | |
1726 | uint32_t oprsz, uint32_t maxsz) | |
1727 | { | |
532ba368 | 1728 | check_size_align(oprsz, maxsz, dofs); |
37ee55a0 | 1729 | if (vece <= MO_64) { |
532ba368 | 1730 | TCGType type = choose_vector_type(NULL, vece, oprsz, 0); |
37ee55a0 RH |
1731 | if (type != 0) { |
1732 | TCGv_vec t_vec = tcg_temp_new_vec(type); | |
1733 | tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs); | |
1734 | do_dup_store(type, dofs, oprsz, maxsz, t_vec); | |
1735 | tcg_temp_free_vec(t_vec); | |
532ba368 | 1736 | } else if (vece <= MO_32) { |
5dd48602 | 1737 | TCGv_i32 in = tcg_temp_ebb_new_i32(); |
532ba368 RH |
1738 | switch (vece) { |
1739 | case MO_8: | |
1740 | tcg_gen_ld8u_i32(in, cpu_env, aofs); | |
1741 | break; | |
1742 | case MO_16: | |
1743 | tcg_gen_ld16u_i32(in, cpu_env, aofs); | |
1744 | break; | |
1745 | default: | |
1746 | tcg_gen_ld_i32(in, cpu_env, aofs); | |
1747 | break; | |
1748 | } | |
1749 | do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0); | |
1750 | tcg_temp_free_i32(in); | |
1751 | } else { | |
5dd48602 | 1752 | TCGv_i64 in = tcg_temp_ebb_new_i64(); |
532ba368 RH |
1753 | tcg_gen_ld_i64(in, cpu_env, aofs); |
1754 | do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0); | |
1755 | tcg_temp_free_i64(in); | |
db432672 | 1756 | } |
fe4b0b5b | 1757 | } else if (vece == 4) { |
db432672 | 1758 | /* 128-bit duplicate. */ |
db432672 RH |
1759 | int i; |
1760 | ||
db432672 RH |
1761 | tcg_debug_assert(oprsz >= 16); |
1762 | if (TCG_TARGET_HAS_v128) { | |
1763 | TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V128); | |
1764 | ||
1765 | tcg_gen_ld_vec(in, cpu_env, aofs); | |
6a176461 | 1766 | for (i = (aofs == dofs) * 16; i < oprsz; i += 16) { |
db432672 RH |
1767 | tcg_gen_st_vec(in, cpu_env, dofs + i); |
1768 | } | |
1769 | tcg_temp_free_vec(in); | |
1770 | } else { | |
5dd48602 RH |
1771 | TCGv_i64 in0 = tcg_temp_ebb_new_i64(); |
1772 | TCGv_i64 in1 = tcg_temp_ebb_new_i64(); | |
db432672 RH |
1773 | |
1774 | tcg_gen_ld_i64(in0, cpu_env, aofs); | |
1775 | tcg_gen_ld_i64(in1, cpu_env, aofs + 8); | |
6a176461 | 1776 | for (i = (aofs == dofs) * 16; i < oprsz; i += 16) { |
db432672 RH |
1777 | tcg_gen_st_i64(in0, cpu_env, dofs + i); |
1778 | tcg_gen_st_i64(in1, cpu_env, dofs + i + 8); | |
1779 | } | |
1780 | tcg_temp_free_i64(in0); | |
1781 | tcg_temp_free_i64(in1); | |
1782 | } | |
532ba368 RH |
1783 | if (oprsz < maxsz) { |
1784 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1785 | } | |
fe4b0b5b RH |
1786 | } else if (vece == 5) { |
1787 | /* 256-bit duplicate. */ | |
1788 | int i; | |
1789 | ||
1790 | tcg_debug_assert(oprsz >= 32); | |
1791 | tcg_debug_assert(oprsz % 32 == 0); | |
1792 | if (TCG_TARGET_HAS_v256) { | |
1793 | TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V256); | |
1794 | ||
1795 | tcg_gen_ld_vec(in, cpu_env, aofs); | |
1796 | for (i = (aofs == dofs) * 32; i < oprsz; i += 32) { | |
1797 | tcg_gen_st_vec(in, cpu_env, dofs + i); | |
1798 | } | |
1799 | tcg_temp_free_vec(in); | |
1800 | } else if (TCG_TARGET_HAS_v128) { | |
1801 | TCGv_vec in0 = tcg_temp_new_vec(TCG_TYPE_V128); | |
1802 | TCGv_vec in1 = tcg_temp_new_vec(TCG_TYPE_V128); | |
1803 | ||
1804 | tcg_gen_ld_vec(in0, cpu_env, aofs); | |
1805 | tcg_gen_ld_vec(in1, cpu_env, aofs + 16); | |
1806 | for (i = (aofs == dofs) * 32; i < oprsz; i += 32) { | |
1807 | tcg_gen_st_vec(in0, cpu_env, dofs + i); | |
1808 | tcg_gen_st_vec(in1, cpu_env, dofs + i + 16); | |
1809 | } | |
1810 | tcg_temp_free_vec(in0); | |
1811 | tcg_temp_free_vec(in1); | |
1812 | } else { | |
1813 | TCGv_i64 in[4]; | |
1814 | int j; | |
1815 | ||
1816 | for (j = 0; j < 4; ++j) { | |
5dd48602 | 1817 | in[j] = tcg_temp_ebb_new_i64(); |
fe4b0b5b RH |
1818 | tcg_gen_ld_i64(in[j], cpu_env, aofs + j * 8); |
1819 | } | |
1820 | for (i = (aofs == dofs) * 32; i < oprsz; i += 32) { | |
1821 | for (j = 0; j < 4; ++j) { | |
1822 | tcg_gen_st_i64(in[j], cpu_env, dofs + i + j * 8); | |
1823 | } | |
1824 | } | |
1825 | for (j = 0; j < 4; ++j) { | |
1826 | tcg_temp_free_i64(in[j]); | |
1827 | } | |
1828 | } | |
1829 | if (oprsz < maxsz) { | |
1830 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
1831 | } | |
1832 | } else { | |
1833 | g_assert_not_reached(); | |
db432672 RH |
1834 | } |
1835 | } | |
1836 | ||
44c94677 RH |
1837 | void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz, |
1838 | uint32_t maxsz, uint64_t x) | |
1839 | { | |
1840 | check_size_align(oprsz, maxsz, dofs); | |
1841 | do_dup(vece, dofs, oprsz, maxsz, NULL, NULL, x); | |
1842 | } | |
1843 | ||
db432672 RH |
1844 | void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, |
1845 | uint32_t oprsz, uint32_t maxsz) | |
1846 | { | |
1847 | static const GVecGen2 g = { | |
1848 | .fni8 = tcg_gen_not_i64, | |
1849 | .fniv = tcg_gen_not_vec, | |
1850 | .fno = gen_helper_gvec_not, | |
1851 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1852 | }; | |
1853 | tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g); | |
1854 | } | |
1855 | ||
1856 | /* Perform a vector addition using normal addition and a mask. The mask | |
1857 | should be the sign bit of each lane. This 6-operation form is more | |
1858 | efficient than separate additions when there are 4 or more lanes in | |
1859 | the 64-bit operation. */ | |
1860 | static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) | |
1861 | { | |
5dd48602 RH |
1862 | TCGv_i64 t1 = tcg_temp_ebb_new_i64(); |
1863 | TCGv_i64 t2 = tcg_temp_ebb_new_i64(); | |
1864 | TCGv_i64 t3 = tcg_temp_ebb_new_i64(); | |
db432672 RH |
1865 | |
1866 | tcg_gen_andc_i64(t1, a, m); | |
1867 | tcg_gen_andc_i64(t2, b, m); | |
1868 | tcg_gen_xor_i64(t3, a, b); | |
1869 | tcg_gen_add_i64(d, t1, t2); | |
1870 | tcg_gen_and_i64(t3, t3, m); | |
1871 | tcg_gen_xor_i64(d, d, t3); | |
1872 | ||
1873 | tcg_temp_free_i64(t1); | |
1874 | tcg_temp_free_i64(t2); | |
1875 | tcg_temp_free_i64(t3); | |
1876 | } | |
1877 | ||
1878 | void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | |
1879 | { | |
88d4005b | 1880 | TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); |
db432672 | 1881 | gen_addv_mask(d, a, b, m); |
db432672 RH |
1882 | } |
1883 | ||
448e7aa2 LZ |
1884 | void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) |
1885 | { | |
1886 | TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80)); | |
5dd48602 RH |
1887 | TCGv_i32 t1 = tcg_temp_ebb_new_i32(); |
1888 | TCGv_i32 t2 = tcg_temp_ebb_new_i32(); | |
1889 | TCGv_i32 t3 = tcg_temp_ebb_new_i32(); | |
448e7aa2 LZ |
1890 | |
1891 | tcg_gen_andc_i32(t1, a, m); | |
1892 | tcg_gen_andc_i32(t2, b, m); | |
1893 | tcg_gen_xor_i32(t3, a, b); | |
1894 | tcg_gen_add_i32(d, t1, t2); | |
1895 | tcg_gen_and_i32(t3, t3, m); | |
1896 | tcg_gen_xor_i32(d, d, t3); | |
1897 | ||
1898 | tcg_temp_free_i32(t1); | |
1899 | tcg_temp_free_i32(t2); | |
1900 | tcg_temp_free_i32(t3); | |
1901 | } | |
1902 | ||
db432672 RH |
1903 | void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) |
1904 | { | |
88d4005b | 1905 | TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); |
db432672 | 1906 | gen_addv_mask(d, a, b, m); |
db432672 RH |
1907 | } |
1908 | ||
3d066e5d LZ |
1909 | void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) |
1910 | { | |
5dd48602 RH |
1911 | TCGv_i32 t1 = tcg_temp_ebb_new_i32(); |
1912 | TCGv_i32 t2 = tcg_temp_ebb_new_i32(); | |
3d066e5d LZ |
1913 | |
1914 | tcg_gen_andi_i32(t1, a, ~0xffff); | |
1915 | tcg_gen_add_i32(t2, a, b); | |
1916 | tcg_gen_add_i32(t1, t1, b); | |
1917 | tcg_gen_deposit_i32(d, t1, t2, 0, 16); | |
1918 | ||
1919 | tcg_temp_free_i32(t1); | |
1920 | tcg_temp_free_i32(t2); | |
1921 | } | |
1922 | ||
db432672 RH |
1923 | void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) |
1924 | { | |
5dd48602 RH |
1925 | TCGv_i64 t1 = tcg_temp_ebb_new_i64(); |
1926 | TCGv_i64 t2 = tcg_temp_ebb_new_i64(); | |
db432672 RH |
1927 | |
1928 | tcg_gen_andi_i64(t1, a, ~0xffffffffull); | |
1929 | tcg_gen_add_i64(t2, a, b); | |
1930 | tcg_gen_add_i64(t1, t1, b); | |
1931 | tcg_gen_deposit_i64(d, t1, t2, 0, 32); | |
1932 | ||
1933 | tcg_temp_free_i64(t1); | |
1934 | tcg_temp_free_i64(t2); | |
1935 | } | |
1936 | ||
53229a77 RH |
1937 | static const TCGOpcode vecop_list_add[] = { INDEX_op_add_vec, 0 }; |
1938 | ||
db432672 RH |
1939 | void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, |
1940 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
1941 | { | |
1942 | static const GVecGen3 g[4] = { | |
1943 | { .fni8 = tcg_gen_vec_add8_i64, | |
1944 | .fniv = tcg_gen_add_vec, | |
1945 | .fno = gen_helper_gvec_add8, | |
53229a77 | 1946 | .opt_opc = vecop_list_add, |
db432672 RH |
1947 | .vece = MO_8 }, |
1948 | { .fni8 = tcg_gen_vec_add16_i64, | |
1949 | .fniv = tcg_gen_add_vec, | |
1950 | .fno = gen_helper_gvec_add16, | |
53229a77 | 1951 | .opt_opc = vecop_list_add, |
db432672 RH |
1952 | .vece = MO_16 }, |
1953 | { .fni4 = tcg_gen_add_i32, | |
1954 | .fniv = tcg_gen_add_vec, | |
1955 | .fno = gen_helper_gvec_add32, | |
53229a77 | 1956 | .opt_opc = vecop_list_add, |
db432672 RH |
1957 | .vece = MO_32 }, |
1958 | { .fni8 = tcg_gen_add_i64, | |
1959 | .fniv = tcg_gen_add_vec, | |
1960 | .fno = gen_helper_gvec_add64, | |
53229a77 | 1961 | .opt_opc = vecop_list_add, |
db432672 RH |
1962 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
1963 | .vece = MO_64 }, | |
1964 | }; | |
1965 | ||
1966 | tcg_debug_assert(vece <= MO_64); | |
1967 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
1968 | } | |
1969 | ||
22fc3527 RH |
1970 | void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs, |
1971 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | |
1972 | { | |
1973 | static const GVecGen2s g[4] = { | |
1974 | { .fni8 = tcg_gen_vec_add8_i64, | |
1975 | .fniv = tcg_gen_add_vec, | |
1976 | .fno = gen_helper_gvec_adds8, | |
53229a77 | 1977 | .opt_opc = vecop_list_add, |
22fc3527 RH |
1978 | .vece = MO_8 }, |
1979 | { .fni8 = tcg_gen_vec_add16_i64, | |
1980 | .fniv = tcg_gen_add_vec, | |
1981 | .fno = gen_helper_gvec_adds16, | |
53229a77 | 1982 | .opt_opc = vecop_list_add, |
22fc3527 RH |
1983 | .vece = MO_16 }, |
1984 | { .fni4 = tcg_gen_add_i32, | |
1985 | .fniv = tcg_gen_add_vec, | |
1986 | .fno = gen_helper_gvec_adds32, | |
53229a77 | 1987 | .opt_opc = vecop_list_add, |
22fc3527 RH |
1988 | .vece = MO_32 }, |
1989 | { .fni8 = tcg_gen_add_i64, | |
1990 | .fniv = tcg_gen_add_vec, | |
1991 | .fno = gen_helper_gvec_adds64, | |
53229a77 | 1992 | .opt_opc = vecop_list_add, |
22fc3527 RH |
1993 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
1994 | .vece = MO_64 }, | |
1995 | }; | |
1996 | ||
1997 | tcg_debug_assert(vece <= MO_64); | |
1998 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]); | |
1999 | } | |
2000 | ||
2001 | void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2002 | int64_t c, uint32_t oprsz, uint32_t maxsz) | |
2003 | { | |
88d4005b | 2004 | TCGv_i64 tmp = tcg_constant_i64(c); |
22fc3527 | 2005 | tcg_gen_gvec_adds(vece, dofs, aofs, tmp, oprsz, maxsz); |
22fc3527 RH |
2006 | } |
2007 | ||
53229a77 RH |
2008 | static const TCGOpcode vecop_list_sub[] = { INDEX_op_sub_vec, 0 }; |
2009 | ||
22fc3527 RH |
2010 | void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs, |
2011 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | |
2012 | { | |
2013 | static const GVecGen2s g[4] = { | |
2014 | { .fni8 = tcg_gen_vec_sub8_i64, | |
2015 | .fniv = tcg_gen_sub_vec, | |
2016 | .fno = gen_helper_gvec_subs8, | |
53229a77 | 2017 | .opt_opc = vecop_list_sub, |
22fc3527 RH |
2018 | .vece = MO_8 }, |
2019 | { .fni8 = tcg_gen_vec_sub16_i64, | |
2020 | .fniv = tcg_gen_sub_vec, | |
2021 | .fno = gen_helper_gvec_subs16, | |
53229a77 | 2022 | .opt_opc = vecop_list_sub, |
22fc3527 RH |
2023 | .vece = MO_16 }, |
2024 | { .fni4 = tcg_gen_sub_i32, | |
2025 | .fniv = tcg_gen_sub_vec, | |
2026 | .fno = gen_helper_gvec_subs32, | |
53229a77 | 2027 | .opt_opc = vecop_list_sub, |
22fc3527 RH |
2028 | .vece = MO_32 }, |
2029 | { .fni8 = tcg_gen_sub_i64, | |
2030 | .fniv = tcg_gen_sub_vec, | |
2031 | .fno = gen_helper_gvec_subs64, | |
53229a77 | 2032 | .opt_opc = vecop_list_sub, |
22fc3527 RH |
2033 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2034 | .vece = MO_64 }, | |
2035 | }; | |
2036 | ||
2037 | tcg_debug_assert(vece <= MO_64); | |
2038 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]); | |
2039 | } | |
2040 | ||
db432672 RH |
2041 | /* Perform a vector subtraction using normal subtraction and a mask. |
2042 | Compare gen_addv_mask above. */ | |
2043 | static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) | |
2044 | { | |
5dd48602 RH |
2045 | TCGv_i64 t1 = tcg_temp_ebb_new_i64(); |
2046 | TCGv_i64 t2 = tcg_temp_ebb_new_i64(); | |
2047 | TCGv_i64 t3 = tcg_temp_ebb_new_i64(); | |
db432672 RH |
2048 | |
2049 | tcg_gen_or_i64(t1, a, m); | |
2050 | tcg_gen_andc_i64(t2, b, m); | |
2051 | tcg_gen_eqv_i64(t3, a, b); | |
2052 | tcg_gen_sub_i64(d, t1, t2); | |
2053 | tcg_gen_and_i64(t3, t3, m); | |
2054 | tcg_gen_xor_i64(d, d, t3); | |
2055 | ||
2056 | tcg_temp_free_i64(t1); | |
2057 | tcg_temp_free_i64(t2); | |
2058 | tcg_temp_free_i64(t3); | |
2059 | } | |
2060 | ||
2061 | void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | |
2062 | { | |
88d4005b | 2063 | TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); |
db432672 | 2064 | gen_subv_mask(d, a, b, m); |
db432672 RH |
2065 | } |
2066 | ||
448e7aa2 LZ |
2067 | void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) |
2068 | { | |
2069 | TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80)); | |
5dd48602 RH |
2070 | TCGv_i32 t1 = tcg_temp_ebb_new_i32(); |
2071 | TCGv_i32 t2 = tcg_temp_ebb_new_i32(); | |
2072 | TCGv_i32 t3 = tcg_temp_ebb_new_i32(); | |
448e7aa2 LZ |
2073 | |
2074 | tcg_gen_or_i32(t1, a, m); | |
2075 | tcg_gen_andc_i32(t2, b, m); | |
2076 | tcg_gen_eqv_i32(t3, a, b); | |
2077 | tcg_gen_sub_i32(d, t1, t2); | |
2078 | tcg_gen_and_i32(t3, t3, m); | |
2079 | tcg_gen_xor_i32(d, d, t3); | |
2080 | ||
2081 | tcg_temp_free_i32(t1); | |
2082 | tcg_temp_free_i32(t2); | |
2083 | tcg_temp_free_i32(t3); | |
2084 | } | |
2085 | ||
db432672 RH |
2086 | void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) |
2087 | { | |
88d4005b | 2088 | TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); |
db432672 | 2089 | gen_subv_mask(d, a, b, m); |
db432672 RH |
2090 | } |
2091 | ||
3d066e5d LZ |
2092 | void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) |
2093 | { | |
5dd48602 RH |
2094 | TCGv_i32 t1 = tcg_temp_ebb_new_i32(); |
2095 | TCGv_i32 t2 = tcg_temp_ebb_new_i32(); | |
3d066e5d LZ |
2096 | |
2097 | tcg_gen_andi_i32(t1, b, ~0xffff); | |
2098 | tcg_gen_sub_i32(t2, a, b); | |
2099 | tcg_gen_sub_i32(t1, a, t1); | |
2100 | tcg_gen_deposit_i32(d, t1, t2, 0, 16); | |
2101 | ||
2102 | tcg_temp_free_i32(t1); | |
2103 | tcg_temp_free_i32(t2); | |
2104 | } | |
2105 | ||
db432672 RH |
2106 | void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) |
2107 | { | |
5dd48602 RH |
2108 | TCGv_i64 t1 = tcg_temp_ebb_new_i64(); |
2109 | TCGv_i64 t2 = tcg_temp_ebb_new_i64(); | |
db432672 RH |
2110 | |
2111 | tcg_gen_andi_i64(t1, b, ~0xffffffffull); | |
2112 | tcg_gen_sub_i64(t2, a, b); | |
2113 | tcg_gen_sub_i64(t1, a, t1); | |
2114 | tcg_gen_deposit_i64(d, t1, t2, 0, 32); | |
2115 | ||
2116 | tcg_temp_free_i64(t1); | |
2117 | tcg_temp_free_i64(t2); | |
2118 | } | |
2119 | ||
2120 | void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2121 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2122 | { | |
2123 | static const GVecGen3 g[4] = { | |
2124 | { .fni8 = tcg_gen_vec_sub8_i64, | |
2125 | .fniv = tcg_gen_sub_vec, | |
2126 | .fno = gen_helper_gvec_sub8, | |
53229a77 | 2127 | .opt_opc = vecop_list_sub, |
db432672 RH |
2128 | .vece = MO_8 }, |
2129 | { .fni8 = tcg_gen_vec_sub16_i64, | |
2130 | .fniv = tcg_gen_sub_vec, | |
2131 | .fno = gen_helper_gvec_sub16, | |
53229a77 | 2132 | .opt_opc = vecop_list_sub, |
db432672 RH |
2133 | .vece = MO_16 }, |
2134 | { .fni4 = tcg_gen_sub_i32, | |
2135 | .fniv = tcg_gen_sub_vec, | |
2136 | .fno = gen_helper_gvec_sub32, | |
53229a77 | 2137 | .opt_opc = vecop_list_sub, |
db432672 RH |
2138 | .vece = MO_32 }, |
2139 | { .fni8 = tcg_gen_sub_i64, | |
2140 | .fniv = tcg_gen_sub_vec, | |
2141 | .fno = gen_helper_gvec_sub64, | |
53229a77 | 2142 | .opt_opc = vecop_list_sub, |
db432672 RH |
2143 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2144 | .vece = MO_64 }, | |
2145 | }; | |
2146 | ||
2147 | tcg_debug_assert(vece <= MO_64); | |
2148 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
2149 | } | |
2150 | ||
53229a77 RH |
2151 | static const TCGOpcode vecop_list_mul[] = { INDEX_op_mul_vec, 0 }; |
2152 | ||
3774030a RH |
2153 | void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, |
2154 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2155 | { | |
2156 | static const GVecGen3 g[4] = { | |
2157 | { .fniv = tcg_gen_mul_vec, | |
2158 | .fno = gen_helper_gvec_mul8, | |
53229a77 | 2159 | .opt_opc = vecop_list_mul, |
3774030a RH |
2160 | .vece = MO_8 }, |
2161 | { .fniv = tcg_gen_mul_vec, | |
2162 | .fno = gen_helper_gvec_mul16, | |
53229a77 | 2163 | .opt_opc = vecop_list_mul, |
3774030a RH |
2164 | .vece = MO_16 }, |
2165 | { .fni4 = tcg_gen_mul_i32, | |
2166 | .fniv = tcg_gen_mul_vec, | |
2167 | .fno = gen_helper_gvec_mul32, | |
53229a77 | 2168 | .opt_opc = vecop_list_mul, |
3774030a RH |
2169 | .vece = MO_32 }, |
2170 | { .fni8 = tcg_gen_mul_i64, | |
2171 | .fniv = tcg_gen_mul_vec, | |
2172 | .fno = gen_helper_gvec_mul64, | |
53229a77 | 2173 | .opt_opc = vecop_list_mul, |
3774030a RH |
2174 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2175 | .vece = MO_64 }, | |
2176 | }; | |
2177 | ||
2178 | tcg_debug_assert(vece <= MO_64); | |
2179 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
2180 | } | |
2181 | ||
22fc3527 RH |
2182 | void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, |
2183 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | |
2184 | { | |
2185 | static const GVecGen2s g[4] = { | |
2186 | { .fniv = tcg_gen_mul_vec, | |
2187 | .fno = gen_helper_gvec_muls8, | |
53229a77 | 2188 | .opt_opc = vecop_list_mul, |
22fc3527 RH |
2189 | .vece = MO_8 }, |
2190 | { .fniv = tcg_gen_mul_vec, | |
2191 | .fno = gen_helper_gvec_muls16, | |
53229a77 | 2192 | .opt_opc = vecop_list_mul, |
22fc3527 RH |
2193 | .vece = MO_16 }, |
2194 | { .fni4 = tcg_gen_mul_i32, | |
2195 | .fniv = tcg_gen_mul_vec, | |
2196 | .fno = gen_helper_gvec_muls32, | |
53229a77 | 2197 | .opt_opc = vecop_list_mul, |
22fc3527 RH |
2198 | .vece = MO_32 }, |
2199 | { .fni8 = tcg_gen_mul_i64, | |
2200 | .fniv = tcg_gen_mul_vec, | |
2201 | .fno = gen_helper_gvec_muls64, | |
53229a77 | 2202 | .opt_opc = vecop_list_mul, |
22fc3527 RH |
2203 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2204 | .vece = MO_64 }, | |
2205 | }; | |
2206 | ||
2207 | tcg_debug_assert(vece <= MO_64); | |
2208 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]); | |
2209 | } | |
2210 | ||
2211 | void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2212 | int64_t c, uint32_t oprsz, uint32_t maxsz) | |
2213 | { | |
88d4005b | 2214 | TCGv_i64 tmp = tcg_constant_i64(c); |
22fc3527 | 2215 | tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz); |
22fc3527 RH |
2216 | } |
2217 | ||
f49b12c6 RH |
2218 | void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, |
2219 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2220 | { | |
53229a77 | 2221 | static const TCGOpcode vecop_list[] = { INDEX_op_ssadd_vec, 0 }; |
f49b12c6 | 2222 | static const GVecGen3 g[4] = { |
8afaf050 RH |
2223 | { .fniv = tcg_gen_ssadd_vec, |
2224 | .fno = gen_helper_gvec_ssadd8, | |
53229a77 | 2225 | .opt_opc = vecop_list, |
8afaf050 RH |
2226 | .vece = MO_8 }, |
2227 | { .fniv = tcg_gen_ssadd_vec, | |
2228 | .fno = gen_helper_gvec_ssadd16, | |
53229a77 | 2229 | .opt_opc = vecop_list, |
8afaf050 RH |
2230 | .vece = MO_16 }, |
2231 | { .fniv = tcg_gen_ssadd_vec, | |
2232 | .fno = gen_helper_gvec_ssadd32, | |
53229a77 | 2233 | .opt_opc = vecop_list, |
8afaf050 RH |
2234 | .vece = MO_32 }, |
2235 | { .fniv = tcg_gen_ssadd_vec, | |
2236 | .fno = gen_helper_gvec_ssadd64, | |
53229a77 | 2237 | .opt_opc = vecop_list, |
8afaf050 | 2238 | .vece = MO_64 }, |
f49b12c6 RH |
2239 | }; |
2240 | tcg_debug_assert(vece <= MO_64); | |
2241 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
2242 | } | |
2243 | ||
2244 | void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2245 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2246 | { | |
53229a77 | 2247 | static const TCGOpcode vecop_list[] = { INDEX_op_sssub_vec, 0 }; |
f49b12c6 | 2248 | static const GVecGen3 g[4] = { |
8afaf050 RH |
2249 | { .fniv = tcg_gen_sssub_vec, |
2250 | .fno = gen_helper_gvec_sssub8, | |
53229a77 | 2251 | .opt_opc = vecop_list, |
8afaf050 RH |
2252 | .vece = MO_8 }, |
2253 | { .fniv = tcg_gen_sssub_vec, | |
2254 | .fno = gen_helper_gvec_sssub16, | |
53229a77 | 2255 | .opt_opc = vecop_list, |
8afaf050 RH |
2256 | .vece = MO_16 }, |
2257 | { .fniv = tcg_gen_sssub_vec, | |
2258 | .fno = gen_helper_gvec_sssub32, | |
53229a77 | 2259 | .opt_opc = vecop_list, |
8afaf050 RH |
2260 | .vece = MO_32 }, |
2261 | { .fniv = tcg_gen_sssub_vec, | |
2262 | .fno = gen_helper_gvec_sssub64, | |
53229a77 | 2263 | .opt_opc = vecop_list, |
8afaf050 | 2264 | .vece = MO_64 }, |
f49b12c6 RH |
2265 | }; |
2266 | tcg_debug_assert(vece <= MO_64); | |
2267 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
2268 | } | |
2269 | ||
8afaf050 | 2270 | static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) |
f49b12c6 | 2271 | { |
88d4005b | 2272 | TCGv_i32 max = tcg_constant_i32(-1); |
f49b12c6 RH |
2273 | tcg_gen_add_i32(d, a, b); |
2274 | tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d); | |
f49b12c6 RH |
2275 | } |
2276 | ||
8afaf050 | 2277 | static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) |
f49b12c6 | 2278 | { |
88d4005b | 2279 | TCGv_i64 max = tcg_constant_i64(-1); |
f49b12c6 RH |
2280 | tcg_gen_add_i64(d, a, b); |
2281 | tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d); | |
f49b12c6 RH |
2282 | } |
2283 | ||
2284 | void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2285 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2286 | { | |
53229a77 | 2287 | static const TCGOpcode vecop_list[] = { INDEX_op_usadd_vec, 0 }; |
f49b12c6 | 2288 | static const GVecGen3 g[4] = { |
8afaf050 RH |
2289 | { .fniv = tcg_gen_usadd_vec, |
2290 | .fno = gen_helper_gvec_usadd8, | |
53229a77 | 2291 | .opt_opc = vecop_list, |
8afaf050 RH |
2292 | .vece = MO_8 }, |
2293 | { .fniv = tcg_gen_usadd_vec, | |
2294 | .fno = gen_helper_gvec_usadd16, | |
53229a77 | 2295 | .opt_opc = vecop_list, |
8afaf050 RH |
2296 | .vece = MO_16 }, |
2297 | { .fni4 = tcg_gen_usadd_i32, | |
2298 | .fniv = tcg_gen_usadd_vec, | |
f49b12c6 | 2299 | .fno = gen_helper_gvec_usadd32, |
53229a77 | 2300 | .opt_opc = vecop_list, |
f49b12c6 | 2301 | .vece = MO_32 }, |
8afaf050 RH |
2302 | { .fni8 = tcg_gen_usadd_i64, |
2303 | .fniv = tcg_gen_usadd_vec, | |
f49b12c6 | 2304 | .fno = gen_helper_gvec_usadd64, |
53229a77 | 2305 | .opt_opc = vecop_list, |
f49b12c6 RH |
2306 | .vece = MO_64 } |
2307 | }; | |
2308 | tcg_debug_assert(vece <= MO_64); | |
2309 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
2310 | } | |
2311 | ||
8afaf050 | 2312 | static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) |
f49b12c6 | 2313 | { |
88d4005b | 2314 | TCGv_i32 min = tcg_constant_i32(0); |
f49b12c6 RH |
2315 | tcg_gen_sub_i32(d, a, b); |
2316 | tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); | |
f49b12c6 RH |
2317 | } |
2318 | ||
8afaf050 | 2319 | static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) |
f49b12c6 | 2320 | { |
88d4005b | 2321 | TCGv_i64 min = tcg_constant_i64(0); |
f49b12c6 RH |
2322 | tcg_gen_sub_i64(d, a, b); |
2323 | tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d); | |
f49b12c6 RH |
2324 | } |
2325 | ||
2326 | void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2327 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2328 | { | |
53229a77 | 2329 | static const TCGOpcode vecop_list[] = { INDEX_op_ussub_vec, 0 }; |
f49b12c6 | 2330 | static const GVecGen3 g[4] = { |
8afaf050 RH |
2331 | { .fniv = tcg_gen_ussub_vec, |
2332 | .fno = gen_helper_gvec_ussub8, | |
53229a77 | 2333 | .opt_opc = vecop_list, |
8afaf050 RH |
2334 | .vece = MO_8 }, |
2335 | { .fniv = tcg_gen_ussub_vec, | |
2336 | .fno = gen_helper_gvec_ussub16, | |
53229a77 | 2337 | .opt_opc = vecop_list, |
8afaf050 RH |
2338 | .vece = MO_16 }, |
2339 | { .fni4 = tcg_gen_ussub_i32, | |
2340 | .fniv = tcg_gen_ussub_vec, | |
f49b12c6 | 2341 | .fno = gen_helper_gvec_ussub32, |
53229a77 | 2342 | .opt_opc = vecop_list, |
f49b12c6 | 2343 | .vece = MO_32 }, |
8afaf050 RH |
2344 | { .fni8 = tcg_gen_ussub_i64, |
2345 | .fniv = tcg_gen_ussub_vec, | |
f49b12c6 | 2346 | .fno = gen_helper_gvec_ussub64, |
53229a77 | 2347 | .opt_opc = vecop_list, |
f49b12c6 RH |
2348 | .vece = MO_64 } |
2349 | }; | |
2350 | tcg_debug_assert(vece <= MO_64); | |
2351 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
dd0a0fcd RH |
2352 | } |
2353 | ||
2354 | void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2355 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2356 | { | |
53229a77 | 2357 | static const TCGOpcode vecop_list[] = { INDEX_op_smin_vec, 0 }; |
dd0a0fcd RH |
2358 | static const GVecGen3 g[4] = { |
2359 | { .fniv = tcg_gen_smin_vec, | |
2360 | .fno = gen_helper_gvec_smin8, | |
53229a77 | 2361 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2362 | .vece = MO_8 }, |
2363 | { .fniv = tcg_gen_smin_vec, | |
2364 | .fno = gen_helper_gvec_smin16, | |
53229a77 | 2365 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2366 | .vece = MO_16 }, |
2367 | { .fni4 = tcg_gen_smin_i32, | |
2368 | .fniv = tcg_gen_smin_vec, | |
2369 | .fno = gen_helper_gvec_smin32, | |
53229a77 | 2370 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2371 | .vece = MO_32 }, |
2372 | { .fni8 = tcg_gen_smin_i64, | |
2373 | .fniv = tcg_gen_smin_vec, | |
2374 | .fno = gen_helper_gvec_smin64, | |
53229a77 | 2375 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2376 | .vece = MO_64 } |
2377 | }; | |
2378 | tcg_debug_assert(vece <= MO_64); | |
2379 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
2380 | } | |
2381 | ||
2382 | void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2383 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2384 | { | |
53229a77 | 2385 | static const TCGOpcode vecop_list[] = { INDEX_op_umin_vec, 0 }; |
dd0a0fcd RH |
2386 | static const GVecGen3 g[4] = { |
2387 | { .fniv = tcg_gen_umin_vec, | |
2388 | .fno = gen_helper_gvec_umin8, | |
53229a77 | 2389 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2390 | .vece = MO_8 }, |
2391 | { .fniv = tcg_gen_umin_vec, | |
2392 | .fno = gen_helper_gvec_umin16, | |
53229a77 | 2393 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2394 | .vece = MO_16 }, |
2395 | { .fni4 = tcg_gen_umin_i32, | |
2396 | .fniv = tcg_gen_umin_vec, | |
2397 | .fno = gen_helper_gvec_umin32, | |
53229a77 | 2398 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2399 | .vece = MO_32 }, |
2400 | { .fni8 = tcg_gen_umin_i64, | |
2401 | .fniv = tcg_gen_umin_vec, | |
2402 | .fno = gen_helper_gvec_umin64, | |
53229a77 | 2403 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2404 | .vece = MO_64 } |
2405 | }; | |
2406 | tcg_debug_assert(vece <= MO_64); | |
2407 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
2408 | } | |
2409 | ||
2410 | void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2411 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2412 | { | |
53229a77 | 2413 | static const TCGOpcode vecop_list[] = { INDEX_op_smax_vec, 0 }; |
dd0a0fcd RH |
2414 | static const GVecGen3 g[4] = { |
2415 | { .fniv = tcg_gen_smax_vec, | |
2416 | .fno = gen_helper_gvec_smax8, | |
53229a77 | 2417 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2418 | .vece = MO_8 }, |
2419 | { .fniv = tcg_gen_smax_vec, | |
2420 | .fno = gen_helper_gvec_smax16, | |
53229a77 | 2421 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2422 | .vece = MO_16 }, |
2423 | { .fni4 = tcg_gen_smax_i32, | |
2424 | .fniv = tcg_gen_smax_vec, | |
2425 | .fno = gen_helper_gvec_smax32, | |
53229a77 | 2426 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2427 | .vece = MO_32 }, |
2428 | { .fni8 = tcg_gen_smax_i64, | |
2429 | .fniv = tcg_gen_smax_vec, | |
2430 | .fno = gen_helper_gvec_smax64, | |
53229a77 | 2431 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2432 | .vece = MO_64 } |
2433 | }; | |
2434 | tcg_debug_assert(vece <= MO_64); | |
2435 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
2436 | } | |
2437 | ||
2438 | void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2439 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2440 | { | |
53229a77 | 2441 | static const TCGOpcode vecop_list[] = { INDEX_op_umax_vec, 0 }; |
dd0a0fcd RH |
2442 | static const GVecGen3 g[4] = { |
2443 | { .fniv = tcg_gen_umax_vec, | |
2444 | .fno = gen_helper_gvec_umax8, | |
53229a77 | 2445 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2446 | .vece = MO_8 }, |
2447 | { .fniv = tcg_gen_umax_vec, | |
2448 | .fno = gen_helper_gvec_umax16, | |
53229a77 | 2449 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2450 | .vece = MO_16 }, |
2451 | { .fni4 = tcg_gen_umax_i32, | |
2452 | .fniv = tcg_gen_umax_vec, | |
2453 | .fno = gen_helper_gvec_umax32, | |
53229a77 | 2454 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2455 | .vece = MO_32 }, |
2456 | { .fni8 = tcg_gen_umax_i64, | |
2457 | .fniv = tcg_gen_umax_vec, | |
2458 | .fno = gen_helper_gvec_umax64, | |
53229a77 | 2459 | .opt_opc = vecop_list, |
dd0a0fcd RH |
2460 | .vece = MO_64 } |
2461 | }; | |
2462 | tcg_debug_assert(vece <= MO_64); | |
2463 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
f49b12c6 RH |
2464 | } |
2465 | ||
db432672 RH |
2466 | /* Perform a vector negation using normal negation and a mask. |
2467 | Compare gen_subv_mask above. */ | |
2468 | static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m) | |
2469 | { | |
5dd48602 RH |
2470 | TCGv_i64 t2 = tcg_temp_ebb_new_i64(); |
2471 | TCGv_i64 t3 = tcg_temp_ebb_new_i64(); | |
db432672 RH |
2472 | |
2473 | tcg_gen_andc_i64(t3, m, b); | |
2474 | tcg_gen_andc_i64(t2, b, m); | |
2475 | tcg_gen_sub_i64(d, m, t2); | |
2476 | tcg_gen_xor_i64(d, d, t3); | |
2477 | ||
2478 | tcg_temp_free_i64(t2); | |
2479 | tcg_temp_free_i64(t3); | |
2480 | } | |
2481 | ||
2482 | void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b) | |
2483 | { | |
88d4005b | 2484 | TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); |
db432672 | 2485 | gen_negv_mask(d, b, m); |
db432672 RH |
2486 | } |
2487 | ||
2488 | void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b) | |
2489 | { | |
88d4005b | 2490 | TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); |
db432672 | 2491 | gen_negv_mask(d, b, m); |
db432672 RH |
2492 | } |
2493 | ||
2494 | void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b) | |
2495 | { | |
5dd48602 RH |
2496 | TCGv_i64 t1 = tcg_temp_ebb_new_i64(); |
2497 | TCGv_i64 t2 = tcg_temp_ebb_new_i64(); | |
db432672 RH |
2498 | |
2499 | tcg_gen_andi_i64(t1, b, ~0xffffffffull); | |
2500 | tcg_gen_neg_i64(t2, b); | |
2501 | tcg_gen_neg_i64(t1, t1); | |
2502 | tcg_gen_deposit_i64(d, t1, t2, 0, 32); | |
2503 | ||
2504 | tcg_temp_free_i64(t1); | |
2505 | tcg_temp_free_i64(t2); | |
2506 | } | |
2507 | ||
2508 | void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2509 | uint32_t oprsz, uint32_t maxsz) | |
2510 | { | |
53229a77 | 2511 | static const TCGOpcode vecop_list[] = { INDEX_op_neg_vec, 0 }; |
db432672 RH |
2512 | static const GVecGen2 g[4] = { |
2513 | { .fni8 = tcg_gen_vec_neg8_i64, | |
2514 | .fniv = tcg_gen_neg_vec, | |
2515 | .fno = gen_helper_gvec_neg8, | |
53229a77 | 2516 | .opt_opc = vecop_list, |
db432672 RH |
2517 | .vece = MO_8 }, |
2518 | { .fni8 = tcg_gen_vec_neg16_i64, | |
2519 | .fniv = tcg_gen_neg_vec, | |
2520 | .fno = gen_helper_gvec_neg16, | |
53229a77 | 2521 | .opt_opc = vecop_list, |
db432672 RH |
2522 | .vece = MO_16 }, |
2523 | { .fni4 = tcg_gen_neg_i32, | |
2524 | .fniv = tcg_gen_neg_vec, | |
2525 | .fno = gen_helper_gvec_neg32, | |
53229a77 | 2526 | .opt_opc = vecop_list, |
db432672 RH |
2527 | .vece = MO_32 }, |
2528 | { .fni8 = tcg_gen_neg_i64, | |
2529 | .fniv = tcg_gen_neg_vec, | |
2530 | .fno = gen_helper_gvec_neg64, | |
53229a77 | 2531 | .opt_opc = vecop_list, |
db432672 RH |
2532 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2533 | .vece = MO_64 }, | |
2534 | }; | |
2535 | ||
2536 | tcg_debug_assert(vece <= MO_64); | |
2537 | tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); | |
2538 | } | |
2539 | ||
bcefc902 RH |
2540 | static void gen_absv_mask(TCGv_i64 d, TCGv_i64 b, unsigned vece) |
2541 | { | |
5dd48602 | 2542 | TCGv_i64 t = tcg_temp_ebb_new_i64(); |
bcefc902 RH |
2543 | int nbit = 8 << vece; |
2544 | ||
2545 | /* Create -1 for each negative element. */ | |
2546 | tcg_gen_shri_i64(t, b, nbit - 1); | |
2547 | tcg_gen_andi_i64(t, t, dup_const(vece, 1)); | |
2548 | tcg_gen_muli_i64(t, t, (1 << nbit) - 1); | |
2549 | ||
2550 | /* | |
e7e8f33f | 2551 | * Invert (via xor -1) and add one. |
bcefc902 RH |
2552 | * Because of the ordering the msb is cleared, |
2553 | * so we never have carry into the next element. | |
2554 | */ | |
2555 | tcg_gen_xor_i64(d, b, t); | |
e7e8f33f SL |
2556 | tcg_gen_andi_i64(t, t, dup_const(vece, 1)); |
2557 | tcg_gen_add_i64(d, d, t); | |
bcefc902 RH |
2558 | |
2559 | tcg_temp_free_i64(t); | |
2560 | } | |
2561 | ||
2562 | static void tcg_gen_vec_abs8_i64(TCGv_i64 d, TCGv_i64 b) | |
2563 | { | |
2564 | gen_absv_mask(d, b, MO_8); | |
2565 | } | |
2566 | ||
2567 | static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i64 b) | |
2568 | { | |
2569 | gen_absv_mask(d, b, MO_16); | |
2570 | } | |
2571 | ||
2572 | void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2573 | uint32_t oprsz, uint32_t maxsz) | |
2574 | { | |
2575 | static const TCGOpcode vecop_list[] = { INDEX_op_abs_vec, 0 }; | |
2576 | static const GVecGen2 g[4] = { | |
2577 | { .fni8 = tcg_gen_vec_abs8_i64, | |
2578 | .fniv = tcg_gen_abs_vec, | |
2579 | .fno = gen_helper_gvec_abs8, | |
2580 | .opt_opc = vecop_list, | |
2581 | .vece = MO_8 }, | |
2582 | { .fni8 = tcg_gen_vec_abs16_i64, | |
2583 | .fniv = tcg_gen_abs_vec, | |
2584 | .fno = gen_helper_gvec_abs16, | |
2585 | .opt_opc = vecop_list, | |
2586 | .vece = MO_16 }, | |
2587 | { .fni4 = tcg_gen_abs_i32, | |
2588 | .fniv = tcg_gen_abs_vec, | |
2589 | .fno = gen_helper_gvec_abs32, | |
2590 | .opt_opc = vecop_list, | |
2591 | .vece = MO_32 }, | |
2592 | { .fni8 = tcg_gen_abs_i64, | |
2593 | .fniv = tcg_gen_abs_vec, | |
2594 | .fno = gen_helper_gvec_abs64, | |
2595 | .opt_opc = vecop_list, | |
2596 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
2597 | .vece = MO_64 }, | |
2598 | }; | |
2599 | ||
2600 | tcg_debug_assert(vece <= MO_64); | |
2601 | tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); | |
2602 | } | |
2603 | ||
db432672 RH |
2604 | void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, |
2605 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2606 | { | |
2607 | static const GVecGen3 g = { | |
2608 | .fni8 = tcg_gen_and_i64, | |
2609 | .fniv = tcg_gen_and_vec, | |
2610 | .fno = gen_helper_gvec_and, | |
db432672 RH |
2611 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2612 | }; | |
9a9eda78 RH |
2613 | |
2614 | if (aofs == bofs) { | |
2615 | tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); | |
2616 | } else { | |
2617 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); | |
2618 | } | |
db432672 RH |
2619 | } |
2620 | ||
2621 | void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2622 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2623 | { | |
2624 | static const GVecGen3 g = { | |
2625 | .fni8 = tcg_gen_or_i64, | |
2626 | .fniv = tcg_gen_or_vec, | |
2627 | .fno = gen_helper_gvec_or, | |
db432672 RH |
2628 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2629 | }; | |
9a9eda78 RH |
2630 | |
2631 | if (aofs == bofs) { | |
2632 | tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); | |
2633 | } else { | |
2634 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); | |
2635 | } | |
db432672 RH |
2636 | } |
2637 | ||
2638 | void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2639 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2640 | { | |
2641 | static const GVecGen3 g = { | |
2642 | .fni8 = tcg_gen_xor_i64, | |
2643 | .fniv = tcg_gen_xor_vec, | |
2644 | .fno = gen_helper_gvec_xor, | |
db432672 RH |
2645 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2646 | }; | |
9a9eda78 RH |
2647 | |
2648 | if (aofs == bofs) { | |
03ddb6f3 | 2649 | tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); |
9a9eda78 RH |
2650 | } else { |
2651 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); | |
2652 | } | |
db432672 RH |
2653 | } |
2654 | ||
2655 | void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2656 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2657 | { | |
2658 | static const GVecGen3 g = { | |
2659 | .fni8 = tcg_gen_andc_i64, | |
2660 | .fniv = tcg_gen_andc_vec, | |
2661 | .fno = gen_helper_gvec_andc, | |
db432672 RH |
2662 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2663 | }; | |
9a9eda78 RH |
2664 | |
2665 | if (aofs == bofs) { | |
03ddb6f3 | 2666 | tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); |
9a9eda78 RH |
2667 | } else { |
2668 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); | |
2669 | } | |
db432672 RH |
2670 | } |
2671 | ||
2672 | void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2673 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2674 | { | |
2675 | static const GVecGen3 g = { | |
2676 | .fni8 = tcg_gen_orc_i64, | |
2677 | .fniv = tcg_gen_orc_vec, | |
2678 | .fno = gen_helper_gvec_orc, | |
db432672 RH |
2679 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2680 | }; | |
9a9eda78 RH |
2681 | |
2682 | if (aofs == bofs) { | |
03ddb6f3 | 2683 | tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1); |
9a9eda78 | 2684 | } else { |
f550805d RH |
2685 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); |
2686 | } | |
2687 | } | |
2688 | ||
2689 | void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2690 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2691 | { | |
2692 | static const GVecGen3 g = { | |
2693 | .fni8 = tcg_gen_nand_i64, | |
2694 | .fniv = tcg_gen_nand_vec, | |
2695 | .fno = gen_helper_gvec_nand, | |
2696 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
2697 | }; | |
2698 | ||
2699 | if (aofs == bofs) { | |
2700 | tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz); | |
2701 | } else { | |
2702 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); | |
2703 | } | |
2704 | } | |
2705 | ||
2706 | void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2707 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2708 | { | |
2709 | static const GVecGen3 g = { | |
2710 | .fni8 = tcg_gen_nor_i64, | |
2711 | .fniv = tcg_gen_nor_vec, | |
2712 | .fno = gen_helper_gvec_nor, | |
2713 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
2714 | }; | |
2715 | ||
2716 | if (aofs == bofs) { | |
2717 | tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz); | |
2718 | } else { | |
2719 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); | |
2720 | } | |
2721 | } | |
2722 | ||
2723 | void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2724 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
2725 | { | |
2726 | static const GVecGen3 g = { | |
2727 | .fni8 = tcg_gen_eqv_i64, | |
2728 | .fniv = tcg_gen_eqv_vec, | |
2729 | .fno = gen_helper_gvec_eqv, | |
2730 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
2731 | }; | |
2732 | ||
2733 | if (aofs == bofs) { | |
03ddb6f3 | 2734 | tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1); |
f550805d | 2735 | } else { |
9a9eda78 RH |
2736 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); |
2737 | } | |
db432672 | 2738 | } |
d0ec9796 | 2739 | |
22fc3527 RH |
2740 | static const GVecGen2s gop_ands = { |
2741 | .fni8 = tcg_gen_and_i64, | |
2742 | .fniv = tcg_gen_and_vec, | |
2743 | .fno = gen_helper_gvec_ands, | |
22fc3527 RH |
2744 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2745 | .vece = MO_64 | |
2746 | }; | |
2747 | ||
2748 | void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2749 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | |
2750 | { | |
5dd48602 | 2751 | TCGv_i64 tmp = tcg_temp_ebb_new_i64(); |
614dd4f3 | 2752 | tcg_gen_dup_i64(vece, tmp, c); |
22fc3527 RH |
2753 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); |
2754 | tcg_temp_free_i64(tmp); | |
2755 | } | |
2756 | ||
2757 | void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2758 | int64_t c, uint32_t oprsz, uint32_t maxsz) | |
2759 | { | |
88d4005b | 2760 | TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); |
22fc3527 | 2761 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); |
22fc3527 RH |
2762 | } |
2763 | ||
4221aa4a NK |
2764 | void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, |
2765 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | |
2766 | { | |
2767 | static GVecGen2s g = { | |
2768 | .fni8 = tcg_gen_andc_i64, | |
2769 | .fniv = tcg_gen_andc_vec, | |
2770 | .fno = gen_helper_gvec_andcs, | |
2771 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
2772 | .vece = MO_64 | |
2773 | }; | |
2774 | ||
2775 | TCGv_i64 tmp = tcg_temp_ebb_new_i64(); | |
2776 | tcg_gen_dup_i64(vece, tmp, c); | |
70bfde9a | 2777 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &g); |
4221aa4a NK |
2778 | tcg_temp_free_i64(tmp); |
2779 | } | |
2780 | ||
22fc3527 RH |
2781 | static const GVecGen2s gop_xors = { |
2782 | .fni8 = tcg_gen_xor_i64, | |
2783 | .fniv = tcg_gen_xor_vec, | |
2784 | .fno = gen_helper_gvec_xors, | |
22fc3527 RH |
2785 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2786 | .vece = MO_64 | |
2787 | }; | |
2788 | ||
2789 | void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2790 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | |
2791 | { | |
5dd48602 | 2792 | TCGv_i64 tmp = tcg_temp_ebb_new_i64(); |
614dd4f3 | 2793 | tcg_gen_dup_i64(vece, tmp, c); |
22fc3527 RH |
2794 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors); |
2795 | tcg_temp_free_i64(tmp); | |
2796 | } | |
2797 | ||
2798 | void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2799 | int64_t c, uint32_t oprsz, uint32_t maxsz) | |
2800 | { | |
88d4005b | 2801 | TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); |
22fc3527 | 2802 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors); |
22fc3527 RH |
2803 | } |
2804 | ||
2805 | static const GVecGen2s gop_ors = { | |
2806 | .fni8 = tcg_gen_or_i64, | |
2807 | .fniv = tcg_gen_or_vec, | |
2808 | .fno = gen_helper_gvec_ors, | |
22fc3527 RH |
2809 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2810 | .vece = MO_64 | |
2811 | }; | |
2812 | ||
2813 | void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2814 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | |
2815 | { | |
5dd48602 | 2816 | TCGv_i64 tmp = tcg_temp_ebb_new_i64(); |
614dd4f3 | 2817 | tcg_gen_dup_i64(vece, tmp, c); |
22fc3527 RH |
2818 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors); |
2819 | tcg_temp_free_i64(tmp); | |
2820 | } | |
2821 | ||
2822 | void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, | |
2823 | int64_t c, uint32_t oprsz, uint32_t maxsz) | |
2824 | { | |
88d4005b | 2825 | TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); |
22fc3527 | 2826 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors); |
22fc3527 RH |
2827 | } |
2828 | ||
d0ec9796 RH |
2829 | void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) |
2830 | { | |
2831 | uint64_t mask = dup_const(MO_8, 0xff << c); | |
2832 | tcg_gen_shli_i64(d, a, c); | |
2833 | tcg_gen_andi_i64(d, d, mask); | |
2834 | } | |
2835 | ||
2836 | void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) | |
2837 | { | |
2838 | uint64_t mask = dup_const(MO_16, 0xffff << c); | |
2839 | tcg_gen_shli_i64(d, a, c); | |
2840 | tcg_gen_andi_i64(d, d, mask); | |
2841 | } | |
2842 | ||
950ee590 LZ |
2843 | void tcg_gen_vec_shl8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) |
2844 | { | |
2845 | uint32_t mask = dup_const(MO_8, 0xff << c); | |
2846 | tcg_gen_shli_i32(d, a, c); | |
2847 | tcg_gen_andi_i32(d, d, mask); | |
2848 | } | |
2849 | ||
04f2a8bb LZ |
2850 | void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) |
2851 | { | |
2852 | uint32_t mask = dup_const(MO_16, 0xffff << c); | |
2853 | tcg_gen_shli_i32(d, a, c); | |
2854 | tcg_gen_andi_i32(d, d, mask); | |
2855 | } | |
2856 | ||
d0ec9796 RH |
2857 | void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, |
2858 | int64_t shift, uint32_t oprsz, uint32_t maxsz) | |
2859 | { | |
53229a77 | 2860 | static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 }; |
d0ec9796 RH |
2861 | static const GVecGen2i g[4] = { |
2862 | { .fni8 = tcg_gen_vec_shl8i_i64, | |
2863 | .fniv = tcg_gen_shli_vec, | |
2864 | .fno = gen_helper_gvec_shl8i, | |
53229a77 | 2865 | .opt_opc = vecop_list, |
d0ec9796 RH |
2866 | .vece = MO_8 }, |
2867 | { .fni8 = tcg_gen_vec_shl16i_i64, | |
2868 | .fniv = tcg_gen_shli_vec, | |
2869 | .fno = gen_helper_gvec_shl16i, | |
53229a77 | 2870 | .opt_opc = vecop_list, |
d0ec9796 RH |
2871 | .vece = MO_16 }, |
2872 | { .fni4 = tcg_gen_shli_i32, | |
2873 | .fniv = tcg_gen_shli_vec, | |
2874 | .fno = gen_helper_gvec_shl32i, | |
53229a77 | 2875 | .opt_opc = vecop_list, |
d0ec9796 RH |
2876 | .vece = MO_32 }, |
2877 | { .fni8 = tcg_gen_shli_i64, | |
2878 | .fniv = tcg_gen_shli_vec, | |
2879 | .fno = gen_helper_gvec_shl64i, | |
53229a77 | 2880 | .opt_opc = vecop_list, |
d0ec9796 RH |
2881 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2882 | .vece = MO_64 }, | |
2883 | }; | |
2884 | ||
2885 | tcg_debug_assert(vece <= MO_64); | |
2886 | tcg_debug_assert(shift >= 0 && shift < (8 << vece)); | |
2887 | if (shift == 0) { | |
2888 | tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); | |
2889 | } else { | |
2890 | tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); | |
2891 | } | |
2892 | } | |
2893 | ||
2894 | void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) | |
2895 | { | |
2896 | uint64_t mask = dup_const(MO_8, 0xff >> c); | |
2897 | tcg_gen_shri_i64(d, a, c); | |
2898 | tcg_gen_andi_i64(d, d, mask); | |
2899 | } | |
2900 | ||
2901 | void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) | |
2902 | { | |
2903 | uint64_t mask = dup_const(MO_16, 0xffff >> c); | |
2904 | tcg_gen_shri_i64(d, a, c); | |
2905 | tcg_gen_andi_i64(d, d, mask); | |
2906 | } | |
2907 | ||
950ee590 LZ |
2908 | void tcg_gen_vec_shr8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) |
2909 | { | |
2910 | uint32_t mask = dup_const(MO_8, 0xff >> c); | |
2911 | tcg_gen_shri_i32(d, a, c); | |
2912 | tcg_gen_andi_i32(d, d, mask); | |
2913 | } | |
2914 | ||
04f2a8bb LZ |
2915 | void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) |
2916 | { | |
2917 | uint32_t mask = dup_const(MO_16, 0xffff >> c); | |
2918 | tcg_gen_shri_i32(d, a, c); | |
2919 | tcg_gen_andi_i32(d, d, mask); | |
2920 | } | |
2921 | ||
d0ec9796 RH |
2922 | void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, |
2923 | int64_t shift, uint32_t oprsz, uint32_t maxsz) | |
2924 | { | |
53229a77 | 2925 | static const TCGOpcode vecop_list[] = { INDEX_op_shri_vec, 0 }; |
d0ec9796 RH |
2926 | static const GVecGen2i g[4] = { |
2927 | { .fni8 = tcg_gen_vec_shr8i_i64, | |
2928 | .fniv = tcg_gen_shri_vec, | |
2929 | .fno = gen_helper_gvec_shr8i, | |
53229a77 | 2930 | .opt_opc = vecop_list, |
d0ec9796 RH |
2931 | .vece = MO_8 }, |
2932 | { .fni8 = tcg_gen_vec_shr16i_i64, | |
2933 | .fniv = tcg_gen_shri_vec, | |
2934 | .fno = gen_helper_gvec_shr16i, | |
53229a77 | 2935 | .opt_opc = vecop_list, |
d0ec9796 RH |
2936 | .vece = MO_16 }, |
2937 | { .fni4 = tcg_gen_shri_i32, | |
2938 | .fniv = tcg_gen_shri_vec, | |
2939 | .fno = gen_helper_gvec_shr32i, | |
53229a77 | 2940 | .opt_opc = vecop_list, |
d0ec9796 RH |
2941 | .vece = MO_32 }, |
2942 | { .fni8 = tcg_gen_shri_i64, | |
2943 | .fniv = tcg_gen_shri_vec, | |
2944 | .fno = gen_helper_gvec_shr64i, | |
53229a77 | 2945 | .opt_opc = vecop_list, |
d0ec9796 RH |
2946 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
2947 | .vece = MO_64 }, | |
2948 | }; | |
2949 | ||
2950 | tcg_debug_assert(vece <= MO_64); | |
2951 | tcg_debug_assert(shift >= 0 && shift < (8 << vece)); | |
2952 | if (shift == 0) { | |
2953 | tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); | |
2954 | } else { | |
2955 | tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); | |
2956 | } | |
2957 | } | |
2958 | ||
2959 | void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) | |
2960 | { | |
2961 | uint64_t s_mask = dup_const(MO_8, 0x80 >> c); | |
2962 | uint64_t c_mask = dup_const(MO_8, 0xff >> c); | |
5dd48602 | 2963 | TCGv_i64 s = tcg_temp_ebb_new_i64(); |
d0ec9796 RH |
2964 | |
2965 | tcg_gen_shri_i64(d, a, c); | |
2966 | tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */ | |
2967 | tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */ | |
2968 | tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */ | |
2969 | tcg_gen_or_i64(d, d, s); /* include sign extension */ | |
2970 | tcg_temp_free_i64(s); | |
2971 | } | |
2972 | ||
2973 | void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) | |
2974 | { | |
2975 | uint64_t s_mask = dup_const(MO_16, 0x8000 >> c); | |
2976 | uint64_t c_mask = dup_const(MO_16, 0xffff >> c); | |
5dd48602 | 2977 | TCGv_i64 s = tcg_temp_ebb_new_i64(); |
d0ec9796 RH |
2978 | |
2979 | tcg_gen_shri_i64(d, a, c); | |
2980 | tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */ | |
2981 | tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */ | |
2982 | tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */ | |
2983 | tcg_gen_or_i64(d, d, s); /* include sign extension */ | |
2984 | tcg_temp_free_i64(s); | |
2985 | } | |
2986 | ||
950ee590 LZ |
2987 | void tcg_gen_vec_sar8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) |
2988 | { | |
2989 | uint32_t s_mask = dup_const(MO_8, 0x80 >> c); | |
2990 | uint32_t c_mask = dup_const(MO_8, 0xff >> c); | |
5dd48602 | 2991 | TCGv_i32 s = tcg_temp_ebb_new_i32(); |
950ee590 LZ |
2992 | |
2993 | tcg_gen_shri_i32(d, a, c); | |
2994 | tcg_gen_andi_i32(s, d, s_mask); /* isolate (shifted) sign bit */ | |
2995 | tcg_gen_muli_i32(s, s, (2 << c) - 2); /* replicate isolated signs */ | |
2996 | tcg_gen_andi_i32(d, d, c_mask); /* clear out bits above sign */ | |
2997 | tcg_gen_or_i32(d, d, s); /* include sign extension */ | |
2998 | tcg_temp_free_i32(s); | |
2999 | } | |
3000 | ||
04f2a8bb LZ |
3001 | void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) |
3002 | { | |
3003 | uint32_t s_mask = dup_const(MO_16, 0x8000 >> c); | |
3004 | uint32_t c_mask = dup_const(MO_16, 0xffff >> c); | |
5dd48602 | 3005 | TCGv_i32 s = tcg_temp_ebb_new_i32(); |
04f2a8bb LZ |
3006 | |
3007 | tcg_gen_shri_i32(d, a, c); | |
3008 | tcg_gen_andi_i32(s, d, s_mask); /* isolate (shifted) sign bit */ | |
3009 | tcg_gen_andi_i32(d, d, c_mask); /* clear out bits above sign */ | |
3010 | tcg_gen_muli_i32(s, s, (2 << c) - 2); /* replicate isolated signs */ | |
3011 | tcg_gen_or_i32(d, d, s); /* include sign extension */ | |
3012 | tcg_temp_free_i32(s); | |
3013 | } | |
3014 | ||
d0ec9796 RH |
3015 | void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, |
3016 | int64_t shift, uint32_t oprsz, uint32_t maxsz) | |
3017 | { | |
53229a77 | 3018 | static const TCGOpcode vecop_list[] = { INDEX_op_sari_vec, 0 }; |
d0ec9796 RH |
3019 | static const GVecGen2i g[4] = { |
3020 | { .fni8 = tcg_gen_vec_sar8i_i64, | |
3021 | .fniv = tcg_gen_sari_vec, | |
3022 | .fno = gen_helper_gvec_sar8i, | |
53229a77 | 3023 | .opt_opc = vecop_list, |
d0ec9796 RH |
3024 | .vece = MO_8 }, |
3025 | { .fni8 = tcg_gen_vec_sar16i_i64, | |
3026 | .fniv = tcg_gen_sari_vec, | |
3027 | .fno = gen_helper_gvec_sar16i, | |
53229a77 | 3028 | .opt_opc = vecop_list, |
d0ec9796 RH |
3029 | .vece = MO_16 }, |
3030 | { .fni4 = tcg_gen_sari_i32, | |
3031 | .fniv = tcg_gen_sari_vec, | |
3032 | .fno = gen_helper_gvec_sar32i, | |
53229a77 | 3033 | .opt_opc = vecop_list, |
d0ec9796 RH |
3034 | .vece = MO_32 }, |
3035 | { .fni8 = tcg_gen_sari_i64, | |
3036 | .fniv = tcg_gen_sari_vec, | |
3037 | .fno = gen_helper_gvec_sar64i, | |
53229a77 | 3038 | .opt_opc = vecop_list, |
d0ec9796 RH |
3039 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
3040 | .vece = MO_64 }, | |
3041 | }; | |
3042 | ||
3043 | tcg_debug_assert(vece <= MO_64); | |
3044 | tcg_debug_assert(shift >= 0 && shift < (8 << vece)); | |
3045 | if (shift == 0) { | |
3046 | tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); | |
3047 | } else { | |
3048 | tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); | |
3049 | } | |
3050 | } | |
212be173 | 3051 | |
b0f7e744 RH |
3052 | void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) |
3053 | { | |
3054 | uint64_t mask = dup_const(MO_8, 0xff << c); | |
3055 | ||
3056 | tcg_gen_shli_i64(d, a, c); | |
3057 | tcg_gen_shri_i64(a, a, 8 - c); | |
3058 | tcg_gen_andi_i64(d, d, mask); | |
3059 | tcg_gen_andi_i64(a, a, ~mask); | |
3060 | tcg_gen_or_i64(d, d, a); | |
3061 | } | |
3062 | ||
3063 | void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) | |
3064 | { | |
3065 | uint64_t mask = dup_const(MO_16, 0xffff << c); | |
3066 | ||
3067 | tcg_gen_shli_i64(d, a, c); | |
3068 | tcg_gen_shri_i64(a, a, 16 - c); | |
3069 | tcg_gen_andi_i64(d, d, mask); | |
3070 | tcg_gen_andi_i64(a, a, ~mask); | |
3071 | tcg_gen_or_i64(d, d, a); | |
3072 | } | |
3073 | ||
3074 | void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3075 | int64_t shift, uint32_t oprsz, uint32_t maxsz) | |
3076 | { | |
3077 | static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 }; | |
3078 | static const GVecGen2i g[4] = { | |
3079 | { .fni8 = tcg_gen_vec_rotl8i_i64, | |
3080 | .fniv = tcg_gen_rotli_vec, | |
3081 | .fno = gen_helper_gvec_rotl8i, | |
3082 | .opt_opc = vecop_list, | |
3083 | .vece = MO_8 }, | |
3084 | { .fni8 = tcg_gen_vec_rotl16i_i64, | |
3085 | .fniv = tcg_gen_rotli_vec, | |
3086 | .fno = gen_helper_gvec_rotl16i, | |
3087 | .opt_opc = vecop_list, | |
3088 | .vece = MO_16 }, | |
3089 | { .fni4 = tcg_gen_rotli_i32, | |
3090 | .fniv = tcg_gen_rotli_vec, | |
3091 | .fno = gen_helper_gvec_rotl32i, | |
3092 | .opt_opc = vecop_list, | |
3093 | .vece = MO_32 }, | |
3094 | { .fni8 = tcg_gen_rotli_i64, | |
3095 | .fniv = tcg_gen_rotli_vec, | |
3096 | .fno = gen_helper_gvec_rotl64i, | |
3097 | .opt_opc = vecop_list, | |
3098 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
3099 | .vece = MO_64 }, | |
3100 | }; | |
3101 | ||
3102 | tcg_debug_assert(vece <= MO_64); | |
3103 | tcg_debug_assert(shift >= 0 && shift < (8 << vece)); | |
3104 | if (shift == 0) { | |
3105 | tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); | |
3106 | } else { | |
3107 | tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); | |
3108 | } | |
3109 | } | |
3110 | ||
3111 | void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3112 | int64_t shift, uint32_t oprsz, uint32_t maxsz) | |
3113 | { | |
3114 | tcg_debug_assert(vece <= MO_64); | |
3115 | tcg_debug_assert(shift >= 0 && shift < (8 << vece)); | |
3116 | tcg_gen_gvec_rotli(vece, dofs, aofs, -shift & ((8 << vece) - 1), | |
3117 | oprsz, maxsz); | |
3118 | } | |
3119 | ||
b4578cd9 RH |
3120 | /* |
3121 | * Specialized generation vector shifts by a non-constant scalar. | |
3122 | */ | |
3123 | ||
3124 | typedef struct { | |
3125 | void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); | |
3126 | void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); | |
3127 | void (*fniv_s)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32); | |
3128 | void (*fniv_v)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); | |
3129 | gen_helper_gvec_2 *fno[4]; | |
3130 | TCGOpcode s_list[2]; | |
3131 | TCGOpcode v_list[2]; | |
3132 | } GVecGen2sh; | |
3133 | ||
3134 | static void expand_2sh_vec(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3135 | uint32_t oprsz, uint32_t tysz, TCGType type, | |
3136 | TCGv_i32 shift, | |
3137 | void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32)) | |
3138 | { | |
3139 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
3140 | uint32_t i; | |
3141 | ||
3142 | for (i = 0; i < oprsz; i += tysz) { | |
3143 | tcg_gen_ld_vec(t0, cpu_env, aofs + i); | |
3144 | fni(vece, t0, t0, shift); | |
3145 | tcg_gen_st_vec(t0, cpu_env, dofs + i); | |
3146 | } | |
3147 | tcg_temp_free_vec(t0); | |
3148 | } | |
3149 | ||
3150 | static void | |
3151 | do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, | |
3152 | uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g) | |
3153 | { | |
3154 | TCGType type; | |
3155 | uint32_t some; | |
3156 | ||
3157 | check_size_align(oprsz, maxsz, dofs | aofs); | |
3158 | check_overlap_2(dofs, aofs, maxsz); | |
3159 | ||
3160 | /* If the backend has a scalar expansion, great. */ | |
3161 | type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_64); | |
3162 | if (type) { | |
3163 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); | |
3164 | switch (type) { | |
3165 | case TCG_TYPE_V256: | |
3166 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
3167 | expand_2sh_vec(vece, dofs, aofs, some, 32, | |
3168 | TCG_TYPE_V256, shift, g->fniv_s); | |
3169 | if (some == oprsz) { | |
3170 | break; | |
3171 | } | |
3172 | dofs += some; | |
3173 | aofs += some; | |
3174 | oprsz -= some; | |
3175 | maxsz -= some; | |
3176 | /* fallthru */ | |
3177 | case TCG_TYPE_V128: | |
3178 | expand_2sh_vec(vece, dofs, aofs, oprsz, 16, | |
3179 | TCG_TYPE_V128, shift, g->fniv_s); | |
3180 | break; | |
3181 | case TCG_TYPE_V64: | |
3182 | expand_2sh_vec(vece, dofs, aofs, oprsz, 8, | |
3183 | TCG_TYPE_V64, shift, g->fniv_s); | |
3184 | break; | |
3185 | default: | |
3186 | g_assert_not_reached(); | |
3187 | } | |
3188 | tcg_swap_vecop_list(hold_list); | |
3189 | goto clear_tail; | |
3190 | } | |
3191 | ||
3192 | /* If the backend supports variable vector shifts, also cool. */ | |
3193 | type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_64); | |
3194 | if (type) { | |
3195 | const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); | |
3196 | TCGv_vec v_shift = tcg_temp_new_vec(type); | |
3197 | ||
3198 | if (vece == MO_64) { | |
5dd48602 | 3199 | TCGv_i64 sh64 = tcg_temp_ebb_new_i64(); |
b4578cd9 RH |
3200 | tcg_gen_extu_i32_i64(sh64, shift); |
3201 | tcg_gen_dup_i64_vec(MO_64, v_shift, sh64); | |
3202 | tcg_temp_free_i64(sh64); | |
3203 | } else { | |
3204 | tcg_gen_dup_i32_vec(vece, v_shift, shift); | |
3205 | } | |
3206 | ||
3207 | switch (type) { | |
3208 | case TCG_TYPE_V256: | |
3209 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
3210 | expand_2s_vec(vece, dofs, aofs, some, 32, TCG_TYPE_V256, | |
3211 | v_shift, false, g->fniv_v); | |
3212 | if (some == oprsz) { | |
3213 | break; | |
3214 | } | |
3215 | dofs += some; | |
3216 | aofs += some; | |
3217 | oprsz -= some; | |
3218 | maxsz -= some; | |
3219 | /* fallthru */ | |
3220 | case TCG_TYPE_V128: | |
3221 | expand_2s_vec(vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, | |
3222 | v_shift, false, g->fniv_v); | |
3223 | break; | |
3224 | case TCG_TYPE_V64: | |
3225 | expand_2s_vec(vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, | |
3226 | v_shift, false, g->fniv_v); | |
3227 | break; | |
3228 | default: | |
3229 | g_assert_not_reached(); | |
3230 | } | |
3231 | tcg_temp_free_vec(v_shift); | |
3232 | tcg_swap_vecop_list(hold_list); | |
3233 | goto clear_tail; | |
3234 | } | |
3235 | ||
3236 | /* Otherwise fall back to integral... */ | |
3237 | if (vece == MO_32 && check_size_impl(oprsz, 4)) { | |
3238 | expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4); | |
3239 | } else if (vece == MO_64 && check_size_impl(oprsz, 8)) { | |
5dd48602 | 3240 | TCGv_i64 sh64 = tcg_temp_ebb_new_i64(); |
b4578cd9 RH |
3241 | tcg_gen_extu_i32_i64(sh64, shift); |
3242 | expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8); | |
3243 | tcg_temp_free_i64(sh64); | |
3244 | } else { | |
5dd48602 RH |
3245 | TCGv_ptr a0 = tcg_temp_ebb_new_ptr(); |
3246 | TCGv_ptr a1 = tcg_temp_ebb_new_ptr(); | |
3247 | TCGv_i32 desc = tcg_temp_ebb_new_i32(); | |
b4578cd9 RH |
3248 | |
3249 | tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT); | |
3250 | tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); | |
3251 | tcg_gen_addi_ptr(a0, cpu_env, dofs); | |
3252 | tcg_gen_addi_ptr(a1, cpu_env, aofs); | |
3253 | ||
3254 | g->fno[vece](a0, a1, desc); | |
3255 | ||
3256 | tcg_temp_free_ptr(a0); | |
3257 | tcg_temp_free_ptr(a1); | |
3258 | tcg_temp_free_i32(desc); | |
3259 | return; | |
3260 | } | |
3261 | ||
3262 | clear_tail: | |
3263 | if (oprsz < maxsz) { | |
3264 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
3265 | } | |
3266 | } | |
3267 | ||
3268 | void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3269 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) | |
3270 | { | |
3271 | static const GVecGen2sh g = { | |
3272 | .fni4 = tcg_gen_shl_i32, | |
3273 | .fni8 = tcg_gen_shl_i64, | |
3274 | .fniv_s = tcg_gen_shls_vec, | |
3275 | .fniv_v = tcg_gen_shlv_vec, | |
3276 | .fno = { | |
3277 | gen_helper_gvec_shl8i, | |
3278 | gen_helper_gvec_shl16i, | |
3279 | gen_helper_gvec_shl32i, | |
3280 | gen_helper_gvec_shl64i, | |
3281 | }, | |
3282 | .s_list = { INDEX_op_shls_vec, 0 }, | |
3283 | .v_list = { INDEX_op_shlv_vec, 0 }, | |
3284 | }; | |
3285 | ||
3286 | tcg_debug_assert(vece <= MO_64); | |
3287 | do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); | |
3288 | } | |
3289 | ||
3290 | void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3291 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) | |
3292 | { | |
3293 | static const GVecGen2sh g = { | |
3294 | .fni4 = tcg_gen_shr_i32, | |
3295 | .fni8 = tcg_gen_shr_i64, | |
3296 | .fniv_s = tcg_gen_shrs_vec, | |
3297 | .fniv_v = tcg_gen_shrv_vec, | |
3298 | .fno = { | |
3299 | gen_helper_gvec_shr8i, | |
3300 | gen_helper_gvec_shr16i, | |
3301 | gen_helper_gvec_shr32i, | |
3302 | gen_helper_gvec_shr64i, | |
3303 | }, | |
3304 | .s_list = { INDEX_op_shrs_vec, 0 }, | |
3305 | .v_list = { INDEX_op_shrv_vec, 0 }, | |
3306 | }; | |
3307 | ||
3308 | tcg_debug_assert(vece <= MO_64); | |
3309 | do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); | |
3310 | } | |
3311 | ||
3312 | void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3313 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) | |
3314 | { | |
3315 | static const GVecGen2sh g = { | |
3316 | .fni4 = tcg_gen_sar_i32, | |
3317 | .fni8 = tcg_gen_sar_i64, | |
3318 | .fniv_s = tcg_gen_sars_vec, | |
3319 | .fniv_v = tcg_gen_sarv_vec, | |
3320 | .fno = { | |
3321 | gen_helper_gvec_sar8i, | |
3322 | gen_helper_gvec_sar16i, | |
3323 | gen_helper_gvec_sar32i, | |
3324 | gen_helper_gvec_sar64i, | |
3325 | }, | |
3326 | .s_list = { INDEX_op_sars_vec, 0 }, | |
3327 | .v_list = { INDEX_op_sarv_vec, 0 }, | |
3328 | }; | |
3329 | ||
3330 | tcg_debug_assert(vece <= MO_64); | |
3331 | do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); | |
3332 | } | |
3333 | ||
23850a74 RH |
3334 | void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, |
3335 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) | |
3336 | { | |
3337 | static const GVecGen2sh g = { | |
3338 | .fni4 = tcg_gen_rotl_i32, | |
3339 | .fni8 = tcg_gen_rotl_i64, | |
3340 | .fniv_s = tcg_gen_rotls_vec, | |
3341 | .fniv_v = tcg_gen_rotlv_vec, | |
3342 | .fno = { | |
3343 | gen_helper_gvec_rotl8i, | |
3344 | gen_helper_gvec_rotl16i, | |
3345 | gen_helper_gvec_rotl32i, | |
3346 | gen_helper_gvec_rotl64i, | |
3347 | }, | |
3348 | .s_list = { INDEX_op_rotls_vec, 0 }, | |
3349 | .v_list = { INDEX_op_rotlv_vec, 0 }, | |
3350 | }; | |
3351 | ||
3352 | tcg_debug_assert(vece <= MO_64); | |
3353 | do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); | |
3354 | } | |
3355 | ||
bef317d0 NK |
3356 | void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, |
3357 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) | |
3358 | { | |
3359 | TCGv_i32 tmp = tcg_temp_ebb_new_i32(); | |
3360 | ||
3361 | tcg_gen_neg_i32(tmp, shift); | |
3362 | tcg_gen_andi_i32(tmp, tmp, (8 << vece) - 1); | |
3363 | tcg_gen_gvec_rotls(vece, dofs, aofs, tmp, oprsz, maxsz); | |
3364 | tcg_temp_free_i32(tmp); | |
3365 | } | |
3366 | ||
5ee5c14c RH |
3367 | /* |
3368 | * Expand D = A << (B % element bits) | |
3369 | * | |
3370 | * Unlike scalar shifts, where it is easy for the target front end | |
3371 | * to include the modulo as part of the expansion. If the target | |
3372 | * naturally includes the modulo as part of the operation, great! | |
3373 | * If the target has some other behaviour from out-of-range shifts, | |
3374 | * then it could not use this function anyway, and would need to | |
3375 | * do it's own expansion with custom functions. | |
3376 | */ | |
3377 | static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d, | |
3378 | TCGv_vec a, TCGv_vec b) | |
3379 | { | |
3380 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
88d4005b | 3381 | TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); |
5ee5c14c | 3382 | |
88d4005b | 3383 | tcg_gen_and_vec(vece, t, b, m); |
5ee5c14c RH |
3384 | tcg_gen_shlv_vec(vece, d, a, t); |
3385 | tcg_temp_free_vec(t); | |
3386 | } | |
3387 | ||
3388 | static void tcg_gen_shl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | |
3389 | { | |
5dd48602 | 3390 | TCGv_i32 t = tcg_temp_ebb_new_i32(); |
5ee5c14c RH |
3391 | |
3392 | tcg_gen_andi_i32(t, b, 31); | |
3393 | tcg_gen_shl_i32(d, a, t); | |
3394 | tcg_temp_free_i32(t); | |
3395 | } | |
3396 | ||
3397 | static void tcg_gen_shl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | |
3398 | { | |
5dd48602 | 3399 | TCGv_i64 t = tcg_temp_ebb_new_i64(); |
5ee5c14c RH |
3400 | |
3401 | tcg_gen_andi_i64(t, b, 63); | |
3402 | tcg_gen_shl_i64(d, a, t); | |
3403 | tcg_temp_free_i64(t); | |
3404 | } | |
3405 | ||
3406 | void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3407 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
3408 | { | |
3409 | static const TCGOpcode vecop_list[] = { INDEX_op_shlv_vec, 0 }; | |
3410 | static const GVecGen3 g[4] = { | |
3411 | { .fniv = tcg_gen_shlv_mod_vec, | |
3412 | .fno = gen_helper_gvec_shl8v, | |
3413 | .opt_opc = vecop_list, | |
3414 | .vece = MO_8 }, | |
3415 | { .fniv = tcg_gen_shlv_mod_vec, | |
3416 | .fno = gen_helper_gvec_shl16v, | |
3417 | .opt_opc = vecop_list, | |
3418 | .vece = MO_16 }, | |
3419 | { .fni4 = tcg_gen_shl_mod_i32, | |
3420 | .fniv = tcg_gen_shlv_mod_vec, | |
3421 | .fno = gen_helper_gvec_shl32v, | |
3422 | .opt_opc = vecop_list, | |
3423 | .vece = MO_32 }, | |
3424 | { .fni8 = tcg_gen_shl_mod_i64, | |
3425 | .fniv = tcg_gen_shlv_mod_vec, | |
3426 | .fno = gen_helper_gvec_shl64v, | |
3427 | .opt_opc = vecop_list, | |
3428 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
3429 | .vece = MO_64 }, | |
3430 | }; | |
3431 | ||
3432 | tcg_debug_assert(vece <= MO_64); | |
3433 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
3434 | } | |
3435 | ||
3436 | /* | |
3437 | * Similarly for logical right shifts. | |
3438 | */ | |
3439 | ||
3440 | static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d, | |
3441 | TCGv_vec a, TCGv_vec b) | |
3442 | { | |
3443 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
88d4005b | 3444 | TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); |
5ee5c14c | 3445 | |
88d4005b | 3446 | tcg_gen_and_vec(vece, t, b, m); |
5ee5c14c RH |
3447 | tcg_gen_shrv_vec(vece, d, a, t); |
3448 | tcg_temp_free_vec(t); | |
3449 | } | |
3450 | ||
3451 | static void tcg_gen_shr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | |
3452 | { | |
5dd48602 | 3453 | TCGv_i32 t = tcg_temp_ebb_new_i32(); |
5ee5c14c RH |
3454 | |
3455 | tcg_gen_andi_i32(t, b, 31); | |
3456 | tcg_gen_shr_i32(d, a, t); | |
3457 | tcg_temp_free_i32(t); | |
3458 | } | |
3459 | ||
3460 | static void tcg_gen_shr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | |
3461 | { | |
5dd48602 | 3462 | TCGv_i64 t = tcg_temp_ebb_new_i64(); |
5ee5c14c RH |
3463 | |
3464 | tcg_gen_andi_i64(t, b, 63); | |
3465 | tcg_gen_shr_i64(d, a, t); | |
3466 | tcg_temp_free_i64(t); | |
3467 | } | |
3468 | ||
3469 | void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3470 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
3471 | { | |
3472 | static const TCGOpcode vecop_list[] = { INDEX_op_shrv_vec, 0 }; | |
3473 | static const GVecGen3 g[4] = { | |
3474 | { .fniv = tcg_gen_shrv_mod_vec, | |
3475 | .fno = gen_helper_gvec_shr8v, | |
3476 | .opt_opc = vecop_list, | |
3477 | .vece = MO_8 }, | |
3478 | { .fniv = tcg_gen_shrv_mod_vec, | |
3479 | .fno = gen_helper_gvec_shr16v, | |
3480 | .opt_opc = vecop_list, | |
3481 | .vece = MO_16 }, | |
3482 | { .fni4 = tcg_gen_shr_mod_i32, | |
3483 | .fniv = tcg_gen_shrv_mod_vec, | |
3484 | .fno = gen_helper_gvec_shr32v, | |
3485 | .opt_opc = vecop_list, | |
3486 | .vece = MO_32 }, | |
3487 | { .fni8 = tcg_gen_shr_mod_i64, | |
3488 | .fniv = tcg_gen_shrv_mod_vec, | |
3489 | .fno = gen_helper_gvec_shr64v, | |
3490 | .opt_opc = vecop_list, | |
3491 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
3492 | .vece = MO_64 }, | |
3493 | }; | |
3494 | ||
3495 | tcg_debug_assert(vece <= MO_64); | |
3496 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
3497 | } | |
3498 | ||
3499 | /* | |
3500 | * Similarly for arithmetic right shifts. | |
3501 | */ | |
3502 | ||
3503 | static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d, | |
3504 | TCGv_vec a, TCGv_vec b) | |
3505 | { | |
3506 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
88d4005b | 3507 | TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); |
5ee5c14c | 3508 | |
88d4005b | 3509 | tcg_gen_and_vec(vece, t, b, m); |
5ee5c14c RH |
3510 | tcg_gen_sarv_vec(vece, d, a, t); |
3511 | tcg_temp_free_vec(t); | |
3512 | } | |
3513 | ||
3514 | static void tcg_gen_sar_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | |
3515 | { | |
5dd48602 | 3516 | TCGv_i32 t = tcg_temp_ebb_new_i32(); |
5ee5c14c RH |
3517 | |
3518 | tcg_gen_andi_i32(t, b, 31); | |
3519 | tcg_gen_sar_i32(d, a, t); | |
3520 | tcg_temp_free_i32(t); | |
3521 | } | |
3522 | ||
3523 | static void tcg_gen_sar_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | |
3524 | { | |
5dd48602 | 3525 | TCGv_i64 t = tcg_temp_ebb_new_i64(); |
5ee5c14c RH |
3526 | |
3527 | tcg_gen_andi_i64(t, b, 63); | |
3528 | tcg_gen_sar_i64(d, a, t); | |
3529 | tcg_temp_free_i64(t); | |
3530 | } | |
3531 | ||
3532 | void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3533 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
3534 | { | |
3535 | static const TCGOpcode vecop_list[] = { INDEX_op_sarv_vec, 0 }; | |
3536 | static const GVecGen3 g[4] = { | |
3537 | { .fniv = tcg_gen_sarv_mod_vec, | |
3538 | .fno = gen_helper_gvec_sar8v, | |
3539 | .opt_opc = vecop_list, | |
3540 | .vece = MO_8 }, | |
3541 | { .fniv = tcg_gen_sarv_mod_vec, | |
3542 | .fno = gen_helper_gvec_sar16v, | |
3543 | .opt_opc = vecop_list, | |
3544 | .vece = MO_16 }, | |
3545 | { .fni4 = tcg_gen_sar_mod_i32, | |
3546 | .fniv = tcg_gen_sarv_mod_vec, | |
3547 | .fno = gen_helper_gvec_sar32v, | |
3548 | .opt_opc = vecop_list, | |
3549 | .vece = MO_32 }, | |
3550 | { .fni8 = tcg_gen_sar_mod_i64, | |
3551 | .fniv = tcg_gen_sarv_mod_vec, | |
3552 | .fno = gen_helper_gvec_sar64v, | |
3553 | .opt_opc = vecop_list, | |
3554 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
3555 | .vece = MO_64 }, | |
3556 | }; | |
3557 | ||
3558 | tcg_debug_assert(vece <= MO_64); | |
3559 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
3560 | } | |
3561 | ||
5d0ceda9 RH |
3562 | /* |
3563 | * Similarly for rotates. | |
3564 | */ | |
3565 | ||
3566 | static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d, | |
3567 | TCGv_vec a, TCGv_vec b) | |
3568 | { | |
3569 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
88d4005b | 3570 | TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); |
5d0ceda9 | 3571 | |
88d4005b | 3572 | tcg_gen_and_vec(vece, t, b, m); |
5d0ceda9 RH |
3573 | tcg_gen_rotlv_vec(vece, d, a, t); |
3574 | tcg_temp_free_vec(t); | |
3575 | } | |
3576 | ||
3577 | static void tcg_gen_rotl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | |
3578 | { | |
5dd48602 | 3579 | TCGv_i32 t = tcg_temp_ebb_new_i32(); |
5d0ceda9 RH |
3580 | |
3581 | tcg_gen_andi_i32(t, b, 31); | |
3582 | tcg_gen_rotl_i32(d, a, t); | |
3583 | tcg_temp_free_i32(t); | |
3584 | } | |
3585 | ||
3586 | static void tcg_gen_rotl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | |
3587 | { | |
5dd48602 | 3588 | TCGv_i64 t = tcg_temp_ebb_new_i64(); |
5d0ceda9 RH |
3589 | |
3590 | tcg_gen_andi_i64(t, b, 63); | |
3591 | tcg_gen_rotl_i64(d, a, t); | |
3592 | tcg_temp_free_i64(t); | |
3593 | } | |
3594 | ||
3595 | void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3596 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
3597 | { | |
3598 | static const TCGOpcode vecop_list[] = { INDEX_op_rotlv_vec, 0 }; | |
3599 | static const GVecGen3 g[4] = { | |
3600 | { .fniv = tcg_gen_rotlv_mod_vec, | |
3601 | .fno = gen_helper_gvec_rotl8v, | |
3602 | .opt_opc = vecop_list, | |
3603 | .vece = MO_8 }, | |
3604 | { .fniv = tcg_gen_rotlv_mod_vec, | |
3605 | .fno = gen_helper_gvec_rotl16v, | |
3606 | .opt_opc = vecop_list, | |
3607 | .vece = MO_16 }, | |
3608 | { .fni4 = tcg_gen_rotl_mod_i32, | |
3609 | .fniv = tcg_gen_rotlv_mod_vec, | |
3610 | .fno = gen_helper_gvec_rotl32v, | |
3611 | .opt_opc = vecop_list, | |
3612 | .vece = MO_32 }, | |
3613 | { .fni8 = tcg_gen_rotl_mod_i64, | |
3614 | .fniv = tcg_gen_rotlv_mod_vec, | |
3615 | .fno = gen_helper_gvec_rotl64v, | |
3616 | .opt_opc = vecop_list, | |
3617 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
3618 | .vece = MO_64 }, | |
3619 | }; | |
3620 | ||
3621 | tcg_debug_assert(vece <= MO_64); | |
3622 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
3623 | } | |
3624 | ||
3625 | static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d, | |
3626 | TCGv_vec a, TCGv_vec b) | |
3627 | { | |
3628 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
88d4005b | 3629 | TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); |
5d0ceda9 | 3630 | |
88d4005b | 3631 | tcg_gen_and_vec(vece, t, b, m); |
5d0ceda9 RH |
3632 | tcg_gen_rotrv_vec(vece, d, a, t); |
3633 | tcg_temp_free_vec(t); | |
3634 | } | |
3635 | ||
3636 | static void tcg_gen_rotr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | |
3637 | { | |
5dd48602 | 3638 | TCGv_i32 t = tcg_temp_ebb_new_i32(); |
5d0ceda9 RH |
3639 | |
3640 | tcg_gen_andi_i32(t, b, 31); | |
3641 | tcg_gen_rotr_i32(d, a, t); | |
3642 | tcg_temp_free_i32(t); | |
3643 | } | |
3644 | ||
3645 | static void tcg_gen_rotr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | |
3646 | { | |
5dd48602 | 3647 | TCGv_i64 t = tcg_temp_ebb_new_i64(); |
5d0ceda9 RH |
3648 | |
3649 | tcg_gen_andi_i64(t, b, 63); | |
3650 | tcg_gen_rotr_i64(d, a, t); | |
3651 | tcg_temp_free_i64(t); | |
3652 | } | |
3653 | ||
3654 | void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3655 | uint32_t bofs, uint32_t oprsz, uint32_t maxsz) | |
3656 | { | |
3657 | static const TCGOpcode vecop_list[] = { INDEX_op_rotrv_vec, 0 }; | |
3658 | static const GVecGen3 g[4] = { | |
3659 | { .fniv = tcg_gen_rotrv_mod_vec, | |
3660 | .fno = gen_helper_gvec_rotr8v, | |
3661 | .opt_opc = vecop_list, | |
3662 | .vece = MO_8 }, | |
3663 | { .fniv = tcg_gen_rotrv_mod_vec, | |
3664 | .fno = gen_helper_gvec_rotr16v, | |
3665 | .opt_opc = vecop_list, | |
3666 | .vece = MO_16 }, | |
3667 | { .fni4 = tcg_gen_rotr_mod_i32, | |
3668 | .fniv = tcg_gen_rotrv_mod_vec, | |
3669 | .fno = gen_helper_gvec_rotr32v, | |
3670 | .opt_opc = vecop_list, | |
3671 | .vece = MO_32 }, | |
3672 | { .fni8 = tcg_gen_rotr_mod_i64, | |
3673 | .fniv = tcg_gen_rotrv_mod_vec, | |
3674 | .fno = gen_helper_gvec_rotr64v, | |
3675 | .opt_opc = vecop_list, | |
3676 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
3677 | .vece = MO_64 }, | |
3678 | }; | |
3679 | ||
3680 | tcg_debug_assert(vece <= MO_64); | |
3681 | tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); | |
3682 | } | |
3683 | ||
212be173 RH |
3684 | /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ |
3685 | static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
3686 | uint32_t oprsz, TCGCond cond) | |
3687 | { | |
5dd48602 RH |
3688 | TCGv_i32 t0 = tcg_temp_ebb_new_i32(); |
3689 | TCGv_i32 t1 = tcg_temp_ebb_new_i32(); | |
212be173 RH |
3690 | uint32_t i; |
3691 | ||
3692 | for (i = 0; i < oprsz; i += 4) { | |
3693 | tcg_gen_ld_i32(t0, cpu_env, aofs + i); | |
3694 | tcg_gen_ld_i32(t1, cpu_env, bofs + i); | |
4a883870 | 3695 | tcg_gen_negsetcond_i32(cond, t0, t0, t1); |
212be173 RH |
3696 | tcg_gen_st_i32(t0, cpu_env, dofs + i); |
3697 | } | |
3698 | tcg_temp_free_i32(t1); | |
3699 | tcg_temp_free_i32(t0); | |
3700 | } | |
3701 | ||
3702 | static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, | |
3703 | uint32_t oprsz, TCGCond cond) | |
3704 | { | |
5dd48602 RH |
3705 | TCGv_i64 t0 = tcg_temp_ebb_new_i64(); |
3706 | TCGv_i64 t1 = tcg_temp_ebb_new_i64(); | |
212be173 RH |
3707 | uint32_t i; |
3708 | ||
3709 | for (i = 0; i < oprsz; i += 8) { | |
3710 | tcg_gen_ld_i64(t0, cpu_env, aofs + i); | |
3711 | tcg_gen_ld_i64(t1, cpu_env, bofs + i); | |
4a883870 | 3712 | tcg_gen_negsetcond_i64(cond, t0, t0, t1); |
212be173 RH |
3713 | tcg_gen_st_i64(t0, cpu_env, dofs + i); |
3714 | } | |
3715 | tcg_temp_free_i64(t1); | |
3716 | tcg_temp_free_i64(t0); | |
3717 | } | |
3718 | ||
3719 | static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs, | |
3720 | uint32_t bofs, uint32_t oprsz, uint32_t tysz, | |
3721 | TCGType type, TCGCond cond) | |
3722 | { | |
3723 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
3724 | TCGv_vec t1 = tcg_temp_new_vec(type); | |
3725 | uint32_t i; | |
3726 | ||
3727 | for (i = 0; i < oprsz; i += tysz) { | |
3728 | tcg_gen_ld_vec(t0, cpu_env, aofs + i); | |
3729 | tcg_gen_ld_vec(t1, cpu_env, bofs + i); | |
3730 | tcg_gen_cmp_vec(cond, vece, t0, t0, t1); | |
3731 | tcg_gen_st_vec(t0, cpu_env, dofs + i); | |
3732 | } | |
3733 | tcg_temp_free_vec(t1); | |
3734 | tcg_temp_free_vec(t0); | |
3735 | } | |
3736 | ||
3737 | void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, | |
3738 | uint32_t aofs, uint32_t bofs, | |
3739 | uint32_t oprsz, uint32_t maxsz) | |
3740 | { | |
53229a77 | 3741 | static const TCGOpcode cmp_list[] = { INDEX_op_cmp_vec, 0 }; |
212be173 RH |
3742 | static gen_helper_gvec_3 * const eq_fn[4] = { |
3743 | gen_helper_gvec_eq8, gen_helper_gvec_eq16, | |
3744 | gen_helper_gvec_eq32, gen_helper_gvec_eq64 | |
3745 | }; | |
3746 | static gen_helper_gvec_3 * const ne_fn[4] = { | |
3747 | gen_helper_gvec_ne8, gen_helper_gvec_ne16, | |
3748 | gen_helper_gvec_ne32, gen_helper_gvec_ne64 | |
3749 | }; | |
3750 | static gen_helper_gvec_3 * const lt_fn[4] = { | |
3751 | gen_helper_gvec_lt8, gen_helper_gvec_lt16, | |
3752 | gen_helper_gvec_lt32, gen_helper_gvec_lt64 | |
3753 | }; | |
3754 | static gen_helper_gvec_3 * const le_fn[4] = { | |
3755 | gen_helper_gvec_le8, gen_helper_gvec_le16, | |
3756 | gen_helper_gvec_le32, gen_helper_gvec_le64 | |
3757 | }; | |
3758 | static gen_helper_gvec_3 * const ltu_fn[4] = { | |
3759 | gen_helper_gvec_ltu8, gen_helper_gvec_ltu16, | |
3760 | gen_helper_gvec_ltu32, gen_helper_gvec_ltu64 | |
3761 | }; | |
3762 | static gen_helper_gvec_3 * const leu_fn[4] = { | |
3763 | gen_helper_gvec_leu8, gen_helper_gvec_leu16, | |
3764 | gen_helper_gvec_leu32, gen_helper_gvec_leu64 | |
3765 | }; | |
3766 | static gen_helper_gvec_3 * const * const fns[16] = { | |
3767 | [TCG_COND_EQ] = eq_fn, | |
3768 | [TCG_COND_NE] = ne_fn, | |
3769 | [TCG_COND_LT] = lt_fn, | |
3770 | [TCG_COND_LE] = le_fn, | |
3771 | [TCG_COND_LTU] = ltu_fn, | |
3772 | [TCG_COND_LEU] = leu_fn, | |
3773 | }; | |
53229a77 RH |
3774 | |
3775 | const TCGOpcode *hold_list; | |
adb196cb RH |
3776 | TCGType type; |
3777 | uint32_t some; | |
212be173 RH |
3778 | |
3779 | check_size_align(oprsz, maxsz, dofs | aofs | bofs); | |
3780 | check_overlap_3(dofs, aofs, bofs, maxsz); | |
3781 | ||
3782 | if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) { | |
3783 | do_dup(MO_8, dofs, oprsz, maxsz, | |
3784 | NULL, NULL, -(cond == TCG_COND_ALWAYS)); | |
3785 | return; | |
3786 | } | |
3787 | ||
53229a77 RH |
3788 | /* |
3789 | * Implement inline with a vector type, if possible. | |
adb196cb RH |
3790 | * Prefer integer when 64-bit host and 64-bit comparison. |
3791 | */ | |
53229a77 RH |
3792 | hold_list = tcg_swap_vecop_list(cmp_list); |
3793 | type = choose_vector_type(cmp_list, vece, oprsz, | |
adb196cb RH |
3794 | TCG_TARGET_REG_BITS == 64 && vece == MO_64); |
3795 | switch (type) { | |
3796 | case TCG_TYPE_V256: | |
3797 | /* Recall that ARM SVE allows vector sizes that are not a | |
3798 | * power of 2, but always a multiple of 16. The intent is | |
3799 | * that e.g. size == 80 would be expanded with 2x32 + 1x16. | |
3800 | */ | |
3801 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
212be173 RH |
3802 | expand_cmp_vec(vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, cond); |
3803 | if (some == oprsz) { | |
adb196cb | 3804 | break; |
212be173 RH |
3805 | } |
3806 | dofs += some; | |
3807 | aofs += some; | |
3808 | bofs += some; | |
3809 | oprsz -= some; | |
3810 | maxsz -= some; | |
adb196cb RH |
3811 | /* fallthru */ |
3812 | case TCG_TYPE_V128: | |
212be173 | 3813 | expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, cond); |
adb196cb RH |
3814 | break; |
3815 | case TCG_TYPE_V64: | |
212be173 | 3816 | expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, cond); |
adb196cb RH |
3817 | break; |
3818 | ||
3819 | case 0: | |
3820 | if (vece == MO_64 && check_size_impl(oprsz, 8)) { | |
3821 | expand_cmp_i64(dofs, aofs, bofs, oprsz, cond); | |
3822 | } else if (vece == MO_32 && check_size_impl(oprsz, 4)) { | |
3823 | expand_cmp_i32(dofs, aofs, bofs, oprsz, cond); | |
3824 | } else { | |
3825 | gen_helper_gvec_3 * const *fn = fns[cond]; | |
3826 | ||
3827 | if (fn == NULL) { | |
3828 | uint32_t tmp; | |
3829 | tmp = aofs, aofs = bofs, bofs = tmp; | |
3830 | cond = tcg_swap_cond(cond); | |
3831 | fn = fns[cond]; | |
3832 | assert(fn != NULL); | |
3833 | } | |
3834 | tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]); | |
53229a77 | 3835 | oprsz = maxsz; |
212be173 | 3836 | } |
adb196cb RH |
3837 | break; |
3838 | ||
3839 | default: | |
3840 | g_assert_not_reached(); | |
212be173 | 3841 | } |
53229a77 | 3842 | tcg_swap_vecop_list(hold_list); |
212be173 | 3843 | |
212be173 RH |
3844 | if (oprsz < maxsz) { |
3845 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
3846 | } | |
3847 | } | |
38dc1294 | 3848 | |
9622c697 RH |
3849 | static void expand_cmps_vec(unsigned vece, uint32_t dofs, uint32_t aofs, |
3850 | uint32_t oprsz, uint32_t tysz, TCGType type, | |
3851 | TCGCond cond, TCGv_vec c) | |
3852 | { | |
3853 | TCGv_vec t0 = tcg_temp_new_vec(type); | |
3854 | TCGv_vec t1 = tcg_temp_new_vec(type); | |
3855 | uint32_t i; | |
3856 | ||
3857 | for (i = 0; i < oprsz; i += tysz) { | |
3858 | tcg_gen_ld_vec(t1, cpu_env, aofs + i); | |
3859 | tcg_gen_cmp_vec(cond, vece, t0, t1, c); | |
3860 | tcg_gen_st_vec(t0, cpu_env, dofs + i); | |
3861 | } | |
3862 | } | |
3863 | ||
3864 | void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece, uint32_t dofs, | |
3865 | uint32_t aofs, TCGv_i64 c, | |
3866 | uint32_t oprsz, uint32_t maxsz) | |
3867 | { | |
3868 | static const TCGOpcode cmp_list[] = { INDEX_op_cmp_vec, 0 }; | |
3869 | static gen_helper_gvec_2i * const eq_fn[4] = { | |
3870 | gen_helper_gvec_eqs8, gen_helper_gvec_eqs16, | |
3871 | gen_helper_gvec_eqs32, gen_helper_gvec_eqs64 | |
3872 | }; | |
3873 | static gen_helper_gvec_2i * const lt_fn[4] = { | |
3874 | gen_helper_gvec_lts8, gen_helper_gvec_lts16, | |
3875 | gen_helper_gvec_lts32, gen_helper_gvec_lts64 | |
3876 | }; | |
3877 | static gen_helper_gvec_2i * const le_fn[4] = { | |
3878 | gen_helper_gvec_les8, gen_helper_gvec_les16, | |
3879 | gen_helper_gvec_les32, gen_helper_gvec_les64 | |
3880 | }; | |
3881 | static gen_helper_gvec_2i * const ltu_fn[4] = { | |
3882 | gen_helper_gvec_ltus8, gen_helper_gvec_ltus16, | |
3883 | gen_helper_gvec_ltus32, gen_helper_gvec_ltus64 | |
3884 | }; | |
3885 | static gen_helper_gvec_2i * const leu_fn[4] = { | |
3886 | gen_helper_gvec_leus8, gen_helper_gvec_leus16, | |
3887 | gen_helper_gvec_leus32, gen_helper_gvec_leus64 | |
3888 | }; | |
3889 | static gen_helper_gvec_2i * const * const fns[16] = { | |
3890 | [TCG_COND_EQ] = eq_fn, | |
3891 | [TCG_COND_LT] = lt_fn, | |
3892 | [TCG_COND_LE] = le_fn, | |
3893 | [TCG_COND_LTU] = ltu_fn, | |
3894 | [TCG_COND_LEU] = leu_fn, | |
3895 | }; | |
3896 | ||
3897 | TCGType type; | |
3898 | ||
3899 | check_size_align(oprsz, maxsz, dofs | aofs); | |
3900 | check_overlap_2(dofs, aofs, maxsz); | |
3901 | ||
3902 | if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) { | |
3903 | do_dup(MO_8, dofs, oprsz, maxsz, | |
3904 | NULL, NULL, -(cond == TCG_COND_ALWAYS)); | |
3905 | return; | |
3906 | } | |
3907 | ||
3908 | /* | |
3909 | * Implement inline with a vector type, if possible. | |
3910 | * Prefer integer when 64-bit host and 64-bit comparison. | |
3911 | */ | |
3912 | type = choose_vector_type(cmp_list, vece, oprsz, | |
3913 | TCG_TARGET_REG_BITS == 64 && vece == MO_64); | |
3914 | if (type != 0) { | |
3915 | const TCGOpcode *hold_list = tcg_swap_vecop_list(cmp_list); | |
3916 | TCGv_vec t_vec = tcg_temp_new_vec(type); | |
3917 | uint32_t some; | |
3918 | ||
3919 | tcg_gen_dup_i64_vec(vece, t_vec, c); | |
3920 | switch (type) { | |
3921 | case TCG_TYPE_V256: | |
3922 | some = QEMU_ALIGN_DOWN(oprsz, 32); | |
3923 | expand_cmps_vec(vece, dofs, aofs, some, 32, | |
3924 | TCG_TYPE_V256, cond, t_vec); | |
3925 | aofs += some; | |
3926 | dofs += some; | |
3927 | oprsz -= some; | |
3928 | maxsz -= some; | |
3929 | /* fallthru */ | |
3930 | ||
3931 | case TCG_TYPE_V128: | |
3932 | some = QEMU_ALIGN_DOWN(oprsz, 16); | |
3933 | expand_cmps_vec(vece, dofs, aofs, some, 16, | |
3934 | TCG_TYPE_V128, cond, t_vec); | |
3935 | break; | |
3936 | ||
3937 | case TCG_TYPE_V64: | |
3938 | some = QEMU_ALIGN_DOWN(oprsz, 8); | |
3939 | expand_cmps_vec(vece, dofs, aofs, some, 8, | |
3940 | TCG_TYPE_V64, cond, t_vec); | |
3941 | break; | |
3942 | ||
3943 | default: | |
3944 | g_assert_not_reached(); | |
3945 | } | |
3946 | tcg_temp_free_vec(t_vec); | |
3947 | tcg_swap_vecop_list(hold_list); | |
3948 | } else if (vece == MO_64 && check_size_impl(oprsz, 8)) { | |
3949 | TCGv_i64 t0 = tcg_temp_ebb_new_i64(); | |
3950 | uint32_t i; | |
3951 | ||
3952 | for (i = 0; i < oprsz; i += 8) { | |
3953 | tcg_gen_ld_i64(t0, cpu_env, aofs + i); | |
3954 | tcg_gen_negsetcond_i64(cond, t0, t0, c); | |
3955 | tcg_gen_st_i64(t0, cpu_env, dofs + i); | |
3956 | } | |
3957 | tcg_temp_free_i64(t0); | |
3958 | } else if (vece == MO_32 && check_size_impl(oprsz, 4)) { | |
3959 | TCGv_i32 t0 = tcg_temp_ebb_new_i32(); | |
3960 | TCGv_i32 t1 = tcg_temp_ebb_new_i32(); | |
3961 | uint32_t i; | |
3962 | ||
3963 | tcg_gen_extrl_i64_i32(t1, c); | |
3964 | for (i = 0; i < oprsz; i += 8) { | |
3965 | tcg_gen_ld_i32(t0, cpu_env, aofs + i); | |
3966 | tcg_gen_negsetcond_i32(cond, t0, t0, t1); | |
3967 | tcg_gen_st_i32(t0, cpu_env, dofs + i); | |
3968 | } | |
3969 | tcg_temp_free_i32(t0); | |
3970 | tcg_temp_free_i32(t1); | |
3971 | } else { | |
3972 | gen_helper_gvec_2i * const *fn = fns[cond]; | |
3973 | bool inv = false; | |
3974 | ||
3975 | if (fn == NULL) { | |
3976 | cond = tcg_invert_cond(cond); | |
3977 | fn = fns[cond]; | |
3978 | assert(fn != NULL); | |
3979 | inv = true; | |
3980 | } | |
3981 | tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, inv, fn[vece]); | |
3982 | return; | |
3983 | } | |
3984 | ||
3985 | if (oprsz < maxsz) { | |
3986 | expand_clr(dofs + oprsz, maxsz - oprsz); | |
3987 | } | |
3988 | } | |
3989 | ||
3990 | void tcg_gen_gvec_cmpi(TCGCond cond, unsigned vece, uint32_t dofs, | |
3991 | uint32_t aofs, int64_t c, | |
3992 | uint32_t oprsz, uint32_t maxsz) | |
3993 | { | |
3994 | TCGv_i64 tmp = tcg_constant_i64(c); | |
3995 | tcg_gen_gvec_cmps(cond, vece, dofs, aofs, tmp, oprsz, maxsz); | |
3996 | } | |
3997 | ||
38dc1294 RH |
3998 | static void tcg_gen_bitsel_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c) |
3999 | { | |
5dd48602 | 4000 | TCGv_i64 t = tcg_temp_ebb_new_i64(); |
38dc1294 RH |
4001 | |
4002 | tcg_gen_and_i64(t, b, a); | |
4003 | tcg_gen_andc_i64(d, c, a); | |
4004 | tcg_gen_or_i64(d, d, t); | |
4005 | tcg_temp_free_i64(t); | |
4006 | } | |
4007 | ||
4008 | void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs, | |
4009 | uint32_t bofs, uint32_t cofs, | |
4010 | uint32_t oprsz, uint32_t maxsz) | |
4011 | { | |
4012 | static const GVecGen4 g = { | |
4013 | .fni8 = tcg_gen_bitsel_i64, | |
4014 | .fniv = tcg_gen_bitsel_vec, | |
4015 | .fno = gen_helper_gvec_bitsel, | |
4016 | }; | |
4017 | ||
4018 | tcg_gen_gvec_4(dofs, aofs, bofs, cofs, oprsz, maxsz, &g); | |
4019 | } |