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Commit | Line | Data |
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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
951c6300 | 24 | |
c896fe29 | 25 | #include "tcg.h" |
944eea96 | 26 | #include "exec/helper-proto.h" |
c017230d RH |
27 | #include "exec/helper-gen.h" |
28 | ||
951c6300 | 29 | /* Basic output routines. Not for general consumption. */ |
c896fe29 | 30 | |
b7e8b17a RH |
31 | void tcg_gen_op1(TCGOpcode, TCGArg); |
32 | void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); | |
33 | void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); | |
34 | void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); | |
35 | void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); | |
36 | void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); | |
951c6300 RH |
37 | |
38 | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) | |
c896fe29 | 39 | { |
ae8b75dc | 40 | tcg_gen_op1(opc, tcgv_i32_arg(a1)); |
a7812ae4 PB |
41 | } |
42 | ||
951c6300 | 43 | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) |
a7812ae4 | 44 | { |
ae8b75dc | 45 | tcg_gen_op1(opc, tcgv_i64_arg(a1)); |
c896fe29 FB |
46 | } |
47 | ||
951c6300 | 48 | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) |
c896fe29 | 49 | { |
b7e8b17a | 50 | tcg_gen_op1(opc, a1); |
c896fe29 FB |
51 | } |
52 | ||
951c6300 | 53 | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) |
a7812ae4 | 54 | { |
ae8b75dc | 55 | tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); |
a7812ae4 PB |
56 | } |
57 | ||
951c6300 | 58 | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) |
a7812ae4 | 59 | { |
ae8b75dc | 60 | tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); |
a7812ae4 PB |
61 | } |
62 | ||
951c6300 | 63 | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) |
c896fe29 | 64 | { |
ae8b75dc | 65 | tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); |
c896fe29 FB |
66 | } |
67 | ||
951c6300 | 68 | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) |
c896fe29 | 69 | { |
ae8b75dc | 70 | tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); |
ac56dd48 PB |
71 | } |
72 | ||
951c6300 | 73 | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) |
bcb0126f | 74 | { |
b7e8b17a | 75 | tcg_gen_op2(opc, a1, a2); |
bcb0126f PB |
76 | } |
77 | ||
951c6300 RH |
78 | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, |
79 | TCGv_i32 a2, TCGv_i32 a3) | |
a7812ae4 | 80 | { |
ae8b75dc | 81 | tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); |
a7812ae4 PB |
82 | } |
83 | ||
951c6300 RH |
84 | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, |
85 | TCGv_i64 a2, TCGv_i64 a3) | |
a7812ae4 | 86 | { |
ae8b75dc | 87 | tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); |
a7812ae4 PB |
88 | } |
89 | ||
951c6300 RH |
90 | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, |
91 | TCGv_i32 a2, TCGArg a3) | |
ac56dd48 | 92 | { |
ae8b75dc | 93 | tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); |
ac56dd48 PB |
94 | } |
95 | ||
951c6300 RH |
96 | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, |
97 | TCGv_i64 a2, TCGArg a3) | |
ac56dd48 | 98 | { |
ae8b75dc | 99 | tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); |
ac56dd48 PB |
100 | } |
101 | ||
a9751609 RH |
102 | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
103 | TCGv_ptr base, TCGArg offset) | |
a7812ae4 | 104 | { |
ae8b75dc | 105 | tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); |
a7812ae4 PB |
106 | } |
107 | ||
a9751609 RH |
108 | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
109 | TCGv_ptr base, TCGArg offset) | |
a7812ae4 | 110 | { |
ae8b75dc | 111 | tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); |
a7812ae4 PB |
112 | } |
113 | ||
951c6300 RH |
114 | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
115 | TCGv_i32 a3, TCGv_i32 a4) | |
a7812ae4 | 116 | { |
ae8b75dc RH |
117 | tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
118 | tcgv_i32_arg(a3), tcgv_i32_arg(a4)); | |
a7812ae4 PB |
119 | } |
120 | ||
951c6300 RH |
121 | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
122 | TCGv_i64 a3, TCGv_i64 a4) | |
a7812ae4 | 123 | { |
ae8b75dc RH |
124 | tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
125 | tcgv_i64_arg(a3), tcgv_i64_arg(a4)); | |
a7812ae4 PB |
126 | } |
127 | ||
951c6300 RH |
128 | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
129 | TCGv_i32 a3, TCGArg a4) | |
a7812ae4 | 130 | { |
ae8b75dc RH |
131 | tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
132 | tcgv_i32_arg(a3), a4); | |
a7812ae4 PB |
133 | } |
134 | ||
951c6300 RH |
135 | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
136 | TCGv_i64 a3, TCGArg a4) | |
ac56dd48 | 137 | { |
ae8b75dc RH |
138 | tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
139 | tcgv_i64_arg(a3), a4); | |
ac56dd48 PB |
140 | } |
141 | ||
951c6300 RH |
142 | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
143 | TCGArg a3, TCGArg a4) | |
ac56dd48 | 144 | { |
ae8b75dc | 145 | tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); |
c896fe29 FB |
146 | } |
147 | ||
951c6300 RH |
148 | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
149 | TCGArg a3, TCGArg a4) | |
c896fe29 | 150 | { |
ae8b75dc | 151 | tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); |
ac56dd48 PB |
152 | } |
153 | ||
951c6300 RH |
154 | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
155 | TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) | |
a7812ae4 | 156 | { |
ae8b75dc RH |
157 | tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
158 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); | |
a7812ae4 PB |
159 | } |
160 | ||
951c6300 RH |
161 | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
162 | TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) | |
a7812ae4 | 163 | { |
ae8b75dc RH |
164 | tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
165 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); | |
a7812ae4 PB |
166 | } |
167 | ||
951c6300 RH |
168 | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
169 | TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) | |
ac56dd48 | 170 | { |
ae8b75dc RH |
171 | tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
172 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); | |
ac56dd48 PB |
173 | } |
174 | ||
951c6300 RH |
175 | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
176 | TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) | |
ac56dd48 | 177 | { |
ae8b75dc RH |
178 | tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
179 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); | |
c896fe29 FB |
180 | } |
181 | ||
951c6300 RH |
182 | static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
183 | TCGv_i32 a3, TCGArg a4, TCGArg a5) | |
b7767f0f | 184 | { |
ae8b75dc RH |
185 | tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
186 | tcgv_i32_arg(a3), a4, a5); | |
b7767f0f RH |
187 | } |
188 | ||
951c6300 RH |
189 | static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
190 | TCGv_i64 a3, TCGArg a4, TCGArg a5) | |
b7767f0f | 191 | { |
ae8b75dc RH |
192 | tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
193 | tcgv_i64_arg(a3), a4, a5); | |
b7767f0f RH |
194 | } |
195 | ||
951c6300 RH |
196 | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
197 | TCGv_i32 a3, TCGv_i32 a4, | |
198 | TCGv_i32 a5, TCGv_i32 a6) | |
a7812ae4 | 199 | { |
ae8b75dc RH |
200 | tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
201 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), | |
202 | tcgv_i32_arg(a6)); | |
a7812ae4 PB |
203 | } |
204 | ||
951c6300 RH |
205 | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
206 | TCGv_i64 a3, TCGv_i64 a4, | |
207 | TCGv_i64 a5, TCGv_i64 a6) | |
c896fe29 | 208 | { |
ae8b75dc RH |
209 | tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
210 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), | |
211 | tcgv_i64_arg(a6)); | |
ac56dd48 PB |
212 | } |
213 | ||
951c6300 RH |
214 | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
215 | TCGv_i32 a3, TCGv_i32 a4, | |
216 | TCGv_i32 a5, TCGArg a6) | |
be210acb | 217 | { |
ae8b75dc RH |
218 | tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
219 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); | |
be210acb RH |
220 | } |
221 | ||
951c6300 RH |
222 | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
223 | TCGv_i64 a3, TCGv_i64 a4, | |
224 | TCGv_i64 a5, TCGArg a6) | |
be210acb | 225 | { |
ae8b75dc RH |
226 | tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
227 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); | |
be210acb RH |
228 | } |
229 | ||
951c6300 RH |
230 | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
231 | TCGv_i32 a3, TCGv_i32 a4, | |
232 | TCGArg a5, TCGArg a6) | |
ac56dd48 | 233 | { |
ae8b75dc RH |
234 | tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
235 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); | |
a7812ae4 PB |
236 | } |
237 | ||
951c6300 RH |
238 | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
239 | TCGv_i64 a3, TCGv_i64 a4, | |
240 | TCGArg a5, TCGArg a6) | |
a7812ae4 | 241 | { |
ae8b75dc RH |
242 | tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
243 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); | |
c896fe29 FB |
244 | } |
245 | ||
f713d6ad | 246 | |
951c6300 RH |
247 | /* Generic ops. */ |
248 | ||
42a268c2 | 249 | static inline void gen_set_label(TCGLabel *l) |
c896fe29 | 250 | { |
b7e8b17a | 251 | tcg_gen_op1(INDEX_op_set_label, label_arg(l)); |
c896fe29 FB |
252 | } |
253 | ||
42a268c2 | 254 | static inline void tcg_gen_br(TCGLabel *l) |
fb50d413 | 255 | { |
b7e8b17a | 256 | tcg_gen_op1(INDEX_op_br, label_arg(l)); |
951c6300 RH |
257 | } |
258 | ||
f65e19bc PK |
259 | void tcg_gen_mb(TCGBar); |
260 | ||
951c6300 RH |
261 | /* Helper calls. */ |
262 | ||
263 | /* 32 bit ops */ | |
264 | ||
265 | void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
266 | void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); | |
267 | void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
268 | void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); | |
269 | void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
270 | void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
271 | void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
272 | void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
273 | void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
274 | void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
275 | void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
276 | void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
277 | void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
278 | void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
279 | void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
280 | void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
281 | void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
282 | void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
283 | void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
0e28d006 RH |
284 | void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
285 | void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
286 | void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); | |
287 | void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); | |
086920c2 | 288 | void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); |
a768e4e9 | 289 | void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); |
951c6300 RH |
290 | void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
291 | void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
292 | void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
293 | void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
294 | void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, | |
295 | unsigned int ofs, unsigned int len); | |
07cc68d5 RH |
296 | void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, |
297 | unsigned int ofs, unsigned int len); | |
7ec8bab3 RH |
298 | void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, |
299 | unsigned int ofs, unsigned int len); | |
300 | void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, | |
301 | unsigned int ofs, unsigned int len); | |
42a268c2 RH |
302 | void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); |
303 | void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); | |
951c6300 RH |
304 | void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
305 | TCGv_i32 arg1, TCGv_i32 arg2); | |
306 | void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, | |
307 | TCGv_i32 arg1, int32_t arg2); | |
308 | void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, | |
309 | TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); | |
310 | void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, | |
311 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); | |
312 | void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, | |
313 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); | |
314 | void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); | |
315 | void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); | |
5087abfb | 316 | void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
951c6300 RH |
317 | void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); |
318 | void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); | |
319 | void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); | |
320 | void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); | |
321 | void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg); | |
322 | void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); | |
323 | ||
324 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) | |
325 | { | |
326 | tcg_gen_op1_i32(INDEX_op_discard, arg); | |
fb50d413 BS |
327 | } |
328 | ||
a7812ae4 | 329 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 330 | { |
11f4e8f8 | 331 | if (ret != arg) { |
a7812ae4 | 332 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
951c6300 | 333 | } |
c896fe29 FB |
334 | } |
335 | ||
a7812ae4 | 336 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
c896fe29 | 337 | { |
a7812ae4 | 338 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
c896fe29 FB |
339 | } |
340 | ||
951c6300 RH |
341 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
342 | tcg_target_long offset) | |
c896fe29 | 343 | { |
a7812ae4 | 344 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
c896fe29 FB |
345 | } |
346 | ||
951c6300 RH |
347 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
348 | tcg_target_long offset) | |
c896fe29 | 349 | { |
a7812ae4 | 350 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
c896fe29 FB |
351 | } |
352 | ||
951c6300 RH |
353 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
354 | tcg_target_long offset) | |
c896fe29 | 355 | { |
a7812ae4 | 356 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
c896fe29 FB |
357 | } |
358 | ||
951c6300 RH |
359 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
360 | tcg_target_long offset) | |
c896fe29 | 361 | { |
a7812ae4 | 362 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
c896fe29 FB |
363 | } |
364 | ||
951c6300 RH |
365 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, |
366 | tcg_target_long offset) | |
c896fe29 | 367 | { |
a7812ae4 | 368 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
c896fe29 FB |
369 | } |
370 | ||
951c6300 RH |
371 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
372 | tcg_target_long offset) | |
c896fe29 | 373 | { |
a7812ae4 | 374 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
c896fe29 FB |
375 | } |
376 | ||
951c6300 RH |
377 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
378 | tcg_target_long offset) | |
c896fe29 | 379 | { |
a7812ae4 | 380 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
c896fe29 FB |
381 | } |
382 | ||
951c6300 RH |
383 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
384 | tcg_target_long offset) | |
c896fe29 | 385 | { |
a7812ae4 | 386 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
c896fe29 FB |
387 | } |
388 | ||
a7812ae4 | 389 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 390 | { |
a7812ae4 | 391 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
c896fe29 FB |
392 | } |
393 | ||
a7812ae4 | 394 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 395 | { |
a7812ae4 | 396 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
c896fe29 FB |
397 | } |
398 | ||
a7812ae4 | 399 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 400 | { |
951c6300 | 401 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
c896fe29 FB |
402 | } |
403 | ||
a7812ae4 | 404 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 405 | { |
951c6300 | 406 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
c896fe29 FB |
407 | } |
408 | ||
a7812ae4 | 409 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 410 | { |
951c6300 | 411 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
c896fe29 FB |
412 | } |
413 | ||
a7812ae4 | 414 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 415 | { |
a7812ae4 | 416 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
c896fe29 FB |
417 | } |
418 | ||
a7812ae4 | 419 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 420 | { |
a7812ae4 | 421 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
c896fe29 FB |
422 | } |
423 | ||
a7812ae4 | 424 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 425 | { |
a7812ae4 | 426 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
c896fe29 FB |
427 | } |
428 | ||
a7812ae4 | 429 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 430 | { |
a7812ae4 | 431 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
c896fe29 FB |
432 | } |
433 | ||
951c6300 | 434 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 435 | { |
951c6300 RH |
436 | if (TCG_TARGET_HAS_neg_i32) { |
437 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); | |
25c4d9cc | 438 | } else { |
951c6300 | 439 | tcg_gen_subfi_i32(ret, 0, arg); |
25c4d9cc | 440 | } |
31d66551 AJ |
441 | } |
442 | ||
951c6300 | 443 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
31d66551 | 444 | { |
951c6300 RH |
445 | if (TCG_TARGET_HAS_not_i32) { |
446 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); | |
25c4d9cc | 447 | } else { |
951c6300 | 448 | tcg_gen_xori_i32(ret, arg, -1); |
25c4d9cc | 449 | } |
31d66551 AJ |
450 | } |
451 | ||
951c6300 RH |
452 | /* 64 bit ops */ |
453 | ||
454 | void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
455 | void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); | |
456 | void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
457 | void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); | |
458 | void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
459 | void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
460 | void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
461 | void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
462 | void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
463 | void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
464 | void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
465 | void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
466 | void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
467 | void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
468 | void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
469 | void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
470 | void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
471 | void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
472 | void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
0e28d006 RH |
473 | void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
474 | void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
475 | void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); | |
476 | void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); | |
086920c2 | 477 | void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); |
a768e4e9 | 478 | void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); |
951c6300 RH |
479 | void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
480 | void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
481 | void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
482 | void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
483 | void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, | |
484 | unsigned int ofs, unsigned int len); | |
07cc68d5 RH |
485 | void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, |
486 | unsigned int ofs, unsigned int len); | |
7ec8bab3 RH |
487 | void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, |
488 | unsigned int ofs, unsigned int len); | |
489 | void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, | |
490 | unsigned int ofs, unsigned int len); | |
42a268c2 RH |
491 | void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); |
492 | void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); | |
951c6300 RH |
493 | void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
494 | TCGv_i64 arg1, TCGv_i64 arg2); | |
495 | void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, | |
496 | TCGv_i64 arg1, int64_t arg2); | |
497 | void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, | |
498 | TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); | |
499 | void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, | |
500 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); | |
501 | void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, | |
502 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); | |
503 | void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); | |
504 | void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); | |
5087abfb | 505 | void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
951c6300 RH |
506 | void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); |
507 | void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); | |
508 | void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); | |
509 | void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); | |
510 | void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); | |
511 | void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); | |
512 | void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); | |
513 | void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg); | |
514 | void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg); | |
515 | void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); | |
c896fe29 | 516 | |
951c6300 RH |
517 | #if TCG_TARGET_REG_BITS == 64 |
518 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) | |
519 | { | |
520 | tcg_gen_op1_i64(INDEX_op_discard, arg); | |
521 | } | |
c896fe29 | 522 | |
a7812ae4 | 523 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 524 | { |
11f4e8f8 | 525 | if (ret != arg) { |
951c6300 | 526 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
4d07272d | 527 | } |
c896fe29 FB |
528 | } |
529 | ||
a7812ae4 | 530 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 531 | { |
951c6300 | 532 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
c896fe29 FB |
533 | } |
534 | ||
a7812ae4 PB |
535 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
536 | tcg_target_long offset) | |
c896fe29 | 537 | { |
951c6300 | 538 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
c896fe29 FB |
539 | } |
540 | ||
a7812ae4 PB |
541 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
542 | tcg_target_long offset) | |
c896fe29 | 543 | { |
951c6300 | 544 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
c896fe29 FB |
545 | } |
546 | ||
a7812ae4 PB |
547 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
548 | tcg_target_long offset) | |
c896fe29 | 549 | { |
951c6300 | 550 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
c896fe29 FB |
551 | } |
552 | ||
a7812ae4 PB |
553 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
554 | tcg_target_long offset) | |
c896fe29 | 555 | { |
951c6300 | 556 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
c896fe29 FB |
557 | } |
558 | ||
a7812ae4 PB |
559 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
560 | tcg_target_long offset) | |
c896fe29 | 561 | { |
951c6300 | 562 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
c896fe29 FB |
563 | } |
564 | ||
a7812ae4 PB |
565 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
566 | tcg_target_long offset) | |
c896fe29 | 567 | { |
951c6300 | 568 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
c896fe29 FB |
569 | } |
570 | ||
a7812ae4 PB |
571 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
572 | tcg_target_long offset) | |
c896fe29 | 573 | { |
951c6300 | 574 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
c896fe29 FB |
575 | } |
576 | ||
a7812ae4 PB |
577 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
578 | tcg_target_long offset) | |
c896fe29 | 579 | { |
951c6300 | 580 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
c896fe29 FB |
581 | } |
582 | ||
a7812ae4 PB |
583 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
584 | tcg_target_long offset) | |
c896fe29 | 585 | { |
951c6300 | 586 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
c896fe29 FB |
587 | } |
588 | ||
a7812ae4 PB |
589 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
590 | tcg_target_long offset) | |
c896fe29 | 591 | { |
951c6300 | 592 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
c896fe29 FB |
593 | } |
594 | ||
a7812ae4 PB |
595 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
596 | tcg_target_long offset) | |
c896fe29 | 597 | { |
951c6300 | 598 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
c896fe29 FB |
599 | } |
600 | ||
a7812ae4 | 601 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 602 | { |
951c6300 | 603 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
c896fe29 FB |
604 | } |
605 | ||
a7812ae4 | 606 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 607 | { |
951c6300 | 608 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
c896fe29 FB |
609 | } |
610 | ||
a7812ae4 | 611 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 612 | { |
951c6300 | 613 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
c896fe29 FB |
614 | } |
615 | ||
a7812ae4 | 616 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 617 | { |
951c6300 | 618 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
c896fe29 FB |
619 | } |
620 | ||
a7812ae4 | 621 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 622 | { |
951c6300 | 623 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
c896fe29 FB |
624 | } |
625 | ||
a7812ae4 | 626 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 627 | { |
951c6300 | 628 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
629 | } |
630 | ||
a7812ae4 | 631 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 632 | { |
951c6300 | 633 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
634 | } |
635 | ||
a7812ae4 | 636 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 637 | { |
951c6300 | 638 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
5105c556 AJ |
639 | } |
640 | ||
a7812ae4 | 641 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 642 | { |
951c6300 | 643 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
c896fe29 | 644 | } |
951c6300 RH |
645 | #else /* TCG_TARGET_REG_BITS == 32 */ |
646 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, | |
647 | tcg_target_long offset) | |
c896fe29 | 648 | { |
951c6300 | 649 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
650 | } |
651 | ||
951c6300 RH |
652 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
653 | tcg_target_long offset) | |
c896fe29 | 654 | { |
951c6300 | 655 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
656 | } |
657 | ||
951c6300 RH |
658 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
659 | tcg_target_long offset) | |
c896fe29 | 660 | { |
951c6300 | 661 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
662 | } |
663 | ||
951c6300 | 664 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 665 | { |
951c6300 RH |
666 | tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
667 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); | |
c896fe29 FB |
668 | } |
669 | ||
951c6300 | 670 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 671 | { |
951c6300 RH |
672 | tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
673 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); | |
674 | } | |
675 | ||
676 | void tcg_gen_discard_i64(TCGv_i64 arg); | |
677 | void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); | |
678 | void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); | |
679 | void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
680 | void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
681 | void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
682 | void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
683 | void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
684 | void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
685 | void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
686 | void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); | |
687 | void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
688 | void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
689 | void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
690 | void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
691 | void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
692 | void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
693 | void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
694 | #endif /* TCG_TARGET_REG_BITS */ | |
c896fe29 | 695 | |
951c6300 | 696 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 697 | { |
951c6300 RH |
698 | if (TCG_TARGET_HAS_neg_i64) { |
699 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); | |
700 | } else { | |
701 | tcg_gen_subfi_i64(ret, 0, arg); | |
702 | } | |
c896fe29 FB |
703 | } |
704 | ||
951c6300 | 705 | /* Size changing operations. */ |
c896fe29 | 706 | |
951c6300 RH |
707 | void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); |
708 | void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); | |
709 | void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); | |
609ad705 RH |
710 | void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); |
711 | void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); | |
951c6300 RH |
712 | void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); |
713 | void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); | |
c896fe29 | 714 | |
951c6300 | 715 | static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) |
c896fe29 | 716 | { |
951c6300 | 717 | tcg_gen_deposit_i64(ret, lo, hi, 32, 32); |
c896fe29 FB |
718 | } |
719 | ||
951c6300 | 720 | /* QEMU specific operations. */ |
c896fe29 | 721 | |
951c6300 RH |
722 | #ifndef TARGET_LONG_BITS |
723 | #error must include QEMU headers | |
724 | #endif | |
c896fe29 | 725 | |
9aef40ed RH |
726 | #if TARGET_INSN_START_WORDS == 1 |
727 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
728 | static inline void tcg_gen_insn_start(target_ulong pc) | |
c896fe29 | 729 | { |
b7e8b17a | 730 | tcg_gen_op1(INDEX_op_insn_start, pc); |
9aef40ed RH |
731 | } |
732 | # else | |
733 | static inline void tcg_gen_insn_start(target_ulong pc) | |
734 | { | |
b7e8b17a | 735 | tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); |
9aef40ed RH |
736 | } |
737 | # endif | |
738 | #elif TARGET_INSN_START_WORDS == 2 | |
739 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
740 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) | |
741 | { | |
b7e8b17a | 742 | tcg_gen_op2(INDEX_op_insn_start, pc, a1); |
9aef40ed RH |
743 | } |
744 | # else | |
745 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) | |
746 | { | |
b7e8b17a | 747 | tcg_gen_op4(INDEX_op_insn_start, |
9aef40ed RH |
748 | (uint32_t)pc, (uint32_t)(pc >> 32), |
749 | (uint32_t)a1, (uint32_t)(a1 >> 32)); | |
750 | } | |
751 | # endif | |
752 | #elif TARGET_INSN_START_WORDS == 3 | |
753 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
754 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, | |
755 | target_ulong a2) | |
756 | { | |
b7e8b17a | 757 | tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2); |
9aef40ed RH |
758 | } |
759 | # else | |
760 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, | |
761 | target_ulong a2) | |
762 | { | |
b7e8b17a | 763 | tcg_gen_op6(INDEX_op_insn_start, |
9aef40ed RH |
764 | (uint32_t)pc, (uint32_t)(pc >> 32), |
765 | (uint32_t)a1, (uint32_t)(a1 >> 32), | |
766 | (uint32_t)a2, (uint32_t)(a2 >> 32)); | |
767 | } | |
768 | # endif | |
951c6300 | 769 | #else |
9aef40ed | 770 | # error "Unhandled number of operands to insn_start" |
951c6300 | 771 | #endif |
c896fe29 | 772 | |
951c6300 | 773 | static inline void tcg_gen_exit_tb(uintptr_t val) |
c896fe29 | 774 | { |
951c6300 | 775 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
c896fe29 FB |
776 | } |
777 | ||
5b053a4a SF |
778 | /** |
779 | * tcg_gen_goto_tb() - output goto_tb TCG operation | |
780 | * @idx: Direct jump slot index (0 or 1) | |
781 | * | |
782 | * See tcg/README for more info about this TCG operation. | |
783 | * | |
90aa39a1 SF |
784 | * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within |
785 | * the pages this TB resides in because we don't take care of direct jumps when | |
786 | * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a | |
787 | * static address translation, so the destination address is always valid, TBs | |
788 | * are always invalidated properly, and direct jumps are reset when mapping | |
789 | * changes. | |
5b053a4a | 790 | */ |
951c6300 | 791 | void tcg_gen_goto_tb(unsigned idx); |
c896fe29 | 792 | |
cedbcb01 | 793 | /** |
7f11636d | 794 | * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid |
cedbcb01 EC |
795 | * @addr: Guest address of the target TB |
796 | * | |
797 | * If the TB is not valid, jump to the epilogue. | |
798 | * | |
799 | * This operation is optional. If the TCG backend does not implement goto_ptr, | |
800 | * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument. | |
801 | */ | |
7f11636d | 802 | void tcg_gen_lookup_and_goto_ptr(void); |
cedbcb01 | 803 | |
a7812ae4 | 804 | #if TARGET_LONG_BITS == 32 |
a7812ae4 PB |
805 | #define tcg_temp_new() tcg_temp_new_i32() |
806 | #define tcg_global_reg_new tcg_global_reg_new_i32 | |
807 | #define tcg_global_mem_new tcg_global_mem_new_i32 | |
df9247b2 | 808 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
a7812ae4 | 809 | #define tcg_temp_free tcg_temp_free_i32 |
a7812ae4 | 810 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) |
afcb92be | 811 | #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x) |
f713d6ad RH |
812 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 |
813 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 | |
a7812ae4 | 814 | #else |
a7812ae4 PB |
815 | #define tcg_temp_new() tcg_temp_new_i64() |
816 | #define tcg_global_reg_new tcg_global_reg_new_i64 | |
817 | #define tcg_global_mem_new tcg_global_mem_new_i64 | |
df9247b2 | 818 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
a7812ae4 | 819 | #define tcg_temp_free tcg_temp_free_i64 |
a7812ae4 | 820 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) |
afcb92be | 821 | #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x) |
f713d6ad RH |
822 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 |
823 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 | |
a7812ae4 PB |
824 | #endif |
825 | ||
f713d6ad RH |
826 | void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); |
827 | void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); | |
828 | void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); | |
829 | void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); | |
c896fe29 | 830 | |
ac56dd48 | 831 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 832 | { |
f713d6ad | 833 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB); |
c896fe29 FB |
834 | } |
835 | ||
ac56dd48 | 836 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 837 | { |
f713d6ad | 838 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB); |
c896fe29 FB |
839 | } |
840 | ||
ac56dd48 | 841 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 842 | { |
f713d6ad | 843 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW); |
c896fe29 FB |
844 | } |
845 | ||
ac56dd48 | 846 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 847 | { |
f713d6ad | 848 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW); |
c896fe29 FB |
849 | } |
850 | ||
ac56dd48 | 851 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 852 | { |
f713d6ad | 853 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL); |
c896fe29 FB |
854 | } |
855 | ||
ac56dd48 | 856 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 857 | { |
f713d6ad | 858 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL); |
c896fe29 FB |
859 | } |
860 | ||
a7812ae4 | 861 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 | 862 | { |
f713d6ad | 863 | tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ); |
c896fe29 FB |
864 | } |
865 | ||
ac56dd48 | 866 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 867 | { |
f713d6ad | 868 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB); |
c896fe29 FB |
869 | } |
870 | ||
ac56dd48 | 871 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 872 | { |
f713d6ad | 873 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW); |
c896fe29 FB |
874 | } |
875 | ||
ac56dd48 | 876 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 877 | { |
f713d6ad | 878 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL); |
c896fe29 FB |
879 | } |
880 | ||
a7812ae4 | 881 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 | 882 | { |
f713d6ad | 883 | tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ); |
c896fe29 FB |
884 | } |
885 | ||
c482cb11 RH |
886 | void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, |
887 | TCGArg, TCGMemOp); | |
888 | void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, | |
889 | TCGArg, TCGMemOp); | |
890 | ||
891 | void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); | |
892 | void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); | |
893 | void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); | |
894 | void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); | |
895 | void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); | |
896 | void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); | |
897 | void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); | |
898 | void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); | |
899 | void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); | |
900 | void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); | |
901 | void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); | |
902 | void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); | |
903 | void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); | |
904 | void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); | |
905 | void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); | |
906 | void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); | |
907 | void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); | |
908 | void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); | |
909 | ||
f8422f52 | 910 | #if TARGET_LONG_BITS == 64 |
f8422f52 BS |
911 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
912 | #define tcg_gen_mov_tl tcg_gen_mov_i64 | |
913 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 | |
914 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 | |
915 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 | |
916 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 | |
917 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 | |
918 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 | |
919 | #define tcg_gen_ld_tl tcg_gen_ld_i64 | |
920 | #define tcg_gen_st8_tl tcg_gen_st8_i64 | |
921 | #define tcg_gen_st16_tl tcg_gen_st16_i64 | |
922 | #define tcg_gen_st32_tl tcg_gen_st32_i64 | |
923 | #define tcg_gen_st_tl tcg_gen_st_i64 | |
924 | #define tcg_gen_add_tl tcg_gen_add_i64 | |
925 | #define tcg_gen_addi_tl tcg_gen_addi_i64 | |
926 | #define tcg_gen_sub_tl tcg_gen_sub_i64 | |
390efc54 | 927 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
10460c8a | 928 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
f8422f52 BS |
929 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
930 | #define tcg_gen_and_tl tcg_gen_and_i64 | |
931 | #define tcg_gen_andi_tl tcg_gen_andi_i64 | |
932 | #define tcg_gen_or_tl tcg_gen_or_i64 | |
933 | #define tcg_gen_ori_tl tcg_gen_ori_i64 | |
934 | #define tcg_gen_xor_tl tcg_gen_xor_i64 | |
935 | #define tcg_gen_xori_tl tcg_gen_xori_i64 | |
0b6ce4cf | 936 | #define tcg_gen_not_tl tcg_gen_not_i64 |
f8422f52 BS |
937 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
938 | #define tcg_gen_shli_tl tcg_gen_shli_i64 | |
939 | #define tcg_gen_shr_tl tcg_gen_shr_i64 | |
940 | #define tcg_gen_shri_tl tcg_gen_shri_i64 | |
941 | #define tcg_gen_sar_tl tcg_gen_sar_i64 | |
942 | #define tcg_gen_sari_tl tcg_gen_sari_i64 | |
0cf767d6 | 943 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
cb63669a | 944 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
be210acb | 945 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
add1e7ea | 946 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
f730fd27 TS |
947 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
948 | #define tcg_gen_muli_tl tcg_gen_muli_i64 | |
ab36421e AJ |
949 | #define tcg_gen_div_tl tcg_gen_div_i64 |
950 | #define tcg_gen_rem_tl tcg_gen_rem_i64 | |
864951af AJ |
951 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
952 | #define tcg_gen_remu_tl tcg_gen_remu_i64 | |
a768e4b2 | 953 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
ecc7b3aa | 954 | #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 |
e429073d BS |
955 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 |
956 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 | |
957 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 | |
958 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 | |
959 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 | |
0b6ce4cf FB |
960 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
961 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 | |
962 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 | |
963 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 | |
964 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 | |
965 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 | |
911d79ba AJ |
966 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
967 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 | |
968 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 | |
945ca823 | 969 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
3c51a985 | 970 | #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 |
f24cb33e AJ |
971 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
972 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 | |
973 | #define tcg_gen_nand_tl tcg_gen_nand_i64 | |
974 | #define tcg_gen_nor_tl tcg_gen_nor_i64 | |
975 | #define tcg_gen_orc_tl tcg_gen_orc_i64 | |
0e28d006 RH |
976 | #define tcg_gen_clz_tl tcg_gen_clz_i64 |
977 | #define tcg_gen_ctz_tl tcg_gen_ctz_i64 | |
978 | #define tcg_gen_clzi_tl tcg_gen_clzi_i64 | |
979 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 | |
086920c2 | 980 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64 |
a768e4e9 | 981 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64 |
15824571 AJ |
982 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
983 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 | |
984 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 | |
985 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 | |
b7767f0f | 986 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
07cc68d5 | 987 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 |
7ec8bab3 RH |
988 | #define tcg_gen_extract_tl tcg_gen_extract_i64 |
989 | #define tcg_gen_sextract_tl tcg_gen_sextract_i64 | |
a98824ac | 990 | #define tcg_const_tl tcg_const_i64 |
bdffd4a9 | 991 | #define tcg_const_local_tl tcg_const_local_i64 |
ffc5ea09 | 992 | #define tcg_gen_movcond_tl tcg_gen_movcond_i64 |
f6953a73 RH |
993 | #define tcg_gen_add2_tl tcg_gen_add2_i64 |
994 | #define tcg_gen_sub2_tl tcg_gen_sub2_i64 | |
696a8be6 RH |
995 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 |
996 | #define tcg_gen_muls2_tl tcg_gen_muls2_i64 | |
5087abfb | 997 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 |
c482cb11 RH |
998 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 |
999 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 | |
1000 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 | |
1001 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64 | |
1002 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64 | |
1003 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64 | |
1004 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64 | |
1005 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64 | |
1006 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64 | |
1007 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64 | |
f8422f52 | 1008 | #else |
f8422f52 BS |
1009 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
1010 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | |
1011 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 | |
1012 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 | |
1013 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 | |
1014 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 | |
1015 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 | |
1016 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 | |
1017 | #define tcg_gen_ld_tl tcg_gen_ld_i32 | |
1018 | #define tcg_gen_st8_tl tcg_gen_st8_i32 | |
1019 | #define tcg_gen_st16_tl tcg_gen_st16_i32 | |
1020 | #define tcg_gen_st32_tl tcg_gen_st_i32 | |
1021 | #define tcg_gen_st_tl tcg_gen_st_i32 | |
1022 | #define tcg_gen_add_tl tcg_gen_add_i32 | |
1023 | #define tcg_gen_addi_tl tcg_gen_addi_i32 | |
1024 | #define tcg_gen_sub_tl tcg_gen_sub_i32 | |
390efc54 | 1025 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
0045734a | 1026 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
f8422f52 BS |
1027 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
1028 | #define tcg_gen_and_tl tcg_gen_and_i32 | |
1029 | #define tcg_gen_andi_tl tcg_gen_andi_i32 | |
1030 | #define tcg_gen_or_tl tcg_gen_or_i32 | |
1031 | #define tcg_gen_ori_tl tcg_gen_ori_i32 | |
1032 | #define tcg_gen_xor_tl tcg_gen_xor_i32 | |
1033 | #define tcg_gen_xori_tl tcg_gen_xori_i32 | |
0b6ce4cf | 1034 | #define tcg_gen_not_tl tcg_gen_not_i32 |
f8422f52 BS |
1035 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
1036 | #define tcg_gen_shli_tl tcg_gen_shli_i32 | |
1037 | #define tcg_gen_shr_tl tcg_gen_shr_i32 | |
1038 | #define tcg_gen_shri_tl tcg_gen_shri_i32 | |
1039 | #define tcg_gen_sar_tl tcg_gen_sar_i32 | |
1040 | #define tcg_gen_sari_tl tcg_gen_sari_i32 | |
0cf767d6 | 1041 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
cb63669a | 1042 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
be210acb | 1043 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
add1e7ea | 1044 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
f730fd27 TS |
1045 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
1046 | #define tcg_gen_muli_tl tcg_gen_muli_i32 | |
ab36421e AJ |
1047 | #define tcg_gen_div_tl tcg_gen_div_i32 |
1048 | #define tcg_gen_rem_tl tcg_gen_rem_i32 | |
864951af AJ |
1049 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
1050 | #define tcg_gen_remu_tl tcg_gen_remu_i32 | |
a768e4b2 | 1051 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
e429073d | 1052 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
ecc7b3aa | 1053 | #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 |
e429073d BS |
1054 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 |
1055 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 | |
1056 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 | |
1057 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 | |
0b6ce4cf FB |
1058 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
1059 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 | |
1060 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 | |
1061 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 | |
1062 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 | |
1063 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 | |
911d79ba AJ |
1064 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
1065 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 | |
945ca823 | 1066 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
e3eb9806 | 1067 | #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 |
f24cb33e AJ |
1068 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
1069 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 | |
1070 | #define tcg_gen_nand_tl tcg_gen_nand_i32 | |
1071 | #define tcg_gen_nor_tl tcg_gen_nor_i32 | |
1072 | #define tcg_gen_orc_tl tcg_gen_orc_i32 | |
0e28d006 RH |
1073 | #define tcg_gen_clz_tl tcg_gen_clz_i32 |
1074 | #define tcg_gen_ctz_tl tcg_gen_ctz_i32 | |
1075 | #define tcg_gen_clzi_tl tcg_gen_clzi_i32 | |
1076 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 | |
086920c2 | 1077 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32 |
a768e4e9 | 1078 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32 |
15824571 AJ |
1079 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
1080 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 | |
1081 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 | |
1082 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 | |
b7767f0f | 1083 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
07cc68d5 | 1084 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 |
7ec8bab3 RH |
1085 | #define tcg_gen_extract_tl tcg_gen_extract_i32 |
1086 | #define tcg_gen_sextract_tl tcg_gen_sextract_i32 | |
a98824ac | 1087 | #define tcg_const_tl tcg_const_i32 |
bdffd4a9 | 1088 | #define tcg_const_local_tl tcg_const_local_i32 |
ffc5ea09 | 1089 | #define tcg_gen_movcond_tl tcg_gen_movcond_i32 |
f6953a73 RH |
1090 | #define tcg_gen_add2_tl tcg_gen_add2_i32 |
1091 | #define tcg_gen_sub2_tl tcg_gen_sub2_i32 | |
696a8be6 RH |
1092 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 |
1093 | #define tcg_gen_muls2_tl tcg_gen_muls2_i32 | |
5087abfb | 1094 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 |
c482cb11 RH |
1095 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 |
1096 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 | |
1097 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 | |
1098 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32 | |
1099 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32 | |
1100 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32 | |
1101 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32 | |
1102 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32 | |
1103 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32 | |
1104 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32 | |
f8422f52 | 1105 | #endif |
6ddbc6e4 | 1106 | |
71b92699 | 1107 | #if UINTPTR_MAX == UINT32_MAX |
f713d6ad RH |
1108 | # define tcg_gen_ld_ptr(R, A, O) \ |
1109 | tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O)) | |
1110 | # define tcg_gen_discard_ptr(A) \ | |
1111 | tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A)) | |
1112 | # define tcg_gen_add_ptr(R, A, B) \ | |
1113 | tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) | |
1114 | # define tcg_gen_addi_ptr(R, A, B) \ | |
1115 | tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) | |
1116 | # define tcg_gen_ext_i32_ptr(R, A) \ | |
1117 | tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A)) | |
1118 | #else | |
1119 | # define tcg_gen_ld_ptr(R, A, O) \ | |
1120 | tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O)) | |
1121 | # define tcg_gen_discard_ptr(A) \ | |
1122 | tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A)) | |
1123 | # define tcg_gen_add_ptr(R, A, B) \ | |
1124 | tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) | |
1125 | # define tcg_gen_addi_ptr(R, A, B) \ | |
1126 | tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) | |
1127 | # define tcg_gen_ext_i32_ptr(R, A) \ | |
1128 | tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A)) | |
71b92699 | 1129 | #endif /* UINTPTR_MAX == UINT32_MAX */ |