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block: Fix potential Null pointer dereferences in vvfat.c
[mirror_qemu.git] / tcg / tcg-op.h
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c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
951c6300 24
a7ce790a
PM		 25#ifndef TCG_TCG_OP_H
26#define TCG_TCG_OP_H
27
c896fe29 28#include "tcg.h"
944eea96 29#include "exec/helper-proto.h"
c017230d
RH		 30#include "exec/helper-gen.h"
31
951c6300 32/* Basic output routines. Not for general consumption. */
c896fe29 33
b7e8b17a
RH		 34void tcg_gen_op1(TCGOpcode, TCGArg);
35void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
36void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
37void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
38void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
39void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
951c6300 40
d2fd745f
RH		 41void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
42void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
43void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
44
951c6300 45static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
c896fe29 46{
ae8b75dc 47 tcg_gen_op1(opc, tcgv_i32_arg(a1));
a7812ae4
PB		 48}
49
951c6300 50static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
a7812ae4 51{
ae8b75dc 52 tcg_gen_op1(opc, tcgv_i64_arg(a1));
c896fe29
FB		 53}
54
951c6300 55static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
c896fe29 56{
b7e8b17a 57 tcg_gen_op1(opc, a1);
c896fe29
FB		 58}
59
951c6300 60static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
a7812ae4 61{
ae8b75dc 62 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
a7812ae4
PB		 63}
64
951c6300 65static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
a7812ae4 66{
ae8b75dc 67 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
a7812ae4
PB		 68}
69
951c6300 70static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
c896fe29 71{
ae8b75dc 72 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
c896fe29
FB		 73}
74
951c6300 75static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
c896fe29 76{
ae8b75dc 77 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
ac56dd48
PB		 78}
79
951c6300 80static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
bcb0126f 81{
b7e8b17a 82 tcg_gen_op2(opc, a1, a2);
bcb0126f
PB		 83}
84
951c6300
RH		 85static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
86 TCGv_i32 a2, TCGv_i32 a3)
a7812ae4 87{
ae8b75dc 88 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
a7812ae4
PB		 89}
90
951c6300
RH		 91static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
92 TCGv_i64 a2, TCGv_i64 a3)
a7812ae4 93{
ae8b75dc 94 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
a7812ae4
PB		 95}
96
951c6300
RH		 97static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
98 TCGv_i32 a2, TCGArg a3)
ac56dd48 99{
ae8b75dc 100 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
ac56dd48
PB		 101}
102
951c6300
RH		 103static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
104 TCGv_i64 a2, TCGArg a3)
ac56dd48 105{
ae8b75dc 106 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
ac56dd48
PB		 107}
108
a9751609
RH		 109static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
110 TCGv_ptr base, TCGArg offset)
a7812ae4 111{
ae8b75dc 112 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 113}
114
a9751609
RH		 115static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
116 TCGv_ptr base, TCGArg offset)
a7812ae4 117{
ae8b75dc 118 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 119}
120
951c6300
RH		 121static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
122 TCGv_i32 a3, TCGv_i32 a4)
a7812ae4 123{
ae8b75dc
RH		 124 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
125 tcgv_i32_arg(a3), tcgv_i32_arg(a4));
a7812ae4
PB		 126}
127
951c6300
RH		 128static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
129 TCGv_i64 a3, TCGv_i64 a4)
a7812ae4 130{
ae8b75dc
RH		 131 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
132 tcgv_i64_arg(a3), tcgv_i64_arg(a4));
a7812ae4
PB		 133}
134
951c6300
RH		 135static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
136 TCGv_i32 a3, TCGArg a4)
a7812ae4 137{
ae8b75dc
RH		 138 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
139 tcgv_i32_arg(a3), a4);
a7812ae4
PB		 140}
141
951c6300
RH		 142static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
143 TCGv_i64 a3, TCGArg a4)
ac56dd48 144{
ae8b75dc
RH		 145 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
146 tcgv_i64_arg(a3), a4);
ac56dd48
PB		 147}
148
951c6300
RH		 149static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
150 TCGArg a3, TCGArg a4)
ac56dd48 151{
ae8b75dc 152 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
c896fe29
FB		 153}
154
951c6300
RH		 155static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
156 TCGArg a3, TCGArg a4)
c896fe29 157{
ae8b75dc 158 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
ac56dd48
PB		 159}
160
951c6300
RH		 161static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
162 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
a7812ae4 163{
ae8b75dc
RH		 164 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
165 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
a7812ae4
PB		 166}
167
951c6300
RH		 168static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
169 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
a7812ae4 170{
ae8b75dc
RH		 171 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
172 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
a7812ae4
PB		 173}
174
951c6300
RH		 175static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
176 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
ac56dd48 177{
ae8b75dc
RH		 178 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
179 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
ac56dd48
PB		 180}
181
951c6300
RH		 182static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
183 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
ac56dd48 184{
ae8b75dc
RH		 185 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
186 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
c896fe29
FB		 187}
188
951c6300
RH		 189static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
190 TCGv_i32 a3, TCGArg a4, TCGArg a5)
b7767f0f 191{
ae8b75dc
RH		 192 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
193 tcgv_i32_arg(a3), a4, a5);
b7767f0f
RH		 194}
195
951c6300
RH		 196static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
197 TCGv_i64 a3, TCGArg a4, TCGArg a5)
b7767f0f 198{
ae8b75dc
RH		 199 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
200 tcgv_i64_arg(a3), a4, a5);
b7767f0f
RH		 201}
202
951c6300
RH		 203static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
204 TCGv_i32 a3, TCGv_i32 a4,
205 TCGv_i32 a5, TCGv_i32 a6)
a7812ae4 206{
ae8b75dc
RH		 207 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
208 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
209 tcgv_i32_arg(a6));
a7812ae4
PB		 210}
211
951c6300
RH		 212static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
213 TCGv_i64 a3, TCGv_i64 a4,
214 TCGv_i64 a5, TCGv_i64 a6)
c896fe29 215{
ae8b75dc
RH		 216 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
217 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
218 tcgv_i64_arg(a6));
ac56dd48
PB		 219}
220
951c6300
RH		 221static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
222 TCGv_i32 a3, TCGv_i32 a4,
223 TCGv_i32 a5, TCGArg a6)
be210acb 224{
ae8b75dc
RH		 225 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
226 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
be210acb
RH		 227}
228
951c6300
RH		 229static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
230 TCGv_i64 a3, TCGv_i64 a4,
231 TCGv_i64 a5, TCGArg a6)
be210acb 232{
ae8b75dc
RH		 233 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
234 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
be210acb
RH		 235}
236
951c6300
RH		 237static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
238 TCGv_i32 a3, TCGv_i32 a4,
239 TCGArg a5, TCGArg a6)
ac56dd48 240{
ae8b75dc
RH		 241 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
242 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
a7812ae4
PB		 243}
244
951c6300
RH		 245static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
246 TCGv_i64 a3, TCGv_i64 a4,
247 TCGArg a5, TCGArg a6)
a7812ae4 248{
ae8b75dc
RH		 249 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
250 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
c896fe29
FB		 251}
252
f713d6ad 253
951c6300
RH		 254/* Generic ops. */
255
42a268c2 256static inline void gen_set_label(TCGLabel *l)
c896fe29 257{
b7e8b17a 258 tcg_gen_op1(INDEX_op_set_label, label_arg(l));
c896fe29
FB		 259}
260
42a268c2 261static inline void tcg_gen_br(TCGLabel *l)
fb50d413 262{
b7e8b17a 263 tcg_gen_op1(INDEX_op_br, label_arg(l));
951c6300
RH		 264}
265
f65e19bc
PK		 266void tcg_gen_mb(TCGBar);
267
951c6300
RH		 268/* Helper calls. */
269
270/* 32 bit ops */
271
272void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
273void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
274void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f 275void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 276void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
277void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f
RH		 278void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
279void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
280void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 281void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
282void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
283void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
284void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
288void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
0e28d006
RH		 291void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
292void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
293void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
294void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
086920c2 295void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
a768e4e9 296void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
951c6300
RH		 297void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
298void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
299void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
300void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
301void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
302 unsigned int ofs, unsigned int len);
07cc68d5
RH		 303void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
304 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 305void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
306 unsigned int ofs, unsigned int len);
307void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
308 unsigned int ofs, unsigned int len);
42a268c2
RH		 309void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
310void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
951c6300
RH		 311void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
312 TCGv_i32 arg1, TCGv_i32 arg2);
313void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
314 TCGv_i32 arg1, int32_t arg2);
315void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
316 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
317void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
318 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
319void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
320 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
321void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
322void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
5087abfb 323void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 324void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
325void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
326void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
327void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
328void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
329void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
b87fb8cd
RH		 330void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
331void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
332void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
333void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 334
335static inline void tcg_gen_discard_i32(TCGv_i32 arg)
336{
337 tcg_gen_op1_i32(INDEX_op_discard, arg);
fb50d413
BS		 338}
339
a7812ae4 340static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 341{
11f4e8f8 342 if (ret != arg) {
a7812ae4 343 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
951c6300 344 }
c896fe29
FB		 345}
346
a7812ae4 347static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
c896fe29 348{
a7812ae4 349 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
c896fe29
FB		 350}
351
951c6300
RH		 352static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
353 tcg_target_long offset)
c896fe29 354{
a7812ae4 355 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 356}
357
951c6300
RH		 358static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
359 tcg_target_long offset)
c896fe29 360{
a7812ae4 361 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 362}
363
951c6300
RH		 364static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
365 tcg_target_long offset)
c896fe29 366{
a7812ae4 367 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 368}
369
951c6300
RH		 370static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
371 tcg_target_long offset)
c896fe29 372{
a7812ae4 373 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 374}
375
951c6300
RH		 376static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
377 tcg_target_long offset)
c896fe29 378{
a7812ae4 379 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 380}
381
951c6300
RH		 382static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
383 tcg_target_long offset)
c896fe29 384{
a7812ae4 385 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 386}
387
951c6300
RH		 388static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
389 tcg_target_long offset)
c896fe29 390{
a7812ae4 391 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 392}
393
951c6300
RH		 394static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
395 tcg_target_long offset)
c896fe29 396{
a7812ae4 397 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 398}
399
a7812ae4 400static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 401{
a7812ae4 402 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 403}
404
a7812ae4 405static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 406{
a7812ae4 407 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 408}
409
a7812ae4 410static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 411{
951c6300 412 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
c896fe29
FB		 413}
414
a7812ae4 415static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 416{
951c6300 417 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
c896fe29
FB		 418}
419
a7812ae4 420static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 421{
951c6300 422 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
c896fe29
FB		 423}
424
a7812ae4 425static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 426{
a7812ae4 427 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 428}
429
a7812ae4 430static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 431{
a7812ae4 432 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 433}
434
a7812ae4 435static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 436{
a7812ae4 437 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 438}
439
a7812ae4 440static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 441{
a7812ae4 442 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 443}
444
951c6300 445static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 446{
951c6300
RH		 447 if (TCG_TARGET_HAS_neg_i32) {
448 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
25c4d9cc 449 } else {
951c6300 450 tcg_gen_subfi_i32(ret, 0, arg);
25c4d9cc 451 }
31d66551
AJ		 452}
453
951c6300 454static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
31d66551 455{
951c6300
RH		 456 if (TCG_TARGET_HAS_not_i32) {
457 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
25c4d9cc 458 } else {
951c6300 459 tcg_gen_xori_i32(ret, arg, -1);
25c4d9cc 460 }
31d66551
AJ		 461}
462
951c6300
RH		 463/* 64 bit ops */
464
465void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
466void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
467void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f 468void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 469void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
470void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f
RH		 471void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
472void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
473void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 474void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
475void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
476void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
477void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
478void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
479void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
480void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
481void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
482void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
483void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
0e28d006
RH		 484void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
485void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
486void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
487void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
086920c2 488void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
a768e4e9 489void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
951c6300
RH		 490void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
491void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
492void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
493void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
494void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
495 unsigned int ofs, unsigned int len);
07cc68d5
RH		 496void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
497 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 498void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
499 unsigned int ofs, unsigned int len);
500void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
501 unsigned int ofs, unsigned int len);
42a268c2
RH		 502void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
503void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
951c6300
RH		 504void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
505 TCGv_i64 arg1, TCGv_i64 arg2);
506void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
507 TCGv_i64 arg1, int64_t arg2);
508void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
509 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
510void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
511 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
512void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
513 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
514void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
515void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
5087abfb 516void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
951c6300
RH		 517void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
518void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
519void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
520void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
521void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
522void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
523void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
524void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
525void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
526void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
b87fb8cd
RH		 527void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
528void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
529void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
530void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
c896fe29 531
951c6300
RH		 532#if TCG_TARGET_REG_BITS == 64
533static inline void tcg_gen_discard_i64(TCGv_i64 arg)
534{
535 tcg_gen_op1_i64(INDEX_op_discard, arg);
536}
c896fe29 537
a7812ae4 538static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 539{
11f4e8f8 540 if (ret != arg) {
951c6300 541 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
4d07272d 542 }
c896fe29
FB		 543}
544
a7812ae4 545static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 546{
951c6300 547 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
c896fe29
FB		 548}
549
a7812ae4
PB		 550static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
551 tcg_target_long offset)
c896fe29 552{
951c6300 553 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 554}
555
a7812ae4
PB		 556static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
557 tcg_target_long offset)
c896fe29 558{
951c6300 559 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 560}
561
a7812ae4
PB		 562static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
563 tcg_target_long offset)
c896fe29 564{
951c6300 565 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 566}
567
a7812ae4
PB		 568static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
569 tcg_target_long offset)
c896fe29 570{
951c6300 571 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 572}
573
a7812ae4
PB		 574static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
575 tcg_target_long offset)
c896fe29 576{
951c6300 577 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 578}
579
a7812ae4
PB		 580static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
581 tcg_target_long offset)
c896fe29 582{
951c6300 583 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 584}
585
a7812ae4
PB		 586static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
587 tcg_target_long offset)
c896fe29 588{
951c6300 589 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 590}
591
a7812ae4
PB		 592static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
593 tcg_target_long offset)
c896fe29 594{
951c6300 595 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 596}
597
a7812ae4
PB		 598static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
599 tcg_target_long offset)
c896fe29 600{
951c6300 601 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 602}
603
a7812ae4
PB		 604static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
605 tcg_target_long offset)
c896fe29 606{
951c6300 607 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 608}
609
a7812ae4
PB		 610static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
611 tcg_target_long offset)
c896fe29 612{
951c6300 613 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 614}
615
a7812ae4 616static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 617{
951c6300 618 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 619}
620
a7812ae4 621static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 622{
951c6300 623 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 624}
625
a7812ae4 626static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 627{
951c6300 628 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
c896fe29
FB		 629}
630
a7812ae4 631static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 632{
951c6300 633 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
c896fe29
FB		 634}
635
a7812ae4 636static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 637{
951c6300 638 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
c896fe29
FB		 639}
640
a7812ae4 641static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 642{
951c6300 643 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 644}
645
a7812ae4 646static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 647{
951c6300 648 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 649}
650
a7812ae4 651static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 652{
951c6300 653 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
5105c556
AJ		 654}
655
a7812ae4 656static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 657{
951c6300 658 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29 659}
951c6300
RH		 660#else /* TCG_TARGET_REG_BITS == 32 */
661static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
662 tcg_target_long offset)
c896fe29 663{
951c6300 664 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 665}
666
951c6300
RH		 667static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
668 tcg_target_long offset)
c896fe29 669{
951c6300 670 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 671}
672
951c6300
RH		 673static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
674 tcg_target_long offset)
c896fe29 675{
951c6300 676 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 677}
678
951c6300 679static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 680{
951c6300
RH		 681 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
682 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
c896fe29
FB		 683}
684
951c6300 685static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 686{
951c6300
RH		 687 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
688 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
689}
690
691void tcg_gen_discard_i64(TCGv_i64 arg);
692void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
693void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
694void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
695void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
696void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
697void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
698void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
699void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
700void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
701void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
702void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
703void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
704void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
705void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
706void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
707void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
708void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
709#endif /* TCG_TARGET_REG_BITS */
c896fe29 710
951c6300 711static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 712{
951c6300
RH		 713 if (TCG_TARGET_HAS_neg_i64) {
714 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
715 } else {
716 tcg_gen_subfi_i64(ret, 0, arg);
717 }
c896fe29
FB		 718}
719
951c6300 720/* Size changing operations. */
c896fe29 721
951c6300
RH		 722void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
723void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
724void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
609ad705
RH		 725void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
726void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
951c6300
RH		 727void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
728void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
c896fe29 729
951c6300 730static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
c896fe29 731{
951c6300 732 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
c896fe29
FB		 733}
734
951c6300 735/* QEMU specific operations. */
c896fe29 736
951c6300
RH		 737#ifndef TARGET_LONG_BITS
738#error must include QEMU headers
739#endif
c896fe29 740
9aef40ed
RH		 741#if TARGET_INSN_START_WORDS == 1
742# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
743static inline void tcg_gen_insn_start(target_ulong pc)
c896fe29 744{
b7e8b17a 745 tcg_gen_op1(INDEX_op_insn_start, pc);
9aef40ed
RH		 746}
747# else
748static inline void tcg_gen_insn_start(target_ulong pc)
749{
b7e8b17a 750 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
9aef40ed
RH		 751}
752# endif
753#elif TARGET_INSN_START_WORDS == 2
754# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
755static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
756{
b7e8b17a 757 tcg_gen_op2(INDEX_op_insn_start, pc, a1);
9aef40ed
RH		 758}
759# else
760static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
761{
b7e8b17a 762 tcg_gen_op4(INDEX_op_insn_start,
9aef40ed
RH		 763 (uint32_t)pc, (uint32_t)(pc >> 32),
764 (uint32_t)a1, (uint32_t)(a1 >> 32));
765}
766# endif
767#elif TARGET_INSN_START_WORDS == 3
768# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
769static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
770 target_ulong a2)
771{
b7e8b17a 772 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
9aef40ed
RH		 773}
774# else
775static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
776 target_ulong a2)
777{
b7e8b17a 778 tcg_gen_op6(INDEX_op_insn_start,
9aef40ed
RH		 779 (uint32_t)pc, (uint32_t)(pc >> 32),
780 (uint32_t)a1, (uint32_t)(a1 >> 32),
781 (uint32_t)a2, (uint32_t)(a2 >> 32));
782}
783# endif
951c6300 784#else
9aef40ed 785# error "Unhandled number of operands to insn_start"
951c6300 786#endif
c896fe29 787
07ea28b4
RH		 788/**
789 * tcg_gen_exit_tb() - output exit_tb TCG operation
790 * @tb: The TranslationBlock from which we are exiting
791 * @idx: Direct jump slot index, or exit request
792 *
793 * See tcg/README for more info about this TCG operation.
794 * See also tcg.h and the block comment above TB_EXIT_MASK.
795 *
796 * For a normal exit from the TB, back to the main loop, @tb should
797 * be NULL and @idx should be 0. Otherwise, @tb should be valid and
798 * @idx should be one of the TB_EXIT_ values.
799 */
800void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx);
c896fe29 801
5b053a4a
SF		 802/**
803 * tcg_gen_goto_tb() - output goto_tb TCG operation
804 * @idx: Direct jump slot index (0 or 1)
805 *
806 * See tcg/README for more info about this TCG operation.
807 *
90aa39a1
SF		 808 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
809 * the pages this TB resides in because we don't take care of direct jumps when
810 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
811 * static address translation, so the destination address is always valid, TBs
812 * are always invalidated properly, and direct jumps are reset when mapping
813 * changes.
5b053a4a 814 */
951c6300 815void tcg_gen_goto_tb(unsigned idx);
c896fe29 816
cedbcb01 817/**
7f11636d 818 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
cedbcb01
EC		 819 * @addr: Guest address of the target TB
820 *
821 * If the TB is not valid, jump to the epilogue.
822 *
823 * This operation is optional. If the TCG backend does not implement goto_ptr,
824 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
825 */
7f11636d 826void tcg_gen_lookup_and_goto_ptr(void);
cedbcb01 827
a7812ae4 828#if TARGET_LONG_BITS == 32
a7812ae4
PB		 829#define tcg_temp_new() tcg_temp_new_i32()
830#define tcg_global_reg_new tcg_global_reg_new_i32
831#define tcg_global_mem_new tcg_global_mem_new_i32
df9247b2 832#define tcg_temp_local_new() tcg_temp_local_new_i32()
a7812ae4 833#define tcg_temp_free tcg_temp_free_i32
f713d6ad
RH		 834#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
835#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
a7812ae4 836#else
a7812ae4
PB		 837#define tcg_temp_new() tcg_temp_new_i64()
838#define tcg_global_reg_new tcg_global_reg_new_i64
839#define tcg_global_mem_new tcg_global_mem_new_i64
df9247b2 840#define tcg_temp_local_new() tcg_temp_local_new_i64()
a7812ae4 841#define tcg_temp_free tcg_temp_free_i64
f713d6ad
RH		 842#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
843#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
a7812ae4
PB		 844#endif
845
f713d6ad
RH		 846void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
847void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
848void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
849void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
c896fe29 850
ac56dd48 851static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 852{
f713d6ad 853 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
c896fe29
FB		 854}
855
ac56dd48 856static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 857{
f713d6ad 858 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
c896fe29
FB		 859}
860
ac56dd48 861static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 862{
f713d6ad 863 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
c896fe29
FB		 864}
865
ac56dd48 866static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 867{
f713d6ad 868 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
c896fe29
FB		 869}
870
ac56dd48 871static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 872{
f713d6ad 873 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
c896fe29
FB		 874}
875
ac56dd48 876static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 877{
f713d6ad 878 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
c896fe29
FB		 879}
880
a7812ae4 881static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 882{
f713d6ad 883 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
c896fe29
FB		 884}
885
ac56dd48 886static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 887{
f713d6ad 888 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
c896fe29
FB		 889}
890
ac56dd48 891static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 892{
f713d6ad 893 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
c896fe29
FB		 894}
895
ac56dd48 896static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 897{
f713d6ad 898 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
c896fe29
FB		 899}
900
a7812ae4 901static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 902{
f713d6ad 903 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
c896fe29
FB		 904}
905
c482cb11
RH		 906void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
907 TCGArg, TCGMemOp);
908void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
909 TCGArg, TCGMemOp);
910
911void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
912void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf 913
c482cb11
RH		 914void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
915void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
916void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
917void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
918void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
919void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
920void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
921void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 922void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
923void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
924void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
925void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
926void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
927void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
928void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
929void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
930
c482cb11
RH		 931void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
932void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
933void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
934void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
935void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
936void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
937void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
938void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 939void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
940void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
941void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
942void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
943void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
944void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
945void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
946void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
c482cb11 947
d2fd745f
RH		 948void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
949void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
950void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
951void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
952void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
953void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
954void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
db432672 955void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
d2fd745f
RH		 956void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
957void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
3774030a 958void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 959void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
960void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
961void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
962void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
963void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
964void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
965void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
966
d0ec9796
RH		 967void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
968void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
969void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
970
212be173
RH		 971void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
972 TCGv_vec a, TCGv_vec b);
973
d2fd745f
RH		 974void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
975void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
976void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
977
f8422f52 978#if TARGET_LONG_BITS == 64
f8422f52
BS		 979#define tcg_gen_movi_tl tcg_gen_movi_i64
980#define tcg_gen_mov_tl tcg_gen_mov_i64
981#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
982#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
983#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
984#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
985#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
986#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
987#define tcg_gen_ld_tl tcg_gen_ld_i64
988#define tcg_gen_st8_tl tcg_gen_st8_i64
989#define tcg_gen_st16_tl tcg_gen_st16_i64
990#define tcg_gen_st32_tl tcg_gen_st32_i64
991#define tcg_gen_st_tl tcg_gen_st_i64
992#define tcg_gen_add_tl tcg_gen_add_i64
993#define tcg_gen_addi_tl tcg_gen_addi_i64
994#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 995#define tcg_gen_neg_tl tcg_gen_neg_i64
10460c8a 996#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 997#define tcg_gen_subi_tl tcg_gen_subi_i64
998#define tcg_gen_and_tl tcg_gen_and_i64
999#define tcg_gen_andi_tl tcg_gen_andi_i64
1000#define tcg_gen_or_tl tcg_gen_or_i64
1001#define tcg_gen_ori_tl tcg_gen_ori_i64
1002#define tcg_gen_xor_tl tcg_gen_xor_i64
1003#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 1004#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 1005#define tcg_gen_shl_tl tcg_gen_shl_i64
1006#define tcg_gen_shli_tl tcg_gen_shli_i64
1007#define tcg_gen_shr_tl tcg_gen_shr_i64
1008#define tcg_gen_shri_tl tcg_gen_shri_i64
1009#define tcg_gen_sar_tl tcg_gen_sar_i64
1010#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 1011#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 1012#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 1013#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 1014#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 1015#define tcg_gen_mul_tl tcg_gen_mul_i64
1016#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 1017#define tcg_gen_div_tl tcg_gen_div_i64
1018#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 1019#define tcg_gen_divu_tl tcg_gen_divu_i64
1020#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 1021#define tcg_gen_discard_tl tcg_gen_discard_i64
ecc7b3aa 1022#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
e429073d
BS		 1023#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1024#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1025#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1026#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1027#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 1028#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
1029#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
1030#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
1031#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
1032#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
1033#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 1034#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
1035#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
1036#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
945ca823 1037#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 1038#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 1039#define tcg_gen_andc_tl tcg_gen_andc_i64
1040#define tcg_gen_eqv_tl tcg_gen_eqv_i64
1041#define tcg_gen_nand_tl tcg_gen_nand_i64
1042#define tcg_gen_nor_tl tcg_gen_nor_i64
1043#define tcg_gen_orc_tl tcg_gen_orc_i64
0e28d006
RH		 1044#define tcg_gen_clz_tl tcg_gen_clz_i64
1045#define tcg_gen_ctz_tl tcg_gen_ctz_i64
1046#define tcg_gen_clzi_tl tcg_gen_clzi_i64
1047#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
086920c2 1048#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
a768e4e9 1049#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
15824571
AJ		 1050#define tcg_gen_rotl_tl tcg_gen_rotl_i64
1051#define tcg_gen_rotli_tl tcg_gen_rotli_i64
1052#define tcg_gen_rotr_tl tcg_gen_rotr_i64
1053#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 1054#define tcg_gen_deposit_tl tcg_gen_deposit_i64
07cc68d5 1055#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
7ec8bab3
RH		 1056#define tcg_gen_extract_tl tcg_gen_extract_i64
1057#define tcg_gen_sextract_tl tcg_gen_sextract_i64
a98824ac 1058#define tcg_const_tl tcg_const_i64
bdffd4a9 1059#define tcg_const_local_tl tcg_const_local_i64
ffc5ea09 1060#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 1061#define tcg_gen_add2_tl tcg_gen_add2_i64
1062#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 1063#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1064#define tcg_gen_muls2_tl tcg_gen_muls2_i64
5087abfb 1065#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
b87fb8cd
RH		 1066#define tcg_gen_smin_tl tcg_gen_smin_i64
1067#define tcg_gen_umin_tl tcg_gen_umin_i64
1068#define tcg_gen_smax_tl tcg_gen_smax_i64
1069#define tcg_gen_umax_tl tcg_gen_umax_i64
c482cb11
RH		 1070#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1071#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1072#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1073#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1074#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1075#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
5507c2bf
RH		 1076#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64
1077#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64
1078#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64
1079#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64
c482cb11
RH		 1080#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1081#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1082#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1083#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
5507c2bf
RH		 1084#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64
1085#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64
1086#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64
1087#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64
d2fd745f 1088#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
f8422f52 1089#else
f8422f52
BS		 1090#define tcg_gen_movi_tl tcg_gen_movi_i32
1091#define tcg_gen_mov_tl tcg_gen_mov_i32
1092#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1093#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1094#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1095#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1096#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1097#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1098#define tcg_gen_ld_tl tcg_gen_ld_i32
1099#define tcg_gen_st8_tl tcg_gen_st8_i32
1100#define tcg_gen_st16_tl tcg_gen_st16_i32
1101#define tcg_gen_st32_tl tcg_gen_st_i32
1102#define tcg_gen_st_tl tcg_gen_st_i32
1103#define tcg_gen_add_tl tcg_gen_add_i32
1104#define tcg_gen_addi_tl tcg_gen_addi_i32
1105#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 1106#define tcg_gen_neg_tl tcg_gen_neg_i32
0045734a 1107#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 1108#define tcg_gen_subi_tl tcg_gen_subi_i32
1109#define tcg_gen_and_tl tcg_gen_and_i32
1110#define tcg_gen_andi_tl tcg_gen_andi_i32
1111#define tcg_gen_or_tl tcg_gen_or_i32
1112#define tcg_gen_ori_tl tcg_gen_ori_i32
1113#define tcg_gen_xor_tl tcg_gen_xor_i32
1114#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 1115#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 1116#define tcg_gen_shl_tl tcg_gen_shl_i32
1117#define tcg_gen_shli_tl tcg_gen_shli_i32
1118#define tcg_gen_shr_tl tcg_gen_shr_i32
1119#define tcg_gen_shri_tl tcg_gen_shri_i32
1120#define tcg_gen_sar_tl tcg_gen_sar_i32
1121#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 1122#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 1123#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 1124#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 1125#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 1126#define tcg_gen_mul_tl tcg_gen_mul_i32
1127#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 1128#define tcg_gen_div_tl tcg_gen_div_i32
1129#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 1130#define tcg_gen_divu_tl tcg_gen_divu_i32
1131#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 1132#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d 1133#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
ecc7b3aa 1134#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
e429073d
BS		 1135#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1136#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1137#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1138#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 1139#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1140#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1141#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1142#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1143#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1144#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba
AJ		 1145#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1146#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
945ca823 1147#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
e3eb9806 1148#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
f24cb33e
AJ		 1149#define tcg_gen_andc_tl tcg_gen_andc_i32
1150#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1151#define tcg_gen_nand_tl tcg_gen_nand_i32
1152#define tcg_gen_nor_tl tcg_gen_nor_i32
1153#define tcg_gen_orc_tl tcg_gen_orc_i32
0e28d006
RH		 1154#define tcg_gen_clz_tl tcg_gen_clz_i32
1155#define tcg_gen_ctz_tl tcg_gen_ctz_i32
1156#define tcg_gen_clzi_tl tcg_gen_clzi_i32
1157#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
086920c2 1158#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
a768e4e9 1159#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
15824571
AJ		 1160#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1161#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1162#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1163#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 1164#define tcg_gen_deposit_tl tcg_gen_deposit_i32
07cc68d5 1165#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
7ec8bab3
RH		 1166#define tcg_gen_extract_tl tcg_gen_extract_i32
1167#define tcg_gen_sextract_tl tcg_gen_sextract_i32
a98824ac 1168#define tcg_const_tl tcg_const_i32
bdffd4a9 1169#define tcg_const_local_tl tcg_const_local_i32
ffc5ea09 1170#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 1171#define tcg_gen_add2_tl tcg_gen_add2_i32
1172#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 1173#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1174#define tcg_gen_muls2_tl tcg_gen_muls2_i32
5087abfb 1175#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
b87fb8cd
RH		 1176#define tcg_gen_smin_tl tcg_gen_smin_i32
1177#define tcg_gen_umin_tl tcg_gen_umin_i32
1178#define tcg_gen_smax_tl tcg_gen_smax_i32
1179#define tcg_gen_umax_tl tcg_gen_umax_i32
c482cb11
RH		 1180#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1181#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1182#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1183#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1184#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1185#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
5507c2bf
RH		 1186#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32
1187#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32
1188#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32
1189#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32
c482cb11
RH		 1190#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1191#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1192#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1193#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
5507c2bf
RH		 1194#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32
1195#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32
1196#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32
1197#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32
d2fd745f 1198#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
f8422f52 1199#endif
6ddbc6e4 1200
71b92699 1201#if UINTPTR_MAX == UINT32_MAX
5bfa8034
RH		 1202# define PTR i32
1203# define NAT TCGv_i32
f713d6ad 1204#else
5bfa8034
RH		 1205# define PTR i64
1206# define NAT TCGv_i64
1207#endif
1208
1209static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1210{
1211 glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
1212}
1213
1214static inline void tcg_gen_discard_ptr(TCGv_ptr a)
1215{
1216 glue(tcg_gen_discard_,PTR)((NAT)a);
1217}
1218
1219static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
1220{
1221 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
1222}
1223
1224static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
1225{
1226 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
1227}
1228
1229static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
1230 intptr_t b, TCGLabel *label)
1231{
1232 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
1233}
1234
1235static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
1236{
1237#if UINTPTR_MAX == UINT32_MAX
1238 tcg_gen_mov_i32((NAT)r, a);
1239#else
1240 tcg_gen_ext_i32_i64((NAT)r, a);
1241#endif
1242}
1243
1244static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
1245{
1246#if UINTPTR_MAX == UINT32_MAX
1247 tcg_gen_extrl_i64_i32((NAT)r, a);
1248#else
1249 tcg_gen_mov_i64((NAT)r, a);
1250#endif
1251}
1252
1253static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
1254{
1255#if UINTPTR_MAX == UINT32_MAX
1256 tcg_gen_extu_i32_i64(r, (NAT)a);
1257#else
1258 tcg_gen_mov_i64(r, (NAT)a);
1259#endif
1260}
1261
1262static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
1263{
1264#if UINTPTR_MAX == UINT32_MAX
1265 tcg_gen_mov_i32(r, (NAT)a);
1266#else
1267 tcg_gen_extrl_i64_i32(r, (NAT)a);
1268#endif
1269}
1270
1271#undef PTR
1272#undef NAT
a7ce790a
PM		 1273
1274#endif /* TCG_TCG_OP_H */
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