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Commit | Line | Data |
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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
951c6300 | 24 | |
c896fe29 | 25 | #include "tcg.h" |
944eea96 | 26 | #include "exec/helper-proto.h" |
c017230d RH |
27 | #include "exec/helper-gen.h" |
28 | ||
951c6300 | 29 | /* Basic output routines. Not for general consumption. */ |
c896fe29 | 30 | |
951c6300 RH |
31 | void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg); |
32 | void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg); | |
33 | void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg); | |
34 | void tcg_gen_op4(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); | |
35 | void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, | |
36 | TCGArg, TCGArg); | |
37 | void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, | |
38 | TCGArg, TCGArg, TCGArg); | |
212c328d | 39 | |
951c6300 RH |
40 | |
41 | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) | |
c896fe29 | 42 | { |
951c6300 | 43 | tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1)); |
a7812ae4 PB |
44 | } |
45 | ||
951c6300 | 46 | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) |
a7812ae4 | 47 | { |
951c6300 | 48 | tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1)); |
c896fe29 FB |
49 | } |
50 | ||
951c6300 | 51 | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) |
c896fe29 | 52 | { |
951c6300 | 53 | tcg_gen_op1(&tcg_ctx, opc, a1); |
c896fe29 FB |
54 | } |
55 | ||
951c6300 | 56 | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) |
a7812ae4 | 57 | { |
951c6300 | 58 | tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); |
a7812ae4 PB |
59 | } |
60 | ||
951c6300 | 61 | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) |
a7812ae4 | 62 | { |
951c6300 | 63 | tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); |
a7812ae4 PB |
64 | } |
65 | ||
951c6300 | 66 | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) |
c896fe29 | 67 | { |
951c6300 | 68 | tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2); |
c896fe29 FB |
69 | } |
70 | ||
951c6300 | 71 | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) |
c896fe29 | 72 | { |
951c6300 | 73 | tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2); |
ac56dd48 PB |
74 | } |
75 | ||
951c6300 | 76 | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) |
bcb0126f | 77 | { |
951c6300 | 78 | tcg_gen_op2(&tcg_ctx, opc, a1, a2); |
bcb0126f PB |
79 | } |
80 | ||
951c6300 RH |
81 | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, |
82 | TCGv_i32 a2, TCGv_i32 a3) | |
a7812ae4 | 83 | { |
951c6300 RH |
84 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), |
85 | GET_TCGV_I32(a2), GET_TCGV_I32(a3)); | |
a7812ae4 PB |
86 | } |
87 | ||
951c6300 RH |
88 | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, |
89 | TCGv_i64 a2, TCGv_i64 a3) | |
a7812ae4 | 90 | { |
951c6300 RH |
91 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), |
92 | GET_TCGV_I64(a2), GET_TCGV_I64(a3)); | |
a7812ae4 PB |
93 | } |
94 | ||
951c6300 RH |
95 | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, |
96 | TCGv_i32 a2, TCGArg a3) | |
ac56dd48 | 97 | { |
951c6300 | 98 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); |
ac56dd48 PB |
99 | } |
100 | ||
951c6300 RH |
101 | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, |
102 | TCGv_i64 a2, TCGArg a3) | |
ac56dd48 | 103 | { |
951c6300 | 104 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); |
ac56dd48 PB |
105 | } |
106 | ||
a9751609 RH |
107 | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
108 | TCGv_ptr base, TCGArg offset) | |
a7812ae4 | 109 | { |
951c6300 | 110 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset); |
a7812ae4 PB |
111 | } |
112 | ||
a9751609 RH |
113 | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
114 | TCGv_ptr base, TCGArg offset) | |
a7812ae4 | 115 | { |
951c6300 | 116 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset); |
a7812ae4 PB |
117 | } |
118 | ||
951c6300 RH |
119 | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
120 | TCGv_i32 a3, TCGv_i32 a4) | |
a7812ae4 | 121 | { |
951c6300 RH |
122 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
123 | GET_TCGV_I32(a3), GET_TCGV_I32(a4)); | |
a7812ae4 PB |
124 | } |
125 | ||
951c6300 RH |
126 | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
127 | TCGv_i64 a3, TCGv_i64 a4) | |
a7812ae4 | 128 | { |
951c6300 RH |
129 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
130 | GET_TCGV_I64(a3), GET_TCGV_I64(a4)); | |
a7812ae4 PB |
131 | } |
132 | ||
951c6300 RH |
133 | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
134 | TCGv_i32 a3, TCGArg a4) | |
a7812ae4 | 135 | { |
951c6300 RH |
136 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
137 | GET_TCGV_I32(a3), a4); | |
a7812ae4 PB |
138 | } |
139 | ||
951c6300 RH |
140 | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
141 | TCGv_i64 a3, TCGArg a4) | |
ac56dd48 | 142 | { |
951c6300 RH |
143 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
144 | GET_TCGV_I64(a3), a4); | |
ac56dd48 PB |
145 | } |
146 | ||
951c6300 RH |
147 | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
148 | TCGArg a3, TCGArg a4) | |
ac56dd48 | 149 | { |
951c6300 | 150 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); |
c896fe29 FB |
151 | } |
152 | ||
951c6300 RH |
153 | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
154 | TCGArg a3, TCGArg a4) | |
c896fe29 | 155 | { |
951c6300 | 156 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); |
ac56dd48 PB |
157 | } |
158 | ||
951c6300 RH |
159 | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
160 | TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) | |
a7812ae4 | 161 | { |
951c6300 RH |
162 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
163 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5)); | |
a7812ae4 PB |
164 | } |
165 | ||
951c6300 RH |
166 | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
167 | TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) | |
a7812ae4 | 168 | { |
951c6300 RH |
169 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
170 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5)); | |
a7812ae4 PB |
171 | } |
172 | ||
951c6300 RH |
173 | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
174 | TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) | |
ac56dd48 | 175 | { |
951c6300 RH |
176 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
177 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5); | |
ac56dd48 PB |
178 | } |
179 | ||
951c6300 RH |
180 | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
181 | TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) | |
ac56dd48 | 182 | { |
951c6300 RH |
183 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
184 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5); | |
c896fe29 FB |
185 | } |
186 | ||
951c6300 RH |
187 | static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
188 | TCGv_i32 a3, TCGArg a4, TCGArg a5) | |
b7767f0f | 189 | { |
951c6300 RH |
190 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
191 | GET_TCGV_I32(a3), a4, a5); | |
b7767f0f RH |
192 | } |
193 | ||
951c6300 RH |
194 | static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
195 | TCGv_i64 a3, TCGArg a4, TCGArg a5) | |
b7767f0f | 196 | { |
951c6300 RH |
197 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
198 | GET_TCGV_I64(a3), a4, a5); | |
b7767f0f RH |
199 | } |
200 | ||
951c6300 RH |
201 | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
202 | TCGv_i32 a3, TCGv_i32 a4, | |
203 | TCGv_i32 a5, TCGv_i32 a6) | |
a7812ae4 | 204 | { |
951c6300 RH |
205 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
206 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), | |
207 | GET_TCGV_I32(a6)); | |
a7812ae4 PB |
208 | } |
209 | ||
951c6300 RH |
210 | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
211 | TCGv_i64 a3, TCGv_i64 a4, | |
212 | TCGv_i64 a5, TCGv_i64 a6) | |
c896fe29 | 213 | { |
951c6300 RH |
214 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
215 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), | |
216 | GET_TCGV_I64(a6)); | |
ac56dd48 PB |
217 | } |
218 | ||
951c6300 RH |
219 | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
220 | TCGv_i32 a3, TCGv_i32 a4, | |
221 | TCGv_i32 a5, TCGArg a6) | |
be210acb | 222 | { |
951c6300 RH |
223 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
224 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6); | |
be210acb RH |
225 | } |
226 | ||
951c6300 RH |
227 | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
228 | TCGv_i64 a3, TCGv_i64 a4, | |
229 | TCGv_i64 a5, TCGArg a6) | |
be210acb | 230 | { |
951c6300 RH |
231 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
232 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6); | |
be210acb RH |
233 | } |
234 | ||
951c6300 RH |
235 | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
236 | TCGv_i32 a3, TCGv_i32 a4, | |
237 | TCGArg a5, TCGArg a6) | |
ac56dd48 | 238 | { |
951c6300 RH |
239 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
240 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6); | |
a7812ae4 PB |
241 | } |
242 | ||
951c6300 RH |
243 | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
244 | TCGv_i64 a3, TCGv_i64 a4, | |
245 | TCGArg a5, TCGArg a6) | |
a7812ae4 | 246 | { |
951c6300 RH |
247 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
248 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6); | |
c896fe29 FB |
249 | } |
250 | ||
f713d6ad | 251 | |
951c6300 RH |
252 | /* Generic ops. */ |
253 | ||
42a268c2 | 254 | static inline void gen_set_label(TCGLabel *l) |
c896fe29 | 255 | { |
42a268c2 | 256 | tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l)); |
c896fe29 FB |
257 | } |
258 | ||
42a268c2 | 259 | static inline void tcg_gen_br(TCGLabel *l) |
fb50d413 | 260 | { |
42a268c2 | 261 | tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l)); |
951c6300 RH |
262 | } |
263 | ||
951c6300 RH |
264 | /* Helper calls. */ |
265 | ||
266 | /* 32 bit ops */ | |
267 | ||
268 | void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
269 | void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); | |
270 | void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
271 | void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); | |
272 | void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
273 | void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
274 | void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
275 | void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
276 | void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
277 | void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | |
278 | void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
279 | void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
280 | void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
281 | void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
282 | void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
283 | void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
284 | void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
285 | void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
286 | void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
287 | void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
288 | void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
289 | void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); | |
290 | void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); | |
291 | void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, | |
292 | unsigned int ofs, unsigned int len); | |
42a268c2 RH |
293 | void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); |
294 | void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); | |
951c6300 RH |
295 | void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
296 | TCGv_i32 arg1, TCGv_i32 arg2); | |
297 | void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, | |
298 | TCGv_i32 arg1, int32_t arg2); | |
299 | void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, | |
300 | TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); | |
301 | void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, | |
302 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); | |
303 | void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, | |
304 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); | |
305 | void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); | |
306 | void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); | |
307 | void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); | |
308 | void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); | |
309 | void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); | |
310 | void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); | |
311 | void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg); | |
312 | void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); | |
313 | ||
314 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) | |
315 | { | |
316 | tcg_gen_op1_i32(INDEX_op_discard, arg); | |
fb50d413 BS |
317 | } |
318 | ||
a7812ae4 | 319 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 320 | { |
951c6300 | 321 | if (!TCGV_EQUAL_I32(ret, arg)) { |
a7812ae4 | 322 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
951c6300 | 323 | } |
c896fe29 FB |
324 | } |
325 | ||
a7812ae4 | 326 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
c896fe29 | 327 | { |
a7812ae4 | 328 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
c896fe29 FB |
329 | } |
330 | ||
951c6300 RH |
331 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
332 | tcg_target_long offset) | |
c896fe29 | 333 | { |
a7812ae4 | 334 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
c896fe29 FB |
335 | } |
336 | ||
951c6300 RH |
337 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
338 | tcg_target_long offset) | |
c896fe29 | 339 | { |
a7812ae4 | 340 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
c896fe29 FB |
341 | } |
342 | ||
951c6300 RH |
343 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
344 | tcg_target_long offset) | |
c896fe29 | 345 | { |
a7812ae4 | 346 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
c896fe29 FB |
347 | } |
348 | ||
951c6300 RH |
349 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
350 | tcg_target_long offset) | |
c896fe29 | 351 | { |
a7812ae4 | 352 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
c896fe29 FB |
353 | } |
354 | ||
951c6300 RH |
355 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, |
356 | tcg_target_long offset) | |
c896fe29 | 357 | { |
a7812ae4 | 358 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
c896fe29 FB |
359 | } |
360 | ||
951c6300 RH |
361 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
362 | tcg_target_long offset) | |
c896fe29 | 363 | { |
a7812ae4 | 364 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
c896fe29 FB |
365 | } |
366 | ||
951c6300 RH |
367 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
368 | tcg_target_long offset) | |
c896fe29 | 369 | { |
a7812ae4 | 370 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
c896fe29 FB |
371 | } |
372 | ||
951c6300 RH |
373 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
374 | tcg_target_long offset) | |
c896fe29 | 375 | { |
a7812ae4 | 376 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
c896fe29 FB |
377 | } |
378 | ||
a7812ae4 | 379 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 380 | { |
a7812ae4 | 381 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
c896fe29 FB |
382 | } |
383 | ||
a7812ae4 | 384 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 385 | { |
a7812ae4 | 386 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
c896fe29 FB |
387 | } |
388 | ||
a7812ae4 | 389 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 390 | { |
951c6300 | 391 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
c896fe29 FB |
392 | } |
393 | ||
a7812ae4 | 394 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 395 | { |
951c6300 | 396 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
c896fe29 FB |
397 | } |
398 | ||
a7812ae4 | 399 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 400 | { |
951c6300 | 401 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
c896fe29 FB |
402 | } |
403 | ||
a7812ae4 | 404 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 405 | { |
a7812ae4 | 406 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
c896fe29 FB |
407 | } |
408 | ||
a7812ae4 | 409 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 410 | { |
a7812ae4 | 411 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
c896fe29 FB |
412 | } |
413 | ||
a7812ae4 | 414 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 415 | { |
a7812ae4 | 416 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
c896fe29 FB |
417 | } |
418 | ||
a7812ae4 | 419 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 420 | { |
a7812ae4 | 421 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
c896fe29 FB |
422 | } |
423 | ||
951c6300 | 424 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 425 | { |
951c6300 RH |
426 | if (TCG_TARGET_HAS_neg_i32) { |
427 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); | |
25c4d9cc | 428 | } else { |
951c6300 | 429 | tcg_gen_subfi_i32(ret, 0, arg); |
25c4d9cc | 430 | } |
31d66551 AJ |
431 | } |
432 | ||
951c6300 | 433 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
31d66551 | 434 | { |
951c6300 RH |
435 | if (TCG_TARGET_HAS_not_i32) { |
436 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); | |
25c4d9cc | 437 | } else { |
951c6300 | 438 | tcg_gen_xori_i32(ret, arg, -1); |
25c4d9cc | 439 | } |
31d66551 AJ |
440 | } |
441 | ||
951c6300 RH |
442 | /* 64 bit ops */ |
443 | ||
444 | void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
445 | void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); | |
446 | void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
447 | void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); | |
448 | void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
449 | void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
450 | void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
451 | void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
452 | void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
453 | void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | |
454 | void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
455 | void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
456 | void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
457 | void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
458 | void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
459 | void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
460 | void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
461 | void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
462 | void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
463 | void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
464 | void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
465 | void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
466 | void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); | |
467 | void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, | |
468 | unsigned int ofs, unsigned int len); | |
42a268c2 RH |
469 | void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); |
470 | void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); | |
951c6300 RH |
471 | void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
472 | TCGv_i64 arg1, TCGv_i64 arg2); | |
473 | void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, | |
474 | TCGv_i64 arg1, int64_t arg2); | |
475 | void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, | |
476 | TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); | |
477 | void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, | |
478 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); | |
479 | void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, | |
480 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); | |
481 | void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); | |
482 | void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); | |
483 | void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); | |
484 | void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); | |
485 | void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); | |
486 | void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); | |
487 | void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); | |
488 | void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); | |
489 | void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); | |
490 | void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg); | |
491 | void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg); | |
492 | void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); | |
c896fe29 | 493 | |
951c6300 RH |
494 | #if TCG_TARGET_REG_BITS == 64 |
495 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) | |
496 | { | |
497 | tcg_gen_op1_i64(INDEX_op_discard, arg); | |
498 | } | |
c896fe29 | 499 | |
a7812ae4 | 500 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 501 | { |
fe75bcf7 | 502 | if (!TCGV_EQUAL_I64(ret, arg)) { |
951c6300 | 503 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
4d07272d | 504 | } |
c896fe29 FB |
505 | } |
506 | ||
a7812ae4 | 507 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 508 | { |
951c6300 | 509 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
c896fe29 FB |
510 | } |
511 | ||
a7812ae4 PB |
512 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
513 | tcg_target_long offset) | |
c896fe29 | 514 | { |
951c6300 | 515 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
c896fe29 FB |
516 | } |
517 | ||
a7812ae4 PB |
518 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
519 | tcg_target_long offset) | |
c896fe29 | 520 | { |
951c6300 | 521 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
c896fe29 FB |
522 | } |
523 | ||
a7812ae4 PB |
524 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
525 | tcg_target_long offset) | |
c896fe29 | 526 | { |
951c6300 | 527 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
c896fe29 FB |
528 | } |
529 | ||
a7812ae4 PB |
530 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
531 | tcg_target_long offset) | |
c896fe29 | 532 | { |
951c6300 | 533 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
c896fe29 FB |
534 | } |
535 | ||
a7812ae4 PB |
536 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
537 | tcg_target_long offset) | |
c896fe29 | 538 | { |
951c6300 | 539 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
c896fe29 FB |
540 | } |
541 | ||
a7812ae4 PB |
542 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
543 | tcg_target_long offset) | |
c896fe29 | 544 | { |
951c6300 | 545 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
c896fe29 FB |
546 | } |
547 | ||
a7812ae4 PB |
548 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
549 | tcg_target_long offset) | |
c896fe29 | 550 | { |
951c6300 | 551 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
c896fe29 FB |
552 | } |
553 | ||
a7812ae4 PB |
554 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
555 | tcg_target_long offset) | |
c896fe29 | 556 | { |
951c6300 | 557 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
c896fe29 FB |
558 | } |
559 | ||
a7812ae4 PB |
560 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
561 | tcg_target_long offset) | |
c896fe29 | 562 | { |
951c6300 | 563 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
c896fe29 FB |
564 | } |
565 | ||
a7812ae4 PB |
566 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
567 | tcg_target_long offset) | |
c896fe29 | 568 | { |
951c6300 | 569 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
c896fe29 FB |
570 | } |
571 | ||
a7812ae4 PB |
572 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
573 | tcg_target_long offset) | |
c896fe29 | 574 | { |
951c6300 | 575 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
c896fe29 FB |
576 | } |
577 | ||
a7812ae4 | 578 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 579 | { |
951c6300 | 580 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
c896fe29 FB |
581 | } |
582 | ||
a7812ae4 | 583 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 584 | { |
951c6300 | 585 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
c896fe29 FB |
586 | } |
587 | ||
a7812ae4 | 588 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 589 | { |
951c6300 | 590 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
c896fe29 FB |
591 | } |
592 | ||
a7812ae4 | 593 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 594 | { |
951c6300 | 595 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
c896fe29 FB |
596 | } |
597 | ||
a7812ae4 | 598 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 599 | { |
951c6300 | 600 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
c896fe29 FB |
601 | } |
602 | ||
a7812ae4 | 603 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 604 | { |
951c6300 | 605 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
606 | } |
607 | ||
a7812ae4 | 608 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 609 | { |
951c6300 | 610 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
611 | } |
612 | ||
a7812ae4 | 613 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 614 | { |
951c6300 | 615 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
5105c556 AJ |
616 | } |
617 | ||
a7812ae4 | 618 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 619 | { |
951c6300 | 620 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
c896fe29 | 621 | } |
951c6300 RH |
622 | #else /* TCG_TARGET_REG_BITS == 32 */ |
623 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, | |
624 | tcg_target_long offset) | |
c896fe29 | 625 | { |
951c6300 | 626 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
627 | } |
628 | ||
951c6300 RH |
629 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
630 | tcg_target_long offset) | |
c896fe29 | 631 | { |
951c6300 | 632 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
633 | } |
634 | ||
951c6300 RH |
635 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
636 | tcg_target_long offset) | |
c896fe29 | 637 | { |
951c6300 | 638 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
639 | } |
640 | ||
951c6300 | 641 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 642 | { |
951c6300 RH |
643 | tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
644 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); | |
c896fe29 FB |
645 | } |
646 | ||
951c6300 | 647 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 648 | { |
951c6300 RH |
649 | tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
650 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); | |
651 | } | |
652 | ||
653 | void tcg_gen_discard_i64(TCGv_i64 arg); | |
654 | void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); | |
655 | void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); | |
656 | void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
657 | void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
658 | void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
659 | void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
660 | void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
661 | void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
662 | void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | |
663 | void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); | |
664 | void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
665 | void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
666 | void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
667 | void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
668 | void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
669 | void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
670 | void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); | |
671 | #endif /* TCG_TARGET_REG_BITS */ | |
c896fe29 | 672 | |
951c6300 | 673 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 674 | { |
951c6300 RH |
675 | if (TCG_TARGET_HAS_neg_i64) { |
676 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); | |
677 | } else { | |
678 | tcg_gen_subfi_i64(ret, 0, arg); | |
679 | } | |
c896fe29 FB |
680 | } |
681 | ||
951c6300 | 682 | /* Size changing operations. */ |
c896fe29 | 683 | |
951c6300 RH |
684 | void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); |
685 | void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); | |
686 | void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); | |
609ad705 RH |
687 | void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); |
688 | void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); | |
951c6300 RH |
689 | void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); |
690 | void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); | |
c896fe29 | 691 | |
951c6300 | 692 | static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) |
c896fe29 | 693 | { |
951c6300 | 694 | tcg_gen_deposit_i64(ret, lo, hi, 32, 32); |
c896fe29 FB |
695 | } |
696 | ||
951c6300 | 697 | /* QEMU specific operations. */ |
c896fe29 | 698 | |
951c6300 RH |
699 | #ifndef TARGET_LONG_BITS |
700 | #error must include QEMU headers | |
701 | #endif | |
c896fe29 | 702 | |
9aef40ed RH |
703 | #if TARGET_INSN_START_WORDS == 1 |
704 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
705 | static inline void tcg_gen_insn_start(target_ulong pc) | |
c896fe29 | 706 | { |
9aef40ed RH |
707 | tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc); |
708 | } | |
709 | # else | |
710 | static inline void tcg_gen_insn_start(target_ulong pc) | |
711 | { | |
712 | tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, | |
713 | (uint32_t)pc, (uint32_t)(pc >> 32)); | |
714 | } | |
715 | # endif | |
716 | #elif TARGET_INSN_START_WORDS == 2 | |
717 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
718 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) | |
719 | { | |
720 | tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1); | |
721 | } | |
722 | # else | |
723 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) | |
724 | { | |
725 | tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start, | |
726 | (uint32_t)pc, (uint32_t)(pc >> 32), | |
727 | (uint32_t)a1, (uint32_t)(a1 >> 32)); | |
728 | } | |
729 | # endif | |
730 | #elif TARGET_INSN_START_WORDS == 3 | |
731 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
732 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, | |
733 | target_ulong a2) | |
734 | { | |
735 | tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2); | |
736 | } | |
737 | # else | |
738 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, | |
739 | target_ulong a2) | |
740 | { | |
741 | tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start, | |
742 | (uint32_t)pc, (uint32_t)(pc >> 32), | |
743 | (uint32_t)a1, (uint32_t)(a1 >> 32), | |
744 | (uint32_t)a2, (uint32_t)(a2 >> 32)); | |
745 | } | |
746 | # endif | |
951c6300 | 747 | #else |
9aef40ed | 748 | # error "Unhandled number of operands to insn_start" |
951c6300 | 749 | #endif |
c896fe29 | 750 | |
951c6300 | 751 | static inline void tcg_gen_exit_tb(uintptr_t val) |
c896fe29 | 752 | { |
951c6300 | 753 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
c896fe29 FB |
754 | } |
755 | ||
5b053a4a SF |
756 | /** |
757 | * tcg_gen_goto_tb() - output goto_tb TCG operation | |
758 | * @idx: Direct jump slot index (0 or 1) | |
759 | * | |
760 | * See tcg/README for more info about this TCG operation. | |
761 | * | |
90aa39a1 SF |
762 | * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within |
763 | * the pages this TB resides in because we don't take care of direct jumps when | |
764 | * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a | |
765 | * static address translation, so the destination address is always valid, TBs | |
766 | * are always invalidated properly, and direct jumps are reset when mapping | |
767 | * changes. | |
5b053a4a | 768 | */ |
951c6300 | 769 | void tcg_gen_goto_tb(unsigned idx); |
c896fe29 | 770 | |
a7812ae4 | 771 | #if TARGET_LONG_BITS == 32 |
a7812ae4 PB |
772 | #define tcg_temp_new() tcg_temp_new_i32() |
773 | #define tcg_global_reg_new tcg_global_reg_new_i32 | |
774 | #define tcg_global_mem_new tcg_global_mem_new_i32 | |
df9247b2 | 775 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
a7812ae4 | 776 | #define tcg_temp_free tcg_temp_free_i32 |
a7812ae4 | 777 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) |
afcb92be | 778 | #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x) |
fe75bcf7 | 779 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
f713d6ad RH |
780 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 |
781 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 | |
a7812ae4 | 782 | #else |
a7812ae4 PB |
783 | #define tcg_temp_new() tcg_temp_new_i64() |
784 | #define tcg_global_reg_new tcg_global_reg_new_i64 | |
785 | #define tcg_global_mem_new tcg_global_mem_new_i64 | |
df9247b2 | 786 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
a7812ae4 | 787 | #define tcg_temp_free tcg_temp_free_i64 |
a7812ae4 | 788 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) |
afcb92be | 789 | #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x) |
fe75bcf7 | 790 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
f713d6ad RH |
791 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 |
792 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 | |
a7812ae4 PB |
793 | #endif |
794 | ||
f713d6ad RH |
795 | void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); |
796 | void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); | |
797 | void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); | |
798 | void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); | |
c896fe29 | 799 | |
ac56dd48 | 800 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 801 | { |
f713d6ad | 802 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB); |
c896fe29 FB |
803 | } |
804 | ||
ac56dd48 | 805 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 806 | { |
f713d6ad | 807 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB); |
c896fe29 FB |
808 | } |
809 | ||
ac56dd48 | 810 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 811 | { |
f713d6ad | 812 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW); |
c896fe29 FB |
813 | } |
814 | ||
ac56dd48 | 815 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 816 | { |
f713d6ad | 817 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW); |
c896fe29 FB |
818 | } |
819 | ||
ac56dd48 | 820 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 821 | { |
f713d6ad | 822 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL); |
c896fe29 FB |
823 | } |
824 | ||
ac56dd48 | 825 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 826 | { |
f713d6ad | 827 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL); |
c896fe29 FB |
828 | } |
829 | ||
a7812ae4 | 830 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 | 831 | { |
f713d6ad | 832 | tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ); |
c896fe29 FB |
833 | } |
834 | ||
ac56dd48 | 835 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 836 | { |
f713d6ad | 837 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB); |
c896fe29 FB |
838 | } |
839 | ||
ac56dd48 | 840 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 841 | { |
f713d6ad | 842 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW); |
c896fe29 FB |
843 | } |
844 | ||
ac56dd48 | 845 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 846 | { |
f713d6ad | 847 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL); |
c896fe29 FB |
848 | } |
849 | ||
a7812ae4 | 850 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 | 851 | { |
f713d6ad | 852 | tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ); |
c896fe29 FB |
853 | } |
854 | ||
f8422f52 | 855 | #if TARGET_LONG_BITS == 64 |
f8422f52 BS |
856 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
857 | #define tcg_gen_mov_tl tcg_gen_mov_i64 | |
858 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 | |
859 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 | |
860 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 | |
861 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 | |
862 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 | |
863 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 | |
864 | #define tcg_gen_ld_tl tcg_gen_ld_i64 | |
865 | #define tcg_gen_st8_tl tcg_gen_st8_i64 | |
866 | #define tcg_gen_st16_tl tcg_gen_st16_i64 | |
867 | #define tcg_gen_st32_tl tcg_gen_st32_i64 | |
868 | #define tcg_gen_st_tl tcg_gen_st_i64 | |
869 | #define tcg_gen_add_tl tcg_gen_add_i64 | |
870 | #define tcg_gen_addi_tl tcg_gen_addi_i64 | |
871 | #define tcg_gen_sub_tl tcg_gen_sub_i64 | |
390efc54 | 872 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
10460c8a | 873 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
f8422f52 BS |
874 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
875 | #define tcg_gen_and_tl tcg_gen_and_i64 | |
876 | #define tcg_gen_andi_tl tcg_gen_andi_i64 | |
877 | #define tcg_gen_or_tl tcg_gen_or_i64 | |
878 | #define tcg_gen_ori_tl tcg_gen_ori_i64 | |
879 | #define tcg_gen_xor_tl tcg_gen_xor_i64 | |
880 | #define tcg_gen_xori_tl tcg_gen_xori_i64 | |
0b6ce4cf | 881 | #define tcg_gen_not_tl tcg_gen_not_i64 |
f8422f52 BS |
882 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
883 | #define tcg_gen_shli_tl tcg_gen_shli_i64 | |
884 | #define tcg_gen_shr_tl tcg_gen_shr_i64 | |
885 | #define tcg_gen_shri_tl tcg_gen_shri_i64 | |
886 | #define tcg_gen_sar_tl tcg_gen_sar_i64 | |
887 | #define tcg_gen_sari_tl tcg_gen_sari_i64 | |
0cf767d6 | 888 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
cb63669a | 889 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
be210acb | 890 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
add1e7ea | 891 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
f730fd27 TS |
892 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
893 | #define tcg_gen_muli_tl tcg_gen_muli_i64 | |
ab36421e AJ |
894 | #define tcg_gen_div_tl tcg_gen_div_i64 |
895 | #define tcg_gen_rem_tl tcg_gen_rem_i64 | |
864951af AJ |
896 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
897 | #define tcg_gen_remu_tl tcg_gen_remu_i64 | |
a768e4b2 | 898 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
ecc7b3aa | 899 | #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 |
e429073d BS |
900 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 |
901 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 | |
902 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 | |
903 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 | |
904 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 | |
0b6ce4cf FB |
905 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
906 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 | |
907 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 | |
908 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 | |
909 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 | |
910 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 | |
911d79ba AJ |
911 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
912 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 | |
913 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 | |
945ca823 | 914 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
3c51a985 | 915 | #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 |
f24cb33e AJ |
916 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
917 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 | |
918 | #define tcg_gen_nand_tl tcg_gen_nand_i64 | |
919 | #define tcg_gen_nor_tl tcg_gen_nor_i64 | |
920 | #define tcg_gen_orc_tl tcg_gen_orc_i64 | |
15824571 AJ |
921 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
922 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 | |
923 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 | |
924 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 | |
b7767f0f | 925 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
a98824ac | 926 | #define tcg_const_tl tcg_const_i64 |
bdffd4a9 | 927 | #define tcg_const_local_tl tcg_const_local_i64 |
ffc5ea09 | 928 | #define tcg_gen_movcond_tl tcg_gen_movcond_i64 |
f6953a73 RH |
929 | #define tcg_gen_add2_tl tcg_gen_add2_i64 |
930 | #define tcg_gen_sub2_tl tcg_gen_sub2_i64 | |
696a8be6 RH |
931 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 |
932 | #define tcg_gen_muls2_tl tcg_gen_muls2_i64 | |
f8422f52 | 933 | #else |
f8422f52 BS |
934 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
935 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | |
936 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 | |
937 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 | |
938 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 | |
939 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 | |
940 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 | |
941 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 | |
942 | #define tcg_gen_ld_tl tcg_gen_ld_i32 | |
943 | #define tcg_gen_st8_tl tcg_gen_st8_i32 | |
944 | #define tcg_gen_st16_tl tcg_gen_st16_i32 | |
945 | #define tcg_gen_st32_tl tcg_gen_st_i32 | |
946 | #define tcg_gen_st_tl tcg_gen_st_i32 | |
947 | #define tcg_gen_add_tl tcg_gen_add_i32 | |
948 | #define tcg_gen_addi_tl tcg_gen_addi_i32 | |
949 | #define tcg_gen_sub_tl tcg_gen_sub_i32 | |
390efc54 | 950 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
0045734a | 951 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
f8422f52 BS |
952 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
953 | #define tcg_gen_and_tl tcg_gen_and_i32 | |
954 | #define tcg_gen_andi_tl tcg_gen_andi_i32 | |
955 | #define tcg_gen_or_tl tcg_gen_or_i32 | |
956 | #define tcg_gen_ori_tl tcg_gen_ori_i32 | |
957 | #define tcg_gen_xor_tl tcg_gen_xor_i32 | |
958 | #define tcg_gen_xori_tl tcg_gen_xori_i32 | |
0b6ce4cf | 959 | #define tcg_gen_not_tl tcg_gen_not_i32 |
f8422f52 BS |
960 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
961 | #define tcg_gen_shli_tl tcg_gen_shli_i32 | |
962 | #define tcg_gen_shr_tl tcg_gen_shr_i32 | |
963 | #define tcg_gen_shri_tl tcg_gen_shri_i32 | |
964 | #define tcg_gen_sar_tl tcg_gen_sar_i32 | |
965 | #define tcg_gen_sari_tl tcg_gen_sari_i32 | |
0cf767d6 | 966 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
cb63669a | 967 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
be210acb | 968 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
add1e7ea | 969 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
f730fd27 TS |
970 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
971 | #define tcg_gen_muli_tl tcg_gen_muli_i32 | |
ab36421e AJ |
972 | #define tcg_gen_div_tl tcg_gen_div_i32 |
973 | #define tcg_gen_rem_tl tcg_gen_rem_i32 | |
864951af AJ |
974 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
975 | #define tcg_gen_remu_tl tcg_gen_remu_i32 | |
a768e4b2 | 976 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
e429073d | 977 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
ecc7b3aa | 978 | #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 |
e429073d BS |
979 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 |
980 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 | |
981 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 | |
982 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 | |
0b6ce4cf FB |
983 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
984 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 | |
985 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 | |
986 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 | |
987 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 | |
988 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 | |
911d79ba AJ |
989 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
990 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 | |
945ca823 | 991 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
e3eb9806 | 992 | #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 |
f24cb33e AJ |
993 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
994 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 | |
995 | #define tcg_gen_nand_tl tcg_gen_nand_i32 | |
996 | #define tcg_gen_nor_tl tcg_gen_nor_i32 | |
997 | #define tcg_gen_orc_tl tcg_gen_orc_i32 | |
15824571 AJ |
998 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
999 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 | |
1000 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 | |
1001 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 | |
b7767f0f | 1002 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
a98824ac | 1003 | #define tcg_const_tl tcg_const_i32 |
bdffd4a9 | 1004 | #define tcg_const_local_tl tcg_const_local_i32 |
ffc5ea09 | 1005 | #define tcg_gen_movcond_tl tcg_gen_movcond_i32 |
f6953a73 RH |
1006 | #define tcg_gen_add2_tl tcg_gen_add2_i32 |
1007 | #define tcg_gen_sub2_tl tcg_gen_sub2_i32 | |
696a8be6 RH |
1008 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 |
1009 | #define tcg_gen_muls2_tl tcg_gen_muls2_i32 | |
f8422f52 | 1010 | #endif |
6ddbc6e4 | 1011 | |
71b92699 | 1012 | #if UINTPTR_MAX == UINT32_MAX |
f713d6ad RH |
1013 | # define tcg_gen_ld_ptr(R, A, O) \ |
1014 | tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O)) | |
1015 | # define tcg_gen_discard_ptr(A) \ | |
1016 | tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A)) | |
1017 | # define tcg_gen_add_ptr(R, A, B) \ | |
1018 | tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) | |
1019 | # define tcg_gen_addi_ptr(R, A, B) \ | |
1020 | tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) | |
1021 | # define tcg_gen_ext_i32_ptr(R, A) \ | |
1022 | tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A)) | |
1023 | #else | |
1024 | # define tcg_gen_ld_ptr(R, A, O) \ | |
1025 | tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O)) | |
1026 | # define tcg_gen_discard_ptr(A) \ | |
1027 | tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A)) | |
1028 | # define tcg_gen_add_ptr(R, A, B) \ | |
1029 | tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) | |
1030 | # define tcg_gen_addi_ptr(R, A, B) \ | |
1031 | tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) | |
1032 | # define tcg_gen_ext_i32_ptr(R, A) \ | |
1033 | tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A)) | |
71b92699 | 1034 | #endif /* UINTPTR_MAX == UINT32_MAX */ |